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Update UltraScale R5 hardware definition and BSP for 2016.4 SDK tools.

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pull/4/head
Richard Barry 8 years ago
parent ff55eb920c
commit 979e41c9da
11 changed files with 11038 additions and 3095 deletions
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4
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject
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@ -1,8 +1,8 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?> <?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings"> <storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="org.eclipse.cdt.core.default.config.887738538"> <cconfiguration id="org.eclipse.cdt.core.default.config.690704917">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.887738538" moduleId="org.eclipse.cdt.core.settings" name="Configuration"> <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.690704917" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/> <externalSettings/>
<extensions/> <extensions/>
</storageModule> </storageModule>

71
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h
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@ -18,6 +18,8 @@
#include "xparameters_ps.h" #include "xparameters_ps.h"
#define XPS_BOARD_ZCU102
/******************************************************************/ /******************************************************************/
/* /*
@ -385,11 +387,6 @@
#define XPAR_PSU_CRL_APB_S_AXI_HIGHADDR 0xFF85FFFF #define XPAR_PSU_CRL_APB_S_AXI_HIGHADDR 0xFF85FFFF
/* Definitions for peripheral PSU_CSU_0 */
#define XPAR_PSU_CSU_0_S_AXI_BASEADDR 0xFFCA0000
#define XPAR_PSU_CSU_0_S_AXI_HIGHADDR 0xFFCAFFFF
/* Definitions for peripheral PSU_DDR_PHY */ /* Definitions for peripheral PSU_DDR_PHY */
#define XPAR_PSU_DDR_PHY_S_AXI_BASEADDR 0xFD080000 #define XPAR_PSU_DDR_PHY_S_AXI_BASEADDR 0xFD080000
#define XPAR_PSU_DDR_PHY_S_AXI_HIGHADDR 0xFD08FFFF #define XPAR_PSU_DDR_PHY_S_AXI_HIGHADDR 0xFD08FFFF
@ -680,7 +677,7 @@
/******************************************************************/ /******************************************************************/
#define XPAR_XIPIPSU_NUM_INSTANCES 2 #define XPAR_XIPIPSU_NUM_INSTANCES 1
/* Parameter definitions for peripheral psu_ipi_1 */ /* Parameter definitions for peripheral psu_ipi_1 */
#define XPAR_PSU_IPI_1_DEVICE_ID 0 #define XPAR_PSU_IPI_1_DEVICE_ID 0
@ -689,13 +686,6 @@
#define XPAR_PSU_IPI_1_BUFFER_INDEX 0 #define XPAR_PSU_IPI_1_BUFFER_INDEX 0
#define XPAR_PSU_IPI_1_INT_ID 65 #define XPAR_PSU_IPI_1_INT_ID 65
/* Parameter definitions for peripheral psu_ipi_2 */
#define XPAR_PSU_IPI_2_DEVICE_ID 1
#define XPAR_PSU_IPI_2_BASE_ADDRESS 0xFF320000
#define XPAR_PSU_IPI_2_BIT_MASK 0x00000200
#define XPAR_PSU_IPI_2_BUFFER_INDEX 1
#define XPAR_PSU_IPI_2_INT_ID 66
/* Canonical definitions for peripheral psu_ipi_1 */ /* Canonical definitions for peripheral psu_ipi_1 */
#define XPAR_XIPIPSU_0_DEVICE_ID XPAR_PSU_IPI_1_DEVICE_ID #define XPAR_XIPIPSU_0_DEVICE_ID XPAR_PSU_IPI_1_DEVICE_ID
#define XPAR_XIPIPSU_0_BASE_ADDRESS XPAR_PSU_IPI_1_BASE_ADDRESS #define XPAR_XIPIPSU_0_BASE_ADDRESS XPAR_PSU_IPI_1_BASE_ADDRESS
@ -703,13 +693,6 @@
#define XPAR_XIPIPSU_0_BUFFER_INDEX XPAR_PSU_IPI_1_BUFFER_INDEX #define XPAR_XIPIPSU_0_BUFFER_INDEX XPAR_PSU_IPI_1_BUFFER_INDEX
#define XPAR_XIPIPSU_0_INT_ID XPAR_PSU_IPI_1_INT_ID #define XPAR_XIPIPSU_0_INT_ID XPAR_PSU_IPI_1_INT_ID
/* Canonical definitions for peripheral psu_ipi_2 */
#define XPAR_XIPIPSU_1_DEVICE_ID XPAR_PSU_IPI_2_DEVICE_ID
#define XPAR_XIPIPSU_1_BASE_ADDRESS XPAR_PSU_IPI_2_BASE_ADDRESS
#define XPAR_XIPIPSU_1_BIT_MASK XPAR_PSU_IPI_2_BIT_MASK
#define XPAR_XIPIPSU_1_BUFFER_INDEX XPAR_PSU_IPI_2_BUFFER_INDEX
#define XPAR_XIPIPSU_1_INT_ID XPAR_PSU_IPI_2_INT_ID
#define XPAR_XIPIPSU_NUM_TARGETS 11 #define XPAR_XIPIPSU_NUM_TARGETS 11
#define XPAR_PSU_IPI_0_BIT_MASK 0x00000001 #define XPAR_PSU_IPI_0_BIT_MASK 0x00000001
@ -738,54 +721,30 @@
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_MASK XPAR_PSU_IPI_1_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_INDEX 1
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_MASK XPAR_PSU_IPI_2_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_INDEX 2
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_MASK XPAR_PSU_IPI_1_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_INDEX 1
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_MASK XPAR_PSU_IPI_2_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_INDEX 2
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_MASK XPAR_PSU_IPI_1_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_INDEX 1
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_MASK XPAR_PSU_IPI_2_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_INDEX 2
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_MASK XPAR_PSU_IPI_1_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_INDEX 1
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_MASK XPAR_PSU_IPI_2_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_INDEX 2
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 1 #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 1
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH1_MASK XPAR_PSU_IPI_2_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH1_INDEX 2 #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK XPAR_PSU_IPI_2_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX 2
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX 1 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK XPAR_PSU_IPI_3_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_MASK XPAR_PSU_IPI_2_BIT_MASK #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 3
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_INDEX 2 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK XPAR_PSU_IPI_4_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 4
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK XPAR_PSU_IPI_5_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 1 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 5
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK XPAR_PSU_IPI_2_BIT_MASK #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK XPAR_PSU_IPI_6_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 2 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 6
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK XPAR_PSU_IPI_3_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 3
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK XPAR_PSU_IPI_4_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 4
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_MASK XPAR_PSU_IPI_5_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_INDEX 5
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_MASK XPAR_PSU_IPI_6_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_INDEX 6
/* Definitions for driver QSPIPSU */ /* Definitions for driver QSPIPSU */
#define XPAR_XQSPIPSU_NUM_INSTANCES 1 #define XPAR_XQSPIPSU_NUM_INSTANCES 1

56
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c
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@ -101,61 +101,5 @@ XIpiPsu_Config XIpiPsu_ConfigTable[] =
XPAR_PSU_IPI_10_BUFFER_INDEX XPAR_PSU_IPI_10_BUFFER_INDEX
} }
} }
},
{
XPAR_PSU_IPI_2_DEVICE_ID,
XPAR_PSU_IPI_2_BASE_ADDRESS,
XPAR_PSU_IPI_2_BIT_MASK,
XPAR_PSU_IPI_2_BUFFER_INDEX,
XPAR_PSU_IPI_2_INT_ID,
XPAR_XIPIPSU_NUM_TARGETS,
{
{
XPAR_PSU_IPI_0_BIT_MASK,
XPAR_PSU_IPI_0_BUFFER_INDEX
},
{
XPAR_PSU_IPI_1_BIT_MASK,
XPAR_PSU_IPI_1_BUFFER_INDEX
},
{
XPAR_PSU_IPI_2_BIT_MASK,
XPAR_PSU_IPI_2_BUFFER_INDEX
},
{
XPAR_PSU_IPI_3_BIT_MASK,
XPAR_PSU_IPI_3_BUFFER_INDEX
},
{
XPAR_PSU_IPI_4_BIT_MASK,
XPAR_PSU_IPI_4_BUFFER_INDEX
},
{
XPAR_PSU_IPI_5_BIT_MASK,
XPAR_PSU_IPI_5_BUFFER_INDEX
},
{
XPAR_PSU_IPI_6_BIT_MASK,
XPAR_PSU_IPI_6_BUFFER_INDEX
},
{
XPAR_PSU_IPI_7_BIT_MASK,
XPAR_PSU_IPI_7_BUFFER_INDEX
},
{
XPAR_PSU_IPI_8_BIT_MASK,
XPAR_PSU_IPI_8_BUFFER_INDEX
},
{
XPAR_PSU_IPI_9_BIT_MASK,
XPAR_PSU_IPI_9_BUFFER_INDEX
},
{
XPAR_PSU_IPI_10_BIT_MASK,
XPAR_PSU_IPI_10_BUFFER_INDEX
}
}
} }
}; };

12
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss
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@ -186,12 +186,6 @@ BEGIN DRIVER
PARAMETER HW_INSTANCE = psu_crl_apb PARAMETER HW_INSTANCE = psu_crl_apb
END END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = psu_csu_0
END
BEGIN DRIVER BEGIN DRIVER
PARAMETER DRIVER_NAME = csudma PARAMETER DRIVER_NAME = csudma
PARAMETER DRIVER_VER = 1.1 PARAMETER DRIVER_VER = 1.1
@ -408,12 +402,6 @@ BEGIN DRIVER
PARAMETER HW_INSTANCE = psu_ipi_1 PARAMETER HW_INSTANCE = psu_ipi_1
END END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ipipsu
PARAMETER DRIVER_VER = 2.1
PARAMETER HW_INSTANCE = psu_ipi_2
END
BEGIN DRIVER BEGIN DRIVER
PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0 PARAMETER DRIVER_VER = 2.0

8
FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/.project
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@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<projectDescription> <projectDescription>
<name>ZynqMP_ZCU102_hw_platform</name> <name>ZynqMP_ZCU102_hw_platform</name>
<comment>Created by SDK v2016.1</comment> <comment>Created by SDK v2016.4</comment>
<projects> <projects>
</projects> </projects>
<buildSpec> <buildSpec>
@ -11,7 +11,7 @@
</natures> </natures>
<filteredResources> <filteredResources>
<filter> <filter>
<id>1462451796084</id> <id>1484843910633</id>
<name></name> <name></name>
<type>6</type> <type>6</type>
<matcher> <matcher>
@ -20,7 +20,7 @@
</matcher> </matcher>
</filter> </filter>
<filter> <filter>
<id>1462451796084</id> <id>1484843910635</id>
<name></name> <name></name>
<type>6</type> <type>6</type>
<matcher> <matcher>
@ -29,7 +29,7 @@
</matcher> </matcher>
</filter> </filter>
<filter> <filter>
<id>1462451796094</id> <id>1484843910637</id>
<name></name> <name></name>
<type>6</type> <type>6</type>
<matcher> <matcher>

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FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c
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FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h
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FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl
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FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c
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FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h
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FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf
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