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@ -1,6 +1,6 @@
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/******************************************************************************
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*
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* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
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* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -55,6 +55,14 @@
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* of SDR50, SDR104 and HS200.
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* sk 02/16/16 Corrected the Tuning logic.
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* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
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* 2.8 sk 04/20/16 Added new workaround for auto tuning.
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* 3.0 sk 07/07/16 Used usleep API for both arm and microblaze.
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* sk 07/16/16 Added support for UHS modes.
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* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
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* operating modes.
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* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
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* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
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* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
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*
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* </pre>
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*
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@ -62,24 +70,14 @@
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/***************************** Include Files *********************************/
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#include "xsdps.h"
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/*
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* The header sleep.h and API usleep() can only be used with an arm design.
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* MB_Sleep() is used for microblaze design.
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*/
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#if defined (__arm__) || defined (__aarch64__)
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#include "sleep.h"
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#endif
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#ifdef __MICROBLAZE__
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#include "microblaze_sleep.h"
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#endif
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/************************** Constant Definitions *****************************/
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#define UHS_SDR12_SUPPORT 0x1U
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#define UHS_SDR25_SUPPORT 0x2U
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#define UHS_SDR50_SUPPORT 0x4U
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#define UHS_SDR104_SUPPORT 0x8U
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#define UHS_DDR50_SUPPORT 0x10U
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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@ -87,11 +85,13 @@
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/************************** Function Prototypes ******************************/
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s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
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void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
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s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
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static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr);
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#if defined (ARMR5) || defined (__aarch64__)
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s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
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#if defined (__arm__) || defined (__aarch64__)
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static void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
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static void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
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void XSdPs_SetTapDelay(XSdPs *InstancePtr);
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static void XSdPs_DllReset(XSdPs *InstancePtr);
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#endif
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|
/*****************************************************************************/
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@ -320,19 +320,8 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
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XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
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}
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#if defined (__arm__) || defined (__aarch64__)
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usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
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#endif
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|
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#ifdef __MICROBLAZE__
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|
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/* 2 msec delay */
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|
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MB_Sleep(2);
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|
#endif
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StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
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|
|
XSDPS_HOST_CTRL1_OFFSET);
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@ -463,7 +452,6 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
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s32 Status;
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|
|
u32 StatusReg;
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|
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u32 Arg;
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|
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u32 ClockReg;
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|
|
u16 BlkCnt;
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|
|
u16 BlkSize;
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|
|
u8 ReadBuff[64];
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|
|
@ -610,25 +598,10 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
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|
|
Status = XST_FAILURE;
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|
|
goto RETURN_PATH;
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|
|
}
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|
#if defined (__arm__) || defined (__aarch64__)
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|
|
/* Program the Tap delays */
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|
|
XSdPs_SetTapDelay(InstancePtr);
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|
|
#endif
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|
}
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|
|
#if defined (__arm__) || defined (__aarch64__)
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|
|
usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
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#endif
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|
|
#ifdef __MICROBLAZE__
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|
|
/* 2 msec delay */
|
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|
|
MB_Sleep(2);
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|
|
#endif
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|
|
StatusReg = (s32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
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|
|
|
XSDPS_HOST_CTRL1_OFFSET);
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|
|
StatusReg |= XSDPS_HC_SPEED_MASK;
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|
|
@ -667,7 +640,6 @@ s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
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|
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u16 DivCnt;
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|
|
u16 Divisor = 0U;
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|
|
u16 ExtDivisor;
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|
|
u16 ClkLoopCnt;
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|
|
s32 Status;
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|
|
u16 ReadReg;
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@ -682,6 +654,12 @@ s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
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XSDPS_CLK_CTRL_OFFSET, ClockReg);
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|
if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
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|
|
#if defined (ARMR5) || defined (__aarch64__)
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|
|
if ((InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) &&
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|
|
(InstancePtr->Mode != XSDPS_UHS_SPEED_MODE_SDR12))
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|
/* Program the Tap delays */
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|
|
XSdPs_SetTapDelay(InstancePtr);
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|
#endif
|
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|
|
/* Calculate divisor */
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|
for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT;DivCnt++) {
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if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
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@ -890,6 +868,110 @@ s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
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}
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|
/*****************************************************************************/
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|
|
/**
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*
|
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|
|
* API to write EXT_CSD register of eMMC.
|
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|
|
*
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|
|
*
|
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|
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* @param InstancePtr is a pointer to the XSdPs instance.
|
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|
|
* @param Arg is the argument to be sent along with the command
|
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*
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* @return
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* - XST_SUCCESS if successful.
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* - XST_FAILURE if fail.
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*
|
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|
* @note None.
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|
|
*
|
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|
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|
******************************************************************************/
|
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|
|
s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
|
|
|
|
|
{
|
|
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|
|
s32 Status;
|
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|
|
|
u32 StatusReg;
|
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|
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Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
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|
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|
|
if (Status != XST_SUCCESS) {
|
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|
|
Status = XST_FAILURE;
|
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|
|
|
goto RETURN_PATH;
|
|
|
|
|
}
|
|
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|
|
|
|
|
|
/*
|
|
|
|
|
* Check for transfer complete
|
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|
|
|
*/
|
|
|
|
|
do {
|
|
|
|
|
StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
|
|
|
|
XSDPS_NORM_INTR_STS_OFFSET);
|
|
|
|
|
if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
|
|
|
|
|
/*
|
|
|
|
|
* Write to clear error bits
|
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|
|
|
*/
|
|
|
|
|
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
|
|
|
|
|
XSDPS_ERR_INTR_STS_OFFSET,
|
|
|
|
|
XSDPS_ERROR_INTR_ALL_MASK);
|
|
|
|
|
Status = XST_FAILURE;
|
|
|
|
|
goto RETURN_PATH;
|
|
|
|
|
}
|
|
|
|
|
} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
|
|
|
|
|
|
|
|
|
|
/* Write to clear bit */
|
|
|
|
|
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
|
|
|
|
|
XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
|
|
|
|
|
|
|
|
|
|
Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
|
|
|
|
|
XSDPS_RESP0_OFFSET);
|
|
|
|
|
|
|
|
|
|
Status = XST_SUCCESS;
|
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|
|
|
|
|
|
|
|
RETURN_PATH:
|
|
|
|
|
return Status;
|
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|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if defined (ARMR5) || defined (__aarch64__)
|
|
|
|
|
/*****************************************************************************/
|
|
|
|
|
/**
|
|
|
|
|
*
|
|
|
|
|
* API to Identify the supported UHS mode. This API will assign the
|
|
|
|
|
* corresponding tap delay API to the Config_TapDelay pointer based on the
|
|
|
|
|
* supported bus speed.
|
|
|
|
|
*
|
|
|
|
|
*
|
|
|
|
|
* @param InstancePtr is a pointer to the XSdPs instance.
|
|
|
|
|
* @param ReadBuff contains the response for CMD6
|
|
|
|
|
*
|
|
|
|
|
* @return None.
|
|
|
|
|
*
|
|
|
|
|
* @note None.
|
|
|
|
|
*
|
|
|
|
|
******************************************************************************/
|
|
|
|
|
void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
Xil_AssertVoid(InstancePtr != NULL);
|
|
|
|
|
|
|
|
|
|
if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) &&
|
|
|
|
|
(InstancePtr->Config.InputClockHz >= XSDPS_MMC_HS200_MAX_CLK)) {
|
|
|
|
|
InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104;
|
|
|
|
|
InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
|
|
|
|
|
}
|
|
|
|
|
else if (((ReadBuff[13] & UHS_SDR50_SUPPORT) != 0U) &&
|
|
|
|
|
(InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR50_MAX_CLK)) {
|
|
|
|
|
InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR50;
|
|
|
|
|
InstancePtr->Config_TapDelay = XSdPs_sdr50_tapdelay;
|
|
|
|
|
}
|
|
|
|
|
else if (((ReadBuff[13] & UHS_DDR50_SUPPORT) != 0U) &&
|
|
|
|
|
(InstancePtr->Config.InputClockHz >= XSDPS_SD_DDR50_MAX_CLK)) {
|
|
|
|
|
InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_DDR50;
|
|
|
|
|
InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
|
|
|
|
|
}
|
|
|
|
|
else if (((ReadBuff[13] & UHS_SDR25_SUPPORT) != 0U) &&
|
|
|
|
|
(InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR25_MAX_CLK)) {
|
|
|
|
|
InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR25;
|
|
|
|
|
InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR12;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************/
|
|
|
|
|
/**
|
|
|
|
|
@ -1008,7 +1090,7 @@ s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode)
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if((Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
|
|
|
|
|
(Mode == XSDPS_UHS_SPEED_MODE_DDR50)) {
|
|
|
|
|
(Mode == XSDPS_UHS_SPEED_MODE_SDR50)) {
|
|
|
|
|
/* Send tuning pattern */
|
|
|
|
|
Status = XSdPs_Execute_Tuning(InstancePtr);
|
|
|
|
|
if (Status != XST_SUCCESS) {
|
|
|
|
|
@ -1022,22 +1104,18 @@ s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode)
|
|
|
|
|
RETURN_PATH:
|
|
|
|
|
return Status;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
|
|
|
|
|
{
|
|
|
|
|
s32 Status;
|
|
|
|
|
u32 StatusReg;
|
|
|
|
|
u32 Arg;
|
|
|
|
|
u16 BlkCnt;
|
|
|
|
|
u16 BlkSize;
|
|
|
|
|
s32 LoopCnt;
|
|
|
|
|
u16 CtrlReg;
|
|
|
|
|
u8 TuningCount;
|
|
|
|
|
|
|
|
|
|
Xil_AssertNonvoid(InstancePtr != NULL);
|
|
|
|
|
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
|
|
|
|
|
|
|
|
|
BlkCnt = XSDPS_TUNING_CMD_BLKCNT;
|
|
|
|
|
BlkSize = XSDPS_TUNING_CMD_BLKSIZE;
|
|
|
|
|
if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH)
|
|
|
|
|
{
|
|
|
|
|
@ -1056,6 +1134,18 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
|
|
|
|
|
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
|
|
|
|
|
XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* workaround which can work for 1.0/2.0 silicon for auto tuning.
|
|
|
|
|
* This can be revisited for 3.0 silicon if necessary.
|
|
|
|
|
*/
|
|
|
|
|
/* Wait for ~60 clock cycles to reset the tap values */
|
|
|
|
|
(void)usleep(1U);
|
|
|
|
|
|
|
|
|
|
#if defined (ARMR5) || defined (__aarch64__)
|
|
|
|
|
/* Issue DLL Reset to load new SDHC tuned tap values */
|
|
|
|
|
XSdPs_DllReset(InstancePtr);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
for (TuningCount = 0U; TuningCount < MAX_TUNING_COUNT; TuningCount++) {
|
|
|
|
|
|
|
|
|
|
if (InstancePtr->CardType == XSDPS_CARD_SD) {
|
|
|
|
|
@ -1073,6 +1163,13 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
|
|
|
|
|
XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) {
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (TuningCount == 31) {
|
|
|
|
|
#if defined (ARMR5) || defined (__aarch64__)
|
|
|
|
|
/* Issue DLL Reset to load new SDHC tuned tap values */
|
|
|
|
|
XSdPs_DllReset(InstancePtr);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
|
|
|
|
@ -1081,25 +1178,13 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
|
|
|
|
|
goto RETURN_PATH;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* As per controller erratum, program the "SDCLK Frequency
|
|
|
|
|
* Select" of clock control register with a value, say
|
|
|
|
|
* clock/2. Wait for the Internal clock stable and program
|
|
|
|
|
* the desired frequency.
|
|
|
|
|
*/
|
|
|
|
|
CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
|
|
|
|
XSDPS_HOST_CTRL2_OFFSET);
|
|
|
|
|
if ((CtrlReg & XSDPS_HC2_SAMP_CLK_SEL_MASK) != 0U) {
|
|
|
|
|
Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed/2);
|
|
|
|
|
if (Status != XST_SUCCESS) {
|
|
|
|
|
goto RETURN_PATH ;
|
|
|
|
|
}
|
|
|
|
|
Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
|
|
|
|
|
if (Status != XST_SUCCESS) {
|
|
|
|
|
goto RETURN_PATH ;
|
|
|
|
|
}
|
|
|
|
|
/* Wait for ~12 clock cycles to synchronize the new tap values */
|
|
|
|
|
(void)usleep(1U);
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
#if defined (ARMR5) || defined (__aarch64__)
|
|
|
|
|
/* Issue DLL Reset to load new SDHC tuned tap values */
|
|
|
|
|
XSdPs_DllReset(InstancePtr);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
Status = XST_SUCCESS;
|
|
|
|
|
|
|
|
|
|
@ -1107,7 +1192,226 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if defined (__arm__) || defined (__aarch64__)
|
|
|
|
|
#if defined (ARMR5) || defined (__aarch64__)
|
|
|
|
|
/*****************************************************************************/
|
|
|
|
|
/**
|
|
|
|
|
*
|
|
|
|
|
* API to set Tap Delay for SDR104 and HS200 modes
|
|
|
|
|
*
|
|
|
|
|
*
|
|
|
|
|
* @param InstancePtr is a pointer to the XSdPs instance.
|
|
|
|
|
*
|
|
|
|
|
* @return None
|
|
|
|
|
*
|
|
|
|
|
* @note None.
|
|
|
|
|
*
|
|
|
|
|
******************************************************************************/
|
|
|
|
|
void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
|
|
|
|
|
{
|
|
|
|
|
u32 TapDelay;
|
|
|
|
|
(void) CardType;
|
|
|
|
|
|
|
|
|
|
#ifdef XPAR_PSU_SD_0_DEVICE_ID
|
|
|
|
|
if (DeviceId == 0U) {
|
|
|
|
|
/* Program the OTAPDLY */
|
|
|
|
|
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
|
|
|
|
|
TapDelay |= SD0_OTAPDLYENA;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
|
|
|
|
|
if (Bank == 2)
|
|
|
|
|
TapDelay |= SD0_OTAPDLYSEL_HS200_B2;
|
|
|
|
|
else
|
|
|
|
|
TapDelay |= SD0_OTAPDLYSEL_HS200_B0;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
|
|
|
|
|
} else {
|
|
|
|
|
#endif
|
|
|
|
|
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
|
|
|
|
|
TapDelay |= SD1_OTAPDLYENA;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
|
|
|
|
|
if (Bank == 2)
|
|
|
|
|
TapDelay |= SD1_OTAPDLYSEL_HS200_B2;
|
|
|
|
|
else
|
|
|
|
|
TapDelay |= SD1_OTAPDLYSEL_HS200_B0;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
|
|
|
|
|
#ifdef XPAR_PSU_SD_0_DEVICE_ID
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************/
|
|
|
|
|
/**
|
|
|
|
|
*
|
|
|
|
|
* API to set Tap Delay for SDR50 mode
|
|
|
|
|
*
|
|
|
|
|
*
|
|
|
|
|
* @param InstancePtr is a pointer to the XSdPs instance.
|
|
|
|
|
*
|
|
|
|
|
* @return None
|
|
|
|
|
*
|
|
|
|
|
* @note None.
|
|
|
|
|
*
|
|
|
|
|
******************************************************************************/
|
|
|
|
|
void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
|
|
|
|
|
{
|
|
|
|
|
u32 TapDelay;
|
|
|
|
|
(void) Bank;
|
|
|
|
|
(void) CardType;
|
|
|
|
|
|
|
|
|
|
#ifdef XPAR_PSU_SD_0_DEVICE_ID
|
|
|
|
|
if (DeviceId == 0U) {
|
|
|
|
|
/* Program the OTAPDLY */
|
|
|
|
|
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
|
|
|
|
|
TapDelay |= SD0_OTAPDLYENA;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
|
|
|
|
|
TapDelay |= SD0_OTAPDLYSEL_SD50;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
|
|
|
|
|
} else {
|
|
|
|
|
#endif
|
|
|
|
|
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
|
|
|
|
|
TapDelay |= SD1_OTAPDLYENA;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
|
|
|
|
|
TapDelay |= SD1_OTAPDLYSEL_SD50;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
|
|
|
|
|
#ifdef XPAR_PSU_SD_0_DEVICE_ID
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************/
|
|
|
|
|
/**
|
|
|
|
|
*
|
|
|
|
|
* API to set Tap Delay for DDR50 mode
|
|
|
|
|
*
|
|
|
|
|
*
|
|
|
|
|
* @param InstancePtr is a pointer to the XSdPs instance.
|
|
|
|
|
*
|
|
|
|
|
* @return None
|
|
|
|
|
*
|
|
|
|
|
* @note None.
|
|
|
|
|
*
|
|
|
|
|
******************************************************************************/
|
|
|
|
|
void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
|
|
|
|
|
{
|
|
|
|
|
u32 TapDelay;
|
|
|
|
|
(void) Bank;
|
|
|
|
|
|
|
|
|
|
#ifdef XPAR_PSU_SD_0_DEVICE_ID
|
|
|
|
|
if (DeviceId == 0U) {
|
|
|
|
|
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
|
|
|
|
|
TapDelay |= SD0_ITAPCHGWIN;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
|
|
|
|
|
/* Program the ITAPDLY */
|
|
|
|
|
TapDelay |= SD0_ITAPDLYENA;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
|
|
|
|
|
if (CardType== XSDPS_CARD_SD)
|
|
|
|
|
TapDelay |= SD0_ITAPDLYSEL_SD_DDR50;
|
|
|
|
|
else
|
|
|
|
|
TapDelay |= SD0_ITAPDLYSEL_EMMC_DDR50;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
|
|
|
|
|
TapDelay &= ~SD0_ITAPCHGWIN;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
|
|
|
|
|
/* Program the OTAPDLY */
|
|
|
|
|
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
|
|
|
|
|
TapDelay |= SD0_OTAPDLYENA;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
|
|
|
|
|
if (CardType == XSDPS_CARD_SD)
|
|
|
|
|
TapDelay |= SD0_OTAPDLYSEL_SD_DDR50;
|
|
|
|
|
else
|
|
|
|
|
TapDelay |= SD0_OTAPDLYSEL_EMMC_DDR50;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
|
|
|
|
|
} else {
|
|
|
|
|
#endif
|
|
|
|
|
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
|
|
|
|
|
TapDelay |= SD1_ITAPCHGWIN;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
|
|
|
|
|
/* Program the ITAPDLY */
|
|
|
|
|
TapDelay |= SD1_ITAPDLYENA;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
|
|
|
|
|
if (CardType == XSDPS_CARD_SD)
|
|
|
|
|
TapDelay |= SD1_ITAPDLYSEL_SD_DDR50;
|
|
|
|
|
else
|
|
|
|
|
TapDelay |= SD1_ITAPDLYSEL_EMMC_DDR50;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
|
|
|
|
|
TapDelay &= ~SD1_ITAPCHGWIN;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
|
|
|
|
|
/* Program the OTAPDLY */
|
|
|
|
|
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
|
|
|
|
|
TapDelay |= SD1_OTAPDLYENA;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
|
|
|
|
|
if (CardType == XSDPS_CARD_SD)
|
|
|
|
|
TapDelay |= SD1_OTAPDLYSEL_SD_DDR50;
|
|
|
|
|
else
|
|
|
|
|
TapDelay |= SD1_OTAPDLYSEL_EMMC_DDR50;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
|
|
|
|
|
#ifdef XPAR_PSU_SD_0_DEVICE_ID
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************/
|
|
|
|
|
/**
|
|
|
|
|
*
|
|
|
|
|
* API to set Tap Delay for HSD and SDR25 mode
|
|
|
|
|
*
|
|
|
|
|
*
|
|
|
|
|
* @param InstancePtr is a pointer to the XSdPs instance.
|
|
|
|
|
*
|
|
|
|
|
* @return None
|
|
|
|
|
*
|
|
|
|
|
* @note None.
|
|
|
|
|
*
|
|
|
|
|
******************************************************************************/
|
|
|
|
|
void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
|
|
|
|
|
{
|
|
|
|
|
u32 TapDelay;
|
|
|
|
|
(void) Bank;
|
|
|
|
|
|
|
|
|
|
#ifdef XPAR_PSU_SD_0_DEVICE_ID
|
|
|
|
|
if (DeviceId == 0U) {
|
|
|
|
|
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
|
|
|
|
|
TapDelay |= SD0_ITAPCHGWIN;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
|
|
|
|
|
/* Program the ITAPDLY */
|
|
|
|
|
TapDelay |= SD0_ITAPDLYENA;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
|
|
|
|
|
TapDelay |= SD0_ITAPDLYSEL_HSD;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
|
|
|
|
|
TapDelay &= ~SD0_ITAPCHGWIN;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
|
|
|
|
|
/* Program the OTAPDLY */
|
|
|
|
|
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
|
|
|
|
|
TapDelay |= SD0_OTAPDLYENA;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
|
|
|
|
|
if (CardType == XSDPS_CARD_SD)
|
|
|
|
|
TapDelay |= SD0_OTAPDLYSEL_SD_HSD;
|
|
|
|
|
else
|
|
|
|
|
TapDelay |= SD0_OTAPDLYSEL_EMMC_HSD;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
|
|
|
|
|
} else {
|
|
|
|
|
#endif
|
|
|
|
|
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
|
|
|
|
|
TapDelay |= SD1_ITAPCHGWIN;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
|
|
|
|
|
/* Program the ITAPDLY */
|
|
|
|
|
TapDelay |= SD1_ITAPDLYENA;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
|
|
|
|
|
TapDelay |= SD1_ITAPDLYSEL_HSD;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
|
|
|
|
|
TapDelay &= ~SD1_ITAPCHGWIN;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
|
|
|
|
|
/* Program the OTAPDLY */
|
|
|
|
|
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
|
|
|
|
|
TapDelay |= SD1_OTAPDLYENA;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
|
|
|
|
|
if (CardType == XSDPS_CARD_SD)
|
|
|
|
|
TapDelay |= SD1_OTAPDLYSEL_SD_HSD;
|
|
|
|
|
else
|
|
|
|
|
TapDelay |= SD1_OTAPDLYSEL_EMMC_HSD;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
|
|
|
|
|
#ifdef XPAR_PSU_SD_0_DEVICE_ID
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************/
|
|
|
|
|
/**
|
|
|
|
|
*
|
|
|
|
|
@ -1123,30 +1427,91 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
|
|
|
|
|
******************************************************************************/
|
|
|
|
|
void XSdPs_SetTapDelay(XSdPs *InstancePtr)
|
|
|
|
|
{
|
|
|
|
|
u32 DllCtrl, TapDelay;
|
|
|
|
|
if (InstancePtr->Config.DeviceId == XPAR_XSDPS_0_DEVICE_ID) {
|
|
|
|
|
u32 DllCtrl, BankNum, DeviceId, CardType;
|
|
|
|
|
|
|
|
|
|
BankNum = InstancePtr->Config.BankNumber;
|
|
|
|
|
DeviceId = InstancePtr->Config.DeviceId ;
|
|
|
|
|
CardType = InstancePtr->CardType ;
|
|
|
|
|
#ifdef XPAR_PSU_SD_0_DEVICE_ID
|
|
|
|
|
if (DeviceId == 0U) {
|
|
|
|
|
DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
|
|
|
|
|
DllCtrl |= SD0_DLL_RST;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
|
|
|
|
|
if(InstancePtr->BusSpeed == XSDPS_MMC_HS200_MAX_CLK) {
|
|
|
|
|
/* Program the ITAPDLY */
|
|
|
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TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
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TapDelay |= SD0_ITAPCHGWIN;
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XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
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TapDelay |= SD0_ITAPDLYENA;
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XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
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TapDelay &= ~SD0_ITAPCHGWIN;
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XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
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/* Program the OTAPDLY */
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TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLYSEL);
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TapDelay |= SD0_OTAPDLYENA;
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XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLYSEL, TapDelay);
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TapDelay |= SD0_OTAPDLYSEL_HS200;
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XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLYSEL, TapDelay);
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}
|
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|
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InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
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|
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DllCtrl &= ~SD0_DLL_RST;
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|
|
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XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
|
|
|
|
|
} else {
|
|
|
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|
#endif
|
|
|
|
|
DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
|
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|
|
|
DllCtrl |= SD1_DLL_RST;
|
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|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
|
|
|
|
|
InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
|
|
|
|
|
DllCtrl &= ~SD1_DLL_RST;
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
|
|
|
|
|
#ifdef XPAR_PSU_SD_0_DEVICE_ID
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************/
|
|
|
|
|
/**
|
|
|
|
|
*
|
|
|
|
|
* API to reset the DLL
|
|
|
|
|
*
|
|
|
|
|
*
|
|
|
|
|
* @param InstancePtr is a pointer to the XSdPs instance.
|
|
|
|
|
*
|
|
|
|
|
* @return None
|
|
|
|
|
*
|
|
|
|
|
* @note None.
|
|
|
|
|
*
|
|
|
|
|
******************************************************************************/
|
|
|
|
|
static void XSdPs_DllReset(XSdPs *InstancePtr)
|
|
|
|
|
{
|
|
|
|
|
u32 ClockReg, DllCtrl;
|
|
|
|
|
|
|
|
|
|
/* Disable clock */
|
|
|
|
|
ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
|
|
|
|
XSDPS_CLK_CTRL_OFFSET);
|
|
|
|
|
ClockReg &= ~XSDPS_CC_SD_CLK_EN_MASK;
|
|
|
|
|
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
|
|
|
|
|
XSDPS_CLK_CTRL_OFFSET, ClockReg);
|
|
|
|
|
|
|
|
|
|
/* Issue DLL Reset to load zero tap values */
|
|
|
|
|
DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
|
|
|
|
|
if (InstancePtr->Config.DeviceId == 0U) {
|
|
|
|
|
DllCtrl |= SD0_DLL_RST;
|
|
|
|
|
} else {
|
|
|
|
|
DllCtrl |= SD1_DLL_RST;
|
|
|
|
|
}
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
|
|
|
|
|
|
|
|
|
|
/* Wait for 2 micro seconds */
|
|
|
|
|
(void)usleep(2U);
|
|
|
|
|
|
|
|
|
|
/* Release the DLL out of reset */
|
|
|
|
|
DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
|
|
|
|
|
if (InstancePtr->Config.DeviceId == 0U) {
|
|
|
|
|
DllCtrl &= ~SD0_DLL_RST;
|
|
|
|
|
} else {
|
|
|
|
|
DllCtrl &= ~SD1_DLL_RST;
|
|
|
|
|
}
|
|
|
|
|
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
|
|
|
|
|
|
|
|
|
|
/* Wait for internal clock to stabilize */
|
|
|
|
|
ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
|
|
|
|
XSDPS_CLK_CTRL_OFFSET);
|
|
|
|
|
while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
|
|
|
|
|
ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
|
|
|
|
XSDPS_CLK_CTRL_OFFSET);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Enable SD clock */
|
|
|
|
|
ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
|
|
|
|
XSDPS_CLK_CTRL_OFFSET);
|
|
|
|
|
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
|
|
|
|
|
XSDPS_CLK_CTRL_OFFSET,
|
|
|
|
|
ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
/** @} */
|
Richard Barry
8 years ago