e2af102c80
Re-org of RISC-V file structure and naming step 2.
6 years ago
818eeccc0c
Re-org of RISC-V file structure and naming step 1.
6 years ago
3474e750fa
Create folder to hold RISC-V chip specific extensions.
6 years ago
db750d0c82
Update RSIC-V port layer after testing saving and receiving of chip specific registers.
6 years ago
60b133b2c6
Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.
6 years ago
911a1de273
Correct accidental deletion in GenQTest.c.
6 years ago
d369110167
Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings.
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Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.
6 years ago
178fe4f143
Update the Freedom Studio RISC-V project so the gdbinit options are now specified on the command line.
6 years ago
e5daf23d75
Update Freedom Studio RISC-V demo for the latest GCC RISC-V port - not yet tested.
6 years ago
80f6f3e59b
Retarget Softconsole RISC-V demo from IGLOO2 to Renode as it can have more RAM and therefore have more test tasks running.
6 years ago
ce36928ea8
Rename directories in the RISC-V port.
6 years ago
2181c0375e
Backup Microsemi Renode project before adding a build configuration for the target hardware.
6 years ago
8d213b42f2
Add vTimerSetReloadMode() calls to the code coverage tests.
6 years ago
6edabbe7ea
Update the the MPU simulator project to exercise the timer API.
6 years ago
148f588f56
Remove "FromISR' functions from the list of functions that switch to a privileged mode as IRQs are privileged already.
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Add the vTimerSetReloadMode() API function.
6 years ago
8285ca6b5f
Update RISC-V_IGLOO2_Creative_SoftConsole demo to make use of new RISC-V porting layer structure and exercise some external interrupts - all tests currently passing in Renode.
6 years ago
101806906d
Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT.
6 years ago
7cc42b2ab6
Save changes to the RISC-V port layer before making changes necessary to support pulpino too:
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+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other.
+ Handle external interrupts (working with Renode emulator).
+ The _sp linker variable is now called __freertos_irq_stack_top.
6 years ago
866635d2ad
Microsemi RISC-V project:
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Reorganize project to separate Microsemi code into its own directory.
Add many more demo and tests.
6 years ago
6b37800ade
Backup checkin of MiFive demo running in ReNode emulator.
6 years ago
9a136a52df
Backup check in of the Microsemi IGLOO2 Creative Board RISC-V demo - still a work in progress.
6 years ago
4b9dd38d1c
Backup checking of the Freedom Studio RISC-V project - still a work in progress.
6 years ago
65f7a2dc19
Update RISC-V port to use a separate interrupt stack.
6 years ago
e85ea96f78
Some efficiency improvements in Risc-V port.
6 years ago
dc99300fa9
First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo.
6 years ago
d0ef322b13
Add kernel code to the RISC-V-Qemu-sifive_e-FreedomStudio demo.
6 years ago
f7102f2342
Add a starting point for a Freedom Studio Risc V project.
6 years ago
db64297487
Provide each Risc V task with an initial mstatus register value.
6 years ago
8cef339aec
Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress.
6 years ago
baee711cb6
Continue work on Risc V port.
6 years ago
74d0d16aab
Update xTaskRemoveFromEventList() so when tickless idle is used prvResetNextTaskUnblockTime() only gets called if the scheduler is not locked, as it would get called when the scheduler is unlocked in any case.
6 years ago
55ff89373a
Update the method used to detect if a timer is active. Previously the timer was deemed to be inactive if it was not referenced from a list. However, when a timer is updated it is temporarily removed from, then re-added to a list, so now the timer's active status is stored separately.
6 years ago
6fab2b9e0d
Add xTaskGetApplicationTaskTagFromISR(), which is an interrupt safe version of xTaskGetApplicationTaskTagFrom().
6 years ago
1af80854e6
Fix Xtensa project file and some documentation improvements.
6 years ago
c6de0001fa
Added uxTaskGetStackHighWaterMark2(), which is the same as uxTaskGetStackHighWaterMark() other than the return type.
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Allows the task name parameter passed into xTaskCreate() to be NULL.
6 years ago
e3dc5e934b
RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet.
6 years ago
2bcb1ab02b
Add trap handler to RISC-V port so there is no dependency on third party code.
6 years ago
32f35e9130
RISC-V:
...
Added code to setup the timer interrupt - not tested yet.
Added the taskYIELD() implementation - so far just checked it generates an interrupt.
6 years ago
b11eb3a59c
RISC-V work in progress:
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+ Initialise task stack.
+ Successfully jump to start of first task.
6 years ago
0c0f0d0f8f
Minor synching - no functional changes.
6 years ago
ab49c6ae04
Very minor formatting changes, and remove legacy link to V8 upgrade information.
6 years ago
92ae8e7aff
Update version numbers ready for release.
6 years ago
1a235efd2b
Update trace configuration files for the updated trace recorder code.
6 years ago
be9c0730c3
Update trace recorder code to the latest.
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Some minor changes to enable the configREMOVE_STATIC_QUALIFIER constant to be used by those debuggers that cannot cope with statics being used.
6 years ago
21a8ff35dd
Two minor updates in the comments to fix html formatting that was preventing doxygen creating documents correctly.
7 years ago
97a686b2e1
Fix mixed tabs and spaces in the latest TCP patches.
7 years ago
e2750cd388
Case unused return values for memset and memcpy to void in stream_buffer.c to avoid compiler warnings when the warning level is turned up.
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Remove duplicate comment in heap_1.c.
7 years ago
0d6e3df7ec
Minor updates to fix issues with the Segger kernel aware plug since V10.1.0.
7 years ago
9bda04b472
Fix build issues in the FreeRTOS_Plus_TCP_Minimal_Windows_Simulator project:
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+ Set configENABLE_BACKWARD_COMPATIBILITY to 1 in FreeRTOSConfig.h to account for the fact that a member of the List_t structure has been renamed.
+ Provide a dummy implementation of ulApplicationGetNextSequenceNumber() to prevent linker warnings.
7 years ago
893db45834
Changes required for the IAR StateViewer plug-in to work with FreeRTOS V10.1.0.
7 years ago
Richard Barry
Gaurav Aggarwal