Re-org of RISC-V file structure and naming step 2.
Richard Barry
6 years ago
parent
818eeccc0c
commit
e2af102c80
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
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*
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* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
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* is common to all currently supported RISC-V chips. There is only one
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* portASM.S file because the same file is built for all RISC-V target chips.
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*
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* + Header files called freertos_risc_v_chip_specific_extensions.h contain the
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* code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
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* chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
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* as there are multiple RISC-V chip implementations.
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*
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* !!!NOTE!!!
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* CARE MUST BE TAKEN TO INCLUDE THE CORRECT
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* freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP IN USE.
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* If the chip in use includes a core local interrupter (CLINT) and does not
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* include any chip specific register extensions then set the GNU assembler's
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* include path such that the header file contained in the
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32 directory is the header file that is
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* actually inlcuded. Otherwise set the assembler's include patch to the
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* sub-directory off of the
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions directory
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* that contains the freertos_risc_v_chip_specific_extensions.h specific to the
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* target chip.
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*
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*/
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@ -1,27 +1,28 @@
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
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*
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* + The code that is common to all RISC-V chips is implemented in
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
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* portASM.S file because the same file is used no matter which RISC-V chip is
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* in use.
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* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
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* is common to all currently supported RISC-V chips. There is only one
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* portASM.S file because the same file is built for all RISC-V target chips.
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*
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* + The code that tailors the kernel's RISC-V port to a specific RISC-V
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* chip is implemented in freertos_risc_v_port_specific_extensions.h. There
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* is one freertos_risc_v_port_specific_extensions.h that can be used with any
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* RISC-V chip that both includes a standard CLINT and does not add to the
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* base set of RISC-V registers. There are additional
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* freertos_risc_v_port_specific_extensions.h files for RISC-V implementations
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* that do not include a standard CLINT or do add to the base set of RISC-V
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* registers.
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* + Header files called freertos_risc_v_chip_specific_extensions.h contain the
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* code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
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* chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
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* as there are multiple RISC-V chip implementations.
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*
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* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
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* freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP
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* IN USE. To include the correct freertos_risc_v_port_specific_extensions.h
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* header file ensure the path to the correct header file is in the assembler's
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* include path.
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* !!!NOTE!!!
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* CARE MUST BE TAKEN TO INCLUDE THE CORRECT
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* freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP IN USE.
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* If the chip in use includes a core local interrupter (CLINT) and does not
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* include any chip specific register extensions then set the GNU assembler's
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* include path such that the header file contained in the
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32 directory is the header file that is
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* actually inlcuded. Otherwise set the assembler's include patch to the
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* sub-directory off of the
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions directory
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* that contains the freertos_risc_v_chip_specific_extensions.h specific to the
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* target chip.
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*
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* This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips
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* that include a standard CLINT and do not add to the base set of RISC-V
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* registers.
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*/
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