c07f60c383
Adding GCC/Keil/IAR projects for NXP LPC51U68 (CM0+).
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Please see readme.txt for todo items.
5 years ago
9c0e3fe9f1
Cortex M0 GCC/IAR/Keil ports -- tickless support.
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The default portMISSED_COUNTS_FACTOR is set to 45 cycles. User could override this value, if a more accurate count is available.
5 years ago
3cde02a046
RVDS/Keil weak linkage for vPortSetupTimerInterrupt() -- CM4F, CM3
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Test steps are documented in this PR https://github.com/aws/amazon-freertos/pull/1141 .
5 years ago
d58e6a7b09
Use linker script variables for MPU setup for Nuvoton M2351 Keil Project
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Earlier we were using hard-coded addresses for MPU setup which
were ensured to be the same as linker script setup. This change
updates the Keil uVision project for Nuvoton Numaker-PFM-M2351
to use the variables exported from the linker script. This ensures
that the MPU setup never goes out of sync with linker script.
5 years ago
d449c8979d
Use the linker script variables for MPU setup for Keil Simulator Demo
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Earlier we were using hard-coded addresses for MPU setup which
were ensured to be the same as linker script setup. This change
updates the Keil Simulator demo to use the variables exported
from the linker script. This ensures that the MPU setup does not
go out of sync with linker script.
5 years ago
66ce9f7d72
Move warning suppression for IAR compiler to portmacro.h for v8M ports
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IAR produces some warnings which can not be fixed in the source code because
then other compilers start generating warnings. We suppressed those warnings
in the project file before. This change moves the warning suppression from
project files to portmacro.h.
5 years ago
1deeb6dd84
Check socket binding result before doing anything with socket. (This is to address ARG findings.) Breaking the single return rule here, due to precedent violation at line 1039 and 1144.
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prvTransferConnect() now returns:
- pdTRUE: everything's good. pdTRUE = 1.
- -pdFREERTOS_ERRNO_ENOMEM: FreeRTOS_socket() failed. -pdFREERTOS_ERRNO_ENOMEM = -12.
- -pdFREERTOS_ERRNO_EINVAL || -pdFREERTOS_ERRNO_ECANCELED: FreeRTOS_bind() failed. Negative values.
Thus, at line 569 and line 617, needs to check != pdTRUE instead of == pdFALSE.
This commit is done on behalf of Alfred.
5 years ago
9491af1fd7
Fix bug when xQueueOverwrite() and xQueueOverwrite() from ISR are used to overwrite items in two queues that are part of the same set.
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Minor queue optimisations.
5 years ago
e5708b38e9
Add the Labs projects provided in the V10.2.1_191129 zip file.
5 years ago
46e5937529
Remove guards against __ARMCC_VERSION version numbers that were previously used to avoid compiler warnings in some GCC ARM Cortex ports.
5 years ago
d1fb8907ab
Add software timer to the Win32 blinky demo.
5 years ago
07622ed3ee
Remove driver files that generate compiler warnings from the RISC-V_Renode_Emulator_SoftConsole project.
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Update RISC-V ports so the interrupt stack is set to a known value before the scheduler is started if the interrupt stack is statically defined rather than re-using the main.c() stack.
5 years ago
16639d2d63
Update to the latest atomic.h.
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Improve commenting in RISC-V GCC port.
Fix IAR RISC-V port so the first task starts with interrupts enabled.
Add references to third party page ref using newlib with FreeRTOS into the tasks.c file in each place newlib is referenced.
Move the position of the traceTASK_DELETE() trace macro in case of use with a memory allocator that writes over freed memory even when inside a critical section.
Efficiency improvement: Make sure xTaskIncrementTick() does not return pdTRUE when the scheduler is locked. This just prevents an unnecessary yield interrupt (unnecessary as it is ignored) when xYieldPending happens to be pdTRUE.
5 years ago
18916d5820
Rename the RISC-V_RV32_SiFive_Hifive1_GCC folder to RISC-V_RV32_SiFive_HiFive1_FreedomStudio as it is built with Freedom Studio.
5 years ago
5306ba245d
Add nano-specs linker option to HiFive1_GCC demo.
5 years ago
c0741e36ed
Fix spelling mistakes copied and pasted into a couple of RISC-V demo main.c files.
5 years ago
fccc445865
Change version and license text in RISC-V_RV32_SiFive_HiFive1_GCC FreeRTOSConfig.h file.
5 years ago
11c391dfb3
Tidy up main_full.c and change alignment of variable accesses in RegTest.S for the RISC-V_Renode_Emulator_SoftConsole demo.
5 years ago
343fbe795f
Rework RISC-V QEMU example to use vanilla Eclipse in place of Freedom Studio. NOTE: RISC-V QEMU mtime interrupts are not generated consistently.
5 years ago
ef31243396
Add some asserts into the common demo tasks to catch scenarios where the tasks are not being used but the part of the demo/test that gets called from the tick hook is called resultant in an access to objects that were not created.
5 years ago
61a003088d
Update RISK-V GCC port to ensure the first task starts with interrupts enabled - previously its interrupts were only enabled after it yielded for the first time.
5 years ago
a83244a37e
Add the miv-basic.resc reNode script into the RISC-V_Renode_Emulator_SoftConsole demo as it is no longer shipped with the Microsemi tools.
5 years ago
c7c60cff15
Rename RISC-V-Qemu-sive_e_Freedom_Studio directory to RISC-V-Qemu-sifive_e-Eclipse-GCC as it is now using Vanilla Eclipse and vanilla GCC in place of Freedom Studio.
5 years ago
f78ccd077a
Recreate the RISC-V-Qemu demo using Vanilla Eclipse in place of Freedom Studio as there is not a new Freedom Studio project that targets the HiFive1 board, and the updated Freedom Studio version didn't work with this project any more anyway.
5 years ago
d435a7b62d
Move the call to traceTASK_DELETE() to before port portPRE_TASK_DELETE_HOOK() as in the Windows port portPRE_TASK_DELETE_HOOK() never returns.
5 years ago
4922cff4ce
Add IAR demo for the SiFive RISC-V HiFive Rev B board.
5 years ago
f6edf4adf9
Update the RegTest.S file used by several GCC RISC-V demos to ensure correct alignment of constant loads from assembly code.
5 years ago
96e61a10a5
Tidy up the RISC-V_RV32_SiFive_HiFive1_GCC demo ready for its eventual release.
5 years ago
d4216903d9
Added the "full" demo to the RISC-V_RV32_SiFive_HiFive1_GCC demo - backup check in only as still a work in progress.
5 years ago
71d9450836
RIS-V_RV32_SiFive_HiFive1_GCC project now running the blinky demo - still a work in progress.
5 years ago
dbac79045c
Formatting changes only.
5 years ago
dbbebbfcbc
RISC-V-RV32_SiFive_HiFive1_GCC project is now also building the FreeRTOS kernel code - but not using it yet - still a work in progress.
5 years ago
9bb072a2ab
Base project to replace existing Freedom Studio project using latest Freedom Studio project format - builds and executes but does not yet include RTOS code.
5 years ago
fd118f1888
Minor formatting change in comment only.
5 years ago
eb5c60c60b
Update FreeRTOS.h with the version in GitHub. This is also to test submodule.
5 years ago
0fe36e497d
Nordic port. Notes for Richard -- the work items we discussed about for nrf52840-dk and Wiced_CY still remain. The only reason for this commit is we want to test out submodule.
5 years ago
35bc9d7938
Revert 2728. Not because the files are still needed, but because we want to test out submodule.
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Before further updating project files in GitHub, keeping an additional copy.
5 years ago
f001126ea8
Wiced_CY port is not needed anymore. Use GCC/ARM_CRx_No_GIC instead.
5 years ago
9052882500
Adding tickless hooks to GCC/ARM_CRx_No_GIC port.
5 years ago
80c1cb5de1
Correct code comments that referred to taskYIELD_FROM_ISR to portYIELD_FROM_ISR.
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Update RV32 port to use 16 byte-alignment all the time (only strictly necessary when using FLOP instructions).
5 years ago
c217b68d38
sync from github to svn: this version of atomic.h does not have compiler specific symbols. compiler specific optimization is to be merged in each port/<compiler>/<arch> directory.
5 years ago
6f958bbf80
sync from github to svn: Xtensa GCC as-is.
5 years ago
1c5fcc7f05
sync from github to svn: Wiced_CY for AFR Cypress ports.
5 years ago
74df636c78
sync from github to svn: documentation for RISC-V. This may be a temporary parking location.
5 years ago
cc0aee651e
sync from github to svn: Renasas/RX100 #pragma _VECT()
5 years ago
da3d370ff7
RISC-V port updates: The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores.
5 years ago
96bad0f6c3
Minor bug fix in NTPDemo.c -> use of FREERTOS_INVALID_SOCKET in place of NULL.
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Update trace recorder code to account for uxPendedTicks renaming to xPendedTicks.
5 years ago
ab41d89285
Add IAR RISC-V port to SVN - a work in progress.
5 years ago
2b546b1984
Atollic project update for CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC, GCC port.
6 years ago
973a4f9869
Correct alignment of stack top in RISC-V port when configISR_STACK_SIZE_WORDS is defined to a non zero value.
6 years ago
Yuhui.Zheng
Gaurav Aggarwal
Richard Barry
Yuhui Zheng