RISC-V port updates: The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores.
Richard Barry
5 years ago
parent
96bad0f6c3
commit
da3d370ff7
@ -1,109 +0,0 @@
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/*
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* FreeRTOS Kernel V10.2.1
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* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and t
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o permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
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*
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* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
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* is common to all currently supported RISC-V chips. There is only one
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* portASM.S file because the same file is built for all RISC-V target chips.
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*
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* + Header files called freertos_risc_v_chip_specific_extensions.h contain the
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* code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
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* chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
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* as there are multiple RISC-V chip implementations.
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*
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* !!!NOTE!!!
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* TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
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* HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
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* compiler's!) include path. For example, if the chip in use includes a core
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* local interrupter (CLINT) and does not include any chip specific register
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* extensions then add the path below to the assembler's include path:
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
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*
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*/
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/*
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* This freertos_risc_v_chip_specific_extensions.h is for use with Pulpino Ri5cy
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* devices, developed and tested using the Vega board RV32M1RM.
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*/
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#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
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#define __FREERTOS_RISC_V_EXTENSIONS_H__
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#define portasmHAS_CLINT 0
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/* Constants to define the additional registers found on the Pulpino RI5KY. */
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#define lpstart0 0x7b0
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#define lpend0 0x7b1
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#define lpcount0 0x7b2
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#define lpstart1 0x7b4
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#define lpend1 0x7b5
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#define lpcount1 0x7b6
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/* Six additional registers to save and restore, as per the #defines above. */
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#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */
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/* Save additional registers found on the Pulpino. */
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.macro portasmSAVE_ADDITIONAL_REGISTERS
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addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */
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csrr t0, lpstart0 /* Load additional registers into accessible temporary registers. */
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csrr t1, lpend0
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csrr t2, lpcount0
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csrr t3, lpstart1
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csrr t4, lpend1
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csrr t5, lpcount1
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sw t0, 1 * portWORD_SIZE( sp )
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sw t1, 2 * portWORD_SIZE( sp )
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sw t2, 3 * portWORD_SIZE( sp )
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sw t3, 4 * portWORD_SIZE( sp )
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sw t4, 5 * portWORD_SIZE( sp )
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sw t5, 6 * portWORD_SIZE( sp )
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.endm
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/* Restore the additional registers found on the Pulpino. */
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.macro portasmRESTORE_ADDITIONAL_REGISTERS
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lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */
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lw t1, 2 * portWORD_SIZE( sp )
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lw t2, 3 * portWORD_SIZE( sp )
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lw t3, 4 * portWORD_SIZE( sp )
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lw t4, 5 * portWORD_SIZE( sp )
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lw t5, 6 * portWORD_SIZE( sp )
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csrw lpstart0, t0
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csrw lpend0, t1
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csrw lpcount0, t2
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csrw lpstart1, t3
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csrw lpend1, t4
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csrw lpcount1, t5
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addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */
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.endm
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#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
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