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@ -1,5 +1,5 @@
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/*
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FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd.
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FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd.
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All rights reserved
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VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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@ -96,7 +96,7 @@ volatile uint32_t ulCriticalNesting = 9999UL;
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/* ISR to handle manual context switches (from a call to taskYIELD()). */
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void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
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/*
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/*
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* The scheduler can only be started from ARM mode, hence the inclusion of this
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* function here.
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*/
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@ -114,17 +114,17 @@ void vPortISRStartFirstTask( void )
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/*
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* Called by portYIELD() or taskYIELD() to manually force a context switch.
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*
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* When a context switch is performed from the task level the saved task
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* When a context switch is performed from the task level the saved task
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* context is made to look as if it occurred from within the tick ISR. This
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* way the same restore context function can be used when restoring the context
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* saved from the ISR or that saved from a call to vPortYieldProcessor.
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*/
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void vPortYieldProcessor( void )
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{
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/* Within an IRQ ISR the link register has an offset from the true return
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address, but an SWI ISR does not. Add the offset manually so the same
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/* Within an IRQ ISR the link register has an offset from the true return
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address, but an SWI ISR does not. Add the offset manually so the same
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ISR return code can be used in both cases. */
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asm volatile ( "ADD LR, LR, #4" );
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__asm volatile ( "ADD LR, LR, #4" );
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/* Perform the context switch. First save the context of the current task. */
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portSAVE_CONTEXT();
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@ -133,32 +133,32 @@ void vPortYieldProcessor( void )
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vTaskSwitchContext();
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/* Restore the context of the new task. */
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portRESTORE_CONTEXT();
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portRESTORE_CONTEXT();
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}
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/*-----------------------------------------------------------*/
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/*
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/*
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* The ISR used for the scheduler tick depends on whether the cooperative or
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* the preemptive scheduler is being used.
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*/
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#if configUSE_PREEMPTION == 0
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/* The cooperative scheduler requires a normal IRQ service routine to
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/* The cooperative scheduler requires a normal IRQ service routine to
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simply increment the system tick. */
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void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
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void vNonPreemptiveTick( void )
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{
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{
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uint32_t ulDummy;
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/* Increment the tick count - which may wake some tasks but as the
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preemptive scheduler is not being used any woken task is not given
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processor time no matter what its priority. */
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xTaskIncrementTick();
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/* Clear the PIT interrupt. */
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ulDummy = AT91C_BASE_PITC->PITC_PIVR;
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/* End the interrupt in the AIC. */
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AT91C_BASE_AIC->AIC_EOICR = ulDummy;
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}
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@ -171,7 +171,7 @@ void vPortYieldProcessor( void )
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void vPreemptiveTick( void )
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{
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/* Save the context of the current task. */
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portSAVE_CONTEXT();
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portSAVE_CONTEXT();
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/* Increment the tick count - this may wake a task. */
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if( xTaskIncrementTick() != pdFALSE )
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@ -179,10 +179,10 @@ void vPortYieldProcessor( void )
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/* Find the highest priority task that is ready to run. */
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vTaskSwitchContext();
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}
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/* End the interrupt in the AIC. */
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AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;;
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portRESTORE_CONTEXT();
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}
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@ -200,7 +200,7 @@ void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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void vPortDisableInterruptsFromThumb( void )
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{
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asm volatile (
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__asm volatile (
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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@ -208,14 +208,14 @@ void vPortDisableInterruptsFromThumb( void )
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"LDMIA SP!, {R0} \n\t" /* Pop R0. */
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"BX R14" ); /* Return back to thumb. */
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}
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void vPortEnableInterruptsFromThumb( void )
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{
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asm volatile (
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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__asm volatile (
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0} \n\t" /* Pop R0. */
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"BX R14" ); /* Return back to thumb. */
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}
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@ -228,14 +228,14 @@ in a variable, which is then saved as part of the stack context. */
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void vPortEnterCritical( void )
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{
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/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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asm volatile (
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__asm volatile (
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0}" ); /* Pop R0. */
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/* Now interrupts are disabled ulCriticalNesting can be accessed
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/* Now interrupts are disabled ulCriticalNesting can be accessed
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directly. Increment ulCriticalNesting to keep a count of how many times
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portENTER_CRITICAL() has been called. */
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ulCriticalNesting++;
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@ -253,11 +253,11 @@ void vPortExitCritical( void )
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if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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{
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/* Enable interrupts as per portEXIT_CRITICAL(). */
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asm volatile (
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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__asm volatile (
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0}" ); /* Pop R0. */
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}
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}
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Richard Barry
11 years ago