Demo project only: Cyclone V SoC now running from external RAM.

FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.cproject

@@ -41,7 +41,7 @@
 							</tool>
 							<tool id="cdt.managedbuild.tool.gnu.cross.c.linker.451869963" name="Cross GCC Linker" superClass="cdt.managedbuild.tool.gnu.cross.c.linker">
 								<option id="gnu.c.link.option.other.1746198439" name="Other options (-Xlinker [option])" superClass="gnu.c.link.option.other" valueType="stringList">
-									<listOptionValue builtIn="false" value="-TcycloneV-dk-oc-ram.ld"/>
+									<listOptionValue builtIn="false" value="-TcycloneV-dk-ram.ld"/>
 									<listOptionValue builtIn="false" value="--defsym=__cs3_isr_irq=FreeRTOS_IRQ_Handler"/>
 									<listOptionValue builtIn="false" value="--defsym=__cs3_isr_swi=FreeRTOS_SWI_Handler"/>
 									<listOptionValue builtIn="false" value="-Map=RTOSDemo.map"/>

FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main.c

@@ -29,9 +29,21 @@ int main( void )
 
 static void prvSetupHardware( void )
 {
+extern uint8_t __cs3_interrupt_vector;
+uint32_t ulSCTLR, ulVectorTable = ( uint32_t ) &__cs3_interrupt_vector;
+const uint32_t ulVBit = 13U;
+
 	alt_int_global_init();
+
+	/* Clear SCTLR.V for low vectors and map the vector table to the beginning
+	of the code. */
+	__asm( "MRC p15, 0, %0, c1, c0, 0" : "=r" ( ulSCTLR ) );
+	ulSCTLR &= ~( 1 << ulVBit );
+	__asm( "MCR p15, 0, %0, c1, c0, 0" : : "r" ( ulSCTLR ) );
+	__asm( "MCR p15, 0, %0, c12, c0, 0" : : "r" ( ulVectorTable ) );
+
 	cache_init();
-	//_RB_mmu_init();
+	mmu_init();
 }
 /*-----------------------------------------------------------*/