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Added project for Altera Cyclone V SoC, currently running from internal RAM.

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pull/4/head
Richard Barry 10 years ago
parent 3b0854bf96
commit e2f2cfa816
108 changed files with 431276 additions and 0 deletions
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89
FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.cproject
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FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.project
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FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_16550_uart.c
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FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_address_space.c
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/******************************************************************************
*
* alt_address_space.c - API for the Altera SoC FPGA address space.
*
******************************************************************************/
/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#include <stddef.h>
#include "alt_address_space.h"
#include "socal/alt_l3.h"
#include "socal/socal.h"
#include "socal/alt_acpidmap.h"
#include "hwlib.h"
#define ALT_ACP_ID_MAX_INPUT_ID 7
#define ALT_ACP_ID_MAX_OUTPUT_ID 4096
/******************************************************************************/
ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr,
ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr,
ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_bridge_attr,
ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_bridge_attr)
{
uint32_t remap_reg_val = 0;
// Parameter checking and validation...
if (mpu_attr == ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM)
{
remap_reg_val |= ALT_L3_REMAP_MPUZERO_SET(ALT_L3_REMAP_MPUZERO_E_BOOTROM);
}
else if (mpu_attr == ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM)
{
remap_reg_val |= ALT_L3_REMAP_MPUZERO_SET(ALT_L3_REMAP_MPUZERO_E_OCRAM);
}
else
{
return ALT_E_INV_OPTION;
}
if (nonmpu_attr == ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM)
{
remap_reg_val |= ALT_L3_REMAP_NONMPUZERO_SET(ALT_L3_REMAP_NONMPUZERO_E_SDRAM);
}
else if (nonmpu_attr == ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM)
{
remap_reg_val |= ALT_L3_REMAP_NONMPUZERO_SET(ALT_L3_REMAP_NONMPUZERO_E_OCRAM);
}
else
{
return ALT_E_INV_OPTION;
}
if (h2f_bridge_attr == ALT_ADDR_SPACE_H2F_INACCESSIBLE)
{
remap_reg_val |= ALT_L3_REMAP_H2F_SET(ALT_L3_REMAP_H2F_E_INVISIBLE);
}
else if (h2f_bridge_attr == ALT_ADDR_SPACE_H2F_ACCESSIBLE)
{
remap_reg_val |= ALT_L3_REMAP_H2F_SET(ALT_L3_REMAP_H2F_E_VISIBLE);
}
else
{
return ALT_E_INV_OPTION;
}
if (lwh2f_bridge_attr == ALT_ADDR_SPACE_LWH2F_INACCESSIBLE)
{
remap_reg_val |= ALT_L3_REMAP_LWH2F_SET(ALT_L3_REMAP_LWH2F_E_INVISIBLE);
}
else if (lwh2f_bridge_attr == ALT_ADDR_SPACE_LWH2F_ACCESSIBLE)
{
remap_reg_val |= ALT_L3_REMAP_LWH2F_SET(ALT_L3_REMAP_LWH2F_E_VISIBLE);
}
else
{
return ALT_E_INV_OPTION;
}
// Perform the remap.
alt_write_word(ALT_L3_REMAP_ADDR, remap_reg_val);
return ALT_E_SUCCESS;
}
/******************************************************************************/
// Remap the MPU address space view of address 0 to access the SDRAM controller.
// This is done by setting the L2 cache address filtering register start address
// to 0 and leaving the address filtering address end address value
// unmodified. This causes all physical addresses in the range
// address_filter_start <= physical_address < address_filter_end to be directed
// to the to the AXI Master Port M1 which is connected to the SDRAM
// controller. All other addresses are directed to AXI Master Port M0 which
// connect the MPU subsystem to the L3 interconnect.
//
// It is unnecessary to modify the MPU remap options in the L3 remap register
// because those options only affect addresses in the MPU subsystem address
// ranges that are now redirected to the SDRAM controller and never reach the L3
// interconnect anyway.
ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void)
{
uint32_t addr_filt_end = (alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR) &
L2_CACHE_ADDR_FILTERING_END_ADDR_MASK);
return alt_l2_addr_filter_cfg_set(0x0, addr_filt_end);
}
/******************************************************************************/
// Return the L2 cache address filtering registers configuration settings in the
// user provided start and end address range out parameters.
ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start,
uint32_t* addr_filt_end)
{
if (addr_filt_start == NULL || addr_filt_end == NULL)
{
return ALT_E_BAD_ARG;
}
uint32_t addr_filt_start_reg = alt_read_word(L2_CACHE_ADDR_FILTERING_START_ADDR);
uint32_t addr_filt_end_reg = alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR);
*addr_filt_start = (addr_filt_start_reg & L2_CACHE_ADDR_FILTERING_START_ADDR_MASK);
*addr_filt_end = (addr_filt_end_reg & L2_CACHE_ADDR_FILTERING_END_ADDR_MASK);
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start,
uint32_t addr_filt_end)
{
// Address filtering start and end values must be 1 MB aligned.
if ( (addr_filt_start & ~L2_CACHE_ADDR_FILTERING_START_ADDR_MASK)
|| (addr_filt_end & ~L2_CACHE_ADDR_FILTERING_END_ADDR_MASK) )
{
return ALT_E_ARG_RANGE;
}
// While it is possible to set the address filtering end value above its
// reset value and thereby access a larger SDRAM address range, it is not
// recommended. Doing so would potentially obscure any mapped HPS to FPGA
// bridge address spaces and peripherals on the L3 interconnect.
if (addr_filt_end > L2_CACHE_ADDR_FILTERING_END_RESET)
{
return ALT_E_ARG_RANGE;
}
// NOTE: ARM (ARM DDI 0246F CoreLink Level 2 Cache Controller L2C-310 TRM)
// recommends programming the Address Filtering End Register before the
// Address Filtering Start Register to avoid unpredictable behavior between
// the two writes.
alt_write_word(L2_CACHE_ADDR_FILTERING_END_ADDR, addr_filt_end);
// It is recommended that address filtering always remain enabled.
addr_filt_start |= L2_CACHE_ADDR_FILTERING_ENABLE_MASK;
alt_write_word(L2_CACHE_ADDR_FILTERING_START_ADDR, addr_filt_start);
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id,
const uint32_t output_id,
const ALT_ACP_ID_MAP_PAGE_t page,
const uint32_t aruser)
{
if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
{
return ALT_E_BAD_ARG;
}
switch (output_id)
{
case ALT_ACP_ID_OUT_FIXED_ID_2:
alt_write_word(ALT_ACPIDMAP_VID2RD_ADDR,
ALT_ACPIDMAP_VID2RD_MID_SET(input_id)
| ALT_ACPIDMAP_VID2RD_PAGE_SET(page)
| ALT_ACPIDMAP_VID2RD_USER_SET(aruser)
| ALT_ACPIDMAP_VID2RD_FORCE_SET(1UL));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_3:
alt_write_word(ALT_ACPIDMAP_VID3RD_ADDR,
ALT_ACPIDMAP_VID3RD_MID_SET(input_id)
| ALT_ACPIDMAP_VID3RD_PAGE_SET(page)
| ALT_ACPIDMAP_VID3RD_USER_SET(aruser)
| ALT_ACPIDMAP_VID3RD_FORCE_SET(1UL));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_4:
alt_write_word(ALT_ACPIDMAP_VID4RD_ADDR,
ALT_ACPIDMAP_VID4RD_MID_SET(input_id)
| ALT_ACPIDMAP_VID4RD_PAGE_SET(page)
| ALT_ACPIDMAP_VID4RD_USER_SET(aruser)
| ALT_ACPIDMAP_VID4RD_FORCE_SET(1UL));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_5:
alt_write_word(ALT_ACPIDMAP_VID5RD_ADDR,
ALT_ACPIDMAP_VID5RD_MID_SET(input_id)
| ALT_ACPIDMAP_VID5RD_PAGE_SET(page)
| ALT_ACPIDMAP_VID5RD_USER_SET(aruser)
| ALT_ACPIDMAP_VID5RD_FORCE_SET(1UL));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_6:
alt_write_word(ALT_ACPIDMAP_VID6RD_ADDR,
ALT_ACPIDMAP_VID6RD_MID_SET(input_id)
| ALT_ACPIDMAP_VID6RD_PAGE_SET(page)
| ALT_ACPIDMAP_VID6RD_USER_SET(aruser)
| ALT_ACPIDMAP_VID6RD_FORCE_SET(1UL));
break;
default:
return ALT_E_BAD_ARG;
}
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id,
const uint32_t output_id,
const ALT_ACP_ID_MAP_PAGE_t page,
const uint32_t awuser)
{
if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
{
return ALT_E_BAD_ARG;
}
switch (output_id)
{
case ALT_ACP_ID_OUT_FIXED_ID_2:
alt_write_word(ALT_ACPIDMAP_VID2WR_ADDR,
ALT_ACPIDMAP_VID2WR_MID_SET(input_id)
| ALT_ACPIDMAP_VID2WR_PAGE_SET(page)
| ALT_ACPIDMAP_VID2WR_USER_SET(awuser)
| ALT_ACPIDMAP_VID2WR_FORCE_SET(1UL));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_3:
alt_write_word(ALT_ACPIDMAP_VID3WR_ADDR,
ALT_ACPIDMAP_VID3WR_MID_SET(input_id)
| ALT_ACPIDMAP_VID3WR_PAGE_SET(page)
| ALT_ACPIDMAP_VID3WR_USER_SET(awuser)
| ALT_ACPIDMAP_VID3WR_FORCE_SET(1UL));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_4:
alt_write_word(ALT_ACPIDMAP_VID4WR_ADDR,
ALT_ACPIDMAP_VID4WR_MID_SET(input_id)
| ALT_ACPIDMAP_VID4WR_PAGE_SET(page)
| ALT_ACPIDMAP_VID4WR_USER_SET(awuser)
| ALT_ACPIDMAP_VID4WR_FORCE_SET(1UL));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_5:
alt_write_word(ALT_ACPIDMAP_VID5WR_ADDR,
ALT_ACPIDMAP_VID5WR_MID_SET(input_id)
| ALT_ACPIDMAP_VID5WR_PAGE_SET(page)
| ALT_ACPIDMAP_VID5WR_USER_SET(awuser)
| ALT_ACPIDMAP_VID5WR_FORCE_SET(1UL));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_6:
alt_write_word(ALT_ACPIDMAP_VID6WR_ADDR,
ALT_ACPIDMAP_VID6WR_MID_SET(input_id)
| ALT_ACPIDMAP_VID6WR_PAGE_SET(page)
| ALT_ACPIDMAP_VID6WR_USER_SET(awuser)
| ALT_ACPIDMAP_VID6WR_FORCE_SET(1UL)
);
break;
default:
return ALT_E_BAD_ARG;
}
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id)
{
if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
{
return ALT_E_BAD_ARG;
}
uint32_t aruser, page;
switch (output_id)
{
case ALT_ACP_ID_OUT_FIXED_ID_2:
aruser = ALT_ACPIDMAP_VID2RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR));
page = ALT_ACPIDMAP_VID2RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_3:
aruser = ALT_ACPIDMAP_VID3RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR));
page = ALT_ACPIDMAP_VID3RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_4:
aruser = ALT_ACPIDMAP_VID4RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR));
page = ALT_ACPIDMAP_VID4RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_5:
aruser = ALT_ACPIDMAP_VID5RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR));
page = ALT_ACPIDMAP_VID5RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_6:
aruser = ALT_ACPIDMAP_VID6RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR));
page = ALT_ACPIDMAP_VID6RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR));
break;
default:
return ALT_E_BAD_ARG;
}
alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR,
ALT_ACPIDMAP_DYNRD_PAGE_SET(page)
| ALT_ACPIDMAP_DYNRD_USER_SET(aruser));
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id)
{
if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
{
return ALT_E_BAD_ARG;
}
uint32_t awuser, page;
switch (output_id)
{
case ALT_ACP_ID_OUT_FIXED_ID_2:
awuser = ALT_ACPIDMAP_VID2WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR));
page = ALT_ACPIDMAP_VID2WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_3:
awuser = ALT_ACPIDMAP_VID3WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR));
page = ALT_ACPIDMAP_VID3WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_4:
awuser = ALT_ACPIDMAP_VID4WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR));
page = ALT_ACPIDMAP_VID4WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_5:
awuser = ALT_ACPIDMAP_VID5WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR));
page = ALT_ACPIDMAP_VID5WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_6:
awuser = ALT_ACPIDMAP_VID6WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR));
page = ALT_ACPIDMAP_VID6WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR));
break;
default:
return ALT_E_BAD_ARG;
}
alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR,
ALT_ACPIDMAP_DYNWR_PAGE_SET(page)
| ALT_ACPIDMAP_DYNWR_USER_SET(awuser));
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
const uint32_t aruser)
{
alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR,
ALT_ACPIDMAP_DYNRD_PAGE_SET(page)
| ALT_ACPIDMAP_DYNRD_USER_SET(aruser));
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
const uint32_t awuser)
{
alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR,
ALT_ACPIDMAP_DYNWR_PAGE_SET(page)
| ALT_ACPIDMAP_DYNWR_USER_SET(awuser));
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id,
bool * fixed,
uint32_t * input_id,
ALT_ACP_ID_MAP_PAGE_t * page,
uint32_t * aruser)
{
if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
{
return ALT_E_BAD_ARG;
}
switch (output_id)
{
case ALT_ACP_ID_OUT_FIXED_ID_2:
*aruser = ALT_ACPIDMAP_VID2RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
*input_id = ALT_ACPIDMAP_VID2RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
*fixed = ALT_ACPIDMAP_VID2RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_3:
*aruser = ALT_ACPIDMAP_VID3RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
*input_id = ALT_ACPIDMAP_VID3RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
*fixed = ALT_ACPIDMAP_VID3RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_4:
*aruser = ALT_ACPIDMAP_VID4RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
*input_id = ALT_ACPIDMAP_VID4RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
*fixed = ALT_ACPIDMAP_VID4RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_5:
*aruser = ALT_ACPIDMAP_VID5RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
*input_id = ALT_ACPIDMAP_VID5RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
*fixed = ALT_ACPIDMAP_VID5RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_6:
*aruser = ALT_ACPIDMAP_VID6RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
*input_id = ALT_ACPIDMAP_VID6RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
*fixed = ALT_ACPIDMAP_VID6RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_7:
*aruser = ALT_ACPIDMAP_DYNRD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNRD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR));
break;
default:
return ALT_E_BAD_ARG;
}
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id,
bool * fixed,
uint32_t * input_id,
ALT_ACP_ID_MAP_PAGE_t * page,
uint32_t * awuser)
{
if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
{
return ALT_E_BAD_ARG;
}
switch (output_id)
{
case ALT_ACP_ID_OUT_FIXED_ID_2:
*awuser = ALT_ACPIDMAP_VID2WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
*input_id = ALT_ACPIDMAP_VID2WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
*fixed = ALT_ACPIDMAP_VID2WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_3:
*awuser = ALT_ACPIDMAP_VID3WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
*input_id = ALT_ACPIDMAP_VID3WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
*fixed = ALT_ACPIDMAP_VID3WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_4:
*awuser = ALT_ACPIDMAP_VID4WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
*input_id = ALT_ACPIDMAP_VID4WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
*fixed = ALT_ACPIDMAP_VID4WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_5:
*awuser = ALT_ACPIDMAP_VID5WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
*input_id = ALT_ACPIDMAP_VID5WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
*fixed = ALT_ACPIDMAP_VID5WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_6:
*awuser = ALT_ACPIDMAP_VID6WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
*input_id = ALT_ACPIDMAP_VID6WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
*fixed = ALT_ACPIDMAP_VID6WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_7:
*awuser = ALT_ACPIDMAP_DYNWR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNWR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR));
break;
default:
return ALT_E_BAD_ARG;
}
return ALT_E_SUCCESS;
}

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FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_bridge_manager.c
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/******************************************************************************
*
* alt_bridge_manager.c - API for the Altera SoC FPGA bridge manager.
*
******************************************************************************/
/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#include <stddef.h>
#include "alt_bridge_manager.h"
#include "alt_clock_manager.h"
#include "alt_fpga_manager.h"
#include "socal/hps.h"
#include "socal/socal.h"
#include "socal/alt_rstmgr.h"
/******************************************************************************/
ALT_STATUS_CODE alt_bridge_init(ALT_BRIDGE_t bridge,
alt_bridge_fpga_is_ready_t fpga_is_ready,
void* user_arg)
{
uint32_t bridge_reset_mask = 0;
// Validate the bridge parameter and set the appropriate bridge reset mask.
if (bridge == ALT_BRIDGE_LWH2F)
{
bridge_reset_mask = ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK;
}
else if (bridge == ALT_BRIDGE_H2F)
{
bridge_reset_mask = ALT_RSTMGR_BRGMODRST_H2F_SET_MSK;
}
else if (bridge == ALT_BRIDGE_F2H)
{
bridge_reset_mask = ALT_RSTMGR_BRGMODRST_F2H_SET_MSK;
}
else
{
// Invalid bridge argument specified.
return ALT_E_BAD_ARG;
}
// Place and hold the specified bridge in reset.
alt_setbits_word(ALT_RSTMGR_BRGMODRST_ADDR, bridge_reset_mask);
// Validate that bridge clock(s) are configured and stable. Perform the
// clock checks prior other validations that might depend on clocks being
// checked (e.g. FPGA manager dependency on ALT_CLK_L4_MP).
// l4_mp_clk is required for all bridges.
if (alt_clk_is_enabled(ALT_CLK_L4_MP) != ALT_E_TRUE)
{
return ALT_E_BAD_CLK;
}
// Although a stable l3_main_clk is required for H2F and F2H bridges, the
// l3_main_clk is not gated and it runs directly from the Main PLL C1 output
// so if this code is executing it effectively means that this clock is stable
// and hence there are no meaningful validation checks that software can perform
// on the ALT_CLK_L3_MAIN.
// lws2f_axi_clk is required for LWH2F bridge and clocks all LWH2F AXI transactions.
// s2f_axi_clk is required for H2F bridge and clocks all H2F AXI transactions.
// f2s_axi_clk is required for F2H bridge and clocks all F2H AXI transactions.
//
// NOTE: All of these clocks are sourced from the FPGA and provided to the HPS.
// The FPGA must be configured to drive these clocks. Beyond checking that
// the FPGA is configured, there are no HPS control and status mechanisms
// available to check the operational status of these clocks.
// Check that FPGA is powered on.
ALT_FPGA_STATE_t fpga_state = alt_fpga_state_get();
if (fpga_state == ALT_FPGA_STATE_POWER_OFF)
{
return ALT_E_FPGA_PWR_OFF;
}
// Check that FPGA has been configured and is in USER mode.
if (fpga_state != ALT_FPGA_STATE_USER_MODE)
{
return ALT_E_FPGA_NOT_USER_MODE;
}
// If specified, invoke user defined callback function to determine whether the
// FPGA is ready to commence bridge interface transactions. If no user defined
// callback function is specified then proceed on the assumption that the FPGA
// is ready to commence bridge transactions.
if (fpga_is_ready != NULL)
{
ALT_STATUS_CODE fpga_ready_status = fpga_is_ready(user_arg);
if (fpga_ready_status != ALT_E_SUCCESS)
{
// Return the value of the non successful status code as returned from
// the user defined callback function.
return fpga_ready_status;
}
}
// Release the bridge from reset.
alt_clrbits_word(ALT_RSTMGR_BRGMODRST_ADDR, bridge_reset_mask);
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_bridge_uninit(ALT_BRIDGE_t bridge,
alt_bridge_teardown_handshake_t handshake,
void* user_arg)
{
uint32_t bridge_reset_mask = 0;
// Validate the bridge parameter and set the appropriate bridge reset mask.
if (bridge == ALT_BRIDGE_LWH2F)
{
bridge_reset_mask = ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK;
}
else if (bridge == ALT_BRIDGE_H2F)
{
bridge_reset_mask = ALT_RSTMGR_BRGMODRST_H2F_SET_MSK;
}
else if (bridge == ALT_BRIDGE_F2H)
{
bridge_reset_mask = ALT_RSTMGR_BRGMODRST_F2H_SET_MSK;
}
else
{
// Invalid bridge argument specified.
return ALT_E_BAD_ARG;
}
if ((alt_read_word(ALT_RSTMGR_BRGMODRST_ADDR) & bridge_reset_mask) == bridge_reset_mask)
{
// The bridge is already in reset and therefore considered uninitialized.
return ALT_E_SUCCESS;
}
// If specified, invoke user defined callback function to perform the tear-down
// handshake notification protocol with the FPGA. If no user defined callback
// function is specified then proceed without performing any tear-down handshake
// notification protocol with the FPGA.
if (handshake != NULL)
{
ALT_STATUS_CODE handshake_status = handshake(user_arg);
if (handshake_status != ALT_E_SUCCESS)
{
// Return the value of the non successful status code as returned from
// the user defined callback function.
return handshake_status;
}
}
// Place and hold the bridge in reset.
alt_setbits_word(ALT_RSTMGR_BRGMODRST_ADDR, bridge_reset_mask);
return ALT_E_SUCCESS;
}
/******************************************************************************/

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FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_ecc.c
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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#include <stdio.h>
#include "alt_ecc.h"
#include "socal/alt_sysmgr.h"
#include "socal/hps.h"
#include "socal/socal.h"
/////
// NOTE: To enable debugging output, delete the next line and uncomment the
// line after.
#define dprintf(...)
// #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__)
/////
#ifndef ALT_MMU_SMALL_PAGE_SIZE
#define ALT_MMU_SMALL_PAGE_SIZE (4 * 1024)
#endif
//
// This block of memory is scratch space used to scrub any ECC protected memory. It
// is the size of the largest block of memory required aligned to the strictest
// alignment.
// - L2 Data : Up to size of L2 way + size of L1 => 64 KiB + 32 KiB. Must be
// aligned to MMU small page boundary to be properly pageable. (largest RAM,
// strictest alignment)
// - OCRAM : Size of OCRAM => 64 KiB.
// - DMA : 0B.
// - QSPI : 2 KiB.
//
static char block[(64 + 32) * 1024] __attribute__ ((aligned (ALT_MMU_SMALL_PAGE_SIZE)));
__attribute__((weak)) ALT_STATUS_CODE alt_cache_l2_ecc_start(void * block, size_t size)
{
return ALT_E_SUCCESS;
}
static ALT_STATUS_CODE alt_ocram_ecc_start(void * block, size_t size);
__attribute__((weak)) ALT_STATUS_CODE alt_dma_ecc_start(void * block, size_t size)
{
return ALT_E_SUCCESS;
}
__attribute__((weak)) ALT_STATUS_CODE alt_qspi_ecc_start(void * block, size_t size)
{
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_ecc_start(const ALT_ECC_RAM_ENUM_t ram_block)
{
void * ecc_addr;
uint32_t ecc_bits;
switch (ram_block)
{
case ALT_ECC_RAM_L2_DATA:
return alt_cache_l2_ecc_start(block, sizeof(block));
case ALT_ECC_RAM_OCRAM:
return alt_ocram_ecc_start(block, sizeof(block));
case ALT_ECC_RAM_USB0:
ecc_addr = ALT_SYSMGR_ECC_USB0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_USB0_EN_SET_MSK;
break;
case ALT_ECC_RAM_USB1:
ecc_addr = ALT_SYSMGR_ECC_USB1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_USB1_EN_SET_MSK;
break;
case ALT_ECC_RAM_EMAC0:
ecc_addr = ALT_SYSMGR_ECC_EMAC0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK;
break;
case ALT_ECC_RAM_EMAC1:
ecc_addr = ALT_SYSMGR_ECC_EMAC1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_EMAC1_EN_SET_MSK;
break;
case ALT_ECC_RAM_DMA:
return alt_dma_ecc_start(block, sizeof(block));
case ALT_ECC_RAM_CAN0:
ecc_addr = ALT_SYSMGR_ECC_CAN0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_CAN0_EN_SET_MSK;
break;
case ALT_ECC_RAM_CAN1:
ecc_addr = ALT_SYSMGR_ECC_CAN1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_CAN1_EN_SET_MSK;
break;
case ALT_ECC_RAM_NAND:
ecc_addr = ALT_SYSMGR_ECC_NAND_ADDR;
ecc_bits = ALT_SYSMGR_ECC_NAND_EN_SET_MSK;
break;
case ALT_ECC_RAM_QSPI:
return alt_qspi_ecc_start(block, sizeof(block));
case ALT_ECC_RAM_SDMMC:
ecc_addr = ALT_SYSMGR_ECC_SDMMC_ADDR;
ecc_bits = ALT_SYSMGR_ECC_SDMMC_EN_SET_MSK;
break;
default:
return ALT_E_ERROR;
}
alt_setbits_word(ecc_addr, ecc_bits);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_ecc_stop(const ALT_ECC_RAM_ENUM_t ram_block)
{
void * ecc_addr;
uint32_t ecc_bits;
switch (ram_block)
{
case ALT_ECC_RAM_L2_DATA:
ecc_addr = ALT_SYSMGR_ECC_L2_ADDR;
ecc_bits = ALT_SYSMGR_ECC_L2_EN_SET_MSK;
break;
case ALT_ECC_RAM_OCRAM:
ecc_addr = ALT_SYSMGR_ECC_OCRAM_ADDR;
ecc_bits = ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK;
break;
case ALT_ECC_RAM_USB0:
ecc_addr = ALT_SYSMGR_ECC_USB0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_USB0_EN_SET_MSK;
break;
case ALT_ECC_RAM_USB1:
ecc_addr = ALT_SYSMGR_ECC_USB1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_USB1_EN_SET_MSK;
break;
case ALT_ECC_RAM_EMAC0:
ecc_addr = ALT_SYSMGR_ECC_EMAC0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK;
break;
case ALT_ECC_RAM_EMAC1:
ecc_addr = ALT_SYSMGR_ECC_EMAC1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_EMAC1_EN_SET_MSK;
break;
case ALT_ECC_RAM_DMA:
ecc_addr = ALT_SYSMGR_ECC_DMA_ADDR;
ecc_bits = ALT_SYSMGR_ECC_DMA_EN_SET_MSK;
break;
case ALT_ECC_RAM_CAN0:
ecc_addr = ALT_SYSMGR_ECC_CAN0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_CAN0_EN_SET_MSK;
break;
case ALT_ECC_RAM_CAN1:
ecc_addr = ALT_SYSMGR_ECC_CAN1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_CAN1_EN_SET_MSK;
break;
case ALT_ECC_RAM_NAND:
ecc_addr = ALT_SYSMGR_ECC_NAND_ADDR;
ecc_bits = ALT_SYSMGR_ECC_NAND_EN_SET_MSK;
break;
case ALT_ECC_RAM_QSPI:
ecc_addr = ALT_SYSMGR_ECC_QSPI_ADDR;
ecc_bits = ALT_SYSMGR_ECC_QSPI_EN_SET_MSK;
break;
case ALT_ECC_RAM_SDMMC:
ecc_addr = ALT_SYSMGR_ECC_SDMMC_ADDR;
ecc_bits = ALT_SYSMGR_ECC_SDMMC_EN_SET_MSK;
break;
default:
return ALT_E_ERROR;
}
alt_clrbits_word(ecc_addr, ecc_bits);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_ecc_is_enabled(const ALT_ECC_RAM_ENUM_t ram_block)
{
void * ecc_addr;
uint32_t ecc_bits;
switch (ram_block)
{
case ALT_ECC_RAM_L2_DATA:
ecc_addr = ALT_SYSMGR_ECC_L2_ADDR;
ecc_bits = ALT_SYSMGR_ECC_L2_EN_SET_MSK;
break;
case ALT_ECC_RAM_OCRAM:
ecc_addr = ALT_SYSMGR_ECC_OCRAM_ADDR;
ecc_bits = ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK;
break;
case ALT_ECC_RAM_USB0:
ecc_addr = ALT_SYSMGR_ECC_USB0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_USB0_EN_SET_MSK;
break;
case ALT_ECC_RAM_USB1:
ecc_addr = ALT_SYSMGR_ECC_USB1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_USB1_EN_SET_MSK;
break;
case ALT_ECC_RAM_EMAC0:
ecc_addr = ALT_SYSMGR_ECC_EMAC0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK;
break;
case ALT_ECC_RAM_EMAC1:
ecc_addr = ALT_SYSMGR_ECC_EMAC1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_EMAC1_EN_SET_MSK;
break;
case ALT_ECC_RAM_DMA:
ecc_addr = ALT_SYSMGR_ECC_DMA_ADDR;
ecc_bits = ALT_SYSMGR_ECC_DMA_EN_SET_MSK;
break;
case ALT_ECC_RAM_CAN0:
ecc_addr = ALT_SYSMGR_ECC_CAN0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_CAN0_EN_SET_MSK;
break;
case ALT_ECC_RAM_CAN1:
ecc_addr = ALT_SYSMGR_ECC_CAN1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_CAN1_EN_SET_MSK;
break;
case ALT_ECC_RAM_NAND:
ecc_addr = ALT_SYSMGR_ECC_NAND_ADDR;
ecc_bits = ALT_SYSMGR_ECC_NAND_EN_SET_MSK;
break;
case ALT_ECC_RAM_QSPI:
ecc_addr = ALT_SYSMGR_ECC_QSPI_ADDR;
ecc_bits = ALT_SYSMGR_ECC_QSPI_EN_SET_MSK;
break;
case ALT_ECC_RAM_SDMMC:
ecc_addr = ALT_SYSMGR_ECC_SDMMC_ADDR;
ecc_bits = ALT_SYSMGR_ECC_SDMMC_EN_SET_MSK;
break;
default:
return ALT_E_ERROR;
}
if (alt_read_word(ecc_addr) & ecc_bits)
{
return ALT_E_TRUE;
}
else
{
return ALT_E_FALSE;
}
}
/////
ALT_STATUS_CODE alt_ecc_status_get(const ALT_ECC_RAM_ENUM_t ram_block,
uint32_t *status)
{
uint32_t ecc_bits;
uint32_t ecc_mask = 0;
switch (ram_block)
{
// case ALT_ECC_RAM_L2_DATA:
case ALT_ECC_RAM_OCRAM:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_OCRAM_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_OCRAM_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_OCRAM_DERR;
}
break;
case ALT_ECC_RAM_USB0:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_USB0_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_USB0_SERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_USB0_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_USB0_DERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_USB0_DERR;
}
break;
case ALT_ECC_RAM_USB1:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_USB1_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_USB1_SERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_USB1_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_USB1_DERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_USB1_DERR;
}
break;
case ALT_ECC_RAM_EMAC0:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_EMAC0_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_EMAC0_TX_FIFO_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_EMAC0_TX_FIFO_DERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_EMAC0_RX_FIFO_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_EMAC0_RX_FIFO_DERR;
}
break;
case ALT_ECC_RAM_EMAC1:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_EMAC1_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_EMAC1_TX_FIFO_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_EMAC1_TX_FIFO_DERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_EMAC1_RX_FIFO_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_EMAC1_RX_FIFO_DERR;
}
break;
case ALT_ECC_RAM_DMA:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_DMA_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_DMA_SERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_DMA_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_DMA_DERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_DMA_DERR;
}
break;
case ALT_ECC_RAM_CAN0:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_CAN0_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_CAN0_SERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_CAN0_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_CAN0_DERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_CAN0_DERR;
}
break;
case ALT_ECC_RAM_CAN1:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_CAN1_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_CAN1_SERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_CAN1_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_CAN1_DERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_CAN1_DERR;
}
break;
case ALT_ECC_RAM_NAND:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_NAND_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_NAND_BUFFER_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_NAND_BUFFER_DERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_NAND_WR_FIFO_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_NAND_WR_FIFO_DERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_NAND_RD_FIFO_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_NAND_RD_FIFO_DERR;
}
break;
case ALT_ECC_RAM_QSPI:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_QSPI_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_QSPI_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_QSPI_DERR;
}
break;
case ALT_ECC_RAM_SDMMC:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_SDMMC_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_SDMMC_PORT_A_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_SDMMC_PORT_A_DERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_SDMMC_PORT_B_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_SDMMC_PORT_B_DERR;
}
break;
default:
return ALT_E_ERROR;
}
*status = ecc_mask;
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_ecc_status_clear(const ALT_ECC_RAM_ENUM_t ram_block,
const uint32_t ecc_mask)
{
void * ecc_addr;
uint32_t ecc_bits = 0;
switch (ram_block)
{
// case ALT_ECC_RAM_L2_DATA:
case ALT_ECC_RAM_OCRAM:
ecc_addr = ALT_SYSMGR_ECC_OCRAM_ADDR;
if (ecc_mask & ALT_ECC_ERROR_OCRAM_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_OCRAM_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK;
}
break;
case ALT_ECC_RAM_USB0:
ecc_addr = ALT_SYSMGR_ECC_USB0_ADDR;
if (ecc_mask & ALT_ECC_ERROR_USB0_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_USB0_SERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_USB0_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_USB0_DERR_SET_MSK;
}
break;
case ALT_ECC_RAM_USB1:
ecc_addr = ALT_SYSMGR_ECC_USB1_ADDR;
if (ecc_mask & ALT_ECC_ERROR_USB1_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_USB1_SERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_USB1_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_USB1_DERR_SET_MSK;
}
break;
case ALT_ECC_RAM_EMAC0:
ecc_addr = ALT_SYSMGR_ECC_EMAC0_ADDR;
if (ecc_mask & ALT_ECC_ERROR_EMAC0_TX_FIFO_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_EMAC0_TX_FIFO_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_EMAC0_RX_FIFO_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_EMAC0_RX_FIFO_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET_MSK;
}
break;
case ALT_ECC_RAM_EMAC1:
ecc_addr = ALT_SYSMGR_ECC_EMAC1_ADDR;
if (ecc_mask & ALT_ECC_ERROR_EMAC1_TX_FIFO_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_EMAC1_TX_FIFO_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_EMAC1_RX_FIFO_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_EMAC1_RX_FIFO_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET_MSK;
}
break;
case ALT_ECC_RAM_DMA:
ecc_addr = ALT_SYSMGR_ECC_DMA_ADDR;
if (ecc_mask & ALT_ECC_ERROR_DMA_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_DMA_SERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_DMA_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_DMA_DERR_SET_MSK;
}
break;
case ALT_ECC_RAM_CAN0:
ecc_addr = ALT_SYSMGR_ECC_CAN0_ADDR;
if (ecc_mask & ALT_ECC_ERROR_CAN0_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_CAN0_SERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_CAN0_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_CAN0_DERR_SET_MSK;
}
break;
case ALT_ECC_RAM_CAN1:
ecc_addr = ALT_SYSMGR_ECC_CAN1_ADDR;
if (ecc_mask & ALT_ECC_ERROR_CAN1_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_CAN1_SERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_CAN1_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_CAN1_DERR_SET_MSK;
}
break;
case ALT_ECC_RAM_NAND:
ecc_addr = ALT_SYSMGR_ECC_NAND_ADDR;
if (ecc_mask & ALT_ECC_ERROR_NAND_BUFFER_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_NAND_BUFFER_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_NAND_WR_FIFO_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_NAND_WR_FIFO_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_NAND_RD_FIFO_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_NAND_RD_FIFO_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET_MSK;
}
break;
case ALT_ECC_RAM_QSPI:
ecc_addr = ALT_SYSMGR_ECC_QSPI_ADDR;
if (ecc_mask & ALT_ECC_ERROR_QSPI_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_QSPI_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK;
}
break;
case ALT_ECC_RAM_SDMMC:
ecc_addr = ALT_SYSMGR_ECC_SDMMC_ADDR;
if (ecc_mask & ALT_ECC_ERROR_SDMMC_PORT_A_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_SDMMC_PORT_A_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_SDMMC_PORT_B_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_SDMMC_PORT_B_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET_MSK;
}
break;
default:
return ALT_E_ERROR;
}
// Bit 1 is always ECC enable.
// Be sure not to clear other conditions that may be active but not requested to be cleared.
alt_write_word(ecc_addr, (alt_read_word(ecc_addr) & (1 << 0)) | ecc_bits);
return ALT_E_SUCCESS;
}
/////
ALT_STATUS_CODE alt_ecc_serr_inject(const ALT_ECC_RAM_ENUM_t ram_block)
{
void * ecc_addr;
uint32_t ecc_bits;
switch (ram_block)
{
case ALT_ECC_RAM_L2_DATA:
ecc_addr = ALT_SYSMGR_ECC_L2_ADDR;
ecc_bits = ALT_SYSMGR_ECC_L2_INJS_SET_MSK;
break;
case ALT_ECC_RAM_OCRAM:
ecc_addr = ALT_SYSMGR_ECC_OCRAM_ADDR;
ecc_bits = ALT_SYSMGR_ECC_OCRAM_INJS_SET_MSK;
break;
case ALT_ECC_RAM_USB0:
ecc_addr = ALT_SYSMGR_ECC_USB0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_USB0_INJS_SET_MSK;
break;
case ALT_ECC_RAM_USB1:
ecc_addr = ALT_SYSMGR_ECC_USB1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_USB1_INJS_SET_MSK;
break;
case ALT_ECC_RAM_EMAC0:
ecc_addr = ALT_SYSMGR_ECC_EMAC0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET_MSK
| ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET_MSK;
break;
case ALT_ECC_RAM_EMAC1:
ecc_addr = ALT_SYSMGR_ECC_EMAC1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET_MSK
| ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET_MSK;
break;
case ALT_ECC_RAM_DMA:
ecc_addr = ALT_SYSMGR_ECC_DMA_ADDR;
ecc_bits = ALT_SYSMGR_ECC_DMA_INJS_SET_MSK;
break;
case ALT_ECC_RAM_CAN0:
ecc_addr = ALT_SYSMGR_ECC_CAN0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_CAN0_INJS_SET_MSK;
break;
case ALT_ECC_RAM_CAN1:
ecc_addr = ALT_SYSMGR_ECC_CAN1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_CAN1_INJS_SET_MSK;
break;
case ALT_ECC_RAM_NAND:
ecc_addr = ALT_SYSMGR_ECC_NAND_ADDR;
ecc_bits = ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET_MSK
| ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET_MSK
| ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET_MSK;
break;
case ALT_ECC_RAM_QSPI:
ecc_addr = ALT_SYSMGR_ECC_QSPI_ADDR;
ecc_bits = ALT_SYSMGR_ECC_QSPI_INJS_SET_MSK;
break;
case ALT_ECC_RAM_SDMMC:
ecc_addr = ALT_SYSMGR_ECC_SDMMC_ADDR;
ecc_bits = ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET_MSK
| ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET_MSK;
break;
default:
return ALT_E_ERROR;
}
uint32_t reg = alt_read_word(ecc_addr);
alt_write_word(ecc_addr, reg | ecc_bits);
alt_write_word(ecc_addr, reg);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_ecc_derr_inject(const ALT_ECC_RAM_ENUM_t ram_block)
{
void * ecc_addr;
uint32_t ecc_bits;
switch (ram_block)
{
case ALT_ECC_RAM_L2_DATA:
ecc_addr = ALT_SYSMGR_ECC_L2_ADDR;
ecc_bits = ALT_SYSMGR_ECC_L2_INJD_SET_MSK;
break;
case ALT_ECC_RAM_OCRAM:
ecc_addr = ALT_SYSMGR_ECC_OCRAM_ADDR;
ecc_bits = ALT_SYSMGR_ECC_OCRAM_INJD_SET_MSK;
break;
case ALT_ECC_RAM_USB0:
ecc_addr = ALT_SYSMGR_ECC_USB0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_USB0_INJD_SET_MSK;
break;
case ALT_ECC_RAM_USB1:
ecc_addr = ALT_SYSMGR_ECC_USB1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_USB1_INJD_SET_MSK;
break;
case ALT_ECC_RAM_EMAC0:
ecc_addr = ALT_SYSMGR_ECC_EMAC0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET_MSK
| ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET_MSK;
break;
case ALT_ECC_RAM_EMAC1:
ecc_addr = ALT_SYSMGR_ECC_EMAC1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET_MSK
| ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET_MSK;
break;
case ALT_ECC_RAM_DMA:
ecc_addr = ALT_SYSMGR_ECC_DMA_ADDR;
ecc_bits = ALT_SYSMGR_ECC_DMA_INJD_SET_MSK;
break;
case ALT_ECC_RAM_CAN0:
ecc_addr = ALT_SYSMGR_ECC_CAN0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_CAN0_INJD_SET_MSK;
break;
case ALT_ECC_RAM_CAN1:
ecc_addr = ALT_SYSMGR_ECC_CAN1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_CAN1_INJD_SET_MSK;
break;
case ALT_ECC_RAM_NAND:
ecc_addr = ALT_SYSMGR_ECC_NAND_ADDR;
ecc_bits = ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET_MSK
| ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET_MSK
| ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET_MSK;
break;
case ALT_ECC_RAM_QSPI:
ecc_addr = ALT_SYSMGR_ECC_QSPI_ADDR;
ecc_bits = ALT_SYSMGR_ECC_QSPI_INJD_SET_MSK;
break;
case ALT_ECC_RAM_SDMMC:
ecc_addr = ALT_SYSMGR_ECC_SDMMC_ADDR;
ecc_bits = ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET_MSK
| ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET_MSK;
break;
default:
return ALT_E_ERROR;
}
uint32_t reg = alt_read_word(ecc_addr);
alt_write_word(ecc_addr, reg | ecc_bits);
alt_write_word(ecc_addr, reg);
return ALT_E_SUCCESS;
}
/////
static ALT_STATUS_CODE alt_ocram_ecc_start(void * block, size_t size)
{
// CASE 163685: Overflow in ALT_OCRAM_UB_ADDR.
// const uint32_t ocram_size = ((uint32_t)ALT_OCRAM_UB_ADDR - (uint32_t)ALT_OCRAM_LB_ADDR) + 1;
const uint32_t ocram_size = ((uint32_t)0xffffffff - (uint32_t)ALT_OCRAM_LB_ADDR) + 1;
dprintf("DEBUG[ECC][OCRAM]: OCRAM Size = 0x%lx.\n", ocram_size);
// Verify buffer is large enough to contain the entire contents of OCRAM.
if (size < ocram_size)
{
return ALT_E_ERROR;
}
// Verify buffer is word aligned.
if ((uintptr_t)block & (sizeof(uint32_t) - 1))
{
return ALT_E_ERROR;
}
// Read the contents of OCRAM into the provided buffer
uint32_t * block_iter = block;
uint32_t * ocram_iter = ALT_OCRAM_ADDR;
uint32_t size_counter = ocram_size;
while (size_counter)
{
*block_iter = alt_read_word(ocram_iter);
++block_iter;
++ocram_iter;
size_counter -= sizeof(*ocram_iter);
}
// Enable ECC
alt_setbits_word(ALT_SYSMGR_ECC_OCRAM_ADDR, ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK);
// Write back contents of OCRAM from buffer to OCRAM
block_iter = block;
ocram_iter = ALT_OCRAM_ADDR;
size_counter = ocram_size;
while (size_counter)
{
alt_write_word(ocram_iter, *block_iter);
++block_iter;
++ocram_iter;
size_counter -= sizeof(*ocram_iter);
}
// Clear any pending spurious interrupts
alt_write_word(ALT_SYSMGR_ECC_OCRAM_ADDR,
ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK
| ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK
| ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK);
return ALT_E_SUCCESS;
}

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FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_fpga_manager.c
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FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_generalpurpose_io.c
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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
#include "socal/hps.h"
#include "socal/socal.h"
#include "socal/alt_gpio.h"
#include "socal/alt_rstmgr.h"
#include "hwlib.h"
#include "alt_generalpurpose_io.h"
/****************************************************************************************/
/******************************* Useful local definitions *******************************/
/****************************************************************************************/
#define ALT_GPIO_EOPA ALT_GPIO_1BIT_28
#define ALT_GPIO_EOPB ALT_GPIO_1BIT_57
#define ALT_GPIO_EOPC ALT_HLGPI_15
#define ALT_GPIO_BITMASK 0x1FFFFFFF
// expands the zero or one bit to the 29-bit GPIO word
#define ALT_GPIO_ALLORNONE(tst) ((uint32_t) ((tst == 0) ? 0 : ALT_GPIO_BITMASK))
/****************************************************************************************/
/* alt_gpio_init() initializes the GPIO modules */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_init(void)
{
// put GPIO modules into system manager reset if not already there
alt_gpio_uninit();
// release GPIO modules from system reset (w/ two-instruction delay)
alt_replbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK |
ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK |
ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK, 0);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_uninit() uninitializes the GPIO modules */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_uninit(void)
{
// put all GPIO modules into system manager reset
alt_replbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK |
ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK |
ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK,
ALT_GPIO_BITMASK);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_port_datadir_set() sets the specified GPIO data bits to use the data */
/* direction(s) specified. 0 = input (default). 1 = output. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_datadir_set(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask, uint32_t config)
{
volatile uint32_t *addr;
if ((mask & ~ALT_GPIO_BITMASK) || (config & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_SWPORTA_DDR_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_SWPORTA_DDR_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_SWPORTA_DDR_ADDR; }
else { return ALT_E_BAD_ARG; }
alt_replbits_word(addr, mask, config);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_port_datadir_get() returns the data direction configuration of selected */
/* bits of the designated GPIO module. */
/****************************************************************************************/
uint32_t alt_gpio_port_datadir_get(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_SWPORTA_DDR_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_SWPORTA_DDR_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_SWPORTA_DDR_ADDR; }
else { return 0; }
return alt_read_word(addr) & mask;
}
/****************************************************************************************/
/* alt_gpio_port_data_write() sets the GPIO data outputs of the specified GPIO module */
/* to a one or zero. Actual outputs are only set if the data direction for that bit(s) */
/* has previously been set to configure them as output(s). */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_data_write(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask, uint32_t val)
{
volatile uint32_t *addr;
if ((mask & ~ALT_GPIO_BITMASK) || (val & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_SWPORTA_DR_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_SWPORTA_DR_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_SWPORTA_DR_ADDR; }
else { return ALT_E_BAD_ARG; }
alt_replbits_word(addr, mask, val);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_port_data_read() returns the value of the data inputs of the specified */
/* GPIO module. Data direction for these bits must have been previously set to inputs. */
/****************************************************************************************/
#if (!ALT_GPIO_DATAREAD_TEST_MODE)
/* This is the production code version. For software unit testing, set the */
/* ALT_GPIO_DATAREAD_TEST_MODE flag to true in the makefile, which will compile */
/* the GPIO test software version of alt_gpio_port_data_read() instead. */
uint32_t alt_gpio_port_data_read(ALT_GPIO_PORT_t gpio_pid, uint32_t mask)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_EXT_PORTA_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_EXT_PORTA_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_EXT_PORTA_ADDR; }
else { return 0; }
return alt_read_word(addr) & mask;
}
#endif
/****************************************************************************************/
/* alt_gpio_port_int_type_set() sets selected signals of the specified GPIO port to */
/* be either level-sensitive ( =0) or edge-triggered ( =1). */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_int_type_set(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask, uint32_t config)
{
volatile uint32_t *addr;
if ((mask & ~ALT_GPIO_BITMASK) || (config & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTTYPE_LEVEL_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTTYPE_LEVEL_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTTYPE_LEVEL_ADDR; }
else { return ALT_E_BAD_ARG; }
alt_replbits_word(addr, mask, config);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_port_int_type_get() returns the interrupt configuration (edge-triggered or */
/* level-triggered) for the specified signals of the specified GPIO module. */
/****************************************************************************************/
uint32_t alt_gpio_port_int_type_get(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTTYPE_LEVEL_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTTYPE_LEVEL_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTTYPE_LEVEL_ADDR; }
else { return 0; }
return alt_read_word(addr) & mask;
}
/****************************************************************************************/
/* alt_gpio_port_int_pol_set() sets the interrupt polarity of the signals of the */
/* specified GPIO register (when used as inputs) to active-high ( =0) or active-low */
/* ( =1). */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_int_pol_set(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask, uint32_t config)
{
volatile uint32_t *addr;
if ((mask & ~ALT_GPIO_BITMASK) || (config & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INT_POL_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INT_POL_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INT_POL_ADDR; }
else { return ALT_E_BAD_ARG; }
alt_replbits_word(addr, mask, config);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_port_int_pol_get() returns the active-high or active-low polarity */
/* configuration for the possible interrupt sources of the specified GPIO module. */
/* 0 = The interrupt polarity for this bit is set to active-low mode. 1 = The */
/* interrupt polarity for this bit is set to active-highmode. */
/****************************************************************************************/
uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INT_POL_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INT_POL_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INT_POL_ADDR; }
else { return 0; }
return alt_read_word(addr) & mask;
}
/****************************************************************************************/
/* alt_gpio_port_debounce_set() sets the debounce configuration for input signals of */
/* the specified GPIO module. 0 - Debounce is not selected for this signal (default). */
/* 1 - Debounce is selected for this signal. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_debounce_set(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask, uint32_t config)
{
volatile uint32_t *addr;
if ((mask & ~ALT_GPIO_BITMASK) || (config & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_DEBOUNCE_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_DEBOUNCE_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_DEBOUNCE_ADDR; }
else { return ALT_E_BAD_ARG; }
alt_replbits_word(addr, mask, config);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_port_debounce_get() returns the debounce configuration for the input */
/* signals of the specified GPIO register. 0 - Debounce is not selected for this */
/* signal. 1 - Debounce is selected for this signal. */
/****************************************************************************************/
uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_DEBOUNCE_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_DEBOUNCE_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_DEBOUNCE_ADDR; }
else { return 0; }
return alt_read_word(addr) & mask;
}
/****************************************************************************************/
/* alt_gpio_port_sync_set() sets the synchronization configuration for the signals of */
/* the specified GPIO register. This allows for synchronizing level-sensitive */
/* interrupts to the internal clock signal. This is a port-wide option that controls */
/* all level-sensitive interrupt signals of that GPIO port. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_sync_set(ALT_GPIO_PORT_t gpio_pid, uint32_t config)
{
volatile uint32_t *addr;
config = (config != 0) ? 1 : 0;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_LS_SYNC_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_LS_SYNC_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_LS_SYNC_ADDR; }
else { return ALT_E_BAD_ARG; }
alt_write_word(addr, config);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_port_sync_get() returns the synchronization configuration for the signals */
/* of the specified GPIO register. This allows for synchronizing level-sensitive */
/* interrupts to the internal clock signal. This is a port-wide option that controls */
/* all level-sensitive interrupt signals of that GPIO port. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_LS_SYNC_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_LS_SYNC_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_LS_SYNC_ADDR; }
else { return ALT_E_BAD_ARG; } // error
return (alt_read_word(addr) != 0) ? ALT_E_TRUE : ALT_E_FALSE;
}
/****************************************************************************************/
/* alt_gpio_port_config() configures a group of GPIO signals with the same parameters. */
/* Allows for configuring all parameters of a given port at one time. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_config(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask, ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type,
ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounc,
uint32_t data)
{
ALT_STATUS_CODE ret;
// set all affected GPIO bits to inputs
ret = alt_gpio_port_datadir_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(ALT_GPIO_PIN_INPUT));
// the ALT_GPIO_ALLORNONE() macro expands the zero or one bit to the 29-bit GPIO word
// set trigger type
if (ret == ALT_E_SUCCESS)
{
ret = alt_gpio_port_int_type_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(type));
}
// set polarity
if (ret == ALT_E_SUCCESS)
{
alt_gpio_port_int_pol_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(pol));
}
// set debounce
if (ret == ALT_E_SUCCESS)
{
alt_gpio_port_debounce_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(debounc));
}
// set data output(s)
if (ret == ALT_E_SUCCESS)
{
alt_gpio_port_data_write(gpio_pid, mask, ALT_GPIO_ALLORNONE(data));
}
if (ret == ALT_E_SUCCESS)
{
// set data direction of one or more bits to select output
ret = alt_gpio_port_datadir_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(dir));
}
return ret;
}
/****************************************************************************************/
/* Enables the specified GPIO data register interrupts. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_int_enable(ALT_GPIO_PORT_t gpio_pid, uint32_t config)
{
volatile uint32_t *addr;
if (config & ~ALT_GPIO_BITMASK) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTEN_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTEN_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTEN_ADDR; }
else { return ALT_E_BAD_ARG; }
alt_replbits_word(addr, config, UINT32_MAX);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* Disables the specified GPIO data module interrupts. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_int_disable(ALT_GPIO_PORT_t gpio_pid, uint32_t config)
{
volatile uint32_t *addr;
if (config & ~ALT_GPIO_BITMASK) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTEN_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTEN_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTEN_ADDR; }
else { return ALT_E_BAD_ARG; }
alt_replbits_word(addr, config, 0);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* Get the current state of the specified GPIO port interrupts enables. */
/****************************************************************************************/
uint32_t alt_gpio_port_int_enable_get(ALT_GPIO_PORT_t gpio_pid)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTEN_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTEN_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTEN_ADDR; }
else { return 0; }
return alt_read_word(addr);
}
/****************************************************************************************/
/* Masks or unmasks selected interrupt source bits of the data register of the */
/* specified GPIO module. Uses a second bit mask to determine which signals may be */
/* changed by this call. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_int_mask_set(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask, uint32_t val)
{
volatile uint32_t *addr;
if ((mask & ~ALT_GPIO_BITMASK) || (val & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTMSK_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTMSK_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTMSK_ADDR; }
else { return ALT_E_BAD_ARG; } // argument error
alt_replbits_word(addr, mask, val);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* Returns the interrupt source mask of the specified GPIO module. */
/****************************************************************************************/
uint32_t alt_gpio_port_int_mask_get(ALT_GPIO_PORT_t gpio_pid)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTMSK_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTMSK_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTMSK_ADDR; }
else { return 0; } // error
return alt_read_word(addr);
}
/****************************************************************************************/
/* alt_gpio_port_int_status_get() returns the interrupt pending status of all signals */
/* of the specified GPIO register. */
/****************************************************************************************/
uint32_t alt_gpio_port_int_status_get(ALT_GPIO_PORT_t gpio_pid)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTSTAT_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTSTAT_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTSTAT_ADDR; }
else { return 0; } // error
return alt_read_word(addr);
}
/****************************************************************************************/
/* Clear the interrupt pending status of selected signals of the specified GPIO */
/* register. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_int_status_clear(ALT_GPIO_PORT_t gpio_pid,
uint32_t clrmask)
{
volatile uint32_t *addr;
if (clrmask & ~ALT_GPIO_BITMASK) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTSTAT_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTSTAT_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTSTAT_ADDR; }
else { return ALT_E_BAD_ARG; } // argument error
alt_write_word(addr, clrmask);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_port_idcode_get() returns the ID code of the specified GPIO module. */
/****************************************************************************************/
uint32_t alt_gpio_port_idcode_get(ALT_GPIO_PORT_t gpio_pid)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_ID_CODE_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_ID_CODE_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_ID_CODE_ADDR; }
else { return 0; }
return alt_read_word(addr);
}
/****************************************************************************************/
/* alt_gpio_port_ver_get() returns the version code of the specified GPIO module. */
/****************************************************************************************/
uint32_t alt_gpio_port_ver_get(ALT_GPIO_PORT_t gpio_pid)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_VER_ID_CODE_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_VER_ID_CODE_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_VER_ID_CODE_ADDR; }
else { return 0; }
return alt_read_word(addr);
}
/****************************************************************************************/
/* alt_gpio_bit_config() configures one bit (signal) of the GPIO ports. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_bit_config(ALT_GPIO_1BIT_t signal_num,
ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type,
ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounce,
ALT_GPIO_PIN_DATA_t data)
{
ALT_GPIO_PORT_t pid;
uint32_t mask;
pid = alt_gpio_bit_to_pid(signal_num);
mask = 0x1 << alt_gpio_bit_to_port_pin(signal_num);
return alt_gpio_port_config(pid, mask, dir, type, pol, debounce, data);
}
/****************************************************************************************/
/* Returns the configuration parameters of a given GPIO bit. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_bitconfig_get(ALT_GPIO_1BIT_t signal_num,
ALT_GPIO_CONFIG_RECORD_t *config)
{
ALT_STATUS_CODE ret = ALT_E_ERROR;
ALT_GPIO_PORT_t pid;
uint32_t mask, shift;
if ((config != NULL) && (signal_num != ALT_END_OF_GPIO_SIGNALS) && (signal_num <= ALT_LAST_VALID_GPIO_BIT))
{
pid = alt_gpio_bit_to_pid(signal_num);
shift = alt_gpio_bit_to_port_pin(signal_num);
if ((pid != ALT_GPIO_PORT_UNKNOWN) && (shift <= ALT_GPIO_BIT_MAX))
{
config->signal_number = signal_num;
mask = 0x00000001 << shift;
config->direction = (alt_gpio_port_datadir_get(pid, mask) == 0) ? ALT_GPIO_PIN_INPUT : ALT_GPIO_PIN_OUTPUT;
config->type = (alt_gpio_port_int_type_get(pid, mask) == 0) ? ALT_GPIO_PIN_LEVEL_TRIG_INT : ALT_GPIO_PIN_EDGE_TRIG_INT;
// save the following data whatever the state of config->direction
config->polarity = (alt_gpio_port_int_pol_get(pid, mask) == 0) ? ALT_GPIO_PIN_ACTIVE_LOW : ALT_GPIO_PIN_ACTIVE_HIGH;
config->debounce = (alt_gpio_port_debounce_get(pid, mask) == 0) ? ALT_GPIO_PIN_NODEBOUNCE : ALT_GPIO_PIN_DEBOUNCE;
config->data = (alt_gpio_port_data_read(pid, mask) == 0) ? ALT_GPIO_PIN_DATAZERO : ALT_GPIO_PIN_DATAONE;
ret = ALT_E_SUCCESS;
}
}
return ret;
}
/****************************************************************************************/
/* alt_gpio_group_config() configures a list of GPIO bits. The GPIO bits do not have */
/* to be configured the same, as was the case for the mask version of this function, */
/* alt_gpio_port_config(). Each bit may be configured differently and bits may be */
/* listed in any order. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_group_config(ALT_GPIO_CONFIG_RECORD_t* config_array, uint32_t len)
{
ALT_STATUS_CODE ret = ALT_E_ERROR;
if (config_array != NULL)
{
if (config_array->signal_number == ALT_END_OF_GPIO_SIGNALS) { ret = ALT_E_SUCCESS; }
// catches the condition where the pointers are good, but the
// first index is the escape character - which isn't an error
else
{
for (; (len-- > 0) && (config_array->signal_number != ALT_END_OF_GPIO_SIGNALS) && (config_array != NULL); config_array++)
{
ret = alt_gpio_bit_config(config_array->signal_number,
config_array->direction, config_array->type, config_array->polarity,
config_array->debounce, config_array->data);
if ((config_array->direction == ALT_GPIO_PIN_OUTPUT) && (ret == ALT_E_SUCCESS))
{
// if the pin is set to be an output, set it to the correct value
alt_gpio_port_data_write(alt_gpio_bit_to_pid(config_array->signal_number),
0x1 << alt_gpio_bit_to_port_pin(config_array->signal_number),
ALT_GPIO_ALLORNONE(config_array->data));
// ret should retain the value returned by alt_gpio_bit_config() above
// and should not be changed by the alt_gpio_port_data_write() call.
}
if (((ret != ALT_E_SUCCESS) && (config_array->signal_number <= ALT_LAST_VALID_GPIO_BIT))
|| ((ret == ALT_E_SUCCESS) && (config_array->signal_number > ALT_LAST_VALID_GPIO_BIT)))
{
ret = ALT_E_ERROR;
break;
}
}
}
}
return ret;
}
/****************************************************************************************/
/* Returns a list of the pin signal indices and the associated configuration settings */
/* (data direction, interrupt type, polarity, debounce, and synchronization) of that */
/* list of signals. Only the signal indices in the first field of each configuration */
/* record need be filled in. This function will fill in all the other fields of the */
/* configuration record, returning all configuration parameters in the array. A signal */
/* number index in the array equal to ALT_END_OF_GPIO_SIGNALS (-1) also terminates the */
/* function. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array,
uint32_t len)
{
ALT_STATUS_CODE ret = ALT_E_ERROR;
if ((config_array != NULL) && (config_array->signal_number == ALT_END_OF_GPIO_SIGNALS))
{
ret = ALT_E_SUCCESS;
}
else
{
for ( ; (len > 0) && (config_array != NULL) && (config_array->signal_number != ALT_END_OF_GPIO_SIGNALS)
&& (config_array->signal_number <= ALT_LAST_VALID_GPIO_BIT); len--)
{
ret = alt_gpio_bitconfig_get(config_array->signal_number, config_array);
config_array++;
if (ret != ALT_E_SUCCESS) { break; }
}
}
return ret;
}
/****************************************************************************************/
/* Another way to return a configuration list. The difference between this version and */
/* alt_gpio_group_config_get() is that this version follows a separate list of signal */
/* indices instead of having the signal list provided in the first field of the */
/* configuration records in the array. This function will fill in the fields of the */
/* configuration record, returning all configuration parameters in the array. A signal */
/* number index in the array equal to ALT_END_OF_GPIO_SIGNALS (-1) also terminates */
/* operation. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_group_config_get2(ALT_GPIO_1BIT_t* pinid_array,
ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len)
{
ALT_STATUS_CODE ret = ALT_E_ERROR;
if ((config_array != NULL) && (pinid_array != NULL) && (*pinid_array == ALT_END_OF_GPIO_SIGNALS))
{
ret = ALT_E_SUCCESS;
// catches the condition where the pointers are good, but the
// first index is the escape character - which isn't an error
}
else
{
for ( ;(len > 0) && (pinid_array != NULL) && (*pinid_array != ALT_END_OF_GPIO_SIGNALS) && (config_array != NULL); len--)
{
ret = alt_gpio_bitconfig_get(*pinid_array, config_array);
config_array++;
pinid_array++;
if (ret != ALT_E_SUCCESS) { break; }
}
}
return ret;
}
/****************************************************************************************/
/* A useful utility function. Extracts the GPIO port ID from the supplied GPIO Signal */
/* Index Number. */
/****************************************************************************************/
ALT_GPIO_PORT_t alt_gpio_bit_to_pid(ALT_GPIO_1BIT_t pin_num)
{
ALT_GPIO_PORT_t pid = ALT_GPIO_PORT_UNKNOWN;
if (pin_num <= ALT_GPIO_EOPA) { pid = ALT_GPIO_PORTA; }
else if (pin_num <= ALT_GPIO_EOPB) { pid = ALT_GPIO_PORTB; }
else if (pin_num <= ALT_GPIO_EOPC) { pid = ALT_GPIO_PORTC; }
return pid;
}
/****************************************************************************************/
/* A useful utility function. Extracts the GPIO signal (pin) mask from the supplied */
/* GPIO Signal Index Number. */
/****************************************************************************************/
ALT_GPIO_PORTBIT_t alt_gpio_bit_to_port_pin(ALT_GPIO_1BIT_t pin_num)
{
if (pin_num <= ALT_GPIO_EOPA) {}
else if (pin_num <= ALT_GPIO_EOPB) { pin_num -= (ALT_GPIO_EOPA + 1); }
else if (pin_num <= ALT_GPIO_EOPC) { pin_num -= (ALT_GPIO_EOPB + 1); }
else { return ALT_END_OF_GPIO_PORT_SIGNALS; }
return (ALT_GPIO_PORTBIT_t) pin_num;
}
/****************************************************************************************/
/* A useful utility function. Extracts the GPIO Signal Index Number from the supplied */
/* GPIO port ID and signal mask. If passed a bitmask composed of more than one signal, */
/* the signal number of the lowest bitmask presented is returned. */
/****************************************************************************************/
ALT_GPIO_1BIT_t alt_gpio_port_pin_to_bit(ALT_GPIO_PORT_t pid,
uint32_t bitmask)
{
uint32_t i;
for (i=0; i <= ALT_GPIO_BITNUM_MAX ;i++)
{
if (bitmask & 0x00000001)
{
if (pid == ALT_GPIO_PORTA) {}
else if (pid == ALT_GPIO_PORTB) { i += ALT_GPIO_EOPA + 1; }
else if (pid == ALT_GPIO_PORTC) { i += ALT_GPIO_EOPB + 1; }
else { return ALT_END_OF_GPIO_SIGNALS; }
return (ALT_GPIO_1BIT_t) i;
}
bitmask >>= 1;
}
return ALT_END_OF_GPIO_SIGNALS;
}

557
FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_globaltmr.c
Unescape Escape View File

@ -0,0 +1,557 @@
/******************************************************************************
*
* alt_globaltmr.c - API for the Altera SoC FPGA global timer.
*
******************************************************************************/
/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include "socal/hps.h"
#include "socal/socal.h"
#include "hwlib.h"
#include "alt_mpu_registers.h"
#include "alt_globaltmr.h"
#include "alt_clock_manager.h" // for getting clock bus frequency
/************************************************************************************************************/
/************************************************************************************************************/
/* The global timer is common to both ARM CPUs and also to the FPGA fabric.There is no good way to know what
effect halting the global timer might have on the other ARM CPU. It was decided that once the global
timer was started, there should not be a way included in this API to halt it. It is possible to achieve
much of the same effect by disabling the global timer comparison functionality instead. The global timer
has hardware that can automatically add the count value to the current value of the global timer when
the timer reaches the comparison value.
*/
/************************************************************************************************************/
/*************************************************************************************************************
* alt_globaltmr_is_running() is an internal function, not published in the API.
* It checks and returns the state of the enable bit of the global timer but doesn't check the comparison
* mode bit.
*************************************************************************************************************/
bool alt_globaltmr_is_running(void)
{
return alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & GLOBALTMR_ENABLE_BIT;
}
/****************************************************************************************/
/* alt_globaltmr_uninit() uninitializes the global timer modules */
/****************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_uninit(void)
{
alt_clrbits_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET,
GLOBALTMR_COMP_ENABLE_BIT | GLOBALTMR_INT_ENABLE_BIT |
GLOBALTMR_AUTOINC_ENABLE_BIT);
// do NOT clear the global timer enable bit or prescaler setting
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_COMP_LO_REG_OFFSET, 0);
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_COMP_HI_REG_OFFSET, 0);
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_AUTOINC_REG_OFFSET, 0);
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_INT_STAT_REG_OFFSET, GLOBALTMR_INT_STATUS_BIT);
/* clear any interrupts by writing one to sticky bit */
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_globaltmr_init() initializes the global timer module */
/****************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_init(void)
{
alt_globaltmr_uninit();
alt_setbits_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET, GLOBALTMR_ENABLE_BIT);
return ALT_E_SUCCESS;
}
/*************************************************************************************************************
* alt_globaltmr_stop() doesn't actually stop the global timer, instead it stops the virtual representation
* of the global timer as a typical countdown timer. The timer will no longer compare the global timer value
* to the global timer compare value, will not auto-increment the comparator value, and will not set the
* interrupt.
*************************************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_stop(void)
{
uint32_t regdata; // value to read & write
regdata = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET);
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET, regdata & ~GLOBALTMR_COMP_ENABLE_BIT);
return ALT_E_SUCCESS;
}
/*************************************************************************************************************
* alt_globaltmr_start() sets the comparison mode of the global timer, allowing it to be used as a typical
* countdown timer. If auto-increment mode is enabled, it will operate as a free-running timer.
*************************************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_start(void)
{
uint32_t regdata; // value to read & write
regdata = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET);
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET, regdata | (GLOBALTMR_COMP_ENABLE_BIT | GLOBALTMR_ENABLE_BIT));
return ALT_E_SUCCESS;
}
/*************************************************************************************************************
* alt_globaltmr_get() returns the current value of the 64-bit global timer as two unsigned 32-bit quantities.
*************************************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_get(uint32_t* highword, uint32_t* loword)
{
ALT_STATUS_CODE ret = ALT_E_ERROR;
uint32_t hi, lo, temp; // temporary variables
uint32_t cnt = 3; // Timeout counter, do 3 tries
if ((highword == NULL) || (loword == NULL)) { ret = ALT_E_BAD_ARG; }
else
{
hi = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CNTR_HI_REG_OFFSET);
do {
temp = hi;
lo = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CNTR_LO_REG_OFFSET);
hi = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CNTR_HI_REG_OFFSET);
} while ((temp != hi) && (cnt--)); // has the high-order word read the same twice yet?
// note that if the first condition is true, cnt is neither tested nor decremented
if (cnt) {
*highword = hi;
*loword = lo;
ret = ALT_E_SUCCESS;
}
}
return ret;
}
/*************************************************************************************************************
* alt_globaltmr_get64() returns the current value of the global timer as an unsigned 64-bit quantity.
*************************************************************************************************************/
uint64_t alt_globaltmr_get64(void)
{
uint64_t ret = 0; // zero a very unlikely value for this timer
uint32_t hi, lo, temp; // temporary variables
uint32_t cnt = 3; // Timeout counter, do 3 tries
hi = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CNTR_HI_REG_OFFSET);
do {
temp = hi;
lo = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CNTR_LO_REG_OFFSET);
hi = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CNTR_HI_REG_OFFSET);
} while ((temp != hi) && (cnt--)); // has the high-order word read the same twice yet?
// note that if the first condition is true, cnt is neither tested nor decremented
if (cnt)
{
ret = (uint64_t) hi;
ret = (ret << (sizeof(uint32_t)*8)) | lo;
}
return ret;
}
/*************************************************************************************************************
* alt_globaltmr_counter_get_low32() returns the least-significant 32 bits of the current global timer value.
*************************************************************************************************************/
uint32_t alt_globaltmr_counter_get_low32(void)
{
return alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CNTR_LO_REG_OFFSET);
}
/*************************************************************************************************************
* alt_globaltmr_counter_get_hi32() returns the most-significant 32 bits of the current global timer value.
*************************************************************************************************************/
uint32_t alt_globaltmr_counter_get_hi32(void)
{
return alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CNTR_HI_REG_OFFSET);
}
/*************************************************************************************************************
* alt_globaltmr_comp_set() writes the 64-bit comparator register with two 32-bit words.
*************************************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_comp_set(uint32_t highword, uint32_t loword)
{
bool was_comping = false;
ALT_STATUS_CODE ret = ALT_E_ERROR;
if (alt_globaltmr_is_comp_mode()) // necessary to prevent a spurious interrupt
{
was_comping = true;
ret = alt_globaltmr_comp_mode_stop();
if (ret != ALT_E_SUCCESS) { return ret; }
}
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_COMP_LO_REG_OFFSET, loword);
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_COMP_HI_REG_OFFSET, highword);
ret = ALT_E_SUCCESS;
if (was_comping) { ret = alt_globaltmr_comp_mode_start(); }
// If global timer was in comparison mode before, re-enable it before returning
return ret;
}
/*************************************************************************************************************
* alt_globaltmr_comp_set64() writes the 64-bit comparator register with the supplied 64-bit value.
*************************************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_comp_set64(uint64_t compval)
{
ALT_STATUS_CODE ret = ALT_E_ERROR;
bool was_comping = false;
if (alt_globaltmr_is_comp_mode())
{
was_comping = true;
ret = alt_globaltmr_comp_mode_stop();
if (ret != ALT_E_SUCCESS) { return ret; }
}
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_COMP_LO_REG_OFFSET, (uint32_t) (compval & UINT32_MAX));
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_COMP_HI_REG_OFFSET,
(uint32_t) ((compval >> (sizeof(uint32_t)*8)) & UINT32_MAX));
ret = ALT_E_SUCCESS;
if (was_comping) { ret = alt_globaltmr_comp_mode_start(); }
// If global timer was in comparison mode before, re-enable it
return ret;
}
/*************************************************************************************************************
* alt_globaltmr_comp_get() returns the 64 bits of the current global timer comparator value via two
* uint32_t pointers.
*************************************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_comp_get(uint32_t *hiword, uint32_t *loword)
{
if ((hiword == NULL) || (loword == NULL)) {return ALT_E_ERROR; }
*loword = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_COMP_LO_REG_OFFSET);
*hiword = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_COMP_HI_REG_OFFSET);
/* no need to read these multiple times since the register is not expected to change mid-read */
return ALT_E_SUCCESS;
}
/*************************************************************************************************************
* alt_globaltmr_comp_get64() returns all 64 bits of the current global timer comparator value.
*************************************************************************************************************/
uint64_t alt_globaltmr_comp_get64(void)
{
uint64_t ret;
ret = ((uint64_t) alt_read_word(GLOBALTMR_BASE + GLOBALTMR_COMP_HI_REG_OFFSET)) << (sizeof(uint32_t)*8);
ret = ret | ((uint64_t) alt_read_word(GLOBALTMR_BASE + GLOBALTMR_COMP_LO_REG_OFFSET));
return ret;
}
/*************************************************************************************************************
* alt_globaltmr_remain_get64() returns a 64-bit quantity that represents the difference between the
* current comparator value and the current global timer value. If the comparator register was updated by
* the autoincrement circuitry (and the global timer has not subsequently crossed over the comparator
* value a second time), this difference will always be expressable in 32 bits. If the user has manually
* set the comparator value, however, this may not be true and more than 32 bits may be required to express
* the difference.
*************************************************************************************************************/
#define alt_globaltmr_remain_get64() (alt_globaltmr_comp_get64() - alt_globaltmr_get64())
/*************************************************************************************************************
* alt_globaltmr_remain_get() returns a 32-bit quantity that represents the difference between the
* current comparator value and the current global timer value. If the comparator register was updated by
* the autoincrement circuitry (and the global timer has not subsequently crossed over the comparator
* value a second time), this difference will always be expressable in 32 bits. If the user has manually
* set the comparator value, however, this may not be true and more than 32 bits may be required to express
* the difference.
*************************************************************************************************************/
uint32_t alt_globaltmr_remain_get(void)
{
return (uint32_t) (alt_globaltmr_comp_get64() - alt_globaltmr_get64());
}
/*************************************************************************************************************
* alt_globaltmr_comp_mode_start() sets the comparison enable bit of the global timer, enabling
* comparison mode operation.
*************************************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_comp_mode_start(void)
{
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET,
alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) | GLOBALTMR_COMP_ENABLE_BIT);
return ALT_E_SUCCESS;
}
/*************************************************************************************************************
* alt_globaltmr_comp_mode_stop() clears the comparison enable bit of the global timer, disabling
* comparison mode operation.
*************************************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_comp_mode_stop(void)
{
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET,
alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & ~GLOBALTMR_COMP_ENABLE_BIT);
return ALT_E_SUCCESS;
}
/*************************************************************************************************************
* alt_globaltmr_is_comp_mode() checks and returns the state of the comparison enable bit of the global timer.
*************************************************************************************************************/
bool alt_globaltmr_is_comp_mode(void)
{
return alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & GLOBALTMR_COMP_ENABLE_BIT;
}
/*************************************************************************************************************
* alt_globaltmr_prescaler_get() returns the value of the prescaler setting of the global timer, which is one
* less than the actual counter divisor. Valid output = 0-255.
*************************************************************************************************************/
uint32_t alt_globaltmr_prescaler_get(void)
{
return (alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & GLOBALTMR_PS_MASK) >> GLOBALTMR_PS_SHIFT;
}
/*************************************************************************************************************
* alt_globaltmr_prescaler_set() sets the prescaler value of the global timer, which is one
* less than the actual counter divisor.
*************************************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_prescaler_set(uint32_t val)
{
// It is not defined in the ARM global timer spec if the prescaler can be rewritten while
//the global timer is counting or not. This is how we find out:
uint32_t regdata;
if (val > UINT8_MAX) return ALT_E_BAD_ARG;
regdata = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & ~GLOBALTMR_PS_MASK;
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET, regdata | (val << GLOBALTMR_PS_SHIFT));
return ALT_E_SUCCESS;
}
/*************************************************************************************************************
* alt_globaltmr_autoinc_set() safely writes a value to the auto-increment register of the global timer.
*************************************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_autoinc_set(uint32_t inc)
{
ALT_STATUS_CODE ret = ALT_E_ERROR;
bool was_comping = false;
if (alt_globaltmr_is_comp_mode())
{
was_comping = true;
ret = alt_globaltmr_comp_mode_stop();
// if timer is currently in comparison mode, disable comparison mode
if (ret != ALT_E_SUCCESS) { return ret; }
}
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_AUTOINC_REG_OFFSET, inc);
ret = ALT_E_SUCCESS;
if (was_comping) { ret = alt_globaltmr_comp_mode_start(); }
// If global timer was in comparison mode before, re-enable it
return ret;
}
/*************************************************************************************************************
* alt_globaltmr_autoinc_get() returns the value of the auto-increment register of the global timer.
*************************************************************************************************************/
uint32_t alt_globaltmr_autoinc_get(void)
{
return alt_read_word(GLOBALTMR_BASE + GLOBALTMR_AUTOINC_REG_OFFSET);
}
/*************************************************************************************************************
* alt_globaltmr_autoinc_mode_start() sets the auto-increment enable bit of the global timer, putting it into
* auto-increment or periodic timer mode.
*************************************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_autoinc_mode_start(void)
{
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET,
alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) | GLOBALTMR_AUTOINC_ENABLE_BIT);
return ALT_E_SUCCESS;
}
/*************************************************************************************************************
* alt_globaltmr_autoinc_mode_stop() clears the auto-increment enable bit of the global timer, putting it into
* one-shot timer mode.
*************************************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_autoinc_mode_stop(void)
{
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET,
alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & ~GLOBALTMR_AUTOINC_ENABLE_BIT);
return ALT_E_SUCCESS;
}
/*************************************************************************************************************
* alt_globaltmr_is_autoinc_mode() checks and returns the state of the auto-increment enable bit of the global
* timer.
*************************************************************************************************************/
bool alt_globaltmr_is_autoinc_mode(void)
{
return alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & GLOBALTMR_AUTOINC_ENABLE_BIT;
}
/*************************************************************************************************************
* alt_globaltmr_maxcounter_get() returns the maximum possible auto-increment value of the global timer.
*************************************************************************************************************/
uint32_t alt_globaltmr_maxcounter_get(void)
{
return GLOBALTMR_MAX;
}
/*************************************************************************************************************
* alt_globaltmr_int_disable() clears the interrupt enable bit of the global timer.
*************************************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_int_disable(void)
{
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET,
alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & ~GLOBALTMR_INT_ENABLE_BIT);
return ALT_E_SUCCESS;
}
/*************************************************************************************************************
* alt_globaltmr_int_enable() sets the interrupt enable bit of the global timer, allowing the timer to throw an
* interrupt when the global timer value is greater than the comparator value. If the global timer has not
* yet been started, it tries to start it first.
*************************************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_int_enable(void)
{
if (!alt_globaltmr_is_running()) // Is gbl timer running?
{
if ( alt_globaltmr_start() != ALT_E_SUCCESS) { return ALT_E_ERROR; }
}
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET,
alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) | GLOBALTMR_INT_ENABLE_BIT);
return ALT_E_SUCCESS;
}
/*************************************************************************************************************
* alt_globaltmr_int_is_enabled() checks and returns the state of the interrupt bit of the global timer.
*************************************************************************************************************/
bool alt_globaltmr_int_is_enabled(void)
{
return alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & GLOBALTMR_INT_ENABLE_BIT;
}
/*************************************************************************************************************
* alt_globaltmr_int_clear_pending() clears the status of the interrupt pending bit of the global timer.
*************************************************************************************************************/
ALT_STATUS_CODE alt_globaltmr_int_clear_pending(void)
{
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_INT_STAT_REG_OFFSET, GLOBALTMR_INT_STATUS_BIT);
/* clear interrupt sticky bit by writing one to it */
return ALT_E_SUCCESS;
}
/*************************************************************************************************************
* alt_globaltmr_int_is_pending() checks and returns the status of the interrupt pending bit of the global
* timer.
*************************************************************************************************************/
bool alt_globaltmr_int_is_pending(void)
{
return alt_read_word(GLOBALTMR_BASE + GLOBALTMR_INT_STAT_REG_OFFSET) & GLOBALTMR_INT_STATUS_BIT;
}
/*************************************************************************************************************
* alt_globaltmr_int_if_pending_clear() checks and returns the status of the interrupt pending bit of the global
* timer. If the interrupt pending bit is set, this function also clears it.
*************************************************************************************************************/
bool alt_globaltmr_int_if_pending_clear(void)
{
bool ret;
ret = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_INT_STAT_REG_OFFSET) & GLOBALTMR_INT_STATUS_BIT;
if (ret)
{
alt_write_word(GLOBALTMR_BASE + GLOBALTMR_INT_STAT_REG_OFFSET, GLOBALTMR_INT_STATUS_BIT);
} //clear int by writing to sticky bit
return ret;
}

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FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_interrupt_armcc.s
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;*****************************************************************************
;*
;* Copyright 2013 Altera Corporation. All Rights Reserved.
;*
;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions are met:
;*
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;*
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;*
;* 3. The name of the author may not be used to endorse or promote products
;* derived from this software without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
;* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
;* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
;* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
;* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
;* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
;* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
;* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
;* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*
;*****************************************************************************/
;; This is a small stub vector put in front of the ARMCC image to support
;; interrupts.
PRESERVE8
AREA VECTORS, CODE, READONLY
ENTRY
EXPORT alt_interrupt_vector
IMPORT __main
EXPORT alt_int_handler_irq [WEAK]
alt_interrupt_vector
Vectors
LDR PC, alt_reset_addr
LDR PC, alt_undef_addr
LDR PC, alt_svc_addr
LDR PC, alt_prefetch_addr
LDR PC, alt_abort_addr
LDR PC, alt_reserved_addr
LDR PC, alt_irq_addr
LDR PC, alt_fiq_addr
alt_reset_addr DCD alt_int_handler_reset
alt_undef_addr DCD alt_int_handler_undef
alt_svc_addr DCD alt_int_handler_svc
alt_prefetch_addr DCD alt_int_handler_prefetch
alt_abort_addr DCD alt_int_handler_abort
alt_reserved_addr DCD alt_int_handler_reserve
alt_irq_addr DCD alt_int_handler_irq
alt_fiq_addr DCD alt_int_handler_fiq
alt_int_handler_reset
B alt_premain
alt_int_handler_undef
B alt_int_handler_undef
alt_int_handler_svc
B alt_int_handler_svc
alt_int_handler_prefetch
B alt_int_handler_prefetch
alt_int_handler_abort
B alt_int_handler_abort
alt_int_handler_reserve
B alt_int_handler_reserve
alt_int_handler_irq
B alt_int_handler_irq
alt_int_handler_fiq
B alt_int_handler_fiq
;=====
AREA ALT_INTERRUPT_ARMCC, CODE, READONLY
alt_premain FUNCTION
; Enable VFP / NEON.
MRC p15, 0, r0, c1, c0, 2 ; Read CP Access register
ORR r0, r0, #0x00f00000 ; Enable full access to NEON/VFP (Coprocessors 10 and 11)
MCR p15, 0, r0, c1, c0, 2 ; Write CP Access register
ISB
MOV r0, #0x40000000 ; Switch on the VFP and NEON hardware
VMSR fpexc, r0 ; Set EN bit in FPEXC
B __main
ENDFUNC
;=====
AREA ALT_INTERRUPT_ARMCC, CODE, READONLY
EXPORT alt_int_fixup_irq_stack
; void alt_int_fixup_irq_stack(uint32_t stack_irq);
; This is the same implementation of GNU but for ARMCC.
alt_int_fixup_irq_stack FUNCTION
; r4: stack_sys
PUSH {lr}
MOV r4, sp
MSR CPSR_c, #(0x12 :OR: 0x80 :OR: 0x40)
MOV sp, r0
MSR CPSR_c, #(0x1F :OR: 0x80 :OR: 0x40)
MOV sp, r4
POP {lr}
BX lr
ENDFUNC
END

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/******************************************************************************
*
* alt_nand.c - API for the Altera SoC FPGA NAND device.
*
******************************************************************************/
/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#include "hwlib.h"
#include "alt_clock_manager.h"
#include "alt_nand_flash.h"
#include "socal/alt_nand.h"
#include "socal/alt_rstmgr.h"
#include "socal/alt_sysmgr.h"
#include "socal/hps.h"
#include "socal/socal.h"
#include "alt_nand_private.h"
//#include "denali_flash_regs.h"
#include <stdbool.h>
#include <string.h>
#include <stdio.h>
static int s_nand_is_interrupt_enabled = false;
static uint32_t g_nand_interrup_status_register_poll_counter_limit;
static nand_interrupt_handler_t s_nand_interrupt_handler = NULL;
uint32_t alt_nand_number_blocks_of_plane_get(void);
static __inline uint32_t alt_nand_compose_map01_cmd_addr(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr);
static __inline uint32_t alt_nand_get_interrupt_status_register_addr(const uint32_t bank);
static __inline uint32_t alt_nand_get_interrupt_enable_register_addr(const uint32_t bank);
static __inline uint32_t alt_nand_get_device_reset_register_bank(const uint32_t bank);
uint32_t nand_read_register(const uint32_t offset);
static uint32_t real_table[ALT_HHP_NAND_NUM_OF_BLOCK_TOTAL/32];
alt_nand_bad_block_table_t nand_bad_block_table = real_table;
ALT_NAND_MGR_t nand_io =
{
(ALT_NAND_CFG_raw_t*)ALT_NAND_CFG_ADDR,
(ALT_NAND_PARAM_raw_t*)ALT_NAND_PARAM_ADDR,
(ALT_NAND_STAT_raw_t*)ALT_NAND_STAT_ADDR,
(ALT_NAND_ECC_raw_t*)ALT_NAND_ECC_ADDR,
(ALT_NAND_DMA_raw_t*)ALT_NAND_DMA_ADDR,
(uint32_t *)ALT_NANDDATA_ADDR, /*control_address */
ALT_CAST(uint32_t *, (ALT_CAST(char *, (ALT_NANDDATA_ADDR)) + 0x10))
};
ALT_NAND_MGR_t * nand = &nand_io;
FLASH_CHARACTERIZATION_t memory =
{
/*manufacturer id */ ALT_HHP_NAND_MANUFACTURER_ID,
/*device_id */ ALT_HHP_NAND_DEVICE_ID,
/*device_param_0 */ 0,
/*device_param_1 */ 0,
/*device_param_2 */ 0,
/*page_size */ ALT_HHP_NAND_PAGE_SIZE,
/*spare_size */ ALT_HHP_NAND_SPARE_SIZE,
/*revision */ ALT_HHP_NAND_REVISION,
/*onfi_device_feature */ 0,
/*onfi_optional_commands */ 0,
/*onfi_timing_mode */ 0,
/*onfi_pgm_cache_timing_mode */ 0,
/*onfi_compliant */ 1,
/*onfi_device_no_of_luns */ 0,
/*onfi_device_no_of_blocks_per_lun */ 0,
/*features */ 0,
/*number_of_planes */ ALT_HHP_NAND_NUMBER_OF_PLANES,
/*pages_per_block */ ALT_HHP_NAND_PAGES_PER_BLOCK,
/*device_width */ ALT_HHP_NAND_DEVICE_WIDTH,
/*block_size */ ALT_HHP_NAND_PAGES_PER_BLOCK * ALT_HHP_NAND_PAGE_SIZE,
/*spare_area_skip_bytes */ ALT_HHP_NAND_SPARE_SKIP,
/*first block of next plane */ ALT_HHP_NAND_FIRST_BLOCK_OF_NEXT_PLANE,
/*page_size_in_32 */ ALT_HHP_NAND_PAGE_SIZE / sizeof(uint32_t),
/*block_shift */ ALT_HHP_NAND_BLOCK_SHIFT,
/*dma_burst_length */ 0,
/*ecc_correct */ ALT_HHP_NAND_ECC_CORRECT,
};
FLASH_CHARACTERIZATION_t * flash = &memory;
ALT_STATUS_CODE alt_nand_flash_init(const bool load_block0_page0,
const bool page_size_512,
alt_nand_flash_custom_init_t custom_init,
void *user_arg)
{
ALT_NAND_CFG_raw_t * cfg = (ALT_NAND_CFG_raw_t *)(nand->cfg);
ALT_NAND_PARAM_raw_t * param = (ALT_NAND_PARAM_raw_t *)(nand->param);
ALT_STATUS_CODE ret = ALT_E_SUCCESS;
uint32_t x;
alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_NAND_SET_MSK);
alt_nand_set_sysmgr_bootstrap_value( ALT_NAND_BOOTSTRAP_INHIBIT_INIT_DISABLE,
load_block0_page0,
page_size_512,
ALT_NAND_BOOTSTRAP_TWO_ROW_ADDR_CYCLES_DISABLE
);
alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_NAND_SET_MSK);
g_nand_interrup_status_register_poll_counter_limit = (uint32_t)(-1);
ret = (*custom_init)(user_arg);
if (ret == ALT_E_RESERVED) // no custom initialization being done
{
alt_nand_reset_bank(0);
}
// Read flash device characterization
flash->manufacturer_id = alt_read_word(&param->manufacturer_id);
flash->device_id = alt_read_word(&param->device_id);
flash->device_param_0 = alt_read_word(&param->device_param_0);
flash->device_param_1 = alt_read_word(&param->device_param_1);
flash->device_param_2 = alt_read_word(&param->device_param_2);
flash->page_size = alt_read_word(&cfg->device_main_area_size);
flash->spare_size = alt_read_word(&cfg->device_spare_area_size);
flash->revision = alt_read_word(&param->revision);
flash->onfi_device_features = alt_read_word(&param->onfi_device_features);
flash->onfi_optional_commands = alt_read_word(&param->onfi_optional_commands);
flash->onfi_timing_mode = alt_read_word(&param->onfi_timing_mode);
flash->onfi_pgm_cache_timing_mode = alt_read_word(&param->onfi_pgm_cache_timing_mode);
flash->onfi_compliant = alt_read_word(&param->onfi_device_no_of_luns) >> 8;
flash->onfi_device_no_of_luns = alt_read_word(&param->onfi_device_no_of_luns) & 0xff;
x = alt_read_word(&param->onfi_device_no_of_blocks_per_lun_l);
flash->onfi_device_no_of_blocks_per_lun = (alt_read_word(&param->onfi_device_no_of_blocks_per_lun_u) << 16) + x;
flash->features = alt_read_word(&param->features);
x = alt_read_word(&cfg->number_of_planes);
switch (x)
{
case 0:
flash->number_of_planes = 1;
break;
case 1:
flash->number_of_planes = 2;
break;
case 3:
flash->number_of_planes = 4;
break;
case 7:
flash->number_of_planes = 4;
break;
default:
flash->number_of_planes = 1;
break;
}
flash->pages_per_block = alt_read_word(&cfg->pages_per_block);
// Device Width register content should automatically update SystemManager:NandGrp:BootStrap:page512 or page512x16 bit
flash->device_width = alt_read_word(&cfg->device_width);
// Set the skip bytes and then read back the result.
alt_write_word(&cfg->spare_area_skip_bytes, flash->spare_area_skip_bytes);
flash->spare_area_skip_bytes = alt_read_word(&cfg->spare_area_skip_bytes);
flash->block_size = flash->pages_per_block * flash->page_size;
flash->first_block_of_next_plane = alt_read_word(&cfg->first_block_of_next_plane);
// Set flash config based on read config
flash->page_size_32 = flash->page_size / sizeof(uint32_t);
flash->page_shift = ffs32(flash->page_size);
flash->block_shift = ffs32(flash->pages_per_block);
alt_nand_rb_pin_mode_clear(ALT_NAND_CFG_RB_PIN_END_BANK0_SET_MSK);
alt_nand_flash_ecc_disable();
alt_write_word(&cfg->first_block_of_next_plane,alt_nand_number_blocks_of_plane_get());
flash->first_block_of_next_plane = alt_read_word(&cfg->first_block_of_next_plane);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_nand_flash_uninit(void)
{
alt_nand_flash_ecc_disable();
alt_nand_dma_set_enabled( false );
return ALT_E_SUCCESS;
}
#define ALT_NAND_INVALID_FLASH_ADDR 0xffffffff
uint32_t alt_nand_block_address_get(const uint32_t addr)
{
return addr >> (flash->block_shift + flash->page_shift);
}
uint32_t alt_nand_page_address_get(const uint32_t addr)
{
return addr >> flash->page_shift & ((1 << flash->block_shift) - 1);
}
uint32_t alt_nand_flash_addr_compose(const uint32_t block_num,
const uint32_t page_num)
{
return (block_num << (flash->block_shift + flash->page_shift)) + (page_num << flash->page_shift);
}
ALT_STATUS_CODE alt_nand_flash_block_erase(const uint32_t block_addr,
alt_nand_callback_t completion_callback,
void *completion_arg)
{
int32_t ret = ALT_E_SUCCESS;
int32_t res = -1;
uint32_t bank = alt_nand_bank_get();
const uint32_t interrup_status_register = alt_nand_get_interrupt_status_register_addr( bank );
const uint32_t addr = alt_nand_compose_map10_cmd_addr( bank, block_addr, 0 );
alt_write_word(interrup_status_register, ALT_HHP_UINT32_MASK );
alt_nand_write_indirect( addr, ALT_HHP_NAND_10_OP_ERASE_BLOCK );
res = alt_nand_poll_for_interrupt_status_register(interrup_status_register,
ALT_NAND_INT_STATUS_TIME_OUT |
ALT_NAND_INT_STATUS_ERASE_COMP |
ALT_NAND_INT_STATUS_ERASE_FAIL);
if (!(res & ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_SET_MSK))
{
//printf("FAIL: erasing not complete. (%08lX, %ld)\n", res, block_addr);
ret = ALT_E_ERROR;
}
return ret;
}
ALT_STATUS_CODE alt_nand_flash_page_read(const uint32_t page_addr,
const uint32_t num_pages,
void *dest,
const uint32_t dest_size)
{
// currently only one page
uint32_t bank = alt_nand_bank_get();
uint32_t page = alt_nand_page_address_get(page_addr);
uint32_t block = alt_nand_block_address_get(page_addr);
return alt_nand_full_page_read_with_map10( bank, block, page, (uint32_t *)dest);
}
ALT_STATUS_CODE alt_nand_flash_page_write(const uint32_t page_addr,
const uint32_t num_pages,
const void *src,
const uint32_t src_size)
{
// currently only one page
uint32_t bank = alt_nand_bank_get();
uint32_t page = alt_nand_page_address_get(page_addr);
uint32_t block = alt_nand_block_address_get(page_addr);
return alt_nand_full_page_write_with_map10( bank, block, page, (uint32_t *)src);
}
ALT_STATUS_CODE alt_nand_flash_page_dma_read(const uint32_t page_addr,
const uint32_t num_pages,
void *dest,
const uint32_t dest_size,
alt_nand_callback_t completion_callback,
void *completion_arg)
{
ALT_STATUS_CODE status = ALT_E_SUCCESS;
uint32_t mem_addr = page_addr;
uint32_t dest_addr = (uint32_t)dest;
uint32_t buff_size = dest_size;
uint32_t bank = alt_nand_bank_get();
uint32_t page;
uint32_t block;
for (int i = 0; (i < num_pages) && (buff_size >= flash->page_size); i++) {
page = alt_nand_page_address_get(mem_addr);
block = alt_nand_block_address_get(mem_addr);
status = alt_nand_dma_page_read(bank, block, page, dest_addr);
if (status == ALT_E_SUCCESS)
{
mem_addr += flash->page_size;
dest_addr += flash->page_size;
buff_size -= flash->page_size;
}
else
break;
}
if (status == ALT_E_SUCCESS)
{
(*completion_callback)(status, completion_arg);
}
return status;
}
ALT_STATUS_CODE alt_nand_flash_page_dma_write(const uint32_t page_addr,
const uint32_t num_pages,
const void *src,
const uint32_t src_size,
alt_nand_callback_t completion_callback,
void *completion_arg)
{
ALT_STATUS_CODE status = ALT_E_SUCCESS;
uint32_t mem_addr = page_addr;
uint32_t src_addr = (uint32_t)src;
uint32_t buff_size = src_size;
uint32_t bank = alt_nand_bank_get();
uint32_t page;
uint32_t block;
for (int i = 0; (i < num_pages) && (buff_size >= flash->page_size); i++) {
page = alt_nand_page_address_get(mem_addr);
block = alt_nand_block_address_get(mem_addr);
status = alt_nand_dma_page_write(bank, block, page, src_addr);
if (status == ALT_E_SUCCESS)
{
mem_addr += flash->page_size;
src_addr += flash->page_size;
buff_size -= flash->page_size;
}
else
break;
}
if (status == ALT_E_SUCCESS)
{
(*completion_callback)(status, completion_arg);
}
return status;
}
ALT_STATUS_CODE alt_nand_flash_ecc_enable(const ALT_NAND_ECC_CORRECTION_t ecc_correction)
{
ALT_NAND_CFG_raw_t * cfg = (ALT_NAND_CFG_raw_t *)(nand->cfg);
alt_setbits_word(&cfg->ecc_enable, ALT_NAND_CFG_ECC_EN_FLAG_SET_MSK);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_nand_flash_ecc_disable(void)
{
ALT_NAND_CFG_raw_t * cfg = (ALT_NAND_CFG_raw_t *)(nand->cfg);
alt_clrbits_word(&cfg->ecc_enable, ALT_NAND_CFG_ECC_EN_FLAG_SET_MSK);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_nand_flash_ecc_status_get(ALT_NAND_FLASH_ECC_STATUS_t *ecc_status)
{
ALT_NAND_ECC_raw_t * ecc = (ALT_NAND_ECC_raw_t *)(nand->ecc);
uint32_t status;
status = alt_read_word(&ecc->ECCCorInfo_b01);
ecc_status->corrected_errors[0] = (status & ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_LSB;
ecc_status->corrected_errors[1] = (status & ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_LSB;
ecc_status->uncorrected_error[0] = (status & ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_LSB;
ecc_status->uncorrected_error[1] = (status & ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_LSB;
status = alt_read_word(&ecc->ECCCorInfo_b23);
ecc_status->corrected_errors[2] = (status & ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_LSB;
ecc_status->corrected_errors[3] = (status & ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_LSB;
ecc_status->uncorrected_error[2] = (status & ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_LSB;
ecc_status->uncorrected_error[3] = (status & ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_LSB;
return ALT_E_SUCCESS;
}
uint32_t alt_nand_int_status_get(void)
{
uint32_t bank = alt_nand_bank_get();
uint32_t reg = alt_nand_get_interrupt_status_register_addr(bank);
return alt_read_word(reg);
}
ALT_STATUS_CODE alt_nand_int_clear(const uint32_t mask)
{
uint32_t bank = alt_nand_bank_get();
uint32_t reg = alt_nand_get_interrupt_status_register_addr(bank);
alt_setbits_word(reg, mask);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_nand_int_disable(const uint32_t mask)
{
uint32_t bank = alt_nand_bank_get();
uint32_t reg = alt_nand_get_interrupt_enable_register_addr(bank);
alt_clrbits_word(reg, mask);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_nand_int_enable(const uint32_t mask)
{
uint32_t bank = alt_nand_bank_get();
uint32_t reg = alt_nand_get_interrupt_enable_register_addr(bank);
alt_setbits_word(reg, mask);
return ALT_E_SUCCESS;
}
uint32_t alt_nand_num_planes_get(void)
{
return flash->number_of_planes;
}
uint32_t alt_nand_number_blocks_of_plane_get(void)
{
return (flash->onfi_device_no_of_blocks_per_lun / flash->number_of_planes);
}
uint32_t alt_nand_first_block_of_next_plane(void)
{
return flash->first_block_of_next_plane;
}
uint32_t alt_nand_num_blocks_get(void)
{
return (alt_nand_num_planes_get() * alt_nand_number_blocks_of_plane_get()) ;
}
uint32_t alt_nand_num_pages_per_block_get(void)
{
return flash->pages_per_block;
}
uint32_t alt_nand_sector_size_get(void)
{
return ALT_HHP_NAND_SECTOR_SIZE;
}
uint32_t alt_nand_spare_size_get(void)
{
return flash->spare_size;
}
bool alt_nand_block_is_bad(const uint32_t block_addr)
{
return false;
}
ALT_STATUS_CODE alt_nand_bad_block_table_get(alt_nand_bad_block_table_t bad_block_table,
const uint32_t bad_block_table_len)
{
alt_nand_callback_t dma_callback = &alt_nand_dma_page_callback;
uint32_t completion_arg = 0;
uint32_t total_blocks = (flash->onfi_device_no_of_luns * flash->onfi_device_no_of_blocks_per_lun);
uint32_t addr = (total_blocks - 1) << (flash->block_shift + flash->page_shift); // highest block is reseved for bad block table
uint32_t buff[ALT_HHP_NAND_PAGE_SIZE];
alt_nand_flash_page_dma_read( addr, 1, buff, sizeof(buff), dma_callback, &completion_arg);
for (int i = 0; i <ALT_HHP_NAND_NUM_OF_BLOCK_TOTAL/32; i++)
{
bad_block_table[i] = buff[i];
}
return ALT_E_SUCCESS;
}
void alt_nand_rb_pin_mode_set(uint32_t mask)
{
ALT_NAND_CFG_raw_t * cfg = (ALT_NAND_CFG_raw_t *)(nand->cfg);
alt_setbits_word(&cfg->rb_pin_enabled, mask);
}
void alt_nand_rb_pin_mode_clear(uint32_t mask)
{
ALT_NAND_CFG_raw_t * cfg = (ALT_NAND_CFG_raw_t *)(nand->cfg);
alt_clrbits_word(&cfg->rb_pin_enabled, mask);
}
void alt_nand_reset_bank(uint32_t bank)
{
ALT_NAND_CFG_raw_t * cfg = (ALT_NAND_CFG_raw_t *)(nand->cfg);
uint32_t interrup_status_register = alt_nand_get_interrupt_status_register_addr(bank);
uint32_t device_reset_bank = alt_nand_get_device_reset_register_bank(bank);
// Write on clear of all interrupt status
alt_write_word(interrup_status_register, ALT_HHP_UINT32_MASK);
// Controller sends a RESET command to device
alt_setbits_word(&cfg->device_reset, device_reset_bank);
alt_nand_poll_for_interrupt_status_register(interrup_status_register, ALT_NAND_STAT_INTR_STAT0_RST_COMP_SET_MSK);
// Write on clear of all interrupt status
alt_write_word(interrup_status_register, ALT_HHP_UINT32_MASK);
}
/*
* Count the consecutive zero bits (trailing) on the right in parallel
*
* Some bit fiddleing stuff.
* From... http://graphics.stanford.edu/~seander/bithacks.html
*/
uint32_t ffs32(uint32_t v)
{
uint32_t r = 0;
do
{
if(v == 0)
break;
if(v & 0xFFFF0000){v >>= 16;r |= 16;}
if(v & 0x0000FF00){v >>= 8;r |= 8;}
if(v & 0x000000F0){v >>= 4;r |= 4;}
if(v & 0x0000000C){v >>= 2;r |= 2;}
if(v & 0x00000002){ ;r |= 1;}
} while(0);
return(r);
}
uint32_t alt_nand_poll_for_interrupt_status_register(uint32_t interrup_status_register, uint32_t interrup_status_mask )
{
uint32_t ret;
uint32_t i = 0;
if ( !s_nand_is_interrupt_enabled )
{
ret = alt_read_word( interrup_status_register );
while( !( ret & (interrup_status_mask | ALT_NAND_INT_STATUS_UNSUP_CMD ) ) )
{
ret = alt_read_word( interrup_status_register );
//printf("<alt_nand_poll for interrupt status register>->interrupt status reg = %08lX\n", ret);
if ( ++i == g_nand_interrup_status_register_poll_counter_limit )
{
break;
}
}
if ( ret & ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET_MSK )
{
//printf( "Warning: Unsupported CMD interrupt INTR_STATUS_UNSUP_CMD is raised!!!!\n" );
}
}
else
{
ret = s_nand_interrupt_handler( interrup_status_register, interrup_status_mask );
}
return ret;
}
int32_t alt_nand_full_page_read_with_map10(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t *buffer )
{
int32_t ret = ALT_E_SUCCESS;
int32_t res = -1;
const uint32_t PAGES_TO_READ = 1; // NOTE: Only 2 bits wide
const uint32_t interrup_status_register = alt_nand_get_interrupt_status_register_addr( bank );
const uint32_t addr = alt_nand_compose_map10_cmd_addr( bank, block_addr, page_addr );
alt_write_word( interrup_status_register, ALT_HHP_UINT32_MASK );
// Sets up a pipeline read-ahead of for a read (0x2001)
alt_nand_write_indirect( addr, ALT_HHP_NAND_10_OP_READ_PIPE | PAGES_TO_READ );
res = alt_nand_poll_for_interrupt_status_register( interrup_status_register,
ALT_NAND_INT_STATUS_TIME_OUT |
ALT_NAND_INT_STATUS_LOAD_COMP );
if((res & ALT_NAND_INT_STATUS_LOAD_COMP) != 0)
{
alt_nand_full_page_read_with_map10_post_read_with_map01( bank, block_addr, page_addr, buffer);
}
else
{
//printf("FAIL: Timeout loading NAND page. (%08lX,%ld,%ld)\n", res, bank, page_addr);
ret = ALT_E_ERROR;
}
return ret;
}
uint32_t alt_nand_get_device_reset_register_bank(const uint32_t bank)
{
uint32_t ret=0;
switch( bank )
{
case 0:
ret = ALT_NAND_CFG_DEVICE_RST_BANK0_SET_MSK;
break;
case 1:
ret = ALT_NAND_CFG_DEVICE_RST_BANK1_SET_MSK;
break;
case 2:
ret = ALT_NAND_CFG_DEVICE_RST_BANK2_SET_MSK;
break;
case 3:
ret = ALT_NAND_CFG_DEVICE_RST_BANK3_SET_MSK;
break;
default:
// info_assert(0, "Do not support more than 4 banks");
break;
}
return ret;
}
uint32_t alt_nand_get_interrupt_status_register_addr(const uint32_t bank)
{
ALT_NAND_STAT_raw_t * stat = (ALT_NAND_STAT_raw_t *)(nand->stat);
uint32_t ret=0;
switch( bank )
{
case 0:
ret = (uint32_t)(&stat->intr_status0);
break;
case 1:
ret = (uint32_t)(&stat->intr_status1);
break;
case 2:
ret = (uint32_t)(&stat->intr_status2);
break;
case 3:
ret = (uint32_t)(&stat->intr_status3);
break;
default:
// info_assert(0, "Do not support more than 4 banks");
break;
}
return ret;
}
uint32_t alt_nand_get_interrupt_enable_register_addr(uint32_t bank)
{
uint32_t interrup_enable_register=0;
ALT_NAND_STAT_raw_t * stat = (ALT_NAND_STAT_raw_t *)(nand->stat);
switch( bank )
{
case 0:
interrup_enable_register = (uint32_t)(&stat->intr_en0);
//printf("interrupt status register: %08lX \n", interrup_enable_register);
break;
case 1:
interrup_enable_register = (uint32_t)(&stat->intr_en1);
break;
case 2:
interrup_enable_register = (uint32_t)(&stat->intr_en2);
break;
case 3:
interrup_enable_register = (uint32_t)(&stat->intr_en3);
break;
default:
// info_assert(0, "Do not support more than 4 banks");
break;
}
return interrup_enable_register;
}
uint32_t alt_nand_compose_map01_cmd_addr(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr)
{
const uint32_t BANK_MASK = 0x3;
const uint32_t BLOCK_ADDR_MASK = (1 << (23 - flash->block_shift + 1)) - 1;
const uint32_t PAGE_ADDR_MASK = (1 << flash->block_shift) - 1;
const uint32_t ret = ALT_HHP_NAND_MODE_01 |
((bank & BANK_MASK) << ALT_HHP_NAND_ADDR_MAP_BANK_SEL_LSB_INDEX) |
((block_addr & BLOCK_ADDR_MASK) << flash->block_shift) |
(page_addr & PAGE_ADDR_MASK);
return ret;
}
uint32_t alt_nand_compose_map10_cmd_addr(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr)
{
const uint32_t BANK_MASK = 0x3;
const uint32_t BLOCK_ADDR_MASK = (1 << (23 - flash->block_shift + 1)) - 1;
const uint32_t PAGE_ADDR_MASK = (1 << flash->block_shift) - 1;
const uint32_t ret = ALT_HHP_NAND_MODE_10 |
((bank & BANK_MASK) << ALT_HHP_NAND_ADDR_MAP_BANK_SEL_LSB_INDEX) |
((block_addr & BLOCK_ADDR_MASK) << flash->block_shift) |
(page_addr & PAGE_ADDR_MASK);
return ret;
}
void alt_nand_write_indirect(const uint32_t address, const uint32_t value)
{
alt_write_word(nand->ctrl_addr, address);
alt_write_word(nand->data_addr, value);
}
uint32_t alt_nand_read_indirect(const uint32_t address)
{
alt_write_word(nand->ctrl_addr, address);
return alt_read_word(nand->data_addr);
}
void alt_nand_full_page_read_with_map10_post_read_with_map01(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t *buffer)
{
const uint32_t addr = alt_nand_compose_map01_cmd_addr( bank, block_addr, page_addr );
uint32_t *cur = buffer;
uint32_t i;
for( i = 0; i < flash->page_size_32; ++i )
{
*cur++ = alt_nand_read_indirect( addr );
}
}
int32_t alt_nand_full_page_write_with_map10(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, const uint32_t *buffer)
{
int32_t ret = 0;
int32_t res = -1;
const uint32_t PAGES_TO_READ = 1; // NOTE: Only 2 bits wide
const uint32_t interrup_status_register = alt_nand_get_interrupt_status_register_addr( bank );
const uint32_t addr = alt_nand_compose_map10_cmd_addr( bank, block_addr, page_addr );
alt_write_word( interrup_status_register, ALT_HHP_UINT32_MASK );
// Sets up a pipeline read-ahead of “01” pages.“W” = 0 for a read (0x2001)
alt_nand_write_indirect( addr, ALT_HHP_NAND_10_OP_WRITE_PIPE | PAGES_TO_READ );
//
// don't forget this one, it is a hardware bug
//
for (int i = 0; i < 10000; i++) ;
// Temporarily disable status check as RTL doesn't seem to raise any flag.
// But, it works.
//res = alt_nand_poll_for_interrupt_status_register( interrup_status_register, INTR_STATUS0__TIME_OUT | INTR_STATUS0__PIPE_CPYBCK_CMD_COMP );
res = ALT_NAND_INT_STATUS_PIPE_CPYBCK_CMD_COMP;
if((res & ALT_NAND_INT_STATUS_PIPE_CPYBCK_CMD_COMP) != 0)
{
alt_nand_full_page_write_with_map10_post_write_with_map01( bank, block_addr, page_addr, buffer );
}
else
{
//printf("FAIL: Timeout loading NAND page. (%08lX,%ld,%ld)\n", res, bank, page_addr);
ret = 1;
}
return ret;
}
void alt_nand_full_page_write_with_map10_post_write_with_map01(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, const uint32_t *buffer)
{
const uint32_t addr = alt_nand_compose_map01_cmd_addr( bank, block_addr, page_addr );
const uint32_t *cur = buffer;
uint32_t i;
for( i = 0; i < flash->page_size_32; ++i )
{
alt_nand_write_indirect( addr, *cur++ );
}
}
void alt_nand_set_sysmgr_bootstrap_value( uint32_t bootstrp_inhibit_init,
uint32_t bootstrp_inhibit_b0p0_load,
uint32_t bootstrp_512b_device,
uint32_t bootstrp_two_row_addr_cycles)
{
uint32_t settings = ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET(bootstrp_inhibit_init) |
ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET(bootstrp_512b_device) |
ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET(bootstrp_inhibit_b0p0_load) |
ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET(bootstrp_two_row_addr_cycles);
alt_write_word(ALT_SYSMGR_NAND_BOOTSTRAP_ADDR, settings);
}
uint32_t alt_nand_bank_get(void)
{
// on SOC, only bank 0 of physical memory is connected
return ALT_NAND_FLASH_MEM_BANK_0;
}
int32_t alt_nand_dma_page_write( const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t mem_addr )
{
int32_t ret = 0;
uint32_t res;
const uint32_t interrup_status_register = alt_nand_get_interrupt_status_register_addr( bank );
alt_write_word( interrup_status_register, ALT_HHP_UINT32_MASK );
alt_nand_dma_set_enabled( true );
alt_nand_dma_write_cmd_structure( bank, block_addr, page_addr, 1, mem_addr, false, 64);
res = alt_nand_poll_for_interrupt_status_register( interrup_status_register,
ALT_NAND_INT_STATUS_DMA_CMD_COMP |
ALT_NAND_INT_STATUS_PROGRAM_FAIL |
ALT_NAND_INT_STATUS_LOCKED_BLK );
// 10.8. Order of interrupt status bits assertion 8.
if ( !(res & ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET_MSK) )
{
//printf( "Error: DMA command is incomplete: 0x%lx\n", res );
ret = res;
}
alt_nand_dma_set_enabled( false );
return ret;
}
int32_t alt_nand_dma_page_read( const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t mem_addr )
{
int32_t ret = 0;
uint32_t res;
const uint32_t interrup_status_register = alt_nand_get_interrupt_status_register_addr( bank );
alt_write_word( interrup_status_register, ALT_HHP_UINT32_MASK );
alt_nand_dma_set_enabled( true );
alt_nand_dma_write_cmd_structure( bank, block_addr, page_addr, 1, mem_addr, true, 64 );
res = alt_nand_poll_for_interrupt_status_register( interrup_status_register,
ALT_NAND_INT_STATUS_DMA_CMD_COMP |
ALT_NAND_INT_STATUS_ECC_UNCOR_ERR);
// 10.8. Order of interrupt status bits assertion 9.
if ( !(res & ALT_NAND_INT_STATUS_DMA_CMD_COMP) )
{
//printf( "Error: DMA command is incomplete: 0x%lx\n", res );
ret = res;
}
alt_nand_dma_set_enabled( false );
return ret;
}
void alt_nand_dma_set_enabled( int32_t is_enabled )
{
ALT_NAND_DMA_raw_t * dma = (ALT_NAND_DMA_raw_t *)(nand->dma);
alt_write_word(&dma->dma_enable, ( is_enabled ? ALT_NAND_DMA_DMA_EN_FLAG_SET_MSK : 0 ) );
alt_read_word( &dma->dma_enable);
}
void alt_nand_dma_write_cmd_structure( const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, const uint32_t page_count, uint64_t mem_addr, int32_t is_read_op, const uint32_t burst_len )
{
const uint32_t MODE_BANK_MASK = 0xFF000000;
uint32_t addr = alt_nand_compose_map10_cmd_addr( bank, block_addr, page_addr );
// Transaction 1
// Table 7.2. Address Encoding
// Table 7.3. Data
alt_nand_write_indirect( addr, 0x2000 | (is_read_op ? 0x0 : 0x100) | page_count);
// Transaction 2
// Table 7.4. Address Encoding
// Table 7.5. Data
addr &= MODE_BANK_MASK;
addr |= ((uint16_t)(mem_addr >> 16) << 8);
alt_nand_write_indirect( addr, 0x2200 );
// Transaction 3
// Table 7.6. Address Encoding
// Table 7.7. Data
addr &= MODE_BANK_MASK;
addr |= ((uint16_t)mem_addr << 8);
alt_nand_write_indirect( addr, 0x2300 );
// Transaction 4
// Table 7.8. Address Encoding
// Table 7.9. Data
addr &= MODE_BANK_MASK;
addr |= 0x10000 | burst_len << 8; // Enable INTR_STATUS__DMA_CMD_COMP always.
alt_nand_write_indirect( addr, 0x2400);
}
ALT_STATUS_CODE alt_nand_flash_init_manual(void *user_arg)
{
//printf("Entered Custom Init Routine for NAND.\n");
return ALT_E_RESERVED;
}
void alt_nand_erase_block_callback(ALT_STATUS_CODE status, void *callback_arg)
{
//printf("NAND Block Erase Callback is successful.\n");
return;
}
void alt_nand_dma_page_callback(ALT_STATUS_CODE status, void *callback_arg)
{
//printf("NAND DMA read Callback is successful.\n");
return;
}
uint32_t nand_read_register(const uint32_t offset)
{
return alt_read_word(&nand->cfg + offset);
}

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FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_qspi.c
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135
FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_reset_manager.c
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/******************************************************************************
*
* alt_reset_manager.c - API for the Altera SoC FPGA reset manager.
*
******************************************************************************/
/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#include "alt_reset_manager.h"
#include "socal/socal.h"
#include "socal/hps.h"
#include "socal/alt_rstmgr.h"
/////
uint32_t alt_reset_event_get(void)
{
return alt_read_word(ALT_RSTMGR_STAT_ADDR);
}
ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask)
{
alt_write_word(ALT_RSTMGR_STAT_ADDR, event_mask);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_reset_cold_reset(void)
{
alt_write_word(ALT_RSTMGR_CTL_ADDR, ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay,
uint32_t nRST_pin_clk_assertion,
bool sdram_refresh_enable,
bool fpga_mgr_handshake,
bool scan_mgr_handshake,
bool fpga_handshake,
bool etr_stall)
{
// Cached register values
uint32_t ctrl_reg = ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK;
uint32_t counts_reg = 0;
/////
// Validate warm_reset_delay is above 16 and below the field width
if ((warm_reset_delay < 16) || (warm_reset_delay >= (1 << ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH)))
{
return ALT_E_BAD_ARG;
}
// Validate nRST_pin_clk_assertion delay is non-zero and below the field width
if (!nRST_pin_clk_assertion)
{
return ALT_E_ERROR;
}
if (nRST_pin_clk_assertion >= (1 << ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH))
{
return ALT_E_BAD_ARG;
}
// Update counts register with warm_reset_delay information
counts_reg |= ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(warm_reset_delay);
// Update counts register with nRST_pin_clk_assertion information
counts_reg |= ALT_RSTMGR_COUNTS_NRSTCNT_SET(nRST_pin_clk_assertion);
/////
// Update ctrl register with the specified option flags
if (sdram_refresh_enable)
{
ctrl_reg |= ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK;
}
if (fpga_mgr_handshake)
{
ctrl_reg |= ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK;
}
if (scan_mgr_handshake)
{
ctrl_reg |= ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK;
}
if (fpga_handshake)
{
ctrl_reg |= ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK;
}
if (etr_stall)
{
ctrl_reg |= ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK;
}
/////
// Commit registers to hardware
alt_write_word(ALT_RSTMGR_COUNTS_ADDR, counts_reg);
alt_write_word(ALT_RSTMGR_CTL_ADDR, ctrl_reg);
return ALT_E_SUCCESS;
}

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/******************************************************************************
*
* alt_system_manager.c - API for the Altera SoC FPGA system manager
*
******************************************************************************/
/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#include "alt_system_manager.h"
#include "socal/alt_sysmgr.h"
#include "socal/socal.h"
#include "socal/hps.h"
/////
ALT_STATUS_CODE alt_fpga_interface_enable(ALT_FPGA_INTERFACE_t intfc)
{
switch (intfc)
{
case ALT_FPGA_INTERFACE_GLOBAL:
return alt_setbits_word(ALT_SYSMGR_FPGAINTF_GBL_ADDR,
ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK);
case ALT_FPGA_INTERFACE_RESET_REQ:
return alt_setbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR,
ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK);
case ALT_FPGA_INTERFACE_JTAG_ENABLE:
return alt_setbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR,
ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK);
case ALT_FPGA_INTERFACE_CONFIG_IO:
return alt_setbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR,
ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK);
case ALT_FPGA_INTERFACE_BSCAN:
return alt_setbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR,
ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK);
case ALT_FPGA_INTERFACE_TRACE:
return alt_setbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR,
ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK);
case ALT_FPGA_INTERFACE_DBG_APB:
return alt_setbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR,
1 << 5);
case ALT_FPGA_INTERFACE_STM:
return alt_setbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR,
ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK);
case ALT_FPGA_INTERFACE_CTI:
return alt_setbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR,
ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK);
case ALT_FPGA_INTERFACE_EMAC0:
return alt_setbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR,
ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK);
case ALT_FPGA_INTERFACE_EMAC1:
return alt_setbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR,
ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK);
case ALT_FPGA_INTERFACE_SPIM0:
return alt_setbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR,
1 << 0);
case ALT_FPGA_INTERFACE_SPIM1:
return alt_setbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR,
1 << 1);
case ALT_FPGA_INTERFACE_NAND:
return alt_setbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR,
1 << 4);
case ALT_FPGA_INTERFACE_SDMMC:
return alt_setbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR,
1 << 5);
default:
return ALT_E_BAD_ARG;
}
}
ALT_STATUS_CODE alt_fpga_interface_disable(ALT_FPGA_INTERFACE_t intfc)
{
switch (intfc)
{
case ALT_FPGA_INTERFACE_GLOBAL:
return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_GBL_ADDR,
ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK);
case ALT_FPGA_INTERFACE_RESET_REQ:
return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR,
ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK);
case ALT_FPGA_INTERFACE_JTAG_ENABLE:
return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR,
ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK);
case ALT_FPGA_INTERFACE_CONFIG_IO:
return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR,
ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK);
case ALT_FPGA_INTERFACE_BSCAN:
return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR,
ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK);
case ALT_FPGA_INTERFACE_TRACE:
return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR,
ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK);
case ALT_FPGA_INTERFACE_DBG_APB:
return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR,
1 << 5);
case ALT_FPGA_INTERFACE_STM:
return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR,
ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK);
case ALT_FPGA_INTERFACE_CTI:
return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR,
ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK);
case ALT_FPGA_INTERFACE_EMAC0:
return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR,
ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK);
case ALT_FPGA_INTERFACE_EMAC1:
return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR,
ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK);
case ALT_FPGA_INTERFACE_SPIM0:
return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR,
1 << 0);
case ALT_FPGA_INTERFACE_SPIM1:
return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR,
1 << 1);
case ALT_FPGA_INTERFACE_NAND:
return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR,
1 << 4);
case ALT_FPGA_INTERFACE_SDMMC:
return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR,
1 << 5);
default:
return ALT_E_BAD_ARG;
}
}
ALT_STATUS_CODE alt_fpga_interface_is_enabled(ALT_FPGA_INTERFACE_t intfc)
{
switch (intfc)
{
case ALT_FPGA_INTERFACE_GLOBAL:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_GBL_ADDR) &
ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_RESET_REQ:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) &
ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_JTAG_ENABLE:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) &
ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_CONFIG_IO:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) &
ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_BSCAN:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) &
ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_TRACE:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) &
ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_DBG_APB:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) &
(1 << 5)) != 0) ? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_STM:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) &
ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_CTI:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) &
ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_EMAC0:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) &
ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_EMAC1:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) &
ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_SPIM0:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) &
(1 << 0)) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_SPIM1:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) &
(1 << 1)) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_NAND:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) &
(1 << 4)) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_SDMMC:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) &
(1 << 5)) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
default:
return ALT_E_BAD_ARG;
}
}

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/*! \file
* Altera - SoC FPGA Address Space Manager
*/
/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ALT_ADDRESS_SPACE_H__
#define __ALT_ADDRESS_SPACE_H__
#include <stdbool.h>
#include "hwlib.h"
#include "socal/hps.h"
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/******************************************************************************/
// ARM Level 2 Cache Controller L2C-310 Register Interface
// Address Filtering Start Register
// The Address Filtering Start Register is a read and write register.
// Bits Field Description
// :-------|:--------------------------|:-----------------------------------------
// [31:20] | address_filtering_start | Address filtering start address for
// | | bits [31:20] of the filtering address.
// [19:1] | Reserved | SBZ/RAZ
// [0] | address_filtering_enable | 0 - address filtering disabled
// | | 1 - address filtering enabled.
// Address Filtering Start Register Address
#define L2_CACHE_ADDR_FILTERING_START_OFST 0xC00
#define L2_CACHE_ADDR_FILTERING_START_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_START_OFST)
// Address Filtering Start Register - Start Value Mask
#define L2_CACHE_ADDR_FILTERING_START_ADDR_MASK 0xFFF00000
// Address Filtering Start Register - Reset Start Address Value (1 MB)
#define L2_CACHE_ADDR_FILTERING_START_RESET 0x100000
// Address Filtering Start Register - Enable Flag Mask
#define L2_CACHE_ADDR_FILTERING_ENABLE_MASK 0x00000001
// Address Filtering Start Register - Reset Enable Flag Value (Enabled)
#define L2_CACHE_ADDR_FILTERING_ENABLE_RESET 0x1
// Address Filtering End Register
// The Address Filtering End Register is a read and write register.
// Bits Field Description
// :-------|:--------------------------|:-----------------------------------------
// [31:20] | address_filtering_end | Address filtering end address for bits
// | | [31:20] of the filtering address.
// [19:0] | Reserved | SBZ/RAZ
// Address Filtering End Register Address
#define L2_CACHE_ADDR_FILTERING_END_OFST 0xC04
#define L2_CACHE_ADDR_FILTERING_END_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_END_OFST)
// Address Filtering End Register - End Value Mask
#define L2_CACHE_ADDR_FILTERING_END_ADDR_MASK 0xFFF00000
// Address Filtering End Register - Reset End Address Value (3 GiB)
#define L2_CACHE_ADDR_FILTERING_END_RESET 0xC0000000
#ifndef __ASSEMBLY__
/******************************************************************************/
/*! \addtogroup ADDR_SPACE_MGR The Address Space Manager
*
* This module contains group APIs for managing the HPS address space. This
* module contains group APIs to manage:
* * Memory Map Control
* * Memory Coherence
* * Cache Managment
* * MMU Managment
*
* @{
*/
/******************************************************************************/
/*! \addtogroup ADDR_SPACE_MGR_REMAP Address Space Mapping Control
*
* This group API provides functions to map and remap selected address ranges
* into the accessible (visible) views of the MPU and non MPU address spaces.
*
* \b Caveats
*
* \b NOTE: Caution should be observed when remapping address 0 to different
* memory. The code performing the remapping operation should not be executing
* in the address range being remapped to different memory.
*
* For example, if address 0 is presently mapped to OCRAM and the code is
* preparing to remap address 0 to SDRAM, then the code must not be executing in
* the range 0 to 64 KB as this address space is about to be remapped to
* different memory. If the code performing the remap operation is executing
* from OCRAM then it needs to be executing from its permanently mapped OCRAM
* address range in upper memory (i.e. ALT_OCRAM_LB_ADDR to ALT_OCRAM_UB_ADDR).
*
* \b NOTE: The MPU address space view is controlled by two disparate hardware
* control interfaces: the L3 remap register and the L2 cache address filtering
* registers. To complicate matters, the L3 remap register is write-only which
* means not only that current remap register state cannot be read but also that
* a read-modify-write operation cannot be performed on the register.
*
* This should not present a problem in most use case scenarios except for the
* case where a current MPU address space mapping of 0 to SDRAM is being changed
* to to a mapping of 0 to Boot ROM or OCRAM.
*
* In this case, a two step process whereby the L3 remap register is first set
* to the new desired MPU address 0 mapping and then the L2 cache address
* filtering registers have their address ranges adjusted accordingly must be
* followed. An example follows:
\verbatim
// 1 MB reset default value for address filtering start
#define L2_CACHE_ADDR_FILTERING_START_RESET 0x100000
uint32_t addr_filt_start;
uint32_t addr_filt_end;
// Perform L3 remap register programming first by setting the desired new MPU
// address space 0 mapping. Assume OCRAM for the example.
alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM, ...);
// Next, adjust the L2 cache address filtering range. Set the start address to
// the default reset value and retain the existing end address configuration.
alt_l2_addr_filter_cfg_get(&addr_filt_start, &addr_filt_end);
if (addr_filt_start != L2_CACHE_ADDR_FILTERING_START_RESET)
{
alt_l2_addr_filter_cfg_set(L2_CACHE_ADDR_FILTERING_START_RESET, addr_filt_end);
}
\endverbatim
* @{
*/
/******************************************************************************/
/*!
* This type definition enumerates the MPU address space attributes.
*
* The MPU address space consists of the ARM Cortex A9 processors and associated
* processor peripherals (cache, MMU).
*/
typedef enum ALT_ADDR_SPACE_MPU_ATTR_e
{
ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM, /*!< Maps the Boot ROM to address
* 0x0 for the MPU L3 master. Note
* that the Boot ROM is also
* always mapped to address
* 0xfffd_0000 for the MPU L3
* master independent of
* attribute.
*/
ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address
* 0x0 for the MPU L3 master. Note
* that the On-chip RAM is also
* always mapped to address
* 0xffff_0000 for the MPU L3
* master independent of this
* attribute.
*/
} ALT_ADDR_SPACE_MPU_ATTR_t;
/******************************************************************************/
/*!
* This type definition enumerates the non-MPU address space attributes.
*
* The non-MPU address space consists of the non-MPU L3 masters including the
* DMA controllers (standalone and those built into peripherals), the F2H AXI
* Bridge, and the DAP.
*/
typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e
{
ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM, /*!< Maps the SDRAM to address 0x0
* for the non-MPU L3 masters.
*/
ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address
* 0x0 for the non-MPU L3
* masters. Note that the On-chip
* RAM is also always mapped to
* address 0xffff_0000 for the
* non-MPU L3 masters independent
* of this attribute.
*/
} ALT_ADDR_SPACE_NONMPU_ATTR_t;
/******************************************************************************/
/*!
* This type definition enumerates the HPS to FPGA bridge accessiblity
* attributes.
*/
typedef enum ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_e
{
ALT_ADDR_SPACE_H2F_INACCESSIBLE, /*!< The H2F AXI Bridge is not
* visible to L3 masters. Accesses
* to the associated address range
* return an AXI decode error to
* the master.
*/
ALT_ADDR_SPACE_H2F_ACCESSIBLE /*!< The H2F AXI Bridge is visible
* to L3 masters.
*/
} ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t;
/******************************************************************************/
/*!
* This type definition enumerates the Lightweight HPS to FPGA bridge
* accessiblity attributes.
*/
typedef enum ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_e
{
ALT_ADDR_SPACE_LWH2F_INACCESSIBLE, /*!< The LWH2F AXI Bridge is not
* visible to L3 masters. Accesses
* to the associated address range
* return an AXI decode error to
* the master.
*/
ALT_ADDR_SPACE_LWH2F_ACCESSIBLE /*!< The LWH2F AXI Bridge is visible
* to L3 masters.
*/
} ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t;
/******************************************************************************/
/*!
* Configures the mapped and accessible (visible) address ranges for the HPS
* MPU, non-MPU, and Bridge address spaces.
*
* \param mpu_attr
* The MPU address space configuration attributes.
*
* \param nonmpu_attr
* The non-MPU address space configuration attributes.
*
* \param h2f_attr
* The H2F Bridge attribute mapping and accessibility attributes.
*
* \param lwh2f_attr
* The Lightweight H2F Bridge attribute mapping and accessibility
* attributes.
*
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_INV_OPTION One or more invalid attribute options were
* specified.
*/
ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr,
ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr,
ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_attr,
ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_attr);
/******************************************************************************/
/*!
* Maps SDRAM to address 0x0 for the MPU address space view.
*
* When address 0x0 is mapped to the Boot ROM or on-chip RAM, only the lowest
* 64KB of the boot region are accessible because the size of the Boot ROM and
* on-chip RAM are only 64KB. Addresses in the range 0x100000 (1MiB) to
* 0xC0000000 (3GiB) access SDRAM and addresses in the range 0xC0000000 (3GiB) to
* 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MiB of SDRAM is not
* accessible to the MPU unless address 0 is remapped to SDRAM after reset.
*
* This function remaps the addresses between 0x0 to 0x100000 (1MiB) to access
* SDRAM.
*
* \internal
* The remap to address 0x0 is achieved by configuring the L2 cache Address
* Filtering Registers to redirect address 0x0 to \e sdram_end_addr to the SDRAM
* AXI (M1) master port by calling:
*
* alt_l2_addr_filter_cfg_set(0x0, <current_addr_filt_end_value>);
*
* See: <em>ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical
* Reference Manual, Section 3.3.12 Address Filtering </em>.
* \endinternal
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void);
/*! @} */
/******************************************************************************/
/*! \addtogroup L2_ADDR_FLTR L2 Cache Address Filter
*
* The L2 cache address filter controls where physical addresses within certain
* ranges of the MPU address space are directed.
*
* The L2 cache has master port connections to the L3 interconnect and the SDRAM
* controller. A programmable address filter controls which portions of the
* 32-bit physical address space use each master.
*
* When l2 address filtering is configured and enabled, a physical address will
* be redirected to one master or the other based upon the address filter
* configuration.
*
* If \b address_filter_start <= \e physical_address < \b address_filter_end:
* * then redirect \e physical_address to AXI Master Port M1 (SDRAM controller)
* * else redirect \e physical_address to AXI Master Port M0 (L3 interconnect)
*
* See: <em>ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical
* Reference Manual, Section 3.3.12 Address Filtering </em> for more information.
* @{
*/
/******************************************************************************/
/*!
* Get the L2 cache address filtering configuration settings.
*
* \param addr_filt_start
* [out] An output parameter variable for the address filtering
* start address for the range of physical addresses redirected to
* the SDRAM AXI master port. The value returned is always a 1 MiB
* aligned address.
*
* \param addr_filt_end
* [out] An output parameter variable for the address filtering
* end address for the range of physical addresses redirected to
* the SDRAM AXI master port. The value returned is always a 1 MiB
* aligned address.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG An bad argument was passed. Either \e addr_filt_start
* or \e addr_filt_end or both are invalid addresses.
*/
ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start,
uint32_t* addr_filt_end);
/******************************************************************************/
/*!
* Set the L2 cache address filtering configuration settings.
*
* Address filtering start and end values must be 1 MiB aligned.
*
* \param addr_filt_start
* The address filtering start address for the range of physical
* addresses redirected to the SDRAM AXI master port. Only bits
* [31:20] of the address are valid. Any bits outside the range
* [31:20] are invalid and will cause an error status to be
* returned.
*
* \param addr_filt_end
* The address filtering end address for the range of physical
* addresses redirected to the SDRAM AXI master port. Only bits
* [31:20] of the address are valid. Any bits outside the range
* [31:20] are invalid and will cause an error status to be
* returned.
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or
* more address arguments do not satisfy the argument
* constraints.
*/
ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start,
uint32_t addr_filt_end);
/*! @} */
/******************************************************************************/
/*! \addtogroup ADDR_SPACE_MGR_MEM_COHERENCE ACP Memory Coherence and ID Mapping
*
* This API provides management of the ACP ID Mapper that enables data coherent
* access to the MPU address space by external masters. The set of external
* masters include L3 master peripherals and FPGA soft IP.
*
* The Accelerator Coherency Port (ACP) allows peripherals - including FPGA
* based soft IP - to maintain data coherency with the Cortex-A9 MPCore
* processors and the Snoop Control Unit (SCU).
*
* The ACP supports up to six masters. However, soft IP implemented in the FPGA
* fabric can have a larger number of masters that need to access the ACP. The
* ACP ID Mapper expands the number of masters able to access the ACP. The ACP
* ID Mapper is situated between the interconnect and the ACP of the MPU
* subsystem. It has the following characteristics:
* * Support for up to six concurrent ID mappings.
* * 1 GiB coherent window into 4 GiB MPU address space
* * Remaps the 5-bit user sideband signals used by the Snoop Control Unit (SCU)
* and L2 cache.
*
* The function of the ACP ID Mapper is to map 12-bit Advanced Microcontroller
* Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) IDs (input
* identifiers) from the Level 3 (L3) interconnect to 3-bit AXI IDs (output
* identifiers) required by the ACP slave port.
*
* The ACP ID Mapper supports the two ID mapping modes:
* * Dynamic Mapping - In this mode an input ID is automatically mapped to an
* available output ID. The dynamic mode is more flexible because the hardware
* handles the mapping. The hardware mapping allows an output ID to be used
* for more than one input ID. Output IDs are assigned to input IDs on a
* first-come, first-served basis.
* * Fixed Mapping - In this mode there is a one-to-one mapping from input IDs
* to output IDs.
*
* Out of the total of eight ACP output ID values, only six are available to the
* ACP ID Mapper for remapping. The first two output IDs (0 and 1) are
* dedicated to the Cortex-A9 processor cores in the MPU subsystem, leaving the
* last six output IDs (2-7) available to the ACP ID mapper. Output IDs 2-6
* support fixed and dynamic modes of operation while output ID 7 supports
* dynamic mode only.
*
* The following table summarizes the usage of the 3-bit ouput ID values by the
* ACP ID Mapper and their settings at reset.
*
* Output ID | Usage | Reset State
* :-----------|:--------------------------------------------------|:------------
* 0 | Reserved for Cortex-A9 cores. | -
* 1 | Reserved for Cortex-A9 cores. | -
* 2 | Assigned to Debug Access Port (DAP) input ID at | Fixed
* : | reset. After reset, can be reconfigured to either | DAP Master
* : | fixed or dynamic. |:
* 3 | Configurable fixed or dynamic mode. | Dynamic
* 4 | Configurable fixed or dynamic mode. | Dynamic
* 5 | Configurable fixed or dynamic mode. | Dynamic
* 6 | Configurable fixed or dynamic mode. | Dynamic
* 7 | Dynamic mode only. | Dynamic
*
* Where <em>Output ID</em> is the ACP ID Mapper output value that goes to the ACP.
*
* Additionally, for masters unable to drive the AXI user sideband signals of
* incoming transactions, the ACP ID Mapper allows control of the AXI user
* sideband signal values. Not all masters drive these signals, so the ACP ID
* Mapper makes it possible to drive the 5-bit user sideband signal with either
* a default value (in dynamic mode) or specific values (in fixed mode).
*
* The ACP ID Mapper can also control which 1 GiB coherent window into memory is
* accessed by masters of the L3 interconnect. Each fixed mapping can be
* assigned a different user sideband signal and memory window to allow specific
* settings for different masters. All dynamic mappings share a common user
* sideband signal and memory window setting. One important exception, however,
* is that the ACP ID mapper always allows user sideband signals from the
* FPGA-to-HPS bridge to pass through to the ACP regardless of the configured
* user sideband value associated with the ID.
*
* The ACP ID Mapper has a 1 GiB address window into the MPU address space, which
* is by default a view into the bottom 1 GiB of SDRAM. The ACP ID Mapper allows
* transactions to be routed to different 1 GiB-sized memory views, called pages,
* in both dynamic and fixed modes.
*
* See: <em>Chapter 6: Cortex-A9 Microprocessor Unit Subsystem</em> in
* <em>Volume 3: Hard Processor System Technical Reference Manual</em> of the
* <em>Arria V or Cyclone V Device Handbook</em> for a complete discussion of
* the operation and restrictions on the ACP and the ACP ID Mapper.
*
* @{
*/
/******************************************************************************/
/*!
* \name External Master ID Macros
*
* These macros define the HPS external master identifiers that are 12-bit input
* IDs to the ACP ID Mapper. Some of the masters have a range of identifier
* values assigned to them and are distinguished by taking a <em>(var)\</em>
* argument.
* @{
*/
/*! Bit mask for the relevant 12 bits of an external master ID */
#define ALT_ACP_ID_MAP_MASTER_ID_MASK 0xfff
/*! Master ID for L2M0 */
#define ALT_ACP_ID_MAP_MASTER_ID_L2M0(var) (0x00000002 | (0x000007f8 & (var)))
/*! Master ID for DMA */
#define ALT_ACP_ID_MAP_MASTER_ID_DMA(var) (0x00000001 | (0x00000078 & (var)))
/*! Master ID for EMAC0 */
#define ALT_ACP_ID_MAP_MASTER_ID_EMAC0(var) (0x00000801 | (0x00000878 & (var)))
/*! Master ID for EMAC1 */
#define ALT_ACP_ID_MAP_MASTER_ID_EMAC1(var) (0x00000802 | (0x00000878 & (var)))
/*! Master ID for USB0 */
#define ALT_ACP_ID_MAP_MASTER_ID_USB0 0x00000803
/*! Master ID for USB1 */
#define ALT_ACP_ID_MAP_MASTER_ID_USB1 0x00000806
/*! Master ID for NAND controller */
#define ALT_ACP_ID_MAP_MASTER_ID_NAND(var) (0x00000804 | (0x00000ff8 & (var)))
/*! Master ID for Embedded Trace Router (ETR) */
#define ALT_ACP_ID_MAP_MASTER_ID_TMC 0x00000800
/*! Master ID for Debug Access Port (DAP) */
#define ALT_ACP_ID_MAP_MASTER_ID_DAP 0x00000004
/*! Master ID for SD/MMC controller */
#define ALT_ACP_ID_MAP_MASTER_ID_SDMMC 0x00000805
/*! Master ID for FPGA to HPS (F2H) bridge - conduit for soft IP masters in FPGA fabric */
#define ALT_ACP_ID_MAP_MASTER_ID_F2H(var) (0x00000000 | (0x000007f8 & (var)))
/*! @} */
/******************************************************************************/
/*!
* This type defines the enumerations 3-bit output ids to ACP ID mapper.
*/
typedef enum ALT_ACP_ID_OUTPUT_ID_e
{
ALT_ACP_ID_OUT_FIXED_ID_2 = 2, /*!< Assigned to the input ID of the DAP at reset.
* After reset, can be either fixed or dynamic,
* programmed by software.
*/
ALT_ACP_ID_OUT_DYNAM_ID_3 = 3, /*!< Fixed or dynamic, programmed by software output id */
ALT_ACP_ID_OUT_DYNAM_ID_4 = 4, /*!< Fixed or dynamic, programmed by software output id */
ALT_ACP_ID_OUT_DYNAM_ID_5 = 5, /*!< Fixed or dynamic, programmed by software output id */
ALT_ACP_ID_OUT_DYNAM_ID_6 = 6, /*!< Fixed or dynamic, programmed by software output id */
ALT_ACP_ID_OUT_DYNAM_ID_7 = 7 /*!< Dynamic mapping only */
} ALT_ACP_ID_OUTPUT_ID_t;
/*!
* This type defines the enumerations used to specify the 1 GiB page view of the
* MPU address space used by an ACP ID mapping configuration.
*/
typedef enum ALT_ACP_ID_MAP_PAGE_e
{
ALT_ACP_ID_MAP_PAGE_0 = 0, /*!< Page 0 - MPU address range 0x00000000 - 0x3FFFFFFF */
ALT_ACP_ID_MAP_PAGE_1 = 1, /*!< Page 1 - MPU address range 0x40000000 - 0x7FFFFFFF */
ALT_ACP_ID_MAP_PAGE_2 = 2, /*!< Page 2 - MPU address range 0x80000000 - 0xBFFFFFFF */
ALT_ACP_ID_MAP_PAGE_3 = 3 /*!< Page 3 - MPU address range 0xC0000000 - 0xFFFFFFFF */
} ALT_ACP_ID_MAP_PAGE_t;
/******************************************************************************/
/*!
* Configure a fixed ACP ID mapping for read transactions originating from
* external masters identified by \e input_id. The \e input_id value is
* translated to the specified 3-bit \e output_id required by the ACP slave
* port.
*
* \param input_id
* The 12 bit external master ID originating read transactions
* targeted for ID translation. Valid argument range must be 0 <=
* \e output_id <= 4095.
*
* \param output_id
* The 3-bit output ID value the ACP ID Mapper translates read
* transactions identified by \e input_id to. This is the value
* propogated to the ACP slave port. Valid argument values must be
* 0 <= \e output_id <= 7.
*
* \param page
* The MPU address space page view to use for the ACP window used
* by the ID tranlation mapping.
*
* \param aruser
* The 5-bit AXI ARUSER read user sideband signal value to use for
* masters unable to drive the AXI user sideband signals. Valid
* argument range is 0 <= \e aruser <= 31.
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_RESERVED The argument value is reserved or unavailable.
* \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or
* more of the \e input_id, and/or \e output_id
* arguments violates its range constraint.
* \retval ALT_E_BAD_ARG The \e page argument is invalid.
*/
ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id,
const uint32_t output_id,
const ALT_ACP_ID_MAP_PAGE_t page,
const uint32_t aruser);
/******************************************************************************/
/*!
* Configure a fixed ACP ID mapping for write transactions originating from
* external masters identified by \e input_id. The \e input_id value is
* translated to the specified 3-bit \e output_id required by the ACP slave
* port.
*
* \param input_id
* The 12 bit external master ID originating write transactions
* targeted for ID translation. Valid argument range must be 0 <=
* \e output_id <= 4095.
*
* \param output_id
* The 3-bit output ID value the ACP ID Mapper translates write
* transactions identified by \e input_id to. This is the value
* propogated to the ACP slave port. Valid argument values must be
* 0 <= \e output_id <= 7.
*
* \param page
* The MPU address space page view to use for the ACP window used
* by the ID tranlation mapping.
*
* \param awuser
* The 5-bit AXI AWUSER write user sideband signal value to use for
* masters unable to drive the AXI user sideband signals. Valid
* argument range is 0 <= \e awuser <= 31.
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_RESERVED The argument value is reserved or unavailable.
* \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or
* more of the \e input_id, and/or \e output_id
* arguments violates its range constraint.
* \retval ALT_E_BAD_ARG The \e page argument is invalid.
*/
ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id,
const uint32_t output_id,
const ALT_ACP_ID_MAP_PAGE_t page,
const uint32_t awuser);
/******************************************************************************/
/*!
* Configure the designated 3-bit output ID as an available identifier resource
* for use by the dynamic ID mapping function of the ACP ID Mapper for read
* transactions. The \e output_id value is available for dynamic assignment to
* external master read transaction IDs that do not have an explicit fixed ID
* mapping.
*
* \param output_id
* The 3-bit output ID value designated as an available ID for use
* by the dynamic mapping function of the ACP ID Mapper. The \e
* ouput_id value is used exclusively for dynamic ID mapping until
* reconfigured as a fixed ID mapping by a call to
* alt_acp_id_map_fixed_read_set(). Valid argument values must be
* 0 <= \e output_id <= 7.
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_RESERVED The argument value is reserved or unavailable.
* \retval ALT_E_ARG_RANGE An argument violates a range constraint.
*/
ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id);
/******************************************************************************/
/*!
* Configure the designated 3-bit output ID as an available identifier resource
* for use by the dynamic ID mapping function of the ACP ID Mapper for write
* transactions. The \e output_id value is available for dynamic assignment to
* external master write transaction IDs that do not have an explicit fixed ID
* mapping.
*
* \param output_id
* The 3-bit output ID value designated as an available ID for use
* by the dynamic mapping function of the ACP ID Mapper. The \e
* ouput_id value is used exclusively for dynamic ID mapping until
* reconfigured as a fixed ID mapping by a call to
* alt_acp_id_map_fixed_write_set(). Valid argument values must be
* 0 <= \e output_id <= 7.
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_RESERVED The argument value is reserved or unavailable.
* \retval ALT_E_ARG_RANGE An argument violates a range constraint.
*/
ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id);
/******************************************************************************/
/*!
* Configure the page and user read sideband signal options that are applied to
* all read transactions that have their input IDs dynamically mapped.
*
* \param page
* The MPU address space page view to use for the ACP window used
* by the dynamic ID tranlation mapping.
*
* \param aruser
* The 5-bit AXI ARUSER read user sideband signal value to use for
* masters unable to drive the AXI user sideband signals. Valid
* argument range is 0 <= \e aruser <= 31.
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_RESERVED The argument value is reserved or unavailable.
* \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or
* more of the \e page and/or \e aruser
* arguments violates its range constraint.
* \retval ALT_E_BAD_ARG The \e mid argument is not a valid master
* identifier.
*/
ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
const uint32_t aruser);
/******************************************************************************/
/*!
* Configure the page and user write sideband signal options that are applied to
* all write transactions that have their input IDs dynamically mapped.
*
* \param page
* The MPU address space page view to use for the ACP window used
* by the dynamic ID tranlation mapping.
*
* \param awuser
* The 5-bit AXI AWUSER write user sideband signal value to use for
* masters unable to drive the AXI user sideband signals. Valid
* argument range is 0 <= \e aruser <= 31.
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_RESERVED The argument value is reserved or unavailable.
* \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or
* more of the \e page and/or \e awuser
* arguments violates its range constraint.
* \retval ALT_E_BAD_ARG The \e mid argument is not a valid master
* identifier.
*/
ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
const uint32_t awuser);
/******************************************************************************/
/*!
* Return the current read transaction mapping configuration used by the ACP ID
* Mapper for the specified output ID.
*
* If \e output_id is configured as a fixed mapping then \b true is returned in
* the \e fixed output parameter and the translation mapping options configured
* for that \e output_id are returned in the other output parameters.
*
* If \e output_id is configured as a dynamic mapping then \b false is returned
* in the \e fixed output parameter and the translation mapping options
* configured for all dynamically remapped output IDs are returned in the other
* output parameters.
*
* \param output_id
* The output ID to return the mapping configuration for. 0 <= \e
* output_id <= 7.
*
* \param fixed
* [out] Set to \b true if the specified \e output_id is a fixed ID
* mapping configuration. Set to \b false if the mapping
* configuration is dynamic.
*
* \param input_id
* [out] The input ID of the external master that a fixed ID
* mapping is applied to for the \e output_id. If \e fixed is \b
* false then this output parameter is set to 0 and its value
* should be considered as not applicable.
*
* \param page
* [out] The MPU address space page view used by the mapping
* configuration.
*
* \param aruser
* [out] The 5-bit AXI ARUSER read user sideband signal value used
* by the mapping configuration when masters are unable to drive
* the AXI user sideband signals.
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_RESERVED The argument value is reserved or unavailable.
* \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e
* output_id argument violates its range constraint.
*/
ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id,
bool* fixed,
uint32_t* input_id,
ALT_ACP_ID_MAP_PAGE_t* page,
uint32_t* aruser);
/******************************************************************************/
/*!
* Return the current write transaction mapping configuration used by the ACP ID
* Mapper for the specified output ID.
*
* If \e output_id is configured as a fixed mapping then \b true is returned in
* the \e fixed output parameter and the translation mapping options configured
* for that \e output_id are returned in the other output parameters.
*
* If \e output_id is configured as a dynamic mapping then \b false is returned
* in the \e fixed output parameter and the translation mapping options
* configured for all dynamically remapped output IDs are returned in the other
* output parameters.
*
* \param output_id
* The output ID to return the mapping configuration for. 0 <= \e
* output_id <= 7.
*
* \param fixed
* [out] Set to \b true if the specified \e output_id is a fixed ID
* mapping configuration. Set to \b false if the mapping
* configuration is dynamic.
*
* \param input_id
* [out] The input ID of the external master that a fixed ID
* mapping is applied to for the \e output_id. If \e fixed is \b
* false then this output parameter is set to 0 and its value
* should be considered as not applicable.
*
* \param page
* [out] The MPU address space page view used by the mapping
* configuration.
*
* \param awuser
* [out] The 5-bit AXI AWUSER write user sideband signal value used
* by the mapping configuration when masters are unable to drive
* the AXI user sideband signals.
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_RESERVED The argument value is reserved or unavailable.
* \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e
* output_id argument violates its range constraint.
*/
ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id,
bool* fixed,
uint32_t* input_id,
ALT_ACP_ID_MAP_PAGE_t* page,
uint32_t* awuser);
/*! @} */
/*! @} */
#endif /* __ASSEMBLY__ */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_ADDRESS_SPACE_H__ */

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/*! \file
* Altera - SoC FPGA FPGA/HPS Bridge Management
*/
/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ALT_BRG_MGR_H__
#define __ALT_BRG_MGR_H__
#include "hwlib.h"
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/******************************************************************************/
/*! \addtogroup ALT_BRIDGE The AXI Bridge Manager
*
* The functions in this group manage access, configuration, and control of the
* AXI bridges between the FPGA and HPS.
*
* @{
*/
/******************************************************************************/
/*!
* This type definition enumerates the AXI bridge interfaces between the FPGA
* and HPS.
*/
typedef enum ALT_BRIDGE_e
{
ALT_BRIDGE_F2H, /*!< FPGA-to-HPS AXI bridge providing a
* high-performance, statically configurable
* width interface that gives the FPGA the
* ability to:
* * master transactions to slaves in the HPS
* * have full visibility into the HPS address space
* * access the coherent memory interface (ACP)
*
* The width (32/64/128 bits) of this bridge
* is statically configurable at design time
* using \e Quartus.
*/
ALT_BRIDGE_H2F, /*!< HPS-to-FPGA AXI bridge providing a
* statically configurable width,
* high-performance master interface to the
* FPGA fabric. The bridge provides a 1GB
* address space and gives any master in the
* HPS system access to logic, peripherals,
* and memory implemented in the FPGA.
*/
ALT_BRIDGE_LWH2F /*!< Lightweight HPS-to-FPGA AXI bridge
* providing a secondary, fixed-width, smaller
* address space, lower-performance master
* interface to the FPGA fabric. The bridge
* provides a 2MB address space and gives any
* master in the HPS access to logic,
* peripherals, and memory implemented in the
* FPGA fabric. The bridge master exposed to
* the FPGA fabric has a fixed data width of
* 32 bits.
*
* The bridge provides clock crossing logic to
* allow the logic in the FPGA to run
* asynchronous to the HPS. The bridge
* simplifies the process of connecting the
* HPS to soft logic. Soft logic can even be
* designed to support only a subset of the
* full AXI protocol that the bridge
* supports. Use the lightweight HPS-to-FPGA
* bridge for high-latency, low-bandwidth
* traffic, such as memory-mapped register
* accesses of FPGA peripherals. This approach
* diverts traffic from the high-performance
* HPS-to-FPGA bridge, which can improve
* overall performance.
*/
} ALT_BRIDGE_t;
/******************************************************************************/
/*!
* Type definition for a callback function prototype used by the
* alt_bridge_init() bridge initialization function to determine whether the
* FPGA is ready to begin transactions across the bridge interface.
*
* The implementation of the callback function is user defined allowing the user
* to define a flexible signaling protocol for the FPGA to indicate its
* readiness to begin transactions across the initialized bridge interface.
*
* The range of values returned by the callback function may be extended per the
* user defined FPGA readiness signaling protocol but any return value other
* than ALT_E_SUCCESS will be interpreted by the alt_bridge_init() bridge
* initialization function as an indication that the FPGA is not ready to
* commence bridge interface transactions.
*
* \param user_arg
* This is a user defined parameter available to pass additional
* data that might be needed to support the user defined FPGA
* readiness signaling protocol.
*
* \retval ALT_E_SUCCESS The FPGA is ready to commence bridge interface
* transactions.
* \retval ALT_E_ERROR An error has occurred. The FPGA is not ready to
* commence bridge interface transactions.
* \retval ALT_E_TMO The FPGA failed to signal a ready to commence
* bridge interface transactions indication before
* the response timeout period expired.
*/
typedef ALT_STATUS_CODE (*alt_bridge_fpga_is_ready_t)(void* user_arg);
/******************************************************************************/
/*!
* Initialize the bridge for bus transactions by bringing up the interface in a
* safe, controlled sequence.
*
* The following actions are performed as part of the process of initializing
* the bridge interface for transactions:
*
* * Sets and holds bridge interface in reset.
* * Ensures that the bridge interface is ready by asserting that:
* - FPGA is powered and configured (i.e. in USER mode).
* - Bridge interface clock is ready and stable.
* - FPGA soft IP is ready for transactions across the bridge interface.
* * Releases bridge interface from reset.
*
* The mechanism used by alt_bridge_init() to determine whether the FPGA soft IP
* is ready to begin bus transactions across the interface is the user defined
* callback \e fpga_is_ready.
*
* \internal
* This process of software controlled bring-up of HPS/FPGA interfaces is
* detailed in <em> Hammerhead-P HPS FPGA Interface NPP, Section 4 Software
* Bring-up/Tear-down</em>.
* \endinternal
*
* \param bridge
* The bridge interface to initialize.
*
* \param fpga_is_ready
* A pointer to a user defined callback function to determine
* whether the FPGA is ready to commence bridge interface
* transactions. If NULL is passed, then bridge interface
* initialization proceeds without making a determination of
* whether the FPGA is ready to commence bridge interface
* transactions or not.
*
* \param user_arg
* A user defined argument value for passing support data to the \e
* fpga_is_ready callback function.
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_bridge_init(ALT_BRIDGE_t bridge,
alt_bridge_fpga_is_ready_t fpga_is_ready,
void* user_arg);
/******************************************************************************/
/*!
* Type definition for a callback function prototype used by the
* alt_bridge_uninit() function to conduct a handshake protocol with the FPGA
* notifying it that the bridge interface is being taken down.
*
* The callback function implementation is user defined and allows the user to
* implement a flexible handshake notification protocol with the FPGA to allow
* an orderly interface shutdown prior to the bridge being taken down.
*
* The handshake protocol is user defined but normally consists of two parts:
* * The processor notifies the FPGA soft IP that the bridge interface is being
* taken down. The notification mechanism used to signal the FPGA is user
* defined.
* * The process waits for an acknowledgement response from the FPGA.
*
* The range of return values for the callback function may be extended per the
* user defined handshake notification protocol but any return value other than
* ALT_E_SUCCESS will be interpreted by the alt_bridge_uninit() function as an
* indication that the handshake protocol was unsuccessful.
*
* \param user_arg
* This is a user defined parameter available to pass additional
* data that might be needed to support the user defined handshake
* notification protocol.
*
* \retval ALT_E_SUCCESS The handshake notification protocol was successful.
* \retval ALT_E_ERROR An error has occurred. The handshake notification
* protocol was unsuccessful.
* \retval ALT_E_TMO The handshake notification protocol failed
* because a response timeout period expired.
*/
typedef ALT_STATUS_CODE (*alt_bridge_teardown_handshake_t)(void* user_arg);
/******************************************************************************/
/*!
* Uninitialize the bridge by tearing down the interface in a safe and
* controlled sequence.
*
* The process of taking down the bridge interface entails:
* * Optional: Conduct teardown handshake notification protocol
* - Bridge Manager informs FPGA that the bridge interface is being torn down.
* - Bridge Manager waits for FPGA response to notification.
* * Processor waits for the completion of outstanding transactions on the AXI
* bridge. Note, that HPS has no mechanism to track outstanding AXI transactions;
* this needs to be provided by the customer design.
* * Places and holds the bridge interface in reset.
*
* The mechanism used by alt_bridge_uninit() to initiate the handshake
* notification to the FPGA soft IP that the bridge interface is being taken
* down is the user defined \e handshake callback.
*
* \internal
* This function implements the software controlled tear-down procedure detailed
* in <em> Hammerhead-P HPS FPGA Interface NPP, Section 4 Software
* Bring-up/Tear-down</em>.
* \endinternal
*
* \param bridge
* The bridge interface to uninitialize.
*
* \param handshake
* A pointer to a user defined tear-down handshake protocol. If
* NULL is passed, then the bridge interface take down proceeds
* without conducting any handshake notification protocol.
*
* \param user_arg
* A user defined argument value for passing support data to the
* \e teardown_hs callback function.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_bridge_uninit(ALT_BRIDGE_t bridge,
alt_bridge_teardown_handshake_t handshake,
void* user_arg);
/*! @} */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_BRG_MGR_H__ */

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ALT_CACHE_H__
#define __ALT_CACHE_H__
#include "hwlib.h"
#ifdef __cplusplus
extern "C"
{
#endif
/*!
* \addtogroup CACHE_MGR Cache Management API
*
* This module defines the cache management API for enabling and disabling L1
* data cache, L1 instruction cache, L1 dynamic branch prediction caches, L1
* TLB cache, and L2 cache in the SoC. As well, many it allows users to perform
* cache maintenance operations on these caches. This includes the following
* operations:
* * Invalidate: Marks the cache line as being invalid, freeing up the space
* to cache other data. All APIs which enable caches invalidates the memory
* before being enabling the cache.
* * Clean: If the cache line is dirty, it synchronizes the cache line data
* with the upper level memory system and marks that line as clean. All APIs
* which disable caches cleans the memory before disabling the cache.
* * Purge: A term used in this API as a short form for clean and invalidate.
* This operation cleans and invalidates a cache line in that order, as a
* single command to the cache controller.
*
* The following reference materials were used in the design of this API:
* * ARM&reg; Architecture Reference Manual, ARMv7-A and ARMv7-R edition
* * Cortex&trade;-A9 Technical Reference Manual
* * Cortex&trade;-A9 MPCore Technical Reference Manual
* * CoreLink&trade; Level 2 Cache Controller L2C-310 Technical Reference
* Manual
*
* @{
*/
/*!
* \addtogroup CACHE_SYS System Level Cache Management API
*
* This API group provides cache maintenance operations which affects multiple
* cache levels.
*
* The enable and disable functions enables and disables all caches in the
* system respectively. For caches shared by the CPU core(s), particularly the
* L2 cache, once that cache is enabled or disabled it will not be invalidated
* or cleaned again respectively. This allows the safe system-wide enable and
* disable to be used in single-core and multi-core scenarios.
*
* For cache maintenance operations, this API implements the procedures
* outlined in the L2C-310 Technical Reference Manual, section 3.3.10,
* subsection "System cache maintenance considerations". This allows for a
* convenient way to invalidate, clean, or clean and invalidate cache data from
* the L1 to L2 to L3 while avoiding any potential race conditions in
* mutli-core or multi-master scenarios. It assumes that the L1 and L2 cache is
* set in "non-exclusive" mode. This means a segment of data can reside in both
* the L1 and L2 simultaneously. This is the default mode for caches in the
* system.
*
* The current implementation of the system cache APIs assumes that the MMU is
* configured with a flat memory mapping or that every virtual address matches
* perfectly with the physical address. This restriction may be lifted in a
* future release of the cache API implementation.
*
* @{
*/
/*!
* Enables support for a non-flat virtual memory. A flat virtual memory is
* where every virtual address matches exactly to the physical address, making
* the virtual to physical translation trivial. Adding support for non-flat
* adds some overhead for the VA to PA translation and error detection.
*
* To enable non-flat virtual memory support, defined
* ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY=1 in your Makefile when compiling
* HWLibs.
*/
#ifndef ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY
#define ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY (0)
#endif
/*!
* This is the system wide cache line size, given in bytes.
*/
#define ALT_CACHE_LINE_SIZE 32
/*!
* Enables all caches and features which improve reliability and speed on all
* cache controllers visible to the current CPU core. This includes parity
* error detection. Cache controllers visible to multiple CPU cores, for
* example the L2, will first be checked to be disabled before being enabled.
* All necessary cache maintenance operations will be done automatically.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_system_enable(void);
/*!
* Disables all cache controllers visible to the current CPU core. Cache
* controllers visible to multiple CPU cores, for example the L2, will first
* be checked to be enabled before being disabled. All necessary cache
* maintenance operations will be done automatically.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_system_disable(void);
/*!
* Invalidates the specified contents of all cache levels visible to the
* current CPU core for the given memory segment.
*
* The memory segment address and length specified must align to the
* characteristics of the cache line. This means the address and length must be
* multiples of the cache line size. To determine the cache line size, use the
* \b ALT_CACHE_LINE_SIZE macro.
*
* The following pseudocode outlines the operations carried out by this
* function:
* -# L2 invalidate address(es)
* -# L2 cache sync
* -# L1 invalidate address(es)
* -# DSB instruction
*
* The current implementation of the system cache APIs assumes that the MMU is
* configured with a flat memory mapping or that every virtual address matches
* perfectly with the physical address. This restriction may be lifted in a
* future release of the cache API implementation.
*
* \param vaddress
* The virtual address of the memory segment to be invalidated.
*
* \param length
* The length of the memory segment to be invalidated.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG The memory segment is invalid.
* \retval ALT_E_TMO The memory operation timed out.
*/
ALT_STATUS_CODE alt_cache_system_invalidate(void * vaddress, size_t length);
/*!
* Cleans the specified contents of all cache levels visible to the current
* CPU core for the given memory segment.
*
* The memory segment address and length specified must align to the
* characteristics of the cache line. This means the address and length must be
* multiples of the cache line size. To determine the cache line size, use the
* \b ALT_CACHE_LINE_SIZE macro.
*
* The following pseudocode outlines the operations carried out by this
* function:
* -# L1 clean address(es)
* -# DSB instruction
* -# L2 clean address(es)
* -# L2 cache sync
*
* The current implementation of the system cache APIs assumes that the MMU is
* configured with a flat memory mapping or that every virtual address matches
* perfectly with the physical address. This restriction may be lifted in a
* future release of the cache API implementation.
*
* \param vaddress
* The virtual address of the memory segment to be cleaned.
*
* \param length
* The length of the memory segment to be cleaned.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG The memory segment is invalid.
* \retval ALT_E_TMO The memory operation timed out.
*/
ALT_STATUS_CODE alt_cache_system_clean(void * vaddress, size_t length);
/*!
* Cleans and invalidates the specified contents of all cache levels visible
* to the current CPU core for the given memory segment.
*
* The memory segment address and length specified must align to the
* characteristics of the cache line. This means the address and length must be
* multiples of the cache line size. To determine the cache line size, use the
* \b ALT_CACHE_LINE_SIZE macro.
*
* The following pseudocode outlines the operations carried out by this
* function:
* -# L1 clean address(es)
* -# DSB instruction
* -# L2 clean and invalidate address(es)
* -# L2 cache sync
* -# L1 invalidate address(es)
* -# DSB instruction
*
* The current implementation of the system cache APIs assumes that the MMU is
* configured with a flat memory mapping or that every virtual address matches
* perfectly with the physical address. This restriction may be lifted in a
* future release of the cache API implementation.
*
* \param vaddress
* The virtual address of the memory segment to be purged.
*
* \param length
* The length of the memory segment to be purged.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG The memory segment is invalid.
* \retval ALT_E_TMO The memory operation timed out.
*/
ALT_STATUS_CODE alt_cache_system_purge(void * vaddress, size_t length);
/*!
* @}
*/
/*!
* \addtogroup CACHE_L1 L1 Cache Management API
*
* This API group provides functions to interact with various components of the
* L1 cache on the SoCFPGA. This includes the following cache components:
* * Instruction Cache
* * Data Cache
* * Parity error detection
* * Dynamic branch prediction
* * Data prefetching
*
* The API within this group only affects the L1 cache on the current CPU. To
* interact the L1 cache on another CPU, the API must be called from that other
* CPU.
*
* With respect to bring-up, the L1 and L2 cache controller setups are fully
* independent. The L2 can be setup at any time, before or after the L1 is setup.
* \internal
* Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up".
* \endinternal
*
* @{
*/
/*!
* Enables all L1 caches and features on the current CPU core. This includes
* the instruction cache, data cache, parity error detection, branch target
* address cache, global history buffer, and data prefetching. All necessary
* maintenance tasks will be taken care of.
*
* This function should not be mixed with other L1 cache related functions
* which enable or disable caches individually.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_enable_all(void);
/*!
* Disables all L1 caches and features on the current CPU core. This includes
* the instruction cache, data cache, parity error detection, branch target
* address cache, global history buffer, and data prefetching. All necessary
* maintenance tasks will be taken care of.
*
* This function should not be mixed with other L1 cache related functions
* which enable or disable caches individually.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_disable_all(void);
/*!
* Enables the L1 instruction cache on the current CPU core. If the cache is
* already enabled, nothing is done. Otherwise the instruction cache is first
* invalidated before being enabled.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_instruction_enable(void);
/*!
* Disables the L1 instruction cache on the current CPU core.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_instruction_disable(void);
/*!
* Returns \b true when the L1 instruction cache is enabled and \b false when
* it is disabled on the current CPU core.
*
* \retval true The L1 instruction cache is enabled.
* \retval false The L1 instruction cache is disabled.
*/
bool alt_cache_l1_instruction_is_enabled(void);
/*!
* Invalidates the contents of the L1 instruction cache on the current CPU
* core.
*
* Normally this is done automatically as part of
* alt_cache_l1_instruction_enable(), but in certain circumstances it may be
* necessary to invalidate it manually. An example of this situation is when
* the address space is remapped and the processor executes instructions from
* the new memory area.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_instruction_invalidate(void);
/*!
* Enables the L1 data cache on the current CPU core.
*
* If the cache is already enabled nothing is done. Otherwise the data cache is
* first invalidated before being enabled.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_data_enable(void);
/*!
* Disables the L1 data cache on the current CPU core.
*
* If the cache is already disabled nothing is done. Otherwise the data cache
* is first cleaned before being disabled.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_data_disable(void);
/*!
* Returns \b true when the L1 data cache is enabled and \b false when it is
* disabled on the current CPU core.
*
* \retval true The L1 data cache is enabled.
* \retval false The L1 data cache is disabled.
*/
bool alt_cache_l1_data_is_enabled(void);
/*!
* Invalidates the specified contents of the L1 data cache on the current CPU
* core for the given memory segment.
*
* The memory segment address and length specified must align to the
* characteristics of the cache line. This means the address and length must be
* multiples of the cache line size. To determine the cache line size, use the
* \b ALT_CACHE_LINE_SIZE macro.
*
* \param vaddress
* The virtual address of the memory segment to be invalidated.
*
* \param length
* The length of the memory segment to be invalidated.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG The memory segment is invalid.
*/
ALT_STATUS_CODE alt_cache_l1_data_invalidate(void * vaddress, size_t length);
/*!
* Invalidates the entire contents of the L1 data cache on the current CPU
* core.
*
* Normally this is done automatically as part of alt_cache_l1_data_enable(),
* but in certain circumstances it may be necessary to invalidate it manually.
* An example of this situation is when the address space is remapped and the
* processor accesses memory from the new memory area.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_data_invalidate_all(void);
/*!
* Cleans the specified contents of the L1 data cache on the current CPU core
* for the given memory segment.
*
* The memory segment address and length specified must align to the
* characteristics of the cache line. This means the address and length must be
* multiples of the cache line size. To determine the cache line size, use the
* \b ALT_CACHE_LINE_SIZE macro.
*
* \param vaddress
* The virtual address of the memory segment to be cleaned.
*
* \param length
* The length of the memory segment to be cleaned.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG The memory segment is invalid.
*/
ALT_STATUS_CODE alt_cache_l1_data_clean(void * vaddress, size_t length);
/*!
* Cleans the entire L1 data cache for the current CPU core.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_data_clean_all(void);
/*!
* Cleans and invalidates the specified contents of the L1 data cache on the
* current CPU core for the given memory segment.
*
* The memory segment address and length specified must align to the
* characteristics of the cache line. This means the address and length must be
* multiples of the cache line size. To determine the cache line size, use the
* \b ALT_CACHE_LINE_SIZE macro.
*
* Normally this is done automatically as part of alt_cache_l1_data_disable(),
* but in certain circumstances it may be necessary to purged it manually.
* An example of this situation is when the address space is remapped and the
* processor accesses memory from the new memory area.
*
* \param vaddress
* The virtual address of the memory segment to be purged.
*
* \param length
* The length of the memory segment to be purged.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG The memory segment is invalid.
*/
ALT_STATUS_CODE alt_cache_l1_data_purge(void * vaddress, size_t length);
/*!
* Cleans and invalidates the entire L1 data cache for the current CPU core.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_data_purge_all(void);
/*!
* Enables the parity error detection feature in the L1 caches on the current
* CPU core.
*
* Ideally parity should be enabled before any L1 caches are enabled. If the
* instruction, data, and / or dynamic branch predictor caches are already
* enabled, they will first be cleaned (if needed) and disabled before parity
* is enabled in hardware. Afterwards, the affected caches will be invalidated
* and enabled.
*
* Parity and TLB interaction deserves special attention. The TLB is considered
* to be a L1 cache but is enabled when the MMU, which is grouped in another
* API, is enabled. Due to the system-wide influence of the MMU, it cannot be
* disabled and enabled with impunity as the other L1 caches, which are
* designed to operate as transparently as possible. Thus parity error
* detection must be enabled before the L1 TLB cache, and by extension the MMU,
* is enabled.
*
* For a parity error to be reported, the appropriate CPU PARITYFAIL interrupt
* for the current CPU core must be enabled using the interrupt controller API.
* For CPU0, ALT_INT_INTERRUPT_CPU0_PARITYFAIL is asserted if any parity error
* is detected while the other PARITYFAIL interrupts are for parity errors in a
* specific memory. Refer to the interrupt controller API for more details
* about programming the interrupt controller.
*
* In the event of a parity error is detected, the appropriate CPU parity
* interrupt will be raised. CPU parity interrupts are all edge triggered and
* are cleared by acknowledging them in the interrupt controller API.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_parity_enable(void);
/*!
* Disables parity error detection in the L1 caches.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_parity_disable(void);
/*!
* Returns \b true when parity error detection is enabled and \b false when it
* is disabled on the current CPU core.
*
* \retval true Parity error detection for L1 caches is
* enabled.
* \retval false Parity error detection for L1 caches is
* disabled.
*/
bool alt_cache_l1_parity_is_enabled(void);
/*!
* Enables the dynamic branch predictor features on the current CPU core.
*
* This operation enables both the Branch Target Address Cache (BTAC) and
* the Global History Buffer (GHB). Affected caches are automatically
* invalidated before use.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_branch_enable(void);
/*!
* Disables the dynamic branch predictor features on the current CPU core.
*
* This operation disables both the Branch Target Address Cache (BTAC) and
* the Global History Buffer (GHB).
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_branch_disable(void);
/*!
* Returns \b true when both the dynamic predictor features are enabled and
* \b false when they are disabled on the current CPU core.
*
* \retval true The L1 branch predictor caches are all enabled.
* \retval false Some or all L1 branch predictor caches are
* disabled.
*/
bool alt_cache_l1_branch_is_enabled(void);
/*!
* Invalidates the dynamic branch predictor feature caches on the current CPU
* core.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_branch_invalidate(void);
/*!
* Enables the L1 cache data prefetch feature on the current CPU core.
*
* This allows data to be prefetched into the data cache before it is to be
* used. For example in a loop the current iteration may want to preload the
* data which will be used in the next teration. This is done by using the PLD
* instructions.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_prefetch_enable(void);
/*!
* Disables the L1 cache data prefetch feature on the current CPU core.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l1_prefetch_disable(void);
/*!
* Returns \b true if the L1 cache data prefetch feature is enabled and
* \b false if it is disabled on the current CPU core.
*
* \retval true The L1 data cache prefetch feature is enabled.
* \retval false The L1 data cache prefetch feature is disabled.
*/
bool alt_cache_l1_prefetch_is_enabled(void);
/*!
* @}
*/
/*!
* \addtogroup CACHE_L2 L2 Cache Management API
*
* This API group provides functions to interact with various features of the
* L2 cache on the SoCFPGA. This includes the following features:
* * L2 cache
* * Parity error detection
* * Data prefetching
* * Interrupt Management
*
* \internal
* Additional features that may be implemented in the future:
* * Lockdown
* * Event counter
* \endinternal
*
* The API within this group affects the L2 cache which is visible to all CPUs
* on the system.
*
* With respect to bring-up, the L1 and L2 cache controller setups are fully
* independent. The L2 can be setup at any time, before or after the L1 is setup.
* \internal
* Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up".
* \endinternal
*
* @{
*/
/*!
* Initializes the L2 cache controller.
*
* \retval ALT_E_SUCCESS Successful status.
* \retval ALT_E_ERROR Details about error status code
*/
ALT_STATUS_CODE alt_cache_l2_init(void);
/*!
* Uninitializes the L2 cache controller.
*
* \retval ALT_E_SUCCESS Successful status.
* \retval ALT_E_ERROR Details about error status code
*/
ALT_STATUS_CODE alt_cache_l2_uninit(void);
/*!
* Enables the L2 cache features for data and instruction prefetching.
*
* Prefetching can be enabled or disabled while the L2 cache is enabled.
* \internal
* Source: Use the Prefetch Control Register.
* \endinternal
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l2_prefetch_enable(void);
/*!
* Disables the L2 cache features for data and instruction prefetching.
*
* Prefetching can be enabled or disabled while the L2 cache is enabled.
* \internal
* Source: Use the Prefetch Control Register.
* \endinternal
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l2_prefetch_disable(void);
/*!
* Returns \b true if either L2 cache data or instruction prefetch features are
* enabled and \b false if no prefetching features are enabled.
*
* \retval true The L2 data and instruction prefetch features
* are enabled.
* \retval false Some L2 data and instruction prefetch features
* are disabled.
*/
bool alt_cache_l2_prefetch_is_enabled(void);
/*!
* Enables parity error detection in the L2 cache.
*
* Ideally parity should be enabled before the L2 cache is enabled. If the
* cache is already enabled, it will first be cleaned and disabled before
* parity is enabled in hardware. Afterwards, the cache will be invalidated and
* enabled.
*
* For a parity error to be reported, the ALT_CACHE_L2_INTERRUPT_PARRD and / or
* ALT_CACHE_L2_INTERRUPT_PARRT interrupt condition(s) must be enabled. This is
* done by calling alt_cache_l2_int_enable(). As well, the L2 cache interrupt
* must be enabled using the interrupt controller API. Refer to the interrupt
* controller API for more details about programming the interrupt controller.
*
* In the event of a parity error is detected, the appropriate L2 cache parity
* interrupt will be raised. To clear the parity interrupt(s), the appropriate
* L2 cache parity interrupt must be cleared by calling
* alt_cache_l2_int_status_clear().
*
* For ECC support, refer to the ECC related API documentation for more
* information.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l2_parity_enable(void);
/*!
* Disables parity error detection in the L2 cache.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l2_parity_disable(void);
/*!
* Returns \b true when parity error detection is enabled and \b false when it
* is disabled.
*
* \retval true The L2 cache parity error detection feature is
* enabled.
* \retval false The L2 cache parity error detection feature is
* disabled.
*/
bool alt_cache_l2_parity_is_enabled(void);
/*!
* Enables the L2 cache.
*
* If the L2 cache is already enabled, nothing is done. Otherwise the entire
* contents of the cache is first invalidated before being enabled.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l2_enable(void);
/*!
* Disables the L2 cache.
*
* If the L2 cache is already disabled, nothing is done. Otherwise the entire
* contents of the cache is first cleaned before being disabled.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l2_disable(void);
/*!
* Returns \b true when the L2 cache is enabled and \b false when it is
* disabled.
*
* \retval true The L2 cache is enabled.
* \retval false The L2 cache is disabled.
*/
bool alt_cache_l2_is_enabled(void);
/*!
* Flushes the L2 cache controller hardware buffers.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_TMO The memory operation timed out.
*/
ALT_STATUS_CODE alt_cache_l2_sync(void);
/*!
* Invalidates the specified contents of the L2 cache for the given memory
* segment.
*
* The memory segment address and length specified must align to the
* characteristics of the cache line. This means the address and length must be
* multiples of the cache line size. To determine the cache line size, use the
* \b ALT_CACHE_LINE_SIZE macro.
*
* \param paddress
* The physical address of the memory segment to be invalidated.
*
* \param length
* The length of the memory segment to be invalidated.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG The memory segment is invalid.
* \retval ALT_E_TMO The memory operation timed out.
*/
ALT_STATUS_CODE alt_cache_l2_invalidate(void * paddress, size_t length);
/*!
* Invalidates th entire contents of the L2 cache.
*
* Normally this is done automatically as part of alt_cache_l2_enable(), but
* in certain circumstances it may be necessary to invalidate it manually. An
* example of this situation is when the address space is remapped and the
* processor accesses memory from the new memory area.
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_TMO The memory operation timed out.
*/
ALT_STATUS_CODE alt_cache_l2_invalidate_all(void);
/*!
* Cleans the specified contents of the L2 cache for the given memory segment.
*
* The memory segment address and length specified must align to the
* characteristics of the cache line. This means the address and length must be
* multiples of the cache line size. To determine the cache line size, use the
* \b ALT_CACHE_LINE_SIZE macro.
*
* \param paddress
* The physical address of the memory segment to be cleaned.
*
* \param length
* The length of the memory segment to be cleaned.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG The memory segment is invalid.
* \retval ALT_E_TMO The memory operation timed out.
*/
ALT_STATUS_CODE alt_cache_l2_clean(void * paddress, size_t length);
/*!
* Cleans the entire L2 cache. All L2 cache controller interrupts will be
* temporarily disabled while the clean operation is in progress and restored
* once the it is finished.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_TMO The memory operation timed out.
*/
ALT_STATUS_CODE alt_cache_l2_clean_all(void);
/*!
* Cleans and invalidates the specified contents of the L2 cache for the
* given memory segment.
*
* The memory segment address and length specified must align to the
* characteristics of the cache line. This means the address and length must be
* multiples of the cache line size. To determine the cache line size, use the
* \b ALT_CACHE_LINE_SIZE macro.
*
* \param paddress
* The physical address of the memory segment to be purged.
*
* \param length
* The length of the memory segment to be purged.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG The memory segment is invalid.
*/
ALT_STATUS_CODE alt_cache_l2_purge(void * paddress, size_t length);
/*!
* Cleans and invalidates the entire L2 cache. All L2 cache controller
* interrupts will be temporarily disabled while the clean and invalidate
* operation is in progress and restored once the it is finished.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_TMO The memory operation timed out.
*/
ALT_STATUS_CODE alt_cache_l2_purge_all(void);
/*!
* This type definition enumerates all the interrupt conditions that can be
* generated by the L2 cache controller as register mask values.
*/
enum ALT_CACHE_L2_INTERRUPT_e
{
/*! Decode error received on the master ports from L3. */
ALT_CACHE_L2_INTERRUPT_DECERR = 1 << 8,
/*! Slave error received on the master ports from L3. */
ALT_CACHE_L2_INTERRUPT_SLVERR = 1 << 7,
/*! Error on the L2 data RAM read. */
ALT_CACHE_L2_INTERRUPT_ERRRD = 1 << 6,
/*! Error on the L2 tag RAM read. */
ALT_CACHE_L2_INTERRUPT_ERRRT = 1 << 5,
/*! Error on the L2 data RAM write. */
ALT_CACHE_L2_INTERRUPT_ERRWD = 1 << 4,
/*! Error on the L2 tag RAM write. */
ALT_CACHE_L2_INTERRUPT_ERRWT = 1 << 3,
/*! Parity error on the L2 data RAM read. */
ALT_CACHE_L2_INTERRUPT_PARRD = 1 << 2,
/*! Parity error on the L2 tag RAM read. */
ALT_CACHE_L2_INTERRUPT_PARRT = 1 << 1,
/*! Event counter overflow or increment. */
ALT_CACHE_L2_INTERRUPT_ECNTR = 1 << 0
};
typedef enum ALT_CACHE_L2_INTERRUPT_e ALT_CACHE_L2_INTERRUPT_t;
/*!
* Enables the L2 cache controller interrupts for the specified set of
* condition(s).
*
* \param interrupt
* A register mask of the selected L2 cache controller
* interrupting conditions.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l2_int_enable(uint32_t interrupt);
/*!
* Disables the L2 cache controller interrupts for the specified set of
* condition(s).
*
* \param interrupt
* A register mask of the selected L2 cache controller
* interrupting conditions.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l2_int_disable(uint32_t interrupt);
/*!
* Gets the condition(s) causing the L2 cache controller to interrupt as a
* register mask.
*
* \returns A register mask of the currently asserted and enabled
* conditions resulting in an interrupt being generated.
*/
uint32_t alt_cache_l2_int_status_get(void);
/*!
* Clears the specified conditon(s) causing the L2 cache controller to
* interrupt as a mask. Condition(s) specified which are not causing an
* interrupt or condition(s) specified which are not enabled are ignored.
*
* \param interrupt
* A register mask of the selected L2 cache controller
* interrupting conditions.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_cache_l2_int_status_clear(uint32_t interrupt);
/*!
* @}
*/
/*!
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALT_CACHE_H__ */

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
/*!
* \file
*
* Contains the definition of an opaque data structure that contains raw
* configuration information for a clock group.
*/
#ifndef __ALT_CLK_GRP_H__
#define __ALT_CLK_GRP_H__
#include "hwlib.h"
#include "socal/alt_clkmgr.h"
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*!
* This type definition enumerates the clock groups
*/
typedef enum ALT_CLK_GRP_e
{
ALT_MAIN_PLL_CLK_GRP, /*!< Main PLL clock group */
ALT_PERIPH_PLL_CLK_GRP, /*!< Peripheral PLL clock group */
ALT_SDRAM_PLL_CLK_GRP /*!< SDRAM PLL clock group */
} ALT_CLK_GRP_t;
/*!
* This type definition defines an opaque data structure for holding the
* configuration settings for a complete clock group.
*/
typedef struct ALT_CLK_GROUP_RAW_CFG_s
{
uint32_t verid; /*!< SoC FPGA version identifier. This field
* encapsulates the silicon identifier and
* version information associated with this
* clock group configuration. It is used to
* assert that this clock group configuration
* is valid for this device. */
uint32_t siliid2; /*!< Reserved register - reserved for future
* device IDs or capability flags. */
ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator. */
/*!
* This union holds the register values for configuration of the set of
* possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator
* identifies the valid clock group union data member.
*/
union ALT_CLK_GROUP_RAW_CFG_u
{
/*! Clock group configuration for Main PLL group. */
union
{
ALT_CLKMGR_MAINPLL_t fld; /*!< Field access. */
ALT_CLKMGR_MAINPLL_raw_t raw; /*!< Raw access. */
} mainpllgrp;
/*! Clock group configuration for Peripheral PLL group. */
union
{
ALT_CLKMGR_PERPLL_t fld; /*!< Field access. */
ALT_CLKMGR_PERPLL_raw_t raw; /*!< Raw access. */
} perpllgrp;
/*! Clock group configuration for SDRAM PLL group. */
union
{
ALT_CLKMGR_SDRPLL_t fld; /*!< Field access. */
ALT_CLKMGR_SDRPLL_raw_t raw; /*!< Raw access. */
} sdrpllgrp;
} clkgrp;
} ALT_CLK_GROUP_RAW_CFG_t;
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_CLK_GRP_H__ */

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ALT_DMA_COMMON_H__
#define __ALT_DMA_COMMON_H__
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*!
* \addtogroup ALT_DMA_COMMON DMA Controller Common API Definitions
*
* This module contains the common definitions for the DMA controller related
* APIs.
*
* @{
*/
/*!
* This type definition enumerates the DMA controller channel threads.
*/
typedef enum ALT_DMA_CHANNEL_e
{
ALT_DMA_CHANNEL_0 = 0, /*!< DMA Channel Thread 0 */
ALT_DMA_CHANNEL_1 = 1, /*!< DMA Channel Thread 1 */
ALT_DMA_CHANNEL_2 = 2, /*!< DMA Channel Thread 2 */
ALT_DMA_CHANNEL_3 = 3, /*!< DMA Channel Thread 3 */
ALT_DMA_CHANNEL_4 = 4, /*!< DMA Channel Thread 4 */
ALT_DMA_CHANNEL_5 = 5, /*!< DMA Channel Thread 5 */
ALT_DMA_CHANNEL_6 = 6, /*!< DMA Channel Thread 6 */
ALT_DMA_CHANNEL_7 = 7 /*!< DMA Channel Thread 7 */
}
ALT_DMA_CHANNEL_t;
/*!
* This type definition enumerates the SoC system peripherals implementing the
* required request interface that enables direct DMA transfers to/from the
* device.
*
* FPGA soft IP interface to the DMA are required to comply with the Synopsys
* protocol.
*
* Request interface numbers 4 through 7 are multiplexed between the CAN
* controllers and soft logic implemented in the FPGA fabric. The selection
* between the CAN controller and FPGA interfaces is determined at DMA
* initialization.
*/
typedef enum ALT_DMA_PERIPH_e
{
ALT_DMA_PERIPH_FPGA_0 = 0, /*!< FPGA soft IP interface 0 */
ALT_DMA_PERIPH_FPGA_1 = 1, /*!< FPGA soft IP interface 1 */
ALT_DMA_PERIPH_FPGA_2 = 2, /*!< FPGA soft IP interface 2 */
ALT_DMA_PERIPH_FPGA_3 = 3, /*!< FPGA soft IP interface 3 */
ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 = 4, /*!< Selectively MUXed FPGA 4 or CAN 0 interface 1 */
ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 = 5, /*!< Selectively MUXed FPGA 5 or CAN 0 interface 2 */
ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 = 6, /*!< Selectively MUXed FPGA 6 or CAN 1 interface 1 */
ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 = 7, /*!< Selectively MUXed FPGA 7 or CAN 1 interface 2 */
ALT_DMA_PERIPH_FPGA_4 = 4, /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */
ALT_DMA_PERIPH_FPGA_5 = 5, /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */
ALT_DMA_PERIPH_FPGA_6 = 6, /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */
ALT_DMA_PERIPH_FPGA_7 = 7, /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */
ALT_DMA_PERIPH_CAN0_IF1 = 4, /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */
ALT_DMA_PERIPH_CAN0_IF2 = 5, /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */
ALT_DMA_PERIPH_CAN1_IF1 = 6, /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */
ALT_DMA_PERIPH_CAN1_IF2 = 7, /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */
ALT_DMA_PERIPH_I2C0_TX = 8, /*!< I<sup>2</sup>C 0 TX */
ALT_DMA_PERIPH_I2C0_RX = 9, /*!< I<sup>2</sup>C 0 RX */
ALT_DMA_PERIPH_I2C1_TX = 10, /*!< I<sup>2</sup>C 1 TX */
ALT_DMA_PERIPH_I2C1_RX = 11, /*!< I<sup>2</sup>C 1 RX */
ALT_DMA_PERIPH_I2C2_TX = 12, /*!< I<sup>2</sup>C 2 TX */
ALT_DMA_PERIPH_I2C2_RX = 13, /*!< I<sup>2</sup>C 2 RX */
ALT_DMA_PERIPH_I2C3_TX = 14, /*!< I<sup>2</sup>C 3 TX */
ALT_DMA_PERIPH_I2C3_RX = 15, /*!< I<sup>2</sup>C 3 RX */
ALT_DMA_PERIPH_SPI0_MASTER_TX = 16, /*!< SPI 0 Master TX */
ALT_DMA_PERIPH_SPI0_MASTER_RX = 17, /*!< SPI 0 Master RX */
ALT_DMA_PERIPH_SPI0_SLAVE_TX = 18, /*!< SPI 0 Slave TX */
ALT_DMA_PERIPH_SPI0_SLAVE_RX = 19, /*!< SPI 0 Slave RX */
ALT_DMA_PERIPH_SPI1_MASTER_TX = 20, /*!< SPI 1 Master TX */
ALT_DMA_PERIPH_SPI1_MASTER_RX = 21, /*!< SPI 1 Master RX */
ALT_DMA_PERIPH_SPI1_SLAVE_TX = 22, /*!< SPI 1 Slave TX */
ALT_DMA_PERIPH_SPI1_SLAVE_RX = 23, /*!< SPI 1 Slave RX */
ALT_DMA_PERIPH_QSPI_FLASH_TX = 24, /*!< QSPI Flash TX */
ALT_DMA_PERIPH_QSPI_FLASH_RX = 25, /*!< QSPI Flash RX */
ALT_DMA_PERIPH_STM = 26, /*!< System Trace Macrocell */
ALT_DMA_PERIPH_RESERVED = 27, /*!< Reserved */
ALT_DMA_PERIPH_UART0_TX = 28, /*!< UART 0 TX */
ALT_DMA_PERIPH_UART0_RX = 29, /*!< UART 0 RX */
ALT_DMA_PERIPH_UART1_TX = 30, /*!< UART 1 TX */
ALT_DMA_PERIPH_UART1_RX = 31 /*!< UART 1 RX */
}
ALT_DMA_PERIPH_t;
/*!
* This type enumerates the DMA security state options available.
*/
typedef enum ALT_DMA_SECURITY_e
{
ALT_DMA_SECURITY_DEFAULT = 0, /*!< Use the default security value (e.g. reset default) */
ALT_DMA_SECURITY_SECURE = 1, /*!< Secure */
ALT_DMA_SECURITY_NONSECURE = 2 /*!< Non-secure */
}
ALT_DMA_SECURITY_t;
/*!
* This type definition enumerates the DMA event-interrupt resources.
*/
typedef enum ALT_DMA_EVENT_e
{
ALT_DMA_EVENT_0 = 0, /*!< DMA Event 0 */
ALT_DMA_EVENT_1 = 1, /*!< DMA Event 1 */
ALT_DMA_EVENT_2 = 2, /*!< DMA Event 2 */
ALT_DMA_EVENT_3 = 3, /*!< DMA Event 3 */
ALT_DMA_EVENT_4 = 4, /*!< DMA Event 4 */
ALT_DMA_EVENT_5 = 5, /*!< DMA Event 5 */
ALT_DMA_EVENT_6 = 6, /*!< DMA Event 6 */
ALT_DMA_EVENT_7 = 7, /*!< DMA Event 7 */
ALT_DMA_EVENT_ABORT = 8 /*!< DMA Abort Event */
}
ALT_DMA_EVENT_t;
/*!
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_DMA_COMMON_H__ */

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ALT_DMA_PROGRAM_H__
#define __ALT_DMA_PROGRAM_H__
#include "hwlib.h"
#include "alt_dma_common.h"
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*!
* \addtogroup ALT_DMA_PRG DMA Controller Programming API
*
* This API provides functions for dynamically defining and assembling microcode
* programs for execution on the DMA controller.
*
* The microcode program assembly API provides users with the ability to develop
* highly optimized and tailored algorithms for data transfer between SoC FPGA
* IP blocks and/or system memory.
*
* The same microcode program assembly facilities are also used to implement the
* functions found in the HWLIB Common DMA Operations functional API.
*
* An ALT_DMA_PROGRAM_t structure is used to contain and assemble a DMA
* microcode program. The storage for an ALT_DMA_PROGRAM_t stucture is allocated
* from used specified system memory. Once a microcode program has been
* assembled in a ALT_DMA_PROGRAM_t it may be excecuted on a designated DMA
* channel thread. The microcode program may be rerun on any DMA channel thread
* whenever required as long as the integrity of the ALT_DMA_PROGRAM_t
* containing the program is maintained.
*
* @{
*/
/*!
* This preprocessor declares the DMA channel thread microcode instruction
* cache line width in bytes. It is recommended that the program buffers be
* sized to a multiple of the cache line size. This will allow for the most
* efficient microcode speed and space utilization.
*/
#define ALT_DMA_PROGRAM_CACHE_LINE_SIZE (32)
/*!
* This preprocessor declares the DMA channel thread microcode instruction
* cache line count. Thus the total size of the cache is the cache line size
* multipled by the cache line count. Programs larger than the cache size risk
* having a cache miss while executing.
*/
#define ALT_DMA_PROGRAM_CACHE_LINE_COUNT (16)
/*!
* This preprocessor definition determines the size of the program buffer
* within the ALT_DMA_PROGRAM_t structure. This size should provide adequate
* size for most DMA microcode programs. If calls within this API are
* reporting out of memory response codes, consider increasing the provisioned
* program buffersize.
*
* To specify another DMA microcode program buffer size, redefine the macro
* below by defining ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE to another size in
* your Makefile. It is recommended that the size be a multiple of the
* microcode engine cache line size. See ALT_DMA_PROGRAM_CACHE_LINE_SIZE for
* more information. The largest supported buffer size is 65536 bytes.
*/
#ifndef ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE
#define ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE (ALT_DMA_PROGRAM_CACHE_LINE_SIZE * ALT_DMA_PROGRAM_CACHE_LINE_COUNT)
#endif
/*!
* This type defines the structure used to assemble and contain a microcode
* program which can be executed by the DMA controller. The internal members
* are undocumented and should not be altered outside of this API.
*/
typedef struct ALT_DMA_PROGRAM_s
{
uint32_t flag;
uint16_t buffer_start;
uint16_t code_size;
uint16_t loop0;
uint16_t loop1;
uint16_t sar;
uint16_t dar;
/*
* Add a little extra space so that regardless of where this structure
* sits in memory, a suitable start address can be aligned to the cache
* line stride while providing the requested buffer space.
*/
uint8_t program[ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE +
ALT_DMA_PROGRAM_CACHE_LINE_SIZE];
}
ALT_DMA_PROGRAM_t;
/*!
* This type definition enumerates the DMA controller register names for use in
* microcode program definition.
*/
typedef enum ALT_DMA_PROGRAM_REG_e
{
/*! Source Address Register */
ALT_DMA_PROGRAM_REG_SAR = 0x0,
/*! Destination Address Register */
ALT_DMA_PROGRAM_REG_DAR = 0x2,
/*! Channel Control Register */
ALT_DMA_PROGRAM_REG_CCR = 0x1
}
ALT_DMA_PROGRAM_REG_t;
/*!
* This type definition enumerates the instruction modifier options available
* for use with selected DMA microcode instructions.
*
* The enumerations values are context dependent upon the instruction being
* modified.
*
* For the <b>DMALD[S|B]</b>, <b>DMALDP\<S|B></b>, <b>DMAST[S|B]</b>, and
* <b>DMASTP\<S|B></b> microcode instructions, the enumeration
* ALT_DMA_PROGRAM_INST_MOD_SINGLE specifies the <b>S</b> option modifier
* while the enumeration ALT_DMA_PROGRAM_INST_MOD_BURST specifies the <b>B</b>
* option modifier. The enumeration ALT_DMA_PROGRAM_INST_MOD_NONE specifies
* that no modifier is present for instructions where use of <b>[S|B]</b> is
* optional.
*
* For the <b>DMAWFP</b> microcode instruction, the enumerations
* ALT_DMA_PROGRAM_INST_MOD_SINGLE, ALT_DMA_PROGRAM_INST_MOD_BURST, or
* ALT_DMA_PROGRAM_INST_MOD_PERIPH each specify one of the corresponding
* options <b>\<single|burst|periph></b>.
*/
typedef enum ALT_DMA_PROGRAM_INST_MOD_e
{
/*!
* This DMA instruction modifier specifies that no special modifier is
* added to the instruction.
*/
ALT_DMA_PROGRAM_INST_MOD_NONE,
/*!
* Depending on the DMA microcode instruction modified, this modifier
* specifies <b>S</b> case for a <b>[S|B]</b> or a <b>\<single></b> for a
* <b>\<single|burst|periph></b>.
*/
ALT_DMA_PROGRAM_INST_MOD_SINGLE,
/*!
* Depending on the DMA microcode instruction modified, this modifier
* specifies <b>B</b> case for a <b>[S|B]</b> or a <b>\<burst></b> for a
* <b>\<single|burst|periph></b>.
*/
ALT_DMA_PROGRAM_INST_MOD_BURST,
/*!
* This DMA instruction modifier specifies a <b>\<periph></b> for a
* <b>\<single|burst|periph></b>.
*/
ALT_DMA_PROGRAM_INST_MOD_PERIPH
}
ALT_DMA_PROGRAM_INST_MOD_t;
/*!
* This function initializes a system memory buffer for use as a DMA microcode
* program buffer. This should be the first API call made on the program
* buffer type.
*
* \param pgm
* A pointer to a DMA program buffer structure.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR Details about error status code
*/
ALT_STATUS_CODE alt_dma_program_init(ALT_DMA_PROGRAM_t * pgm);
/*!
* This function verifies that the DMA microcode program buffer is no longer
* in use and performs any needed uninitialization steps.
*
* \param pgm
* A pointer to a DMA program buffer structure.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR Details about error status code
*/
ALT_STATUS_CODE alt_dma_program_uninit(ALT_DMA_PROGRAM_t * pgm);
/*!
* This function clears the existing DMA microcode program in the given
* program buffer.
*
* \param pgm
* A pointer to a DMA program buffer structure.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR Details about error status code.
*/
ALT_STATUS_CODE alt_dma_program_clear(ALT_DMA_PROGRAM_t * pgm);
/*!
* This function validate that the given DMA microcode program buffer contains
* a well formed program. If caches are enabled, the program buffer contents
* will be cleaned to RAM.
*
* \param pgm
* A pointer to a DMA program buffer structure.
*
* \retval ALT_E_SUCCESS The given program is well formed.
* \retval ALT_E_ERROR The given program is not well formed.
* \retval ALT_E_TMO The cache operation timed out.
*/
ALT_STATUS_CODE alt_dma_program_validate(const ALT_DMA_PROGRAM_t * pgm);
/*!
* This function reports the number bytes incremented for the register
* specified. The purpose is to determine the progress of an ongoing DMA
* transfer.
*
* It is implemented by calculating the difference of the programmed SAR or DAR
* with the current channel SAR or DAR register value.
*
* \param pgm
* A pointer to a DMA program buffer structure.
*
* \param channel
* The channel that the program is running on.
*
* \param reg
* Register to change the value for. Valid for only
* ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR.
*
* \param current
* The current snapshot value of the register read from the DMA
* channel.
*
* \param progress
* [out] A pointer to a memory location that will be used to store
* the number of bytes transfered.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR Details about error status code.
* \retval ALT_E_BAD_ARG The specified channel is invalid, the specified
* register is invalid, or the DMAMOV for the
* specified register has not yet been assembled
* in the current program buffer.
*/
ALT_STATUS_CODE alt_dma_program_progress_reg(ALT_DMA_PROGRAM_t * pgm,
ALT_DMA_PROGRAM_REG_t reg,
uint32_t current, uint32_t * progress);
/*!
* This function updates a pre-existing DMAMOV value affecting the SAR or DAR
* registers. This allows for pre-assembled programs that can be used on
* different source and destination addresses.
*
* \param pgm
* A pointer to a DMA program buffer structure.
*
* \param reg
* Register to change the value for. Valid for only
* ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR.
*
* \param val
* The value to update to.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR Details about error status code.
* \retval ALT_E_BAD_ARG The specified register is invalid or the DMAMOV
* for the specified register has not yet been
* assembled in the current program buffer.
*/
ALT_STATUS_CODE alt_dma_program_update_reg(ALT_DMA_PROGRAM_t * pgm,
ALT_DMA_PROGRAM_REG_t reg, uint32_t val);
/*!
*/
/*!
* Assembles a DMAADDH (Add Halfword) instruction into the microcode program
* buffer. This instruction uses 3 bytes of buffer space.
*
* \param pgm
* The DMA program buffer to contain the assembled instruction.
*
* \param addr_reg
* The channel address register (ALT_DMA_PROGRAM_REG_DAR or
* ALT_DMA_PROGRAM_REG_SAR) to add the value to.
*
* \param val
* The 16-bit unsigned value to add to the channel address
* register.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
* \retval ALT_E_BAD_ARG Invalid channel register specified.
*/
// Assembler Syntax: DMAADDH <address_register>, <16-bit immediate>
ALT_STATUS_CODE alt_dma_program_DMAADDH(ALT_DMA_PROGRAM_t * pgm,
ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val);
/*!
* Assembles a DMAADNH (Add Negative Halfword) instruction into the microcode
* program buffer. This instruction uses 3 bytes of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \param addr_reg
* The channel address register (ALT_DMA_PROGRAM_REG_DAR or
* ALT_DMA_PROGRAM_REG_SAR) to add the value to.
*
* \param val
* The 16-bit unsigned value to add to the channel address
* register.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
* \retval ALT_E_BAD_ARG Invalid channel register specified.
*/
// Assembler Syntax: DMAADNH <address_register>, <16-bit immediate>
ALT_STATUS_CODE alt_dma_program_DMAADNH(ALT_DMA_PROGRAM_t * pgm,
ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val);
/*!
* Assembles a DMAEND (End) instruction into the microcode program buffer.
* This instruction uses 1 byte of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
*/
// Assembler Syntax: DMAEND
ALT_STATUS_CODE alt_dma_program_DMAEND(ALT_DMA_PROGRAM_t * pgm);
/*!
* Assembles a DMAFLUSHP (Flush Peripheral) instruction into the microcode
* program buffer. This instruction uses 2 bytes of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \param periph
* The peripheral to flush.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
* \retval ALT_E_BAD_ARG Invalid peripheral specified.
*/
// Assembler Syntax: DMAFLUSHP <peripheral>
ALT_STATUS_CODE alt_dma_program_DMAFLUSHP(ALT_DMA_PROGRAM_t * pgm,
ALT_DMA_PERIPH_t periph);
/*!
* Assembles a DMAGO (Go) instruction into the microcode program buffer. This
* instruction uses 6 bytes of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \param channel
* The stopped channel to act upon.
*
* \param val
* The value to write to the channel program counter register.
*
* \param sec
* The security state for the operation.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
* \retval ALT_E_BAD_ARG Invalid channel or security specified.
*/
// Assembler Syntax: DMAGO <channel_number>, <32-bit_immediate> [, ns]
ALT_STATUS_CODE alt_dma_program_DMAGO(ALT_DMA_PROGRAM_t * pgm,
ALT_DMA_CHANNEL_t channel, uint32_t val,
ALT_DMA_SECURITY_t sec);
/*!
* Assembles a DMAKILL (Kill) instruction into the microcode program buffer.
* This instruction uses 1 byte of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
*/
// Assembler Syntax: DMAKILL
ALT_STATUS_CODE alt_dma_program_DMAKILL(ALT_DMA_PROGRAM_t * pgm);
/*!
* Assembles a DMALD (Load) instruction into the microcode program buffer.
* This instruction uses 1 byte of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \param mod
* The program instruction modifier for the type of transfer.
* Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and
* ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
* \retval ALT_E_BAD_ARG Invalid instruction modifier specified.
*/
// Assembler Syntax: DMALD[S|B]
ALT_STATUS_CODE alt_dma_program_DMALD(ALT_DMA_PROGRAM_t * pgm,
ALT_DMA_PROGRAM_INST_MOD_t mod);
/*!
* Assembles a DMALDP (Load and notify Peripheral) instruction into the
* microcode program buffer. This instruction uses 2 bytes of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \param mod
* The program instruction modifier for the type of transfer.
* Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and
* ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
*
* \param periph
* The peripheral to notify.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
* \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral
* specified.
*/
// Assembler Syntax: DMALDP<S|B> <peripheral>
ALT_STATUS_CODE alt_dma_program_DMALDP(ALT_DMA_PROGRAM_t * pgm,
ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph);
/*!
* Assembles a DMALP (Loop) instruction into the microcode program buffer.
* This instruction uses 2 bytes of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \param iterations
* The number of iterations to run for. Valid values are 1 - 256.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
* \retval ALT_E_BAD_ARG Invalid iterations specified.
* \retval ALT_E_BAD_OPERATION All loop registers are in use.
*/
// Assembler Syntax: DMALP [<LC0>|<LC1>] <loop_iterations>
ALT_STATUS_CODE alt_dma_program_DMALP(ALT_DMA_PROGRAM_t * pgm,
uint32_t iterations);
/*!
* Assembles a DMALPEND (Loop End) instruction into the microcode program
* buffer. This instruction uses 2 bytes of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \param mod
* The program instruction modifier for the loop terminator. Only
* ALT_DMA_PROGRAM_INST_MOD_NONE, ALT_DMA_PROGRAM_INST_MOD_SINGLE
* and ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
* \retval ALT_E_BAD_ARG Invalid instruction modifier specified.
* \retval ALT_E_ARG_RANGE Loop size is too large to be supported.
* \retval ALT_E_BAD_OPERATION A valid DMALP or DMALPFE was not added to
* the program buffer before adding this
* DMALPEND instruction.
*/
// Assembler Syntax: DMALPEND[S|B]
ALT_STATUS_CODE alt_dma_program_DMALPEND(ALT_DMA_PROGRAM_t * pgm,
ALT_DMA_PROGRAM_INST_MOD_t mod);
/*!
* Assembles a DMALPFE (Loop Forever) instruction into the microcode program
* buffer. No instruction is added to the buffer but a previous DMALPEND to
* create an infinite loop.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
*/
// Assembler Syntax: DMALPFE
ALT_STATUS_CODE alt_dma_program_DMALPFE(ALT_DMA_PROGRAM_t * pgm);
/*!
* Assembles a DMAMOV (Move) instruction into the microcode program buffer.
* This instruction uses 6 bytes of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \param chan_reg
* The channel non-looping register (ALT_DMA_PROGRAM_REG_SAR,
* ALT_DMA_PROGRAM_REG_DAR or ALT_DMA_PROGRAM_REG_CCR) to copy
* the value to.
*
* \param val
* The value to write to the specified register.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
* \retval ALT_E_BAD_ARG Invalid channel register specified.
*/
// Assembler Syntax: DMAMOV <destination_register>, <32-bit_immediate>
ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm,
ALT_DMA_PROGRAM_REG_t chan_reg, uint32_t val);
/*!
* Assembles a DMANOP (No Operation) instruction into the microcode program
* buffer. This instruction uses 1 byte of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
*/
// Assembler Syntax: DMANOP
ALT_STATUS_CODE alt_dma_program_DMANOP(ALT_DMA_PROGRAM_t * pgm);
/*!
* Assembles a DMARMB (Read Memory Barrier) instruction into the microcode
* program buffer. This instruction uses 1 byte of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
*/
// Assembler Syntax: DMARMB
ALT_STATUS_CODE alt_dma_program_DMARMB(ALT_DMA_PROGRAM_t * pgm);
/*!
* Assembles a DMASEV (Send Event) instruction into the microcode program
* buffer. This instruction uses 2 byte of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \param evt
* The event to send.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
* \retval ALT_E_BAD_ARG Invalid event specified.
*/
// Assembler Syntax: DMASEV <event_num>
ALT_STATUS_CODE alt_dma_program_DMASEV(ALT_DMA_PROGRAM_t * pgm,
ALT_DMA_EVENT_t evt);
/*!
* Assembles a DMAST (Store) instruction into the microcode program buffer.
* This instruction uses 1 byte of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \param mod
* The program instruction modifier for the type of transfer.
* Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and
* ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
*/
// Assembler Syntax: DMAST[S|B]
ALT_STATUS_CODE alt_dma_program_DMAST(ALT_DMA_PROGRAM_t * pgm,
ALT_DMA_PROGRAM_INST_MOD_t mod);
/*!
* Assembles a DMASTP (Store and notify Peripheral) instruction into the
* microcode program buffer. This instruction uses 2 bytes of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \param mod
* The program instruction modifier for the type of transfer.
* Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and
* ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
*
* \param periph
* The peripheral to notify.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
* \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral
* specified.
*/
// Assembler Syntax: DMASTP<S|B> <peripheral>
ALT_STATUS_CODE alt_dma_program_DMASTP(ALT_DMA_PROGRAM_t * pgm,
ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph);
/*!
* Assembles a DMASTZ (Store Zero) instruction into the microcode program
* buffer. This instruction uses 1 byte of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
*/
// Assembler Syntax: DMASTZ
ALT_STATUS_CODE alt_dma_program_DMASTZ(ALT_DMA_PROGRAM_t * pgm);
/*!
* Assembles a DMAWFE (Wait For Event) instruction into the microcode program
* buffer. This instruction uses 2 byte of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \param evt
* The event to wait for.
*
* \param invalid
* If invalid is set to true, the instruction will be configured
* to invalidate the instruction cache for the current DMA
* thread.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
* \retval ALT_E_BAD_ARG Invalid event specified.
*/
// Assembler Syntax: DMAWFE <event_num>[, invalid]
ALT_STATUS_CODE alt_dma_program_DMAWFE(ALT_DMA_PROGRAM_t * pgm,
ALT_DMA_EVENT_t evt, bool invalid);
/*!
* Assembles a DMAWFP (Wait for Peripheral) instruction into the microcode
* program buffer. This instruction uses 2 bytes of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \param periph
* The peripheral to wait on.
*
* \param mod
* The program instruction modifier for the type of transfer.
* Only ALT_DMA_PROGRAM_INST_MOD_SINGLE,
* ALT_DMA_PROGRAM_INST_MOD_BURST, or
* ALT_DMA_PROGRAM_INST_MOD_PERIPH are valid options.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
* \retval ALT_E_BAD_ARG Invalid peripheral or instruction modifier
* specified.
*/
// Assembler Syntax: DMAWFP <peripheral>, <single|burst|periph>
ALT_STATUS_CODE alt_dma_program_DMAWFP(ALT_DMA_PROGRAM_t * pgm,
ALT_DMA_PERIPH_t periph, ALT_DMA_PROGRAM_INST_MOD_t mod);
/*!
* Assembles a DMAWMB (Write Memory Barrier) instruction into the microcode
* program buffer. This instruction uses 1 byte of buffer space.
*
* \param pgm
* The DMA programm buffer to contain the assembled instruction.
*
* \retval ALT_E_SUCCESS Successful instruction assembly status.
* \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
*/
// Assembler Syntax: DMAWMB
ALT_STATUS_CODE alt_dma_program_DMAWMB(ALT_DMA_PROGRAM_t * pgm);
/*!
* \addtogroup DMA_CCR Support for DMAMOV CCR
*
* The ALT_DMA_CCR_OPT_* macro definitions are defined here to facilitate the
* dynamic microcode programming of the assembler directive:
\verbatim
DMAMOV CCR, [SB<1-16>] [SS<8|16|32|64|128>] [SA<I|F>]
[SP<imm3>] [SC<imm4>]
[DB<1-16>] [DS<8|16|32|64|128>] [DA<I|F>]
[DP<imm3>] [DC<imm4>]
[ES<8|16|32|64|128>]
\endverbatim
* with a DMAMOV instruction (see: alt_dma_program_DMAMOV()).
*
* For example the assembler directive:
\verbatim
DMAMOV CCR SB1 SS32 DB1 DS32
\endverbatim
* would be dynamically programmed with the following API call:
\verbatim
alt_dma_program_DMAMOV( pgm,
ALT_DMA_PROGRAM_REG_CCR,
( ALT_DMA_CCR_OPT_SB1
| ALT_DMA_CCR_OPT_SS32
| ALT_DMA_CCR_OPT_SA_DEFAULT
| ALT_DMA_CCR_OPT_SP_DEFAULT
| ALT_DMA_CCR_OPT_SC_DEFAULT
| ALT_DMA_CCR_OPT_DB1
| ALT_DMA_CCR_OPT_DS32
| ALT_DMA_CCR_OPT_DA_DEFAULT
| ALT_DMA_CCR_OPT_DP_DEFAULT
| ALT_DMA_CCR_OPT_DC_DEFAULT
| ALT_DMA_CCR_OPT_ES8
)
);
\endverbatim
*
* Each CCR option category should be specified regardless of whether it
* specifies a custom value or the normal default value (i.e. an
* ALT_DMA_CCR_OPT_*_DEFAULT.
*
* @{
*/
/*
* Source Address {Fixed,Incrementing}
*/
/*! Source Address Fixed address burst. */
#define ALT_DMA_CCR_OPT_SAF (0 << 0)
/*! Source Address Incrementing address burst. */
#define ALT_DMA_CCR_OPT_SAI (1 << 0)
/*! Source Address Default value. */
#define ALT_DMA_CCR_OPT_SA_DEFAULT ALT_DMA_CCR_OPT_SAI
/*
* Source burst Size (in bits)
*/
/*! Source burst Size of 8 bits. */
#define ALT_DMA_CCR_OPT_SS8 (0 << 1)
/*! Source burst Size of 16 bits. */
#define ALT_DMA_CCR_OPT_SS16 (1 << 1)
/*! Source burst Size of 32 bits. */
#define ALT_DMA_CCR_OPT_SS32 (2 << 1)
/*! Source burst Size of 64 bits. */
#define ALT_DMA_CCR_OPT_SS64 (3 << 1)
/*! Source burst Size of 128 bits. */
#define ALT_DMA_CCR_OPT_SS128 (4 << 1)
/*! Source burst Size default bits. */
#define ALT_DMA_CCR_OPT_SS_DEFAULT ALT_DMA_CCR_OPT_SS8
/*
* Source burst Length (in transfer(s))
*/
/*! Source Burst length of 1 transfer. */
#define ALT_DMA_CCR_OPT_SB1 (0x0 << 4)
/*! Source Burst length of 2 transfers. */
#define ALT_DMA_CCR_OPT_SB2 (0x1 << 4)
/*! Source Burst length of 3 transfers. */
#define ALT_DMA_CCR_OPT_SB3 (0x2 << 4)
/*! Source Burst length of 4 transfers. */
#define ALT_DMA_CCR_OPT_SB4 (0x3 << 4)
/*! Source Burst length of 5 transfers. */
#define ALT_DMA_CCR_OPT_SB5 (0x4 << 4)
/*! Source Burst length of 6 transfers. */
#define ALT_DMA_CCR_OPT_SB6 (0x5 << 4)
/*! Source Burst length of 7 transfers. */
#define ALT_DMA_CCR_OPT_SB7 (0x6 << 4)
/*! Source Burst length of 8 transfers. */
#define ALT_DMA_CCR_OPT_SB8 (0x7 << 4)
/*! Source Burst length of 9 transfers. */
#define ALT_DMA_CCR_OPT_SB9 (0x8 << 4)
/*! Source Burst length of 10 transfers. */
#define ALT_DMA_CCR_OPT_SB10 (0x9 << 4)
/*! Source Burst length of 11 transfers. */
#define ALT_DMA_CCR_OPT_SB11 (0xa << 4)
/*! Source Burst length of 12 transfers. */
#define ALT_DMA_CCR_OPT_SB12 (0xb << 4)
/*! Source Burst length of 13 transfers. */
#define ALT_DMA_CCR_OPT_SB13 (0xc << 4)
/*! Source Burst length of 14 transfers. */
#define ALT_DMA_CCR_OPT_SB14 (0xd << 4)
/*! Source Burst length of 15 transfers. */
#define ALT_DMA_CCR_OPT_SB15 (0xe << 4)
/*! Source Burst length of 16 transfers. */
#define ALT_DMA_CCR_OPT_SB16 (0xf << 4)
/*! Source Burst length default transfers. */
#define ALT_DMA_CCR_OPT_SB_DEFAULT ALT_DMA_CCR_OPT_SB1
/*
* Source Protection
*/
/*! Source Protection bits for AXI bus ARPROT[2:0]. */
#define ALT_DMA_CCR_OPT_SP(imm3) ((imm3) << 8)
/*! Source Protection bits default value. */
#define ALT_DMA_CCR_OPT_SP_DEFAULT ALT_DMA_CCR_OPT_SP(0)
/*
* Source cache
*/
/*! Source Cache bits for AXI bus ARCACHE[2:0]. */
#define ALT_DMA_CCR_OPT_SC(imm4) ((imm4) << 11)
/*! Source Cache bits default value. */
#define ALT_DMA_CCR_OPT_SC_DEFAULT ALT_DMA_CCR_OPT_SC(0)
/*
* Destination Address {Fixed,Incrementing}
*/
/*! Destination Address Fixed address burst. */
#define ALT_DMA_CCR_OPT_DAF (0 << 14)
/*! Destination Address Incrementing address burst. */
#define ALT_DMA_CCR_OPT_DAI (1 << 14)
/*! Destination Address Default value. */
#define ALT_DMA_CCR_OPT_DA_DEFAULT ALT_DMA_CCR_OPT_DAI
/*
* Destination burst Size (in bits)
*/
/*! Destination burst Size of 8 bits. */
#define ALT_DMA_CCR_OPT_DS8 (0 << 15)
/*! Destination burst Size of 16 bits. */
#define ALT_DMA_CCR_OPT_DS16 (1 << 15)
/*! Destination burst Size of 32 bits. */
#define ALT_DMA_CCR_OPT_DS32 (2 << 15)
/*! Destination burst Size of 64 bits. */
#define ALT_DMA_CCR_OPT_DS64 (3 << 15)
/*! Destination burst Size of 128 bits. */
#define ALT_DMA_CCR_OPT_DS128 (4 << 15)
/*! Destination burst Size default bits. */
#define ALT_DMA_CCR_OPT_DS_DEFAULT ALT_DMA_CCR_OPT_DS8
/*
* Destination Burst length (in transfer(s))
*/
/*! Destination Burst length of 1 transfer. */
#define ALT_DMA_CCR_OPT_DB1 (0x0 << 18)
/*! Destination Burst length of 2 transfers. */
#define ALT_DMA_CCR_OPT_DB2 (0x1 << 18)
/*! Destination Burst length of 3 transfers. */
#define ALT_DMA_CCR_OPT_DB3 (0x2 << 18)
/*! Destination Burst length of 4 transfers. */
#define ALT_DMA_CCR_OPT_DB4 (0x3 << 18)
/*! Destination Burst length of 5 transfers. */
#define ALT_DMA_CCR_OPT_DB5 (0x4 << 18)
/*! Destination Burst length of 6 transfers. */
#define ALT_DMA_CCR_OPT_DB6 (0x5 << 18)
/*! Destination Burst length of 7 transfers. */
#define ALT_DMA_CCR_OPT_DB7 (0x6 << 18)
/*! Destination Burst length of 8 transfers. */
#define ALT_DMA_CCR_OPT_DB8 (0x7 << 18)
/*! Destination Burst length of 9 transfers. */
#define ALT_DMA_CCR_OPT_DB9 (0x8 << 18)
/*! Destination Burst length of 10 transfers. */
#define ALT_DMA_CCR_OPT_DB10 (0x9 << 18)
/*! Destination Burst length of 11 transfers. */
#define ALT_DMA_CCR_OPT_DB11 (0xa << 18)
/*! Destination Burst length of 12 transfers. */
#define ALT_DMA_CCR_OPT_DB12 (0xb << 18)
/*! Destination Burst length of 13 transfers. */
#define ALT_DMA_CCR_OPT_DB13 (0xc << 18)
/*! Destination Burst length of 14 transfers. */
#define ALT_DMA_CCR_OPT_DB14 (0xd << 18)
/*! Destination Burst length of 15 transfers. */
#define ALT_DMA_CCR_OPT_DB15 (0xe << 18)
/*! Destination Burst length of 16 transfers. */
#define ALT_DMA_CCR_OPT_DB16 (0xf << 18)
/*! Destination Burst length default transfers. */
#define ALT_DMA_CCR_OPT_DB_DEFAULT ALT_DMA_CCR_OPT_DB1
/*
* Destination Protection
*/
/*! Destination Protection bits for AXI bus AWPROT[2:0]. */
#define ALT_DMA_CCR_OPT_DP(imm3) ((imm3) << 22)
/*! Destination Protection bits default value. */
#define ALT_DMA_CCR_OPT_DP_DEFAULT ALT_DMA_CCR_OPT_DP(0)
/*
* Destination Cache
*/
/*! Destination Cache bits for AXI bus AWCACHE[3,1:0]. */
#define ALT_DMA_CCR_OPT_DC(imm4) ((imm4) << 25)
/*! Destination Cache bits default value. */
#define ALT_DMA_CCR_OPT_DC_DEFAULT ALT_DMA_CCR_OPT_DC(0)
/*
* Endian Swap size (in bits)
*/
/*! Endian Swap: No swap, 8-bit data. */
#define ALT_DMA_CCR_OPT_ES8 (0 << 28)
/*! Endian Swap: Swap bytes within 16-bit data. */
#define ALT_DMA_CCR_OPT_ES16 (1 << 28)
/*! Endian Swap: Swap bytes within 32-bit data. */
#define ALT_DMA_CCR_OPT_ES32 (2 << 28)
/*! Endian Swap: Swap bytes within 64-bit data. */
#define ALT_DMA_CCR_OPT_ES64 (3 << 28)
/*! Endian Swap: Swap bytes within 128-bit data. */
#define ALT_DMA_CCR_OPT_ES128 (4 << 28)
/*! Endian Swap: Default byte swap. */
#define ALT_DMA_CCR_OPT_ES_DEFAULT ALT_DMA_CCR_OPT_ES8
/*! Default CCR register options for a DMAMOV CCR assembler directive. */
#define ALT_DMA_CCR_OPT_DEFAULT \
(ALT_DMA_CCR_OPT_SB1 | ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_SAI | \
ALT_DMA_CCR_OPT_SP(0) | ALT_DMA_CCR_OPT_SC(0) | \
ALT_DMA_CCR_OPT_DB1 | ALT_DMA_CCR_OPT_DS8 | ALT_DMA_CCR_OPT_DAI | \
ALT_DMA_CCR_OPT_DP(0) | ALT_DMA_CCR_OPT_DC(0) | \
ALT_DMA_CCR_OPT_ES8)
/*!
* @}
*/
/*!
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_DMA_PROGRAM_H__ */

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FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_ecc.h
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/*! \file
* Altera - SoC FPGA ECC Management
*/
/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ALT_ECC_H__
#define __ALT_ECC_H__
#include "hwlib.h"
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/******************************************************************************/
/*! \addtogroup ALT_ECC Error Correcting Code (ECC) Management
*
* This module provides programmatic access and control of the Error-Correcting
* Code (ECC) protection features for the embedded RAM blocks in HPS peripherals.
*
* ECC protection can be enabled or disabled for each of the following HPS
* peripheral embedded RAM blocks:
* * L2 Cache Data RAM
* * On-chip RAM (OCRAM)
* * USB 2.0 OTG Controllers
* * Ethernet Media Access Controllers (EMAC)
* * CAN Controllers
* * NAND Flash Controller
* * Quad SPI (QSPI) Flash Controller
* * SD/MMC Controller
* * DMA Controller
*
* All ECC protected peripherals support detection of single bit, correctable
* errors and double bit, non-correctable errors.
*
* With the exception of L2 cache data RAM, each of the ECC protected memories
* generates single and double bit interrupts to the global interrupt controller
* (GIC) and sets error status condition bits in the System Manager. The L2 cache
* interrupt only generates single and double bit interrupts to the global
* interrupt controller (GIC) - no error status conditions are set in the System
* Manager.
*
* When ECC protection is enabled, RAM data should first be written before ever
* being read. Otherwise the ECC syndrome encoding bits for each memory location
* probably contain random uninitialized data that will result in spurious ECC
* errors. A utility function is provided to guarantee proper initialization is
* performed on a memory block once ECC is enabled.
*
* Fault injection capabilities for single, correctable errors and double,
* non-correctable errors are provided for test purposes.
* @{
*/
/******************************************************************************/
/*!
* This type enumerates the ECC protected RAM blocks embedded in HPS peripherals.
*/
typedef enum ALT_ECC_RAM_ENUM_e
{
ALT_ECC_RAM_L2_DATA, /*!< L2 Cache Data RAM */
ALT_ECC_RAM_OCRAM, /*!< On-chip RAM */
ALT_ECC_RAM_USB0, /*!< USB0 Controller RAM */
ALT_ECC_RAM_USB1, /*!< USB1 Controller RAM */
ALT_ECC_RAM_EMAC0, /*!< EMAC0 Receive/Transmit Data FIFO Buffer RAMs */
ALT_ECC_RAM_EMAC1, /*!< EMAC1 Receive/Transmit Data FIFO Buffer RAMs */
ALT_ECC_RAM_DMA, /*!< DMA Controller RAM */
ALT_ECC_RAM_CAN0, /*!< CAN0 RAM */
ALT_ECC_RAM_CAN1, /*!< CAN1 RAM */
ALT_ECC_RAM_NAND, /*!< NAND Controller Buffer, Read FIFO, Write FIFO RAMs */
ALT_ECC_RAM_QSPI, /*!< QSPI Controller RAM */
ALT_ECC_RAM_SDMMC /*!< SD/MMC Controller Port A and Port B RAMs */
} ALT_ECC_RAM_ENUM_t;
/******************************************************************************/
/*!
* This type definition enumerates the ECC status conditions for each of the HPS
* embedded RAM blocks.
*
* The enumerations serve as masks for the ECC status conditions monitored
* in each of the individual embedded RAM blocks. If ECC protection is enabled on
* the selected RAM block, then a mask bit corresponding to the type of ECC error
* is set to 1 if the error occurs.
*
* Additionally, when any of these ECC error conditions occur, then an ECC interrupt
* signal is asserted.
*
* Interrupt sources are cleared by calling alt_ecc_status_clear(). The ECC
* interrupt sources are enabled automatically when ECC is started.
*/
typedef enum ALT_ECC_ERROR_STATUS_e
{
ALT_ECC_ERROR_L2_BYTE_WR = 0x1, /*!< L2 cache ECC protection bits are
* not valid because a cache write
* violated data width and/or
* alignment requirements.
* Interrupt: \b l2_ecc_byte_wr_IRQ
*/
ALT_ECC_ERROR_L2_SERR = 0x2, /*!< L2 Cache
* ECC single bit, correctable error status
* Interrupt: \b l2_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_L2_DERR = 0x4, /*!< L2 Cache
* ECC double bit, non-correctable error status
* Interrupt: \b l2_ecc_uncorrected_IRQ
*/
ALT_ECC_ERROR_OCRAM_SERR = 0x1, /*!< On-chip RAM
* ECC single bit, correctable error status
* Interrupt: \b ram_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_OCRAM_DERR = 0x2, /*!< On-chip RAM
* ECC double bit, non-correctable error status
* Interrupt: \b ram_ecc_uncorrected_IRQ
*/
ALT_ECC_ERROR_USB0_SERR = 0x1, /*!< USB0 Controller
* ECC single bit, correctable error status
* Interrupt: \b usb0_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_USB0_DERR = 0x2, /*!< USB0 Controller
* ECC double bit, non-correctable error status
* Interrupt: \b usb0_ecc_uncorrected_IRQ
*/
ALT_ECC_ERROR_USB1_SERR = 0x1, /*!< USB1 Controller
* ECC single bit, correctable error status
* Interrupt: \b usb1_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_USB1_DERR = 0x2, /*!< USB1 Controller
* ECC double bit, non-correctable error status
* Interrupt: \b usb1_ecc_uncorrected_IRQ
*/
ALT_ECC_ERROR_EMAC0_TX_FIFO_SERR = 0x1, /*!< EMAC0 Transmit Data FIFO Buffer
* ECC single bit, correctable error status
* Interrupt: \b emac0_tx_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_EMAC0_TX_FIFO_DERR = 0x2, /*!< EMAC0 Transmit Data FIFO Buffer
* ECC double bit, non-correctable error status
* Interrupt: \b emac0_tx_ecc_uncorrected_IRQ
*/
ALT_ECC_ERROR_EMAC0_RX_FIFO_SERR = 0x4, /*!< EMAC0 Receive Data FIFO Buffer
* ECC single bit, correctable error status
* Interrupt: \b emac0_rx_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_EMAC0_RX_FIFO_DERR = 0x8, /*!< EMAC0 Receive Data FIFO Buffer
* ECC double bit, non-correctable error status
* Interrupt: \b emac0_rx_ecc_uncorrected_IRQ
*/
ALT_ECC_ERROR_EMAC1_TX_FIFO_SERR = 0x1, /*!< EMAC1 Transmit Data FIFO Buffer
* ECC single bit, correctable error status
* Interrupt: \b emac1_tx_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_EMAC1_TX_FIFO_DERR = 0x2, /*!< EMAC1 Transmit Data FIFO Buffer
* ECC double bit, non-correctable error status
* Interrupt: \b emac1_tx_ecc_uncorrected_IRQ
*/
ALT_ECC_ERROR_EMAC1_RX_FIFO_SERR = 0x4, /*!< EMAC1 Receive Data FIFO Buffer
* ECC single bit, correctable error status
* Interrupt: \b emac1_rx_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_EMAC1_RX_FIFO_DERR = 0x8, /*!< EMAC1 Receive Data FIFO Buffer
* ECC double bit, non-correctable error status
* Interrupt: \b emac1_rx_ecc_uncorrected_IRQ
*/
ALT_ECC_ERROR_DMA_SERR = 0x1, /*!< DMA Controller
* ECC single bit, correctable error status
* Interrupt: \b dma_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_DMA_DERR = 0x2, /*!< DMA Controller
* ECC double bit, non-correctable error status
* Interrupt: \b dma_ecc_uncorrected_IRQ
*/
ALT_ECC_ERROR_CAN0_SERR = 0x1, /*!< CAN0 Controller
* ECC single bit, correctable error status
* Interrupt: \b can0_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_CAN0_DERR = 0x2, /*!< CAN0 Controller
* ECC double bit, non-correctable error status
* Interrupt: \b can0_ecc_uncorrected_IRQ
*/
ALT_ECC_ERROR_CAN1_SERR = 0x1, /*!< CAN1 Controller
* ECC single bit, correctable error status
* Interrupt: \b can1_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_CAN1_DERR = 0x2, /*!< CAN1 Controller
* ECC double bit, non-correctable error status
* Interrupt: \b can1_ecc_uncorrected_IRQ
*/
ALT_ECC_ERROR_NAND_BUFFER_SERR = 0x1, /*!< NAND Controller Buffer RAM
* ECC single bit, correctable error status
* Interrupt: \b nande_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_NAND_BUFFER_DERR = 0x2, /*!< NAND Controller Buffer RAM
* ECC double bit, non-correctable error status
* Interrupt: \b nande_ecc_uncorrected_IRQ
*/
ALT_ECC_ERROR_NAND_WR_FIFO_SERR = 0x4, /*!< NAND Controller Write FIFO
* ECC single bit, correctable error status
* Interrupt: \b nandw_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_NAND_WR_FIFO_DERR = 0x8, /*!< NAND Controller Write FIFO
* ECC double bit, non-correctable error status
* Interrupt: \b nandw_ecc_uncorrected_IRQ
*/
ALT_ECC_ERROR_NAND_RD_FIFO_SERR = 0x10, /*!< NAND Controller Read FIFO
* ECC single bit, correctable error status
* Interrupt: \b nandr_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_NAND_RD_FIFO_DERR = 0x20, /*!< NAND Controller Read FIFO
* ECC double bit, non-correctable error status
* Interrupt: \b nandr_ecc_uncorrected_IRQ
*/
ALT_ECC_ERROR_QSPI_SERR = 0x1, /*!< QSPI Controller
* ECC single bit, correctable error status
* Interrupt: \b qspi_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_QSPI_DERR = 0x2, /*!< QSPI Controller
* ECC double bit, non-correctable error status
* Interrupt: \b qspi_ecc_uncorrected_IRQ
*/
ALT_ECC_ERROR_SDMMC_PORT_A_SERR = 0x1, /*!< SD/MMC Controller Port A
* ECC single bit, correctable error status
* Interrupt: \b sdmmc_porta_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_SDMMC_PORT_A_DERR = 0x2, /*!< SD/MMC Controller Port A
* ECC double bit, non-correctable error status
* Interrupt: \b sdmmc_porta_ecc_uncorrected_IRQ
*/
ALT_ECC_ERROR_SDMMC_PORT_B_SERR = 0x4, /*!< SD/MMC Controller Port B
* ECC single bit, correctable error status
* Interrupt: \b sdmmc_portb_ecc_corrected_IRQ
*/
ALT_ECC_ERROR_SDMMC_PORT_B_DERR = 0x8 /*!< SD/MMC Controller Port B
* ECC double bit, non-correctable error status
* Interrupt: \b sdmmc_portb_ecc_uncorrected_IRQ
*/
} ALT_ECC_ERROR_STATUS_t;
/******************************************************************************/
/*!
* Initializes and starts ECC protection for the specified embedded RAM block.
*
* This function performs any necessary initialization on the embedded RAM block
* for the specified peripheral. The decision on whether to enable ECC protection
* for the peripheral embedded RAM block should be made before commencing normal
* operational use of the peripheral. Ideally, ECC protection for a peripheral
* should be enabled immediately after calling the peripheral's initialization
* function and calling the alt_ecc_init() function designating the applicable
* peripheral embedded RAM block.
*
* For example, the proper initialization sequence for enabling ECC for the QSPI
* controller embedded RAM block is:
\verbatim
alt_qspi_init(); // Initialize the QSPI controller
alt_qspi_enable(); // Enable the QSPI controller.
alt_ecc_start(ALT_ECC_RAM_QSPI); // Bring up ECC protection for QSPI.
\endverbatim
*
* There may be some spurious interrupts that occurs as part of the ECC bring
* up. However at the completion of the ECC bring up, there will be no ECC
* related interrupts pending.
*
* NOTE: The contents of the embedded RAM block are overwritten during
* initialization. This should not normally present a problem as the presumption
* is that this routine is called as part of the peripheral's initialization
* sequence. As well, any special RAM configurations may be overwritten as part
* of the initialization. Particularly, the L2 data RAM may alter the lockdown
* settings.
*
* \param ram_block
* The RAM block to initialize.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG The \e ram_block argument is invalid.
*/
ALT_STATUS_CODE alt_ecc_start(const ALT_ECC_RAM_ENUM_t ram_block);
/******************************************************************************/
/*!
* Stops and Uninitializes ECC protection for the specified embedded RAM block.
*
* \param ram_block
* The RAM block to uninitialize.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG The \e ram_block argument is invalid.
*/
ALT_STATUS_CODE alt_ecc_stop(const ALT_ECC_RAM_ENUM_t ram_block);
/******************************************************************************/
/*!
* Returns ALT_E_TRUE if the specified RAM block is enabled for ECC protection and
* ALT_E_FALSE otherwise.
*
* \param ram_block
* The RAM block to check for ECC protection enablement.
*
* \retval ALT_E_TRUE ECC protection is enabled.
* \retval ALT_E_FALSE ECC protection is not enabled.
* \retval ALT_E_BAD_ARG The \e ram_block argument is invalid.
*/
ALT_STATUS_CODE alt_ecc_is_enabled(const ALT_ECC_RAM_ENUM_t ram_block);
/******************************************************************************/
/*!
* Returns an ECC error status bit mask for the specified RAM block.
*
* The returned bit mask reflects the ECC status conditions for the specified RAM
* block.
*
* \param ram_block
* The RAM block to return the ECC error status mask for.
*
* \param status
* [out] An ECC status condition bit mask is returned indicating the
* single bit, correctable (SERR) and/or double bit, non-correctable
* error (DERR) conditions set for the specified RAM block. A set (1)
* bit indicates an error detection for the corresponding ECC error
* type mask.
*
* \retval ALT_E_TRUE ECC protection is enabled.
* \retval ALT_E_FALSE ECC protection is not enabled.
* \retval ALT_E_BAD_ARG The \e ram_block argument is invalid.
*/
ALT_STATUS_CODE alt_ecc_status_get(const ALT_ECC_RAM_ENUM_t ram_block,
uint32_t *status);
/******************************************************************************/
/*!
* Clears the selected ECC error conditions for the specified RAM block.
*
* A bit mask is returned containing indications of any single bit, correctable
* (SERR) and/or double bit, non-correctable error (DERR) occurrences for the
* specified RAM block. A 1 indicates an error detection of the corresponding
* error type mask position.
*
* \param ram_block
* The RAM block to clear the ECC error condition statuses for.
*
* \param ecc_mask
* A bit mask specification of the ECC error condition statuses (\ref
* ALT_ECC_ERROR_STATUS_t) to clear.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR An invalid \e ecc_mask was specified.
* \retval ALT_E_BAD_ARG Either the \e ram_block or \e ecc_mask argument
* is invalid.
*/
ALT_STATUS_CODE alt_ecc_status_clear(const ALT_ECC_RAM_ENUM_t ram_block,
const uint32_t ecc_mask);
/******************************************************************************/
/*!
* Injects a single bit, correctable error into the specified ECC protected RAM
* block for test purposes. This error will occur at the next write to the
* specified RAM block and will remain pending until such time. For RAM blocks
* which have mutliple RAM sub-blocks, all sub-blocks are injected. This
* affects the EMAC0, EMAC1, NAND, and SDMMC.
*
* ECC protection is required to be enabled on the RAM block.
*
* \param ram_block
* The RAM block to inject the ECC error into.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG The \e ram_block argument is invalid.
* \retval ALT_E_BAD_OPERATION ECC is not enabled on the specified RAM
* block.
*/
ALT_STATUS_CODE alt_ecc_serr_inject(const ALT_ECC_RAM_ENUM_t ram_block);
/******************************************************************************/
/*!
* Injects a double bit, non-correctable error into the specified ECC protected
* RAM block for test purposes. This error will occur at the next write to the
* specified RAM block and will remain pending until such time. For RAM blocks
* which have mutliple RAM sub-blocks, all sub-blocks are injected. This
* affects the EMAC0, EMAC1, NAND, and SDMMC.
*
* ECC protection is required to be enabled on the RAM block.
*
* \param ram_block
* The RAM block to disable ECC protection for.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG The \e ram_block argument is invalid.
* \retval ALT_E_BAD_OPERATION ECC is not enabled on the specified RAM
* block.
*/
ALT_STATUS_CODE alt_ecc_derr_inject(const ALT_ECC_RAM_ENUM_t ram_block);
/*! @} */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_ECC_H__ */

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/*! \file
* Altera - Module Description
*/
/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ALT_GBLTMR_H__
#define __ALT_GBLTMR_H__
#include <stdint.h>
#include <stdbool.h>
#include "hwlib.h"
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/******************************************************************************/
/*! \addtogroup GBLTMR_MGR The Global Timer Manager API
*
* This functional group handles setting and reading various parameters of the
* global 64-bit incrementing counter. There is one 64-bit continuously
* incrementing counter for all CPU cores and it is clocked by PERIPHCLK.
* This section manages the comparator value, compare enable,
* auto-increment value, auto-increment enable, and interrupt enable for the
* CPU that this code is running on (referenced as \b CPU_GLOBAL_TMR).
* @{
*/
/******************************************************************************/
/*! Uninitialize the Global timer module
*
*/
ALT_STATUS_CODE alt_globaltmr_uninit(void);
/******************************************************************************/
/*! Initialize the Global timer module
*
*/
ALT_STATUS_CODE alt_globaltmr_init(void);
/******************************************************************************/
/*!
* Stops the global timer counter compare function for this CPU and disables
* its interrupt. It does
* not stop the global timer itself. This function is identical to calling
* \b alt_gpt_tmr_stop() with a tmr_id of \b CPU_GLOBAL_TMR.
*
*
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_globaltmr_stop(void);
/******************************************************************************/
/*!
* Starts the global timer compare function for this CPU, enables its interrupt
* function and, if free-running mode is selected also enables its
* auto-increment function. If the global timer is not yet running, it starts
* the timer. This function is identical to calling \b alt_gpt_tmr_start()
* with a tmr_id of \b CPU_GLOBAL_TMR.
*
*
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_globaltmr_start(void);
/******************************************************************************/
/*!
* Returns the current counter value of the 64-bit global timer.
*
*
* \param highword
* Location used to return the most significant 32-bit word of
* the current global timer count.
* \param lowword
* Location used to return the least significant 32-bit word
* of the current global timer count.
*
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_globaltmr_get(uint32_t* highword, uint32_t* lowword);
/******************************************************************************/
/*!
* Returns the current counter value of the 64-bit global timer. This function
* is identical to alt_globaltmr_get() except that the value is returned as a
* 64-bit unsigned integer rather than as two 32-bit words.
*
*
*
* \retval uint64_t
* The current value of the 64-bit counter.
*/
uint64_t alt_globaltmr_get64(void);
/******************************************************************************/
/*!
* Returns the 32 low-order bits of the global timer. This
* is identical to calling \b alt_gpt_counter_get() with a tmr_id equal
* to \b CPU_GLOBAL_TMR. Use alt_globaltmr_get() or alt_globaltmr_get64() to
* obtain the full 64-bit timer value.
*
*
*
* \retval uint32_t The current 32-bit counter value.
*/
uint32_t alt_globaltmr_counter_get_low32(void);
/******************************************************************************/
/*!
* Returns the 32 higher-order bits of the global timer. Use alt_globaltmr_get()
* or alt_globaltmr_get64() to obtain the full 64-bit timer value.
*
*
*
* \retval uint32_t The current 32-bit counter value.
*/
uint32_t alt_globaltmr_counter_get_hi32(void);
/******************************************************************************/
/*!
* Sets the value of the 64-bit global timer comparator for this CPU. The
* global timer increments its count and when it reaches this value or above,
* it triggers the following actions. If the interrupt is enabled, it forwards
* an interrupt request to the core. If free-run mode is selected, it adds the
* auto-increment value to the value of the global counter and the resulting
* sum is saved as the new comparator value.
*
*
* \param highword
* The 32 MSBits of the new comparator value.
* \param loword
* The 32 LSBits of the new comparator value.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_globaltmr_comp_set(uint32_t highword, uint32_t loword);
/******************************************************************************/
/*!
* Sets the value of the 64-bit global timer comparator for this CPU. The
* global timer increments its count and when it reaches this value or above,
* it triggers the following actions. If the interrupt is enabled, it forwards
* an interrupt request to the core. If free-run mode is selected, it adds the
* auto-increment value to the value of the global counter and the resulting
* sum is saved as the new comparator value.
*
*
* \param compval
* The new comparator value to set.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_globaltmr_comp_set64(uint64_t compval);
/******************************************************************************/
/*!
* Returns the current 64-bit global timer comparator value for this CPU. The
* global timer increments its count and when it reaches this value or above,
* it triggers the following actions. If the interrupt is enabled, it forwards
* an interrupt request to the core. If free-run mode is selected, it adds the
* auto-increment value to the value of the global counter and the resulting
* sum is saved as the new comparator value. This value will increase by the
* auto-increment value each time the global timer reaches the comparator
* value.
*
*
* \param highword
* Pointer to location to store the 32 MSBits of the comparator value.
* \param lowword
* Pointer to location to store the 32 LSBits of the comparator value.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_globaltmr_comp_get(uint32_t *highword, uint32_t *lowword);
/******************************************************************************/
/*!
* Returns the current 64-bit global timer comparator value for this CPU. The
* global timer increments its count and when it reaches this value or above,
* it triggers the following actions. If the interrupt is enabled, it forwards
* an interrupt request to the core. If free-run mode is selected, it adds the
* auto-increment value to the value of the global counter and the resulting
* sum is saved as the new comparator value. This value will increase by the
* auto-increment value each time the global timer reaches the comparator
* value. This function is identical to alt_globaltmr_comp_get() except that the
* value is returned in a 64-bit unsigned integer rather than as two 32-bit
* words.
*
*
* \retval uint64_t
* The 64-bit value of the global timer comparator.
*/
uint64_t alt_globaltmr_comp_get64(void);
/******************************************************************************/
/*!
* Enables the comparison function of the global timer for this CPU.
*
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_globaltmr_comp_mode_start(void);
/******************************************************************************/
/*!
* Disables the comparison function of the global timer for this CPU.
*
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_globaltmr_comp_mode_stop(void);
/******************************************************************************/
/*!
* Returns the comparison mode selection of the global
* timer for this CPU.
*
*
* \retval FALSE Comparison mode is not enabled.
* \retval TRUE Comparison mode is enabled.
*/
bool alt_globaltmr_is_comp_mode(void);
/******************************************************************************/
/*!
* Returns the clock prescaler value of the global timer.
*
*
* \retval uint32_t The prescaler value. Valid range is 0-255.
* Actual clock divisor ratio is this number plus one.
*/
uint32_t alt_globaltmr_prescaler_get(void);
/******************************************************************************/
/*!
* Sets the clock prescaler value of the global timer.
*
*
* \param val
* The 8-bit prescaler value to load. Valid range is 0-255.
* Actual clock divisor ratio is this number plus one.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_globaltmr_prescaler_set(uint32_t val);
/******************************************************************************/
/*!
* Sets a 32-bit global timer auto-increment value in the global
* timer block for this CPU. The global timer continually increments its count
* and when it reaches the value set in the comparator register or above, if
* both comparison and free-run modes are selected, it adds the value set by this
* function to the comparator value and saves it as the new comparator value.
* This count then sets the time delay until the next global timer compare
* value is reached.
*
*
* \param inc
* Auto-increment value to set.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_globaltmr_autoinc_set(uint32_t inc);
/******************************************************************************/
/*!
* Returns the global timer auto-increment value for this CPU. When the global
* timer reaches the comparator value, if both comparison and free-run modes
* are selected this value is added to the previous comparator value and saved
* as the new comparator value.
*
*
* \retval uint32_t
* The current comparator auto-increment value.
*/
uint32_t alt_globaltmr_autoinc_get(void);
/******************************************************************************/
/*!
* Enables the auto-increment function of the global timer for this CPU.
*
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_globaltmr_autoinc_mode_start(void);
/******************************************************************************/
/*!
* Disables the auto-increment function of the global timer for this CPU.
*
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_globaltmr_autoinc_mode_stop(void);
/******************************************************************************/
/*!
* Returns the auto-increment selection of the global timer for this CPU.
*
*
* \retval FALSE Auto-increment mode is not enabled.
* \retval TRUE Auto-increment mode is enabled.
*/
bool alt_globaltmr_is_autoinc_mode(void);
/******************************************************************************/
/*!
* Returns the maximum counter value available for \b CPU_GLOBAL_TMR. \n
* The value returned does not factor in the value of the clock prescaler.
*
*
*
*
* \retval uint32_t The maximum counter value available for this timer.
* \retval 0 An error occurred.
*
*/
uint32_t alt_globaltmr_maxcounter_get(void);
/******************************************************************************/
/*!
* Disables the interrupt from the global timer module. Identical to calling
* alt_gpt_int_disable() with tmr_id of \b CPU_GLOBAL_TMR.
*
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_globaltmr_int_disable(void);
/******************************************************************************/
#if 0
/*!
*
* Enables the interrupt of the global timer
* module. Identical to calling alt_gpt_int_enable() with tmr_id of
* \b CPU_GLOBAL_TMR. If global timer is not already running, this function
* returns an error.
*
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_globaltmr_int_enable(void);
#else
/*!
*
* Enables the interrupt of the global timer
* module. Identical to calling alt_gpt_int_enable() with tmr_id of
* \b CPU_GLOBAL_TMR. If global timer is not already running, this function
* attempts to start it.
*
*
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_globaltmr_int_enable(void);
#endif
/******************************************************************************/
/*!
* Return \b TRUE if the interrupt of the global timer module is enabled
* and \b FALSE if the interrupt is disabled or masked. Identical to calling
* alt_gpt_int_is_enabled() with tmr_id of
* \b CPU_GLOBAL_TMR.
*
* \internal - note that there's more to this than just enabling the
* interrupt and clearing the status.
* \endinternal
*
*
* \retval TRUE The timer interrupt is currently enabled.
* \retval FALSE The timer interrupt is currently disabled.
*/
bool alt_globaltmr_int_is_enabled(void);
/******************************************************************************/
/*!
* Clear the pending interrupt status of the global timer module. Identical to
* calling alt_gpt_int_clear_pending() with tmr_id of
* \b CPU_GLOBAL_TMR.
*
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_globaltmr_int_clear_pending(void);
/******************************************************************************/
/*!
* Read the state (pending or not) of the interrupt of the global timer
* module without changing the interrupt state. Identical to
* calling alt_gpt_int_is_pending() with tmr_id of
* \b CPU_GLOBAL_TMR.
*
*
*
* \retval TRUE The timer interrupt is currently pending.
* \retval FALSE The timer interrupt is not currently pending.
*/
bool alt_globaltmr_int_is_pending(void);
/******************************************************************************/
/*!
* Read the state of the interrupt of the global timer
* module and if the interrupt is set, clear it. Identical to
* calling alt_gpt_int_is_pending_and_clear() with tmr_id of
* \b CPU_GLOBAL_TMR.
*
*
*
* \retval TRUE The timer interrupt was pending.
* \retval FALSE The timer interrupt was not pending.
*/
bool alt_globaltmr_int_if_pending_clear(void);
/*! @} */
/*! @} */
/*! @} */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_GBLTMR_H__ */

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ALT_HWLIBS_VER_H__
/***********************************************************************
*
* Set of macros to provide version information
*
***********************************************************************/
/* This is the major revision of the Altera ACDS Release */
#define ALTERA_ACDS_MAJOR_REV 13
/* This is the minor revision of the Altera ACDS Release */
#define ALTERA_ACDS_MINOR_REV 1
/* This is an internal HwLibs revision/feature control code. */
/* End-users should NOT depend upon the value of this field */
#define ALTERA_HWLIBS_REV 0
/* This is a text string containing the current release and service pack IDs */
#define ALTERA_ACDS_REV_STR "13.1"
/* This is a text string containing the current SoC EDS ID */
#define ALTERA_SOCEDS_REV_STR "Altera SoC Embedded Design Suite v13.1"
#endif /* __ALT_HWLIBS_VER_H__ */

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ALT_INT_COMMON_H__
#define __ALT_INT_COMMON_H__
#include "hwlib.h"
#include <stdbool.h>
#include <stddef.h>
#ifdef __cplusplus
extern "C"
{
#endif
/*!
* \addtogroup INT_COMMON Interrupt Controller Common Definitions
*
* This module contains the definitions common to the Interrupt Controller
* Low-Level API and Interrupt Controller Manager Interface.
*
* @{
*/
/*!
* This type definition enumerates all the interrupt identification types.
*/
typedef enum ALT_INT_INTERRUPT_e
{
ALT_INT_INTERRUPT_SGI0 = 0, /*!< # */
ALT_INT_INTERRUPT_SGI1 = 1, /*!< # */
ALT_INT_INTERRUPT_SGI2 = 2, /*!< # */
ALT_INT_INTERRUPT_SGI3 = 3, /*!< # */
ALT_INT_INTERRUPT_SGI4 = 4, /*!< # */
ALT_INT_INTERRUPT_SGI5 = 5, /*!< # */
ALT_INT_INTERRUPT_SGI6 = 6, /*!< # */
ALT_INT_INTERRUPT_SGI7 = 7, /*!< # */
ALT_INT_INTERRUPT_SGI8 = 8, /*!< # */
ALT_INT_INTERRUPT_SGI9 = 9, /*!< # */
ALT_INT_INTERRUPT_SGI10 = 10, /*!< # */
ALT_INT_INTERRUPT_SGI11 = 11, /*!< # */
ALT_INT_INTERRUPT_SGI12 = 12, /*!< # */
ALT_INT_INTERRUPT_SGI13 = 13, /*!< # */
ALT_INT_INTERRUPT_SGI14 = 14, /*!< # */
ALT_INT_INTERRUPT_SGI15 = 15,
/*!<
* Software Generated Interrupts (SGI), 0 - 15.
* * All interrupts in this group are software triggered.
*/
ALT_INT_INTERRUPT_PPI_TIMER_GLOBAL = 27, /*!< # */
ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE = 29, /*!< # */
ALT_INT_INTERRUPT_PPI_TIMER_WATCHDOG = 30, /*!< # */
/*!<
* Private Peripheral Interrupts (PPI) for the Global Timer, per CPU
* private timer, and watchdog timer.
* * All interrupts in this group are edge triggered.
*/
ALT_INT_INTERRUPT_CPU0_PARITYFAIL = 32, /*!< # */
ALT_INT_INTERRUPT_CPU0_PARITYFAIL_BTAC = 33, /*!< # */
ALT_INT_INTERRUPT_CPU0_PARITYFAIL_GHB = 34, /*!< # */
ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_TAG = 35, /*!< # */
ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_DATA = 36, /*!< # */
ALT_INT_INTERRUPT_CPU0_PARITYFAIL_TLB = 37, /*!< # */
ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_OUTER = 38, /*!< # */
ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_TAG = 39, /*!< # */
ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_DATA = 40, /*!< # */
ALT_INT_INTERRUPT_CPU0_DEFLAGS0 = 41, /*!< # */
ALT_INT_INTERRUPT_CPU0_DEFLAGS1 = 42, /*!< # */
ALT_INT_INTERRUPT_CPU0_DEFLAGS2 = 43, /*!< # */
ALT_INT_INTERRUPT_CPU0_DEFLAGS3 = 44, /*!< # */
ALT_INT_INTERRUPT_CPU0_DEFLAGS4 = 45, /*!< # */
ALT_INT_INTERRUPT_CPU0_DEFLAGS5 = 46, /*!< # */
ALT_INT_INTERRUPT_CPU0_DEFLAGS6 = 47,
/*!<
* Interrupts sourced from CPU0.
*
* The ALT_INT_INTERRUPT_CPU0_PARITYFAIL interrupt combines the
* BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts
* for CPU0.
*
* * PARITYFAIL interrupts in this group are edge triggered.
* * DEFFLAGS interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_CPU1_PARITYFAIL = 48, /*!< # */
ALT_INT_INTERRUPT_CPU1_PARITYFAIL_BTAC = 49, /*!< # */
ALT_INT_INTERRUPT_CPU1_PARITYFAIL_GHB = 50, /*!< # */
ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_TAG = 51, /*!< # */
ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_DATA = 52, /*!< # */
ALT_INT_INTERRUPT_CPU1_PARITYFAIL_TLB = 53, /*!< # */
ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_OUTER = 54, /*!< # */
ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_TAG = 55, /*!< # */
ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_DATA = 56, /*!< # */
ALT_INT_INTERRUPT_CPU1_DEFLAGS0 = 57, /*!< # */
ALT_INT_INTERRUPT_CPU1_DEFLAGS1 = 58, /*!< # */
ALT_INT_INTERRUPT_CPU1_DEFLAGS2 = 59, /*!< # */
ALT_INT_INTERRUPT_CPU1_DEFLAGS3 = 60, /*!< # */
ALT_INT_INTERRUPT_CPU1_DEFLAGS4 = 61, /*!< # */
ALT_INT_INTERRUPT_CPU1_DEFLAGS5 = 62, /*!< # */
ALT_INT_INTERRUPT_CPU1_DEFLAGS6 = 63,
/*!<
* Interrupts sourced from CPU1.
*
* The ALT_INT_INTERRUPT_CPU1_PARITYFAIL interrupt combines the
* BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts
* for CPU1.
*
* * PARITYFAIL interrupts in this group are edge triggered.
* * DEFFLAGS interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_SCU_PARITYFAIL0 = 64, /*!< # */
ALT_INT_INTERRUPT_SCU_PARITYFAIL1 = 65, /*!< # */
ALT_INT_INTERRUPT_SCU_EV_ABORT = 66,
/*!<
* Interrupts sourced from the Snoop Control Unit (SCU).
* * All interrupts in this group are edge triggered.
*/
ALT_INT_INTERRUPT_L2_ECC_BYTE_WR_IRQ = 67, /*!< # */
ALT_INT_INTERRUPT_L2_ECC_CORRECTED_IRQ = 68, /*!< # */
ALT_INT_INTERRUPT_L2_ECC_UNCORRECTED_IRQ = 69, /*!< # */
ALT_INT_INTERRUPT_L2_COMBINED_IRQ = 70,
/*!<
* Interrupts sourced from the L2 Cache Controller.
*
* The ALT_INT_INTERRUPT_L2_COMBINED_IRQ interrupt combines the cache
* controller internal DECERRINTR, ECNTRINTR, ERRRDINTR, ERRRTINTR,
* ERRWDINTR, ERRWTINTR, PARRDINTR, PARRTINTR, and SLVERRINTR interrupts.
* Consult the L2C documentation for information on these interrupts.
*
* * ECC interrupts in this group are edge triggered.
* * Other interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_DDR_ECC_ERROR_IRQ = 71,
/*!<
* Interrupts sourced from the SDRAM Controller.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_F2S_FPGA_IRQ0 = 72, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ1 = 73, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ2 = 74, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ3 = 75, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ4 = 76, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ5 = 77, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ6 = 78, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ7 = 79, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ8 = 80, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ9 = 81, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ10 = 82, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ11 = 83, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ12 = 84, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ13 = 85, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ14 = 86, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ15 = 87, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ16 = 88, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ17 = 89, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ18 = 90, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ19 = 91, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ20 = 92, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ21 = 93, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ22 = 94, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ23 = 95, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ24 = 96, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ25 = 97, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ26 = 98, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ27 = 99, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ28 = 100, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ29 = 101, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ30 = 102, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ31 = 103, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ32 = 104, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ33 = 105, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ34 = 106, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ35 = 107, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ36 = 108, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ37 = 109, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ38 = 110, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ39 = 111, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ40 = 112, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ41 = 113, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ42 = 114, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ43 = 115, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ44 = 116, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ45 = 117, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ46 = 118, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ47 = 119, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ48 = 120, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ49 = 121, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ50 = 122, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ51 = 123, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ52 = 124, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ53 = 125, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ54 = 126, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ55 = 127, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ56 = 128, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ57 = 129, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ58 = 130, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ59 = 131, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ60 = 132, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ61 = 133, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ62 = 134, /*!< # */
ALT_INT_INTERRUPT_F2S_FPGA_IRQ63 = 135,
/*!<
* Interrupt request from the FPGA logic, 0 - 63.
* * Trigger type depends on the implementation in the FPGA.
*/
ALT_INT_INTERRUPT_DMA_IRQ0 = 136, /*!< # */
ALT_INT_INTERRUPT_DMA_IRQ1 = 137, /*!< # */
ALT_INT_INTERRUPT_DMA_IRQ2 = 138, /*!< # */
ALT_INT_INTERRUPT_DMA_IRQ3 = 139, /*!< # */
ALT_INT_INTERRUPT_DMA_IRQ4 = 140, /*!< # */
ALT_INT_INTERRUPT_DMA_IRQ5 = 141, /*!< # */
ALT_INT_INTERRUPT_DMA_IRQ6 = 142, /*!< # */
ALT_INT_INTERRUPT_DMA_IRQ7 = 143, /*!< # */
ALT_INT_INTERRUPT_DMA_IRQ_ABORT = 144, /*!< # */
ALT_INT_INTERRUPT_DMA_ECC_CORRECTED_IRQ = 145, /*!< # */
ALT_INT_INTERRUPT_DMA_ECC_UNCORRECTED_IRQ = 146,
/*!<
* Interrupts sourced from the DMA Controller.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_EMAC0_IRQ = 147, /*!< # */
ALT_INT_INTERRUPT_EMAC0_TX_ECC_CORRECTED_IRQ = 148, /*!< # */
ALT_INT_INTERRUPT_EMAC0_TX_ECC_UNCORRECTED_IRQ = 149, /*!< # */
ALT_INT_INTERRUPT_EMAC0_RX_ECC_CORRECTED_IRQ = 150, /*!< # */
ALT_INT_INTERRUPT_EMAC0_RX_ECC_UNCORRECTED_IRQ = 151,
/*!<
* Interrupts sourced from the Ethernet MAC 0 (EMAC0).
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_EMAC1_IRQ = 152, /*!< # */
ALT_INT_INTERRUPT_EMAC1_TX_ECC_CORRECTED_IRQ = 153, /*!< # */
ALT_INT_INTERRUPT_EMAC1_TX_ECC_UNCORRECTED_IRQ = 154, /*!< # */
ALT_INT_INTERRUPT_EMAC1_RX_ECC_CORRECTED_IRQ = 155, /*!< # */
ALT_INT_INTERRUPT_EMAC1_RX_ECC_UNCORRECTED_IRQ = 156,
/*!<
* Interrupts sourced from the Ethernet MAC 1 (EMAC1).
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_USB0_IRQ = 157, /*!< # */
ALT_INT_INTERRUPT_USB0_ECC_CORRECTED = 158, /*!< # */
ALT_INT_INTERRUPT_USB0_ECC_UNCORRECTED = 159,
/*!<
* Interrupts sourced from the USB OTG 0.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_USB1_IRQ = 160, /*!< # */
ALT_INT_INTERRUPT_USB1_ECC_CORRECTED = 161, /*!< # */
ALT_INT_INTERRUPT_USB1_ECC_UNCORRECTED = 162,
/*!<
* Interrupts sourced from the USB OTG 1.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_CAN0_STS_IRQ = 163, /*!< # */
ALT_INT_INTERRUPT_CAN0_MO_IRQ = 164, /*!< # */
ALT_INT_INTERRUPT_CAN0_ECC_CORRECTED_IRQ = 165, /*!< # */
ALT_INT_INTERRUPT_CAN0_ECC_UNCORRECTED_IRQ = 166,
/*!<
* Interrupts sourced from the CAN Controller 0.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_CAN1_STS_IRQ = 167, /*!< # */
ALT_INT_INTERRUPT_CAN1_MO_IRQ = 168, /*!< # */
ALT_INT_INTERRUPT_CAN1_ECC_CORRECTED_IRQ = 169, /*!< # */
ALT_INT_INTERRUPT_CAN1_ECC_UNCORRECTED_IRQ = 170,
/*!<
* Interrupts sourced from the CAN Controller 1.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_SDMMC_IRQ = 171, /*!< # */
ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_CORRECTED = 172, /*!< # */
ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_UNCORRECTED = 173, /*!< # */
ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_CORRECTED = 174, /*!< # */
ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_UNCORRECTED = 175,
/*!<
* Interrupts sourced from the SDMMC Controller.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_NAND_IRQ = 176, /*!< # */
ALT_INT_INTERRUPT_NANDR_ECC_CORRECTED_IRQ = 177, /*!< # */
ALT_INT_INTERRUPT_NANDR_ECC_UNCORRECTED_IRQ = 178, /*!< # */
ALT_INT_INTERRUPT_NANDW_ECC_CORRECTED_IRQ = 179, /*!< # */
ALT_INT_INTERRUPT_NANDW_ECC_UNCORRECTED_IRQ = 180, /*!< # */
ALT_INT_INTERRUPT_NANDE_ECC_CORRECTED_IRQ = 181, /*!< # */
ALT_INT_INTERRUPT_NANDE_ECC_UNCORRECTED_IRQ = 182,
/*!<
* Interrupts sourced from the NAND Controller.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_QSPI_IRQ = 183, /*!< # */
ALT_INT_INTERRUPT_QSPI_ECC_CORRECTED_IRQ = 184, /*!< # */
ALT_INT_INTERRUPT_QSPI_ECC_UNCORRECTED_IRQ = 185,
/*!<
* Interrupts sourced from the QSPI Controller.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_SPI0_IRQ = 186, /*!< # */
ALT_INT_INTERRUPT_SPI1_IRQ = 187, /*!< # */
ALT_INT_INTERRUPT_SPI2_IRQ = 188, /*!< # */
ALT_INT_INTERRUPT_SPI3_IRQ = 189,
/*!<
* Interrupts sourced from the SPI Controllers 0 - 3.
* SPI0_IRQ corresponds to SPIM0. SPI1_IRQ corresponds to SPIM1.
* SPI2_IRQ corresponds to SPIS0. SPI3_IRQ corresponds to SPIS1.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_I2C0_IRQ = 190, /*!< # */
ALT_INT_INTERRUPT_I2C1_IRQ = 191, /*!< # */
ALT_INT_INTERRUPT_I2C2_IRQ = 192, /*!< # */
ALT_INT_INTERRUPT_I2C3_IRQ = 193,
/*!<
* Interrupts sourced from the I2C Controllers 0 - 3.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_UART0 = 194, /*!< # */
ALT_INT_INTERRUPT_UART1 = 195,
/*!<
* Interrupts sourced from the UARTs 0 - 1.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_GPIO0 = 196, /*!< # */
ALT_INT_INTERRUPT_GPIO1 = 197, /*!< # */
ALT_INT_INTERRUPT_GPIO2 = 198,
/*!<
* Interrupts sourced from the GPIO 0 - 2.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_TIMER_L4SP_0_IRQ = 199, /*!< # */
ALT_INT_INTERRUPT_TIMER_L4SP_1_IRQ = 200, /*!< # */
ALT_INT_INTERRUPT_TIMER_OSC1_0_IRQ = 201, /*!< # */
ALT_INT_INTERRUPT_TIMER_OSC1_1_IRQ = 202,
/*!<
* Interrupts sourced from the Timer controllers.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_WDOG0_IRQ = 203, /*!< # */
ALT_INT_INTERRUPT_WDOG1_IRQ = 204,
/*!<
* Interrupts sourced from the Watchdog Timers 0 - 1.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_CLKMGR_IRQ = 205,
/*!<
* Interrupts sourced from the Clock Manager.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_MPUWAKEUP_IRQ = 206,
/*!<
* Interrupts sourced from the Clock Manager MPU Wakeup.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_FPGA_MAN_IRQ = 207,
/*!<
* Interrupts sourced from the FPGA Manager.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_NCTIIRQ0 = 208, /*!< # */
ALT_INT_INTERRUPT_NCTIIRQ1 = 209,
/*!<
* Interrupts sourced from the CoreSight for CPU0 and CPU1's CTI.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_RAM_ECC_CORRECTED_IRQ = 210, /*!< # */
ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ = 211
/*!<
* Interrupts sourced from the On-chip RAM.
* * All interrupts in this group are level triggered.
*/
} ALT_INT_INTERRUPT_t;
/*!
* This is the CPU target type. It is used to specify a set of CPUs on the
* system. If only bit 0 is set then it specifies a set of CPUs containing
* only CPU 0. Multiple CPUs can be specified by setting the appropriate bit
* up to the number of CPUs on the system.
*/
typedef uint32_t alt_int_cpu_target_t;
/*!
* This type definition enumerates all the interrupt trigger types.
*/
typedef enum ALT_INT_TRIGGER_e
{
/*!
* Edge triggered interrupt. This applies to Private Peripheral Interrupts
* (PPI) and Shared Peripheral Interrupts (SPI) only, with interrupt IDs
* 16 - 1019.
*/
ALT_INT_TRIGGER_EDGE,
/*!
* Level triggered interrupt. This applies to Private Peripheral
* Interrupts (PPI) and Shared Peripheral Interrupts (SPI) only, with
* interrupt IDs 16 - 1019.
*/
ALT_INT_TRIGGER_LEVEL,
/*!
* Software triggered interrupt. This applies to Software Generated
* Interrupts (SGI) only, with interrupt IDs 0 - 15.
*/
ALT_INT_TRIGGER_SOFTWARE,
/*!
* All triggering types except for those in the Shared Peripheral Interrupts
* (SPI) F2S FPGA family interrupts can be determined by the system
* automatically. In all functions which ask for the triggering type, the
* ALT_INT_TRIGGER_AUTODETECT can be used to select the correct trigger
* type for all non F2S interrupt types.
*/
ALT_INT_TRIGGER_AUTODETECT,
/*!
* The interrupt triggering information is not applicable. This is possibly
* due to querying an invalid interrupt identifier.
*/
ALT_INT_TRIGGER_NA
}
ALT_INT_TRIGGER_t;
/*!
* This type definition enumerates all the target list filter options. This is
* used by the trigger Software Generated Interrupt (SGI) feature to issue a
* SGI to the specified processor(s) in the system. Depending on the target
* list filter and the target list, interrupts can be routed to any
* combinations of CPUs.
*/
typedef enum ALT_INT_SGI_TARGET_e
{
/*!
* This filter list uses the target list parameter to specify which CPUs
* to send the interrupt to. If target list is 0, no interrupts are sent.
*/
ALT_INT_SGI_TARGET_LIST,
/*!
* This filter list sends the interrupt all CPUs except the current CPU.
* The target list parameter is ignored.
*/
ALT_INT_SGI_TARGET_ALL_EXCL_SENDER,
/*!
* This filter list sends the interrupt to the current CPU only. The
* target list parameter is ignored.
*/
ALT_INT_SGI_TARGET_SENDER_ONLY
}
ALT_INT_SGI_TARGET_t;
/*!
* Extracts the CPUID field from the ICCIAR register.
*/
#define ALT_INT_ICCIAR_CPUID_GET(icciar) ((icciar >> 10) & 0x7)
/*!
* Extracts the ACKINTID field from the ICCIAR register.
*/
#define ALT_INT_ICCIAR_ACKINTID_GET(icciar) (icciar & 0x3FF)
/*!
* The callback to use when an interrupt needs to be serviced.
*
* \param icciar The Interrupt Controller CPU Interrupt
* Acknowledgement Register value (ICCIAR) value
* corresponding to the current interrupt.
*
* \param context The user provided context.
*/
typedef void (*alt_int_callback_t)(uint32_t icciar, void * context);
/*!
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALT_INT_COMMON_H__ */

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ALT_MPUSCU_H__
#define __ALT_MPUSCU_H__
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/************************************************************************************************************/
/* alt_mpuscu.h */
/* */
/* Definitions for the ARM Snoop Control Unit, which contains the Snoop Control Unit, the Watchdog */
/* Timer, the Private Timer, the Global Timer, the Interrupt Controller, and the Interrupt Distributor. */
/* */
/************************************************************************************************************/
#ifndef ALT_HPS_ADDR
#define ALT_HPS_ADDR 0x00
#endif
/* ALT_MPUSCU_OFST is defined as a offset from ALT_HPS_ADDR in the SoCAL file hps.h */
/* and is the address of the base of the Snoop Control Unit (SCU) */
#define GLOBALTMR_BASE (ALT_MPUSCU_OFST + GLOBALTMR_MODULE_BASE_OFFSET)
#define CPU_WDTGPT_TMR_BASE (ALT_MPUSCU_OFST + WDOG_TIMER_MODULE_BASE_OFFSET)
#define CPU_PRIVATE_TMR_BASE (ALT_MPUSCU_OFST + CPU_PRIV_TIMER_MODULE_BASE_OFFSET)
#define CPU_INT_CTRL_BASE (ALT_MPUSCU_OFST + INT_CONTROLLER_MODULE_BASE_OFFSET)
#define CPU_INT_DIST_BASE (ALT_MPUSCU_OFST + INT_DISTRIBUTOR_MODULE_BASE_OFFSET)
/* offsets */
/* Global Timer offsets */
#define GLOBALTMR_MODULE_BASE_OFFSET 0x00000200
#define GLOBALTMR_CNTR_LO_REG_OFFSET 0x00000000
#define GLOBALTMR_CNTR_HI_REG_OFFSET 0x00000004
#define GLOBALTMR_CTRL_REG_OFFSET 0x00000008
#define GLOBALTMR_INT_STAT_REG_OFFSET 0x0000000C
#define GLOBALTMR_COMP_LO_REG_OFFSET 0x00000010
#define GLOBALTMR_COMP_HI_REG_OFFSET 0x00000014
#define GLOBALTMR_AUTOINC_REG_OFFSET 0x00000018
/* Global Timer bitmasks */
#define GLOBALTMR_ENABLE_BIT 0x00000001
#define GLOBALTMR_COMP_ENABLE_BIT 0x00000002
#define GLOBALTMR_INT_ENABLE_BIT 0x00000004
#define GLOBALTMR_AUTOINC_ENABLE_BIT 0x00000008
#define GLOBALTMR_PS_MASK 0x0000FF00
#define GLOBALTMR_PS_SHIFT 8
#define GLOBALTMR_INT_STATUS_BIT 0x00000001
/* Global timer constants */
#define GLOBALTMR_MAX 0xFFFFFFFF
#define GLOBALTMR_PS_MAX 0x000000FF
/* Private timer offsets */
#define CPU_PRIV_TIMER_MODULE_BASE_OFFSET 0x00000600
#define CPU_PRIV_TMR_LOAD_REG_OFFSET 0x00000000
#define CPU_PRIV_TMR_CNTR_REG_OFFSET 0x00000004
#define CPU_PRIV_TMR_CTRL_REG_OFFSET 0x00000008
#define CPU_PRIV_TMR_INT_STATUS_REG_OFFSET 0x0000000C
/* Private timer bitmasks */
#define CPU_PRIV_TMR_ENABLE 0x00000001
#define CPU_PRIV_TMR_AUTO_RELOAD 0x00000002
#define CPU_PRIV_TMR_INT_EN 0x00000004
#define CPU_PRIV_TMR_PS_MASK 0x0000FF00
#define CPU_PRIV_TMR_PS_SHIFT 8
#define CPU_PRIV_TMR_INT_STATUS 0x00000001
/* Private timer constants */
#define CPU_PRIV_TMR_MAX 0xFFFFFFFF
#define CPU_PRIV_TMR_PS_MAX 0x000000FF
/* Watchdog timer offsets */
#define WDOG_TIMER_MODULE_BASE_OFFSET 0x00000620
#define WDOG_LOAD_REG_OFFSET 0x00000000
#define WDOG_CNTR_REG_OFFSET 0x00000004
#define WDOG_CTRL_REG_OFFSET 0x00000008
#define WDOG_INTSTAT_REG_OFFSET 0x0000000C
#define WDOG_RSTSTAT_REG_OFFSET 0x00000010
#define WDOG_DISABLE_REG_OFFSET 0x00000014
/* Watchdog timer bitmasks : */
/* Control Register bitmasks */
#define WDOG_TMR_ENABLE 0x00000001
#define WDOG_AUTO_RELOAD 0x00000002
#define WDOG_INT_EN 0x00000004
#define WDOG_WDT_MODE 0x00000008
#define WDOG_PS_MASK 0x0000FF00
#define WDOG_PS_SHIFT 8
/* Interrupt Status Register bitmasks */
#define WDOG_INT_STAT_BIT 0x00000001
/* Reset Status Register bitmasks */
#define WDOG_RST_STAT_BIT 0x00000001
/* Watchdog timer constants */
#define WDOG_TMR_MAX UINT32_MAX
#define WDOG_PS_MAX UINT8_MAX
#define WDOG_DISABLE_VAL0 0x12345678
#define WDOG_DISABLE_VAL1 0x87654321
/* Interrupt Manager offsets */
/* <Add definitions here> */
#define INT_CONTROLLER_MODULE_BASE_OFFSET 0x00000100
#define INT_DISTRIBUTOR_MODULE_BASE_OFFSET 0x00001000
#define INT_DIST_TYPE_REG 0x00000004
/* Upper bound of the MPUSCU address space */
#define MPUSCU_MAX 0x00001FFF
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_MPUSCU_H__ */

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
/*! \file
* Altera - NAND Flash Controller Module
*/
#ifndef __ALT_NAND_PRIVATE_H__
#define __ALT_NAND_PRIVATE_H__
/*
* *****************************************
* Struct for NAND Manager IO block
* which consists of cfg, param, status, ecc and dma register blocks
* located at address: ALT_NAND_CFG_ADDR
* *****************************************
*/
typedef struct {
ALT_NAND_CFG_raw_t* cfg; // nand configuration block
ALT_NAND_PARAM_raw_t* param; // nand parameter block
ALT_NAND_STAT_raw_t* stat; // nand status block
ALT_NAND_ECC_raw_t* ecc; // nand ecc block
ALT_NAND_DMA_raw_t* dma; // nand dma block
volatile uint32_t * const ctrl_addr; // indirect access address control
volatile uint32_t * const data_addr; // fifo access address control
} ALT_NAND_MGR_t;
//
// flash memory characterization
//
typedef struct
{
uint32_t manufacturer_id;
uint32_t device_id;
uint32_t device_param_0;
uint32_t device_param_1;
uint32_t device_param_2;
uint32_t page_size;
uint32_t spare_size;
uint32_t revision;
uint32_t onfi_device_features;
uint32_t onfi_optional_commands;
uint32_t onfi_timing_mode;
uint32_t onfi_pgm_cache_timing_mode;
uint32_t onfi_compliant;
uint32_t onfi_device_no_of_luns;
uint32_t onfi_device_no_of_blocks_per_lun;
uint32_t features;
uint32_t number_of_planes;
uint32_t pages_per_block;
uint32_t device_width;
uint32_t device_main_area_size;
uint32_t device_spare_area_size;
uint32_t block_size;
uint32_t spare_area_skip_bytes;
uint32_t first_block_of_next_plane;
uint32_t page_size_32;
uint32_t page_shift;
uint32_t block_shift;
uint32_t dma_burst_length;
uint32_t ecc_correct;
} FLASH_CHARACTERIZATION_t;
typedef uint32_t (*nand_interrupt_handler_t)(uint32_t interrup_status_register, uint32_t interrup_status_mask );
/*
* Some default values.
*/
#define ALT_HHP_NAND_SECTOR_SIZE (512)
#define ALT_HHP_NAND_PAGE_SIZE (2048)
#define ALT_HHP_NAND_PAGE_SHIFT (11)
#define ALT_HHP_NAND_SPARE_SIZE (128) /* Spare bytes per page. */
#define ALT_HHP_NAND_PAGES_PER_BLOCK (64) /* 128 pages per block (512KB) */
#define ALT_HHP_NAND_BLOCK_SIZE (ALT_HHP_NAND_PAGE_SIZE *ALT_HHP_NAND_PAGES_PER_BLOCK)
#define ALT_HHP_NAND_ECC_CORRECT (8) /* 8 bit ECC. */
#define ALT_HHP_NAND_SPARE_SKIP (2) /* Skip the first 2 bytes of the spare space. */
#define ALT_HHP_NAND_BLOCK_SHIFT (6) /* from page boundary */
#define ALT_HHP_NAND_MANUFACTURER_ID (0x1)
#define ALT_HHP_NAND_DEVICE_ID (0xd3)
#define ALT_HHP_NAND_REVISION (5)
#define ALT_HHP_NAND_NUMBER_OF_PLANES (2)
#define ALT_HHP_NAND_DEVICE_WIDTH (0)
#define ALT_HHP_NAND_FIRST_BLOCK_OF_NEXT_PLANE (2048)
#define ALT_HHP_NAND_NUM_OF_LUNS (2)
#define ALT_HHP_NAND_NUM_OF_BLOCK_PER_LUNS (4096)
#define ALT_HHP_NAND_NUM_OF_BLOCK_TOTAL (ALT_HHP_NAND_NUM_OF_LUNS * ALT_HHP_NAND_NUM_OF_BLOCK_PER_LUNS)
//
// Constants from 8.1. Address Mapping
//
// Table 8.2
#define ALT_HHP_NAND_MODE_00 (0x00000000)
#define ALT_HHP_NAND_MODE_01 (0x04000000)
#define ALT_HHP_NAND_MODE_10 (0x08000000)
#define ALT_HHP_NAND_MODE_11 (0x0C000000)
#define ALT_HHP_NAND_ADDR_MAP_CMD_MAP_LSB_INDEX (26)
#define ALT_HHP_NAND_ADDR_MAP_BANK_SEL_LSB_INDEX (24)
#define ALT_HHP_NAND_ADDR_MAP_MEM_ADDR_LSB_INDEX (0)
#define ALT_HHP_NAND_10_OP_DEFAULT_AREA (0x0042)
#define ALT_HHP_NAND_10_OP_ERASE_BLOCK (0x0001)
#define ALT_HHP_NAND_10_OP_LOAD_PAGE (0x0060)
#define ALT_HHP_NAND_10_OP_DEST_ADDR (0x0061)
#define ALT_HHP_NAND_10_OP_WRITE_PAGE (0x0062)
#define ALT_HHP_NAND_10_OP_READ_PIPE (0x2000)
#define ALT_HHP_NAND_10_OP_WRITE_PIPE (0x2100)
#define ALT_HHP_UINT32_MASK ((uint32_t) -1)
#define ALT_NAND_BOOTSTRAP_INHIBIT_INIT_ENABLE (1)
#define ALT_NAND_BOOTSTRAP_INHIBIT_INIT_DISABLE (0)
#define ALT_NAND_BOOTSTRAP_INHIBIT_B0P0_LOAD_ENABLE (1)
#define ALT_NAND_BOOTSTRAP_INHIBIT_B0P0_LOAD_DISABLE (0)
#define ALT_NAND_BOOTSTRAP_512B_DEVICE_ENABLE (1)
#define ALT_NAND_BOOTSTRAP_512B_DEVICE_DISABLE (0)
#define ALT_NAND_BOOTSTRAP_TWO_ROW_ADDR_CYCLES_EABLE (1)
#define ALT_NAND_BOOTSTRAP_TWO_ROW_ADDR_CYCLES_DISABLE (0)
#define ALT_NAND_FLASH_MEM_BANK_0 (0)
#define ALT_NAND_FLASH_MEM_BANK_1 (1)
#define ALT_NAND_FLASH_MEM_BANK_2 (2)
#define ALT_NAND_FLASH_MEM_BANK_3 (3)
uint32_t alt_nand_poll_for_interrupt_status_register(uint32_t , uint32_t );
uint32_t ffs32(uint32_t);
uint32_t alt_nand_compose_map10_cmd_addr(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr);
int32_t alt_nand_full_page_read_with_map10(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t *buffer);
void alt_nand_write_indirect(const uint32_t address, const uint32_t value);
uint32_t alt_nand_read_indirect(const uint32_t address);
int32_t alt_nand_full_page_write_with_map10(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, const uint32_t *buffer);
void alt_nand_full_page_read_with_map10_post_read_with_map01(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t *buffer);
void alt_nand_full_page_write_with_map10_post_write_with_map01(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, const uint32_t *buffer);
void alt_nand_set_sysmgr_bootstrap_value( uint32_t bootstrp_inhibit_init,
uint32_t bootstrp_inhibit_b0p0_load,
uint32_t bootstrp_512b_device,
uint32_t bootstrp_two_row_addr_cycles);
void alt_nand_reset_bank(uint32_t bank);
uint32_t alt_nand_bank_get(void);
void alt_nand_dma_write_cmd_structure( const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, const uint32_t page_count, uint64_t mem_addr, int32_t is_read_op, const uint32_t burst_len );
void alt_nand_dma_set_enabled( int32_t is_enabled );
int32_t alt_nand_dma_page_read( const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t mem_addr );
int32_t alt_nand_dma_page_write( const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t mem_addr );
ALT_STATUS_CODE alt_nand_flash_init_manual(void *);
void alt_nand_erase_block_callback(ALT_STATUS_CODE, void *);
void alt_nand_dma_page_callback(ALT_STATUS_CODE, void *);
void nand_print_device(void);
uint32_t nand_read_register(uint32_t offset);
void alt_nand_rb_pin_mode_set(uint32_t);
void alt_nand_rb_pin_mode_clear(uint32_t);
#endif /* __ALT_NAND_PRIVATE_H__ */

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
/*! \file
* Altera - QSPI Flash Controller Module
*/
#ifndef __ALT_QSPI_PRIVATE_H__
#define __ALT_QSPI_PRIVATE_H__
#include "socal/socal.h"
//
// This section provisions support for various flash devices.
//
#define ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT 1
/////
#define ALT_QSPI_PAGE_ADDR_MSK 0xFFFFFF00
#define ALT_QSPI_PAGE_SIZE 0x00000100 // 256 B
#define ALT_QSPI_SUBSECTOR_ADDR_MSK 0xFFFFF000
#define ALT_QSPI_SUBSECTOR_SIZE 0x00001000 // 4096 B
#define ALT_QSPI_SECTOR_ADDR_MSK 0xFFFF0000
#define ALT_QSPI_SECTOR_SIZE 0x00010000 // 64 KiB
#define ALT_QSPI_BANK_ADDR_MSK 0xFF000000
#define ALT_QSPI_BANK_SIZE 0x01000000 // 16 MiB
#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT
#define ALT_QSPI_N25Q_DIE_ADDR_MSK 0xFE000000
#define ALT_QSPI_N25Q_DIE_SIZE 0x02000000 // 32 MiB
#endif
/////
// Default delay timing (in ns) for N25Q.
// These values are from the N25Q handbook. The timing correctness is difficult
// to test because the test setup does not feature mutliple chips.
#define ALT_QSPI_TSHSL_NS_DEF (50)
#define ALT_QSPI_TSD2D_NS_DEF (0)
#define ALT_QSPI_TCHSH_NS_DEF (4)
#define ALT_QSPI_TSLCH_NS_DEF (4)
/*
// Default delay timing (in ns)
#define ALT_QSPI_TSHSL_NS_DEF (200)
#define ALT_QSPI_TSD2D_NS_DEF (255)
#define ALT_QSPI_TCHSH_NS_DEF (20)
#define ALT_QSPI_TSLCH_NS_DEF (20)
*/
// Flash commands
#define ALT_QSPI_STIG_OPCODE_READ (0x03)
#define ALT_QSPI_STIG_OPCODE_4BYTE_READ (0x13)
#define ALT_QSPI_STIG_OPCODE_FASTREAD (0x0B)
#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_OUTPUT (0x3B)
#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_OUTPUT (0x6B)
#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_IO (0xBB)
#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO (0xEB)
#define ALT_QSPI_STIG_OPCODE_PP (0x02)
#define ALT_QSPI_STIG_OPCODE_DUAL_PP (0xA2)
#define ALT_QSPI_STIG_OPCODE_QUAD_PP (0x32)
#define ALT_QSPI_STIG_OPCODE_RDID (0x9F)
#define ALT_QSPI_STIG_OPCODE_WREN (0x06)
#define ALT_QSPI_STIG_OPCODE_WRDIS (0x04)
#define ALT_QSPI_STIG_OPCODE_RDSR (0x05)
#define ALT_QSPI_STIG_OPCODE_WRSR (0x01)
#define ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE (0x20)
#define ALT_QSPI_STIG_OPCODE_SEC_ERASE (0xD8)
#define ALT_QSPI_STIG_OPCODE_BULK_ERASE (0xC7)
#define ALT_QSPI_STIG_OPCODE_DIE_ERASE (0xC4)
#define ALT_QSPI_STIG_OPCODE_CHIP_ERASE (0x60)
#define ALT_QSPI_STIG_OPCODE_RD_EXT_REG (0xC8)
#define ALT_QSPI_STIG_OPCODE_WR_EXT_REG (0xC5)
#define ALT_QSPI_STIG_OPCODE_RD_STAT_REG (0x05)
#define ALT_QSPI_STIG_OPCODE_WR_STAT_REG (0x01)
#define ALT_QSPI_STIG_OPCODE_ENTER_4BYTE_MODE (0xB7)
#define ALT_QSPI_STIG_OPCODE_EXIT_4BYTE_MODE (0xE9)
// Micron commands, for 512 Mib, 1 Gib (64 MiB, 128 MiB) parts.
#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT
#define ALT_QSPI_STIG_OPCODE_RESET_EN (0x66)
#define ALT_QSPI_STIG_OPCODE_RESET_MEM (0x99)
#define ALT_QSPI_STIG_OPCODE_RDFLGSR (0x70)
#define ALT_QSPI_STIG_OPCODE_CLRFLGSR (0x50)
#define ALT_QSPI_STIG_OPCODE_DISCVR_PARAM (0x5A)
#endif
// Spansion commands
// #define OPCODE_ECRM (0xFF) // Exit continuous read mode
#define QSPI_READ_CLK_MHZ (50)
#define QSPI_FASTREAD_CLK_MHZ (100)
// Manufacturer ID
#define ALT_QSPI_STIG_RDID_JEDECID_MICRON (0x20)
#define ALT_QSPI_STIG_RDID_JEDECID_NUMONYX (0x20) // Same as Micron
#define ALT_QSPI_STIG_RDID_JEDECID_SPANSION (0xEF)
#define ALT_QSPI_STIG_RDID_JEDECID_WINBOND (0xEF) // Same as Spansion
#define ALT_QSPI_STIG_RDID_JEDECID_MACRONIC (0xC2)
#define ALT_QSPI_STIG_RDID_JEDECID_ATMEL (0x1F)
#define ALT_QSPI_STIG_RDID_JEDECID_GET(value) ((value >> 0) & 0xff)
#define ALT_QSPI_STIG_RDID_CAPACITYID_GET(value) ((value >> 16) & 0xff)
#define ALT_QSPI_STIG_FLAGSR_ERASEPROGRAMREADY_GET(value) ((value >> 7) & 0x1)
#define ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(value) ((value >> 7) & 0x1)
#define ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(value) ((value >> 7) & 0x1)
#define ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(value) ((value >> 5) & 0x1)
#define ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(value) ((value >> 4) & 0x1)
#define ALT_QSPI_STIG_FLAGSR_ADDRESSINGMODE_GET(value) ((value >> 1) & 0x1)
#define ALT_QSPI_STIG_FLAGSR_PROTECTIONERROR_GET(value) ((value >> 0) & 0x1)
#define ALT_QSPI_STIG_SR_BUSY_GET(value) ((value >> 0) & 0x1)
/////
#define ALT_QSPI_TIMEOUT_INFINITE (0xffffffff)
ALT_STATUS_CODE alt_qspi_replace(uint32_t dst, const void * src, size_t size);
ALT_STATUS_CODE alt_qspi_stig_cmd(uint32_t opcode, uint32_t dummy, uint32_t timeout);
ALT_STATUS_CODE alt_qspi_stig_rd_cmd(uint8_t opcode, uint32_t dummy,
uint32_t num_bytes, uint32_t * output,
uint32_t timeout);
ALT_STATUS_CODE alt_qspi_stig_wr_cmd(uint8_t opcode, uint32_t dummy,
uint32_t num_bytes, const uint32_t * input,
uint32_t timeout);
ALT_STATUS_CODE alt_qspi_stig_addr_cmd(uint8_t opcode, uint32_t dummy,
uint32_t address,
uint32_t timeout);
ALT_STATUS_CODE alt_qspi_device_wren(void);
ALT_STATUS_CODE alt_qspi_device_wrdis(void);
ALT_STATUS_CODE alt_qspi_device_rdid(uint32_t * rdid);
ALT_STATUS_CODE alt_qspi_discovery_parameter(uint32_t * param);
ALT_STATUS_CODE alt_qspi_device_bank_select(uint32_t bank);
#endif // __ALT_PRIVATE_QSPI_H__

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/*! \file
* Altera - SoC Reset Manager
*/
/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ALT_RESET_MGR_H__
#define __ALT_RESET_MGR_H__
#include "hwlib.h"
#include <stdbool.h>
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*! \addtogroup RST_MGR The Reset Manager
*
* The Reset Manager API defines functions for accessing, configuring, and
* controlling the HPS reset behavior.
* @{
*/
/******************************************************************************/
/*! \addtogroup RST_MGR_STATUS Reset Status
*
* This functional group provides information on various aspects of SoC reset
* status and timeout events.
*
* @{
*/
/******************************************************************************/
/*!
* This type definition enumerates the set of reset causes and timeout events as
* register mask values.
*/
typedef enum ALT_RESET_EVENT_e
{
/*! Power-On Voltage Detector Cold Reset */
ALT_RESET_EVENT_PORVOLTRST = 0x00000001,
/*! nPOR Pin Cold Reset */
ALT_RESET_EVENT_NPORPINRST = 0x00000002,
/*! FPGA Core Cold Reset */
ALT_RESET_EVENT_FPGACOLDRST = 0x00000004,
/*! CONFIG_IO Cold Reset */
ALT_RESET_EVENT_CONFIGIOCOLDRST = 0x00000008,
/*! Software Cold Reset */
ALT_RESET_EVENT_SWCOLDRST = 0x00000010,
/*! nRST Pin Warm Reset */
ALT_RESET_EVENT_NRSTPINRST = 0x00000100,
/*! FPGA Core Warm Reset */
ALT_RESET_EVENT_FPGAWARMRST = 0x00000200,
/*! Software Warm Reset */
ALT_RESET_EVENT_SWWARMRST = 0x00000400,
/*! MPU Watchdog 0 Warm Reset */
ALT_RESET_EVENT_MPUWD0RST = 0x00001000,
/*! MPU Watchdog 1 Warm Reset */
ALT_RESET_EVENT_MPUWD1RST = 0x00002000,
/*! L4 Watchdog 0 Warm Reset */
ALT_RESET_EVENT_L4WD0RST = 0x00004000,
/*! L4 Watchdog 1 Warm Reset */
ALT_RESET_EVENT_L4WD1RST = 0x00008000,
/*! FPGA Core Debug Reset */
ALT_RESET_EVENT_FPGADBGRST = 0x00040000,
/*! DAP Debug Reset */
ALT_RESET_EVENT_CDBGREQRST = 0x00080000,
/*! SDRAM Self-Refresh Timeout */
ALT_RESET_EVENT_SDRSELFREFTIMEOUT = 0x01000000,
/*! FPGA manager handshake Timeout */
ALT_RESET_EVENT_FPGAMGRHSTIMEOUT = 0x02000000,
/*! SCAN manager handshake Timeout */
ALT_RESET_EVENT_SCANHSTIMEOUT = 0x04000000,
/*! FPGA handshake Timeout */
ALT_RESET_EVENT_FPGAHSTIMEOUT = 0x08000000,
/*! ETR Stall Timeout */
ALT_RESET_EVENT_ETRSTALLTIMEOUT = 0x10000000
} ALT_RESET_EVENT_t;
/******************************************************************************/
/*!
* Gets the reset and timeout events that caused the last reset.
*
* The ALT_RESET_EVENT_t enumeration values should be used to selectively
* examine the returned reset cause(s).
*
* \returns A mask of the reset and/or timeout events that caused the last
* reset.
*/
uint32_t alt_reset_event_get(void);
/******************************************************************************/
/*!
* Clears the reset and timeout events that caused the last reset.
*
* \param event_mask
* A mask of the selected reset and timeout events to clear in the
* Reset Manager \e stat register. The mask selection can be formed
* using the ALT_RESET_EVENT_t enumeration values.
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask);
/*! @} */
/******************************************************************************/
/*! \addtogroup RST_MGR_CTRL Reset Control
*
* This functional group provides global and selective reset control for the SoC
* and its constituent modules.
*
* @{
*/
/******************************************************************************/
/*!
* Initiate a cold reset of the SoC.
*
* If this function is successful, then it should never return.
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_reset_cold_reset(void);
/******************************************************************************/
/*!
* Initiate a warm reset of the SoC.
*
* Perform a hardware sequenced warm reset of the SoC. A hardware sequenced
* reset handshake with certain modules can optionally be requested in an
* attempt to ensure an orderly reset transition.
*
* \param warm_reset_delay
* Specifies the number of cycles after the Reset Manager releases
* the Clock Manager reset before releasing any other hardware
* controlled resets. Value must be greater than 16 and less than
* 256.
*
* \param nRST_pin_clk_assertion
* Specifies that number of clock cycles (osc1_clk?) to externally
* assert the warm reset pin (nRST). 0 <= \e nRST_pin_clk_assertion <=
* (2**20 - 1). A value of 0 prevents any assertion of nRST.
*
* \param sdram_refresh
* Controls whether the contents of SDRAM survive a hardware
* sequenced warm reset. The reset manager requests the SDRAM
* controller to put SDRAM devices into self-refresh mode before
* asserting warm reset signals. An argument value of \b true
* enables the option, \b false disables the option.
*
* \param fpga_mgr_handshake
* Controls whether a handshake between the reset manager and FPGA
* manager occurs before a warm reset. The handshake is used to
* warn the FPGA manager that a warm reset is imminent so it can
* prepare for it by driving its output clock to a quiescent state
* to avoid glitches. An argument value of \b true enables the
* option, \b false disables the option.
*
* \param scan_mgr_handshake
* Controls whether a handshake between the reset manager and scan
* manager occurs before a warm reset. The handshake is used to
* warn the scan manager that a warm reset is imminent so it can
* prepare for it by driving its output clock to a quiescent state
* to avoid glitches. An argument value of \b true enables the
* option, \b false disables the option.
*
* \param fpga_handshake
* Controls whether a handshake between the reset manager and the
* FPGA occurs before a warm reset. The handshake is used to warn
* the FPGA that a warm reset is imminent so that the FPGA prepare
* for the reset event in soft IP. An argument value of \b true
* enables the option, \b false disables the option.
*
* \param etr_stall
* Controls whether the ETR is requested to idle its AXI master
* interface (i.e. finish outstanding transactions and not initiate
* any more) to the L3 Interconnect before a warm reset. An
* argument value of \b true enables the option, \b false disables
* the option.
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay,
uint32_t nRST_pin_clk_assertion,
bool sdram_refresh,
bool fpga_mgr_handshake,
bool scan_mgr_handshake,
bool fpga_handshake,
bool etr_stall);
#if 0
/*! \addtogroup RST_MGR_MPU
*
* This functional group provides reset control for the Cortex-A9 MPU module.
*
* @{
*/
/*! @} */
/*! \addtogroup RST_MGR_PERIPH
*
* This functional group provides inidividual reset control for the HPS
* peripheral modules.
*
* @{
*/
/*! @} */
/*! \addtogroup RST_MGR_BRG
*
* This functional group provides inidividual reset control for the bridge
* interfaces between the HPS and FPGA.
*
* @{
*/
/*! @} */
/*! \addtogroup RST_MGR_MISC
*
* This functional group provides inidividual reset control for miscellaneous
* HPS modules.
*
* @{
*/
/*! @} */
#endif
/*! @} */
/*! @} */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_RESET_MGR_H__ */

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/*! \file
* Altera - SoC FPGA System Manager
*/
/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ALT_SYS_MGR_H__
#define __ALT_SYS_MGR_H__
#include "hwlib.h"
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/******************************************************************************/
/*! \addtogroup SYS_MGR The System Manager
*
* The System Manager API defines functions for control of system operation and
* for other modules requiring external control as part of system integration.
*
* The major functional APIs include:
* * HPS I/O configuration and pin muxing
* * External control of other modules
* * Control and status of ECC
* * Fault injection for ECC and parity errors.
* @{
*/
/******************************************************************************/
/*! \addtogroup SYS_MGR_FPGA_INTERFACE FPGA Interface Group
*
* These functions provide enable/disable control and operational status of the
* signal interfaces between the FPGA and HPS. Selective enabling/disabling of
* interfaces may be required under the following scenarios:
* * Interfaces that are associated with an HPS module but that are not disabled
* when the HPS module associated with the interface is put into reset.
* * An HPS module accepts signals from the FPGA and those signals might
* otherwise interfere with the normal operation of the HPS module.
* @{
*/
/******************************************************************************/
/*!
* This type definition enumerates the FPGA to HPS signal interfaces controlled
* by the functions in this API group.
*/
typedef enum ALT_FPGA_INTERFACE_e
{
ALT_FPGA_INTERFACE_GLOBAL, /*!< All interfaces between the FPGA and
* HPS. If ALT_FPGA_INTERFACE_ALL is disabled
* then all of the individual and module
* interfaces between the FPGA and HPS are
* disabled regardless of their separate
* enable/disable settings. If
* ALT_FPGA_INTERFACE_ALL is enabled then each
* individual and module interface between
* the FPGA and HPS may be separately
* enabled/disabled.
*/
ALT_FPGA_INTERFACE_RESET_REQ, /*!< The reset request interface. This
* interface allows logic in the FPGA to
* request HPS resets. The following reset
* request signals from the FPGA fabric to
* HPS are part of this interface:
* * \b f2h_cold_rst_req_n - Triggers a HPS cold reset
* * \b f2h_warm_rst_req_n - Triggers a HPS warm reset
* * \b f2h_dbg_rst_req_n - Triggers a HPS debug reset
*/
ALT_FPGA_INTERFACE_JTAG_ENABLE, /*!< The JTAG enable interface. This
* interface allows logic in the FPGA
* fabric to disable the HPS JTAG
* operation.
*/
ALT_FPGA_INTERFACE_CONFIG_IO, /*!< The CONFIG_IO interface. This interface
* allows the FPGA JTAG TAP controller to
* execute the CONFIG_IO instruction and
* configure all device I/O (FPGA and
* HPS).
*/
ALT_FPGA_INTERFACE_BSCAN, /*!< The boundary-scan interface. This
* interface allows the FPGA JTAG TAP
* controller to execute boundary-scan
* instructions.
*/
ALT_FPGA_INTERFACE_TRACE, /*!< The trace interface. This interface
* allows the HPS debug logic to send
* trace data to logic in the FPGA.
*/
ALT_FPGA_INTERFACE_DBG_APB, /*!< (Private) The debug APB interface. This
* interface allows the HPS debug logic to
* communicate with debug APB slaves in
* the FPGA fabric.
*/
ALT_FPGA_INTERFACE_STM, /*!< The STM event interface. This interface
* allows logic in the FPGA to trigger
* events to the HPS STM debug module.
*/
ALT_FPGA_INTERFACE_CTI, /*!< The Cross Trigger Interface (CTI). This
* interface allows logic in the FPGA to
* send triggers to HPS debug logic. Note
* that this does not prevent the HPS
* debug logic from sending triggers to
* the FPGA.
*/
ALT_FPGA_INTERFACE_EMAC0, /*!< Signal interface from the FPGA to the
* EMAC0 module.
*/
ALT_FPGA_INTERFACE_EMAC1, /*!< Signal interface from the FPGA to the
* EMAC1 module.
*/
ALT_FPGA_INTERFACE_SPIM0, /*!< (Private) Signal interface from the
* FPGA to the SPI Master 0 module.
*/
ALT_FPGA_INTERFACE_SPIM1, /*!< (Private) Signal interface from the
* FPGA to the SPI Master 0 module.
*/
ALT_FPGA_INTERFACE_NAND, /*!< (Private) Signal interface from the
* FPGA to the NAND Flash Controller
* module.
*/
ALT_FPGA_INTERFACE_SDMMC /*!< (Private) Signal interface from the
* FPGA to the SD/MMC Controller module.
*/
} ALT_FPGA_INTERFACE_t;
/******************************************************************************/
/*!
* Disables the specified FPGA to HPS signal interface.
*
* Isolates and disables the designated FPGA/HPS signal interface. User is
* responsible for determining that the interface is inactive before disabling
* it.
*
* \param intfc
* The interface to disable.
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG The \e intfc argument designates an invalid
* FPGA/HPS signal interface.
*/
ALT_STATUS_CODE alt_fpga_interface_disable(ALT_FPGA_INTERFACE_t intfc);
/******************************************************************************/
/*!
* Enables the specified FPGA to HPS signal interface.
*
* \param intfc
* The interface to enable.
*
* \retval ALT_E_SUCCESS The operation was succesful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG The \e intfc argument designates an invalid
* FPGA/HPS signal interface.
*/
ALT_STATUS_CODE alt_fpga_interface_enable(ALT_FPGA_INTERFACE_t intfc);
/******************************************************************************/
/*!
* Return whether the specified FPGA/HPS signal interface is enabled or not.
*
* \param intfc
* The interface to enable.
*
* \retval ALT_E_TRUE The interface is enabled.
* \retval ALT_E_FALSE The interface is not enabled.
* \retval ALT_E_BAD_ARG The \e intfc argument designates an invalid
* FPGA/HPS signal interface.
*/
ALT_STATUS_CODE alt_fpga_interface_is_enabled(ALT_FPGA_INTERFACE_t intfc);
/*! @} */
/*! @} */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_SYS_MGR_H__ */

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FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_timers.h
Unescape Escape View File

@ -0,0 +1,681 @@
/*! \file
* Altera - Module Description
*/
/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ALT_GPT_H__
#define __ALT_GPT_H__
#include <stdint.h>
#include <stdbool.h>
#include "hwlib.h"
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/******************************************************************************/
/*! \addtogroup GPT_MGR The General Purpose Timer Manager API
*
* There are nine on-chip general purpose timers. Seven timers are available
* to each CPU.\n\n
* There are four types of timers available:
* - Four general-purpose countdown timers available to CPU0, CPU1, or the
* FPGA.\n
* - Each CPU has a private GP countdown timer available only to itself.\n
* - Each CPU has a watchdog timer available only to itself that can work in
* GP timer countdown mode.\n
* - One continuous-countup global timer with compare capabilities available to
* both CPUs and the FPGA.\n\n
* Each type has a somewhat different HW interface This API presents the same
* external interface for each.
*
* @{
*/
/******************************************************************************/
/*!
* This type definition enumerates the names of the timers
* managed by the General Purpose Timers Manager.
*/
typedef enum ALT_GPT_TIMER_e
{
/*!
* \b CPU_GLOBAL_TMR - CPU Core Global timer - There is one 64-bit
* continuously incrementing counter for all CPU cores that is clocked
* by PERIPHCLK. CPU_GLOBAL_TMR selects the comparator value, compare
* enable, autoincrement value, autoincrement enable, and interrupt
* enable for the CPU this code is running on.
*/
ALT_GPT_CPU_GLOBAL_TMR,
/*!
* \b CPU_PRIVATE_TMR - CPU Core 32-bit Private Timer - The private timer
* for the CPU this code is running on. Clocked by PERIPHCLK. Counts
* down to zero and can either stop or restart.
*/
ALT_GPT_CPU_PRIVATE_TMR,
/*!
* \b CPU_WDTGPT_TMR - CPU Core 32-bit Watchdog Timer - The watchdog
* timer can be used as a general-purpose timer by calling
* alt_wdt_response_mode_set() to put the watchdog timer in general-purpose
* timer mode. It is recommended that programmers use the other available
* timers first before using the watchdog timer as there is more software
* overhead involved in using the watchdog timer in this mode. This enum is
* for the core watchdog timer of the CPU this code is running on. Counts
* down to zero and can either stop or restart.
*/
ALT_GPT_CPU_WDTGPT_TMR,
/* Peripheral Timers */
/* OSC1 Clock Group */
/*!
* \b osc1_timer0 - 32-bit timer connected to the L4_OSC1 bus clocked by
* osc1_clk. Counts down to zero and can either stop or restart.
*/
ALT_GPT_OSC1_TMR0,
/*!
* \b osc1_timer1 - 32-bit timer connected to the L4_OSC1 bus clocked by
* osc1_clk. Counts down to zero and can either stop or restart.
*/
ALT_GPT_OSC1_TMR1,
/* L4_SP Clock Group */
/*!
* \b sp_timer0 - 32-bit timer connected to the L4_SP bus clocked by
* l4_sp_clk. Counts down to zero and can either stop or restart.
*/
ALT_GPT_SP_TMR0,
/*!
* \b sp_timer1 - 32-bit timer connected to the L4_SP bus clocked by
* l4_sp_clk. Counts down to zero and can either stop or restart.
*/
ALT_GPT_SP_TMR1
} ALT_GPT_TIMER_t;
/*!
* This type definition enumerates the possible rollover or restart modes
* of the general purpose timers.
*/
typedef enum ALT_GPT_RESTART_MODE_e
{
/*!
* \b ONE-SHOT \b MODE - \b CPU_PRIVATE_TMR,
* \b OSC1_TMR0, \b OSC1_TMR1, \b SP_TMR0, and \b SP_TMR1
* count down from the value set with alt_gpt_counter_set() to
* zero, trigger an interrupt and stop.\n
* The global timer \b CPU_GLOBAL_TMR counts up to the next compare value
* set by the compare value, triggers an interrupt and stops
* comparing.
*/
ALT_GPT_RESTART_MODE_ONESHOT,
/*!
* \b USER-SUPPLIED \b COUNT - For \b CPU_PRIVATE_TMR, \b OSC1_TMR0,
* \b OSC1_TMR1, \b SP_TMR0, and \b SP_TMR1, the timer counts down
* to zero and then resets to a value previously set using
* alt_gpt_counter_set() and continues counting.\n
* \b CPU_GLOBAL_TMR counts up to the comparator value, then adds
* the value set in alt_gpt_counter_set() to the comparator value and
* continues counting.
*/
ALT_GPT_RESTART_MODE_PERIODIC
} ALT_GPT_RESTART_MODE_t;
/******************************************************************************/
/*! \addtogroup GPT_STATUS Enable, Disable, and Status
*
* This functional group handles enabling, disabling, and reading the
* current enable state of the general purpose timers and the global timer.
*
* @{
*/
/******************************************************************************/
/*! Uninitialize all of the general-purpose timer modules
*
*/
ALT_STATUS_CODE alt_gpt_all_tmr_uninit(void);
/******************************************************************************/
/*! Initialize all of the general-purpose timer modules
*
*/
ALT_STATUS_CODE alt_gpt_all_tmr_init(void);
/******************************************************************************/
/*!
* Stop and disable the specified general purpose timer or global timer.
*
*
* \param tmr_id
* The timer identifier.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Tried to stop an invalid timer.
*/
ALT_STATUS_CODE alt_gpt_tmr_stop(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Enable and start the specified general purpose timer or global timer.
*
*
* \param tmr_id
* The timer identifier.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Tried to start an invalid timer.
*/
ALT_STATUS_CODE alt_gpt_tmr_start(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns whether the specified timer is currently running or not.
* For the free-running 64-bit global timer, returns whether its comparison
* mode is enabled or not.
*
* \param tmr_id
* The timer identifier.
*
* \retval ALT_E_TRUE The timer is currently enabled and running.
* \retval ALT_E_FALSE The timer is currently disabled and stopped.
* \retval ALT_E_BAD_ARG Tried to access an invalid timer.
*/
ALT_STATUS_CODE alt_gpt_tmr_is_running(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Restarts the specified general purpose timer with its original value. If
* used for the global timer, it updates the comparator value with the sum of
* the auto-increment value and the current global timer value and enables
* comparison mode.
*
*
* \param tmr_id
* The timer identifier.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Tried to access an invalid timer.
*/
ALT_STATUS_CODE alt_gpt_tmr_reset(ALT_GPT_TIMER_t tmr_id);
/*! @} */
/******************************************************************************/
/*! \addtogroup GPT_COUNTER Counters Interface
*
* This functional group handles setting and reading the general purpose
* timer counters and the global timer.
*
* @{
* */
/******************************************************************************/
/*!
* For tmr_id = \b CPU_PRIVATE_TMR, \b OSC1_TMR0, \b
* OSC1_TMR1, \b SP_TMR0, or \b SP_TMR1, sets the countdown value of the
* specified timer and the value that the counter will reset to (in rollover
* mode) or if restarted (in one-shot mode). It does not automatically start
* the counter. \n For tmr_id = \b CPU_GLOBAL_TMR,
* this function sets the auto-increment value instead, which is similar in
* function to setting the reset value of the other timers. The effect of this
* function is identical to using alt_globaltmr_autoinc_set().
*
*
* \param tmr_id
* The timer identifier.
*
* \param val
* The 32-bit counter value to load.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_gpt_counter_set(ALT_GPT_TIMER_t tmr_id,
uint32_t val);
/******************************************************************************/
/*!
* For tmr_id = \b CPU_PRIVATE_TMR, \b OSC1_TMR0, \b
* OSC1_TMR1, \b SP_TMR0, or \b SP_TMR1, returns the current counter value of
* the specified timer. \n For tmr_id = \b CPU_GLOBAL_TMR, returns the 32
* low-order bits of the counter and is identical to the result returned by
* alt_globaltmr_counter_get_low32(). Use alt_globaltmr_get() to obtain the full
* 64-bit timer value.
*
* \param tmr_id
* The timer identifier.
*
*
* \retval uint32_t The current 32-bit counter value.
*/
uint32_t alt_gpt_counter_get(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* For tmr_id = \b CPU_PRIVATE_TMR, \b OSC1_TMR0, \b
* OSC1_TMR1, \b SP_TMR0, or \b SP_TMR1, returns the counter value that is
* set to be reloaded when the specified timer hits zero. \n
* For tmr_id = \b CPU_GLOBAL_TMR, returns the value that will
* autoincrement the comparator value, which defines the time until the next
* comparator interrupt is triggered. This is similar in function to the
* reset value of the other timers. It is identical to the result returned by
* alt_globaltmr_autoinc_get(). \n The value returned does not take into
* CPU_PRIVATE_TMR and \b CPU_GLOBAL_TMR. The prescaler value may be obtained
* with alt_gpt_prescaler_get().
*
*
* \param tmr_id
* The timer identifier.
*
*
* \retval uint32_t The reset counter value currently set.
* \retval 0 An error occurred.
*/
uint32_t alt_gpt_reset_value_get(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the maximum counter value available for the specified
* timer. Valid for \b CPU_PRIVATE_TMR, \b OSC1_TMR0,
* \b OSC1_TMR1, \b SP_TMR0, \b SP_TMR1, and \b CPU_GLOBAL_TMR. \n
* The value returned does not factor in the value of the clock prescaler
* available for \b CPU_PRIVATE_TMR and \b CPU_GLOBAL_TMR.
*
*
* \param tmr_id
* The timer identifier.
*
*
* \retval uint32_t The maximum counter value available for this timer.
* \retval 0 An error occurred.
*
*/
uint32_t alt_gpt_maxcounter_get(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Sets the clock prescaler value of the specified timer. Valid for \b
* CPU_PRIVATE_TMR and \b CPU_GLOBAL_TMR. Returns an error
* if called with a tmr_id of \b OSC1_TMR0,
* \b OSC1_TMR1, \b SP_TMR0, or \b SP_TMR1 since they have no prescaler.
*
* \param tmr_id
* The timer identifier.
*
* \param val
* The 32-bit prescaler value to load. Valid range is 1-256.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_gpt_prescaler_set(ALT_GPT_TIMER_t tmr_id,
uint32_t val);
/******************************************************************************/
/*!
* Returns the clock prescaler value of the specified timer. Valid for \b
* CPU_PRIVATE_TMR and \b CPU_GLOBAL_TMR. Returns one if
* called with a tmr_id of \b OSC1_TMR0, \b
* OSC1_TMR1, \b SP_TMR0, or \b SP_TMR1 since they have no prescaler.
*
*
* \param tmr_id
* The timer identifier.
*
* \retval uint32_t The prescaler value. Valid range is 1-256.
* Zero indicates an error.
*/
uint32_t alt_gpt_prescaler_get(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the integer portion of the current countdown frequency of the
* specified timer.
*
*
* \param tmr_id
* The timer identifier.
*
* \retval unint32_t The integer portion of the repeat frequency of the
* given timer, measured in Hertz (cycles per second).
*/
uint32_t alt_gpt_freq_get(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the current period of the specified timer measured in seconds.
* If the result is less than 64, alt_gpt_millisecs_get() will give a more
* precise result.
*
* \param tmr_id
* The timer identifier.
*
* \retval uint32_t The current period of the given timer, measured
* in seconds.
*/
uint32_t alt_gpt_time_get(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the current period of the specified timer measured in milliseconds.
*
*
*
* \param tmr_id
* The timer identifier.
*
* \retval uint32_t The current period of the given timer, measured
* in milliseconds. Returns 0 if result cannot fit
* in 32 bits. alt_gpt_time_get() can be used to
* obtain measurements of longer periods.
* alt_gpt_microsecs_get() can be used to obtain
* more precise measurements of shorter periods.
*/
uint32_t alt_gpt_time_millisecs_get(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the current period of the specified timer measured in milliseconds.
*
*
*
* \param tmr_id
* The timer identifier.
*
* \retval uint32_t The current period of the given timer, measured
* in microseconds. Returns 0 if result cannot fit
* in 32 bits. alt_gpt_millisecs_get() and
* alt_gpt_time_get() can be used to obtain
* measurements of longer periods.
*/
uint32_t alt_gpt_time_microsecs_get(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the current time until the specified timer counts
* down to zero, measured in seconds.
*
* \param tmr_id
* The timer identifier.
*
*
* \retval uint32_t The current 32-bit counter value.
*/
uint32_t alt_gpt_curtime_get(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the current time until the specified timer counts
* down to zero, measured in milliseconds. \n Returns 0xFFFFFFFF if the value
* is too large to be expressed in 32 bits.
*
* \param tmr_id
* The timer identifier.
*
*
* \retval uint32_t The current 32-bit counter value.
*/
uint32_t alt_gpt_curtime_millisecs_get(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the current time until the specified timer counts
* down to zero, measured in microseconds. \n Returns 0xFFFFFFFF if the value
* is too large to be expressed in 32 bits.
*
* \param tmr_id
* The timer identifier.
*
*
* \retval uint32_t The current 32-bit counter value.
*/
uint32_t alt_gpt_curtime_microsecs_get(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the current time until the specified timer counts
* down to zero, measured in nanoseconds. \n Returns 0xFFFFFFFF if the value
* is too large to be expressed in 32 bits.
*
* \param tmr_id
* The timer identifier.
*
*
* \retval uint32_t The current 32-bit counter value.
*/
uint32_t alt_gpt_curtime_nanosecs_get(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the maximum available period of the specified
* timer measured in seconds.
*
*
* \param tmr_id
* The timer identifier.
*
* \retval uint32_t The maximum period of the given timer, measured
* in seconds. Returns 0 if result cannot fit
* in 32 bits.
*/
uint32_t alt_gpt_maxtime_get(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the maximum available period of the specified
* timer measured in milliseconds.
*
*
* \param tmr_id
* The timer identifier.
*
* \retval uint32_t The maximum period of the given timer, measured
* in milliseconds. Returns 0 if result cannot fit
* in 32 bits.
*/
uint32_t alt_gpt_maxtime_millisecs_get(ALT_GPT_TIMER_t tmr_id);
/*! @} */
/******************************************************************************/
/*! \addtogroup GPT_INT Interrupts
* This functional group handles managing, setting, clearing, and disabling
* the interrupts of the general purpose timers and the global timer.
* @{ */
/******************************************************************************/
/*!
* Disables the interrupt from the specified general purpose timer or
* global timer module.
*
*
* \param tmr_id
* The timer identifier.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_gpt_int_disable(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Enables the interrupt of the specified general purpose timer or global
* timer module.
*
*
* \param tmr_id
* The timer identifier.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_gpt_int_enable(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Return \b TRUE if the interrupt of the specified timer module is enabled
* and \b FALSE if the interrupt is disabled or masked.
*
* \param tmr_id
* The timer identifier.
*
* \retval TRUE The timer interrupt is currently enabled.
* \retval FALSE The timer interrupt is currently disabled.
*/
bool alt_gpt_int_is_enabled(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Clear the pending interrupt status of the specified timer module.
*
*
* \param tmr_id
* The timer identifier.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_gpt_int_clear_pending(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Read the state (pending or not) of the interrupt of the specified timer
* module without changing the interrupt state.
*
*
* \param tmr_id
* The timer identifier.
*
* \retval ALT_E_TRUE The timer interrupt is currently pending.
* \retval ALT_E_FALSE The timer interrupt is not currently pending.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_gpt_int_is_pending(ALT_GPT_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Read the state of the interrupt of the specified general purpose timer
* module and if the interrupt is set, clear it.
*
*
* \param tmr_id
* The timer identifier.
*
* \retval ALT_E_TRUE The timer interrupt is currently pending.
* \retval ALT_E_FALSE The timer interrupt is not currently pending.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_gpt_int_if_pending_clear(ALT_GPT_TIMER_t tmr_id);
/*! @} */
/******************************************************************************/
/*! \addtogroup GPT_MODE Mode Control
* This functional group handles setting and reading the operational mode of
* the general purpose timers. The module version ID read function is also
* located here.
* @{
*/
/******************************************************************************/
/*!
* Sets the mode of the specified timer, the behavior that occurs when either
* the general-purpose timer counts down to zero or when the the global timer
* reaches its comparator value.
*
*
* \param tmr_id
* The timer identifier.
*
* \param mode
* \b GPT_RESTART_MODE_ONESHOT - To select one-shot mode for
* the timer.
* \n \b GPT_RESTART_MODE_PERIODIC - To select free-run mode for
* the timer.
*
* \internal
* The HHP HPS Timer NPP states that the value of the counter (Timer1LoadCount
* register) must be set to 0xFFFFFFFF before changing this setting to free-
* running mode (and timer must be disabled). The relevent L4 peripheral
* document does not mention the requirement to write 0xFFFFFFFF to the
* Timer1LoadCount register though.
* \endinternal
*
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
ALT_STATUS_CODE alt_gpt_mode_set(ALT_GPT_TIMER_t tmr_id,
ALT_GPT_RESTART_MODE_t mode);
/******************************************************************************/
/*!
* Reads the mode of the specified timer.
*
* \param tmr_id
* The timer identifier.
*
* \retval GPT_RESTART_MODE_ONESHOT Timer is set to one-shot mode.
* \retval GPT_RESTART_MODE_PERIODIC Counter value is set to a
* user-defined value.
* \retval ALT_E_BAD_ARG Invalid input argument.
*/
int32_t alt_gpt_mode_get(ALT_GPT_TIMER_t tmr_id);
/*! @} */
/*! @} */
/*! @} */
/*! @} */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_GPT_H__ */

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FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_watchdog.h
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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ALT_WDOG_H__
#define __ALT_WDOG_H__
#include "hwlib.h"
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/*! \addtogroup WDOG_MGR The Watchdog Timer Manager API
*
* This module defines the Watchdog Timer Manager API for accessing, configuring, and
* controlling the HPS Watchdog Timer resources.
*
*
A typical initialization might be:
\verbatim
ALT_STATUS_CODE ret;
ret = alt_wdog_int_clear(ALT_CPU_WATCHDOG);
if (ret == ALT_E_SUCCESS) {ret = alt_wdog_counter_set(ALT_CPU_WATCHDOG, 0x7FFFFFFF); }
if (ret == ALT_E_SUCCESS) {ret = alt_wdog_core_prescaler_set(0x80); }
if (ret == ALT_E_SUCCESS) {ret = alt_wdog_response_mode_set(ALT_CPU_WATCHDOG, ALT_WDOG_TIMER_MODE_FREERUN); }
if (ret == ALT_E_SUCCESS) {ret = alt_wdog_int_enable(ALT_CPU_WATCHDOG); }
if (ret == ALT_E_SUCCESS) {ret = alt_wdog_start(ALT_CPU_WATCHDOG); }
\endverbatim
Then periodically (before it runs out) call this function to restart the watchdog:
\verbatim
alt_wdog_reset(ALT_CPU_WATCHDOG);
\endverbatim
If the interrupt is enabled in the interrupt manager and is triggered, it can be
cleared like this:
\verbatim
alt_wdog_int_clear(ALT_CPU_WATCHDOG);
\endverbatim
If the interrupt is not enabled in the interrupt manager, you can still poll to
see if it hit zero and clear any pending interrupts like this:
\verbatim
alt_wdog_int_if_pending_clear(ALT_CPU_WATCHDOG);
\endverbatim
*
* @{
*/
/******************************************************************************/
/*!
* This type definition enumerates the names of the timers managed by
* the Watchdog Timers Manager.
*/
typedef enum ALT_WDOG_TIMER_e {
/* OSC1 Clock Group */
/*!
* \b ALT_CPU_WATCHDOG - Each CPU core has its own watchdog timer, which is
* clocked by PERIPHCLK. Can be loaded with any 32-bit counter
* value, not limited to powers of two, and it has an 8-bit prescaler.
* This timer also has a pause-enable input that can allow other HW
* to freeze the countdown.
*/
ALT_WDOG_CPU,
/* OSC1 Clock Group */
/*!
* \b watchdog_timer0 - Connected to the L4_OSC1 bus clocked by osc1_clk.
* Counter values are limited to powers of two between 15 and 31
* and there is no prescaler.
*/
ALT_WDOG0,
/*!
* \b watchdog_timer1 - Connected to the L4_OSC1 bus clocked by osc1_clk.
* Counter values are limited to powers of two between 15 and 31
* and there is no prescaler.
*/
ALT_WDOG1,
/*!
* \b watchdog_init_timer0 - This is for the initial timout only (not
* necessarily immediately after system restart), watchdog_timer0 is then
* used for all subsequent timeouts. Connected to the L4_OSC1 bus clocked
* by osc1_clk.
* Counter values are limited to powers of two between 15 and 31 and
* there is no prescaler.
*/
ALT_WDOG0_INIT,
/*!
* \b watchdog_init_timer1 - This is for the initial timout only (not
* necessarily immediately after system restart), watchdog_timer1 is then
* used for all subsequent timeouts. Connected to the L4_OSC1 bus clocked
* by osc1_clk.
* Counter values are limited to powers of two between 15 and 31 and
* there is no prescaler.
*/
ALT_WDOG1_INIT
} ALT_WDOG_TIMER_t;
/******************************************************************************/
/*!
* This type definition enumerates the encoded countdown values that \b
* ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL, and \b ALT_WATCHDOG1_INITIAL
* can be set to use.
*/
typedef enum ALT_WDOG_TIMEOUT_e {
/*!
* \b ALT_WDOG_TIMEOUT64K - Timeout = 65,536 osc1_clk periods.
*/
ALT_WDOG_TIMEOUT64K,
/*!
* \b ALT_WDOG_TIMEOUT128K - Timeout = 131,072 osc1_clk periods.
*/
ALT_WDOG_TIMEOUT128K,
/*!
* \b ALT_WDOG_TIMEOUT256K - Timeout = 262,144 osc1_clk periods.
*/
ALT_WDOG_TIMEOUT256K,
/*!
* \b ALT_WDOG_TIMEOUT512K - Timeout = 524,288 osc1_clk periods.
*/
ALT_WDOG_TIMEOUT512K,
/*!
* \b ALT_WDOG_TIMEOUT1M - Timeout = 1,048,576 osc1_clk periods.
*/
ALT_WDOG_TIMEOUT1M,
/*!
* \b ALT_WDOG_TIMEOUT2M - Timeout = 2,097,152 osc1_clk periods.
*/
ALT_WDOG_TIMEOUT2M,
/*!
* \b ALT_WDOG_TIMEOUT4M - Timeout = 4,194,304 osc1_clk periods.
*/
ALT_WDOG_TIMEOUT4M,
/*!
* \b ALT_WDOG_TIMEOUT8M - Timeout = 8,388,608 osc1_clk periods.
*/
ALT_WDOG_TIMEOUT8M,
/*!
* \b ALT_WDOG_TIMEOUT16M - Timeout = 16,777,216 osc1_clk periods.
*/
ALT_WDOG_TIMEOUT16M,
/*!
* \b ALT_WDOG_TIMEOUT32M - Timeout = 33,554,432 osc1_clk periods.
*/
ALT_WDOG_TIMEOUT32M,
/*!
* \b ALT_WDOG_TIMEOUT64M - Timeout = 67,108,864 osc1_clk periods.
*/
ALT_WDOG_TIMEOUT64M,
/*!
* \b ALT_WDOG_TIMEOUT128M - Timeout = 134,217,728 osc1_clk periods.
*/
ALT_WDOG_TIMEOUT128M,
/*!
* \b ALT_WDOG_TIMEOUT256M - Timeout = 268,435,456 osc1_clk periods.
*/
ALT_WDOG_TIMEOUT256M,
/*!
* \b ALT_WDOG_TIMEOUT512M - Timeout = 536,870,912 osc1_clk periods.
*/
ALT_WDOG_TIMEOUT512M,
/*!
*
* \b ALT_WDOG_TIMEOUT1G - Timeout = 1,073,741,824 osc1_clk periods.
*/
ALT_WDOG_TIMEOUT1G,
/*!
* \b ALT_WDOG_TIMEOUT2G - Timeout = 2,147,483,648 osc1_clk periods.
*/
ALT_WDOG_TIMEOUT2G
} ALT_WDOG_TIMEOUT_t;
/******************************************************************************/
/*!
* This type definition enumerates the reset types that the watchdog
* timers can be set to trigger.
*/
typedef enum ALT_WDOG_RESET_TYPE_e {
/*!
* \b Reset - For \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL,
* and \b ALT_WATCHDOG1_INITIAL, if the counter reaches zero without being
* reset, generate a system-wide warm reset request.
* This is the default mode out of reset. \n For \b ALT_CPU_WATCHDOG, no
* interrupt is triggered and a reset request is asserted. The response
* to the reset request is set in the reset controller block and may
* not automatically trigger a system reset.
*/
ALT_WDOG_WARM_RESET,
/*!
* \b Interrupt_First - When the counter reaches zero without being
* reset, generate an interrupt. For \b ALT_WATCHDOG0, \b
* ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL, and \b ALT_WATCHDOG1_INITIAL, if the
* interrupt is not cleared by the time a second timeout occurs, then
* generate a system warm reset request. \n For \b ALT_CPU_WATCHDOG, the
* interrupt is triggered and a \b WDRESETREQ
* reset request is asserted. The response to the interrupt and the reset
* request is set in the interrupt and reset controller blocks and may
* not automatically trigger a system reset.
*/
ALT_WDOG_INT_THEN_RESET,
/*!
* \b Timer_mode_oneshot - The \b ALT_CPU_WATCHDOG timer has the capability
* to not only operate as a watchdog timer, but also to operate as a
* general-purpose countdown timer. This selection specifies the \b
* ALT_CPU_WATCHDOG runs
* in one-shot timer mode, and can optionally trigger an interrupt when
* the counter reaches zero without being reset. This
* is the default selection for \b ALT_CPU_WATCHDOG out of reset. \n
* This selection has no meaning for \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b
* ALT_WATCHDOG0_INITIAL, and \b ALT_WATCHDOG1_INITIAL.
*/
ALT_WDOG_TIMER_MODE_ONESHOT,
/*!
* \b Timer_mode_freerun - The \b ALT_CPU_WATCHDOG timer has the capability
* to not only operate as a watchdog timer, but also to operate as a
* general-purpose countdown timer. This selection specifies the \b
* ALT_CPU_WATCHDOG in
* free-run or wraparound timer mode, and can optionally trigger an
* interrupt when the counter reaches zero without being reset. \n
* This selection has no meaning for \b
* ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL, and \b ALT_WATCHDOG1_INITIAL.
*/
ALT_WDOG_TIMER_MODE_FREERUN
} ALT_WDOG_RESET_TYPE_t;
/******************************************************************************/
/*! \addtogroup WDOG_STATUS Watchdog Timer Enable, Disable, Restart, Status
*
* This functional group contains the basic functions to control and manage
* the watchdog timers.
*
* @{
*/
/******************************************************************************/
/*!
* Initialize the watchdog timer module before use
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_wdog_init(void);
/******************************************************************************/
/*!
* Uninitialize the watchdog timer module & return to reset state
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_wdog_uninit(void);
/******************************************************************************/
/*!
* Stop the specified watchdog timer. \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b
* ALT_WATCHDOG0_INITIAL and \b ALT_WATCHDOG1_INITIAL cannot be stopped
* once started.
*
* \param tmr_id
* The watchdog timer identifier.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Tried to stop an invalid watchdog timer.
*/
ALT_STATUS_CODE alt_wdog_stop(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Start the specified watchdog timer.
*
*
* \param tmr_id
* The watchdog timer identifier.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Tried to enable an invalid watchdog timer.
*/
ALT_STATUS_CODE alt_wdog_start(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns whether the specified watchdog timer is currently running or not.
*
*
* \param tmr_id
* The watchdog timer identifier.
*
* \retval TRUE The timer is currently running.
* \retval FALSE The timer is currently not running.
*/
bool alt_wdog_tmr_is_enabled(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Reloads the counter countdown value, clears the timer interrupt, and
* restarts the watchdog timer. User can reset the timer at any time before
* timeout. This is also known as kicking, petting, feeding, waking, or
* walking the watchdog. \n If the timer is reset while stopped, it remains
* stopped, the timer reset value is reloaded and the countdown will start
* from there when it is started. The timer configuration is retained.
*
*
* \param tmr_id
* The watchdog timer identifier.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Tried to reset an invalid watchdog timer.
*/
ALT_STATUS_CODE alt_wdog_reset(ALT_WDOG_TIMER_t tmr_id);
/*! @} */
/******************************************************************************/
/*! \addtogroup WDOG_COUNTERS Watchdog Timer Counter Configuration
*
*
* This functional group implements setting, configuring and reading
* the counters of the watchdog timers.
*
* @{
*/
/******************************************************************************/
/*! Sets the countdown value of the specified timer. This is a regular value
* for \b ALT_CPU_WATCHDOG. For tmr_id = \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b
* ALT_WATCHDOG0_INITIAL or \b ALT_WATCHDOG1_INITIAL however, this is an encoded
* power-of-two value such that 2**(16 + val). \n
* If this value is set before the watchdog timer is started, then this
* value is used from the start. If this value is set after the timer
* has been started, it takes effect when the timer rolls over or the next
* time it is started.
*
* \param tmr_id
* The watchdog timer identifier.
*
* \param val
* The counter value to load.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Tried to write an invalid watchdog timer or
* timeout value.
*/
ALT_STATUS_CODE alt_wdog_counter_set(ALT_WDOG_TIMER_t tmr_id,
uint32_t val);
/******************************************************************************/
/*!
* Returns the current counter value of the specified timer.
*
* \param tmr_id
* The watchdog timer identifier.
*
*
* \retval uint32_t The current 32-bit counter value.
*/
uint32_t alt_wdog_counter_get_current(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the current counter value of the specified timer, as measured in
* milliseconds. For \b ALT_CPU_WATCHDOG, this includes the effects of the
* prescaler setting.
*
* \param tmr_id
* The watchdog timer identifier.
*
*
* \retval uint32_t The current 32-bit counter value (in milliseconds).
*/
uint32_t alt_wdog_counter_get_curtime_millisecs(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the initial counter value of the specified timer as a 32-bit
* integer value. This is the value that will be reloaded when the timer
* is reset or restarted. For the timers where this value is set as an
* encoded powers-of-two between 15 and 31, the value is converted into the
* equivalent binary value before returning it. \n For \b ALT_CPU_WATCHDOG,
* the returned value does not include the effects of the prescaler setting.
*
* \param tmr_id
* The watchdog timer identifier.
*
* \retval uint32_t The current 32-bit counter value.
* 0 Indicates an error.
*/
uint32_t alt_wdog_counter_get_init(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the initial value of the specified timer in nanoseconds.
* This is the value that will be reloaded when the timer is reset or
* restarted. For \b ALT_CPU_WATCHDOG, this includes the effects of the
* prescaler setting. This call returns a more precise result than
* alt_wdog_counter_get_inittime_millisecs(), but as an unsigned 64-bit
* integer.
*
* \param tmr_id
* The watchdog timer identifier.
*
* \retval uint64_t The currently-selected watchdog delay time (in
* nanoseconds).
*/
uint64_t alt_wdog_counter_get_inittime_nanosecs(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the initialized value of the specified timer in milliseconds.
* This is the value that will be reloaded when the timer is reset or
* restarted. For \b ALT_CPU_WATCHDOG, this includes the effects of the
* prescaler setting. This call returns a 32-bit unsigned integer, though is
* less precise than alt_wdog_counter_get_inittime_nanosecs().
*
* \param tmr_id
* The watchdog timer identifier.
*
* \retval uint32_t The currently-selected watchdog delay time (in
* milliseconds).
* 0 Indicates an error.
*/
uint32_t alt_wdog_counter_get_inittime_millisecs(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Sets the value of the CPU watchdog timer \b ALT_CPU_WATCHDOG prescaler.
* Must be set before the watchdog timer is enabled.
*
*
* \param val
* The eight-bit prescaler value to load (maximum 255).
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_BAD_ARG Bad prescaler value specified.
*/
ALT_STATUS_CODE alt_wdog_core_prescaler_set(uint32_t val);
/******************************************************************************/
/*!
* Returns the value of the prescaler of the CPU core watchdog timer
* \b ALT_CPU_WATCHDOG.
*
* \retval val
* The eight-bit prescaler value.
*
*/
uint32_t alt_wdog_core_prescaler_get(void);
/******************************************************************************/
/*!
* Returns the maximum possible counter value of the specified timer as a
* 32-bit value. For the timers where this value is encoded (as
* powers-of-two between 15 and 31), the encoded value is converted into the
* equivalent binary value before returning it. This does not include the
* effects of the prescaler available for \b ALT_CPU_WATCHDOG.
*
* \param tmr_id
* The watchdog timer identifier.
*
* \retval uint32_t The current 32-bit counter value.
*/
uint32_t alt_wdog_counter_get_max(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the maximum possible delay time of the specified timer specified in
* nanoseconds. For \b ALT_CPU_WATCHDOG, this includes the prescaler setting.
* This call returns a more precise reading of the counter than
* alt_wdog_counter_get_max_millisecs(), though in an unsigned 64-bit integer.
*
* \param tmr_id
* The watchdog timer identifier.
*
* \retval uint64_t The maximum delay time before timeout (in
* nanoseconds).
*/
uint64_t alt_wdog_counter_get_max_nanosecs(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the maximum possible delay time of the specified timer specified in
* milliseconds. For \b ALT_CPU_WATCHDOG, this includes the prescaler setting.
* This call returns a 32-bit unsigned integer, though is less precise than
* alt_wdog_counter_get_max_nanosecs().
*
* \param tmr_id
* The watchdog timer identifier.
*
* \retval uint32_t The maximum delay time before timeout (in
* milliseconds).
*/
uint32_t alt_wdog_counter_get_max_millisecs(ALT_WDOG_TIMER_t tmr_id);
/*! @} */
/******************************************************************************/
/*! \addtogroup WDOG_INTS Watchdog Timer Interrupt Management
*
*
* This functional group implements management of the interrupts
* of the watchdog timers.
*
* @{
*/
/******************************************************************************/
/*!
* Disables the interrupt of the specified watchdog timer module.
* If the watchdog timer is one of the watchdog timers that can be used in
* general-purpose mode, and if the timer is in general-purpose timer mode,
* disable the interrupt.
*
* \param tmr_id
* The timer identifier.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Specified an incorrect timer.
*/
ALT_STATUS_CODE alt_wdog_int_disable(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Sets/enables the interrupt of the specified watchdog timer module.
* If the watchdog timer is one of the watchdog timers that can be used in
* general-purpose mode, and if the timer is in general-purpose timer mode,
* enable the interrupt.
*
* \param tmr_id
* The timer identifier.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Specified an incorrect timer.
*/
ALT_STATUS_CODE alt_wdog_int_enable(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the status of the interrupt of the specified watchdog timer module
* but does not clear it. Return \b TRUE if the interrupt of the specified
* general purpose timer module is pending and \b FALSE otherwise.
*
* \param tmr_id
* The timer identifier.
*
* \retval TRUE The timer interrupt is currently pending.
* \retval FALSE The timer interrupt is not currently pending.
*/
bool alt_wdog_int_is_pending(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the state of the interrupt of the specified watchdog timer module.
* If the watchdog timer is one of the watchdog timers that can be used in
* general-purpose mode, and if the timer is in general-purpose timer mode,
* returns \b TRUE if the interrupt of the specified general purpose timer
* module is enabled and \b FALSE if disabled. If the timer is not in
* general-purpose timer mode, returns /b TRUE, as watchdog interrupts are
* always enabled.
*
* \param tmr_id
* The timer identifier.
*
* \retval TRUE The timer interrupt is currently pending.
* \retval FALSE The timer interrupt is not currently pending.
*/
bool alt_wdog_int_is_enabled(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Clears the pending status of the interrupt of the specified watchdog
* timer module.
*
*
* \param tmr_id
* The timer identifier.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
*/
ALT_STATUS_CODE alt_wdog_int_clear(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the status of the interrupt of the specified watchdog timer module
* and also clears it. Return \b TRUE if the interrupt of the specified
* general purpose timer module is pending and \b FALSE otherwise.
*
* \param tmr_id
* The timer identifier.
*
* \retval TRUE The timer interrupt was pending.
* \retval FALSE The timer interrupt was not pending.
*/
bool alt_wdog_int_if_pending_clear(ALT_WDOG_TIMER_t tmr_id);
/*! @} */
#if ALTERA_INTERNAL_ONLY_DOCS
/******************************************************************************/
/*! \addtogroup WDOG_MODE_CONF Watchdog Timer Miscellaneous Configuration
*
* This functional group implements setting and reading the current
* timer mode as well as reading the module component code and version code.
*
* @{
*/
#else
/******************************************************************************/
/*! \addtogroup WDOG_MODE_CONF Watchdog Timer Miscellaneous Configuration
*
* This functional group implements setting and reading the current
* timer mode.
*
* @{
*/
#endif
/******************************************************************************/
/*!
* Sets the timeout response mode of the specified watchdog timer. For \b
* ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL or \b ALT_WATCHDOG1_INITIAL, the
* options are to generate a system reset or to generate an interrupt and then
* generate a system reset if the interrupt is not cleared by the next time
* the watchdog timer counter rolls over.\n
* For \b ALT_CPU_WATCHDOG, the options are to trigger an interrupt request (with
* the result set in the interrupt manager) or a reset request (with the
* result set in the reset manager) plus two more options available
* when it is used as a general-purpose timer.
* \param tmr_id
* The timer identifier.
*
* \param type
* \b ALT_WDOG_WARM_RESET - For \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b
* ALT_WATCHDOG0_INITIAL or \b ALT_WATCHDOG1_INITIAL, reset the core
* immediately. \n For \b ALT_CPU_WATCHDOG, the action is
* determined by the current setting in the reset manager.\n\n
* \b ALT_WDOG_INT_THEN_RESET - For \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b
* ALT_WATCHDOG0_INITIAL or \b ALT_WATCHDOG1_INITIAL, raise an interrupt.
* If the interrupt is not cleared before the timer counts down
* to zero again, reset the CPU cores. \n For \b ALT_CPU_WATCHDOG,
* raise an interrupt. \n\n \b ALT_WDOG_TIMER_MODE_ONESHOT - For \b
* ALT_CPU_WATCHDOG, watchdog timer is set to timer mode and one-shot
* operation is selected.\n\n \b ALT_WDOG_TIMER_MODE_FREERUN - For \b
* ALT_CPU_WATCHDOG, watchdog timer is set to timer mode and free-run
* operation is selected.
*
* \retval ALT_E_SUCCESS The operation was successful.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Specified an incorrect timer or an unsupported
* response mode for the specified timer.
*/
ALT_STATUS_CODE alt_wdog_response_mode_set(ALT_WDOG_TIMER_t tmr_id,
ALT_WDOG_RESET_TYPE_t type);
/******************************************************************************/
/*!
* Returns the response mode of the specified timer.
*
* \param tmr_id
* The timer identifier.
*
*
* \retval ALT_WDOG_WARM_RESET
* For \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL or \b
* ALT_WATCHDOG1_INITIAL, reset the core immediately. \n For \b
* ALT_CPU_WATCHDOG, the action is determined by the current setting
* in the reset manager.
* \retval ALT_WDOG_INT_THEN_RESET Raise an interrupt. For \b ALT_WATCHDOG0, \b
* ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL or \b ALT_WATCHDOG1_INITIAL, if
* the interrupt is not cleared before timer wraps around again,
* reset the CPU cores. \n For \b ALT_CPU_WATCHDOG, the action is
* determined by the current setting in the interrupt manager.
* \retval ALT_WDOG_TIMER_MODE_ONESHOT Core watchdog timer is set to timer
* mode and one-shot operation is selected.
* \retval ALT_WDOG_TIMER_MODE_FREERUN Core watchdog timer is set to timer
* mode and free-run operation is selected.
* \retval ALT_E_ERROR The operation failed.
* \retval ALT_E_BAD_ARG Specified an invalid timer.
*/
int32_t alt_wdog_response_mode_get(ALT_WDOG_TIMER_t tmr_id);
#if ALTERA_INTERNAL_ONLY_DOCS
/******************************************************************************/
/*!
* Returns the component code of the watchdog timer module. \n Only valid
* for \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL or \b
* ALT_WATCHDOG1_INITIAL.
*
* \param tmr_id
* The timer identifier.
*
* \retval uint32_t The component code of the module.
* It should be 0x44570120.
*
* \note This is an Altera Internal Only function
*
*/
uint32_t alt_wdog_compcode_get(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/*!
* Returns the version code of the watchdog timer module. \n Only valid for
* \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL or \b
* ALT_WATCHDOG1_INITIAL.
*
*
* \param tmr_id
* The timer identifier.
*
*
* \retval uint32_t The encoded revision number of the module.
*
* \note This is an Altera Internal Only function
*
*/
uint32_t alt_wdog_ver_get(ALT_WDOG_TIMER_t tmr_id);
#else
/******************************************************************************/
/* Returns the component code of the watchdog timer module. Only valid
* for ALT_WATCHDOG0, ALT_WATCHDOG1, ALT_WATCHDOG0_INITIAL or ALT_WATCHDOG1_INITIAL.
*
* This is an Altera Internal Only function
*/
uint32_t alt_wdog_compcode_get(ALT_WDOG_TIMER_t tmr_id);
/******************************************************************************/
/* Returns the version code of the watchdog timer module. Only valid for
* ALT_WATCHDOG0, ALT_WATCHDOG1, ALT_WATCHDOG0_INITIAL or ALT_WATCHDOG1_INITIAL.
*
* This is an Altera Internal Only function
*/
uint32_t alt_wdog_ver_get(ALT_WDOG_TIMER_t tmr_id);
#endif /* ALTERA_INTERNAL_ONLY_DOCS */
/******************************************************************************/
/*! @} */
/*! @} */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_WDOG_H__ */

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HWLIB_H__
#define __HWLIB_H__
#ifdef __cplusplus
#include <cstddef>
#include <cstdbool>
#include <cstdint>
#else /* __cplusplus */
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#endif /* __cplusplus */
#include "alt_hwlibs_ver.h"
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*!
* The type definition for status codes returned by the HWLIB.
*/
typedef int32_t ALT_STATUS_CODE;
/*! Definitions of status codes returned by the HWLIB. */
/*! The operation was successful. */
#define ALT_E_SUCCESS 0
/*! The operation failed. */
#define ALT_E_ERROR (-1)
/*! FPGA configuration error detected.*/
#define ALT_E_FPGA_CFG (-2)
/*! FPGA CRC error detected. */
#define ALT_E_FPGA_CRC (-3)
/*! An error occurred on the FPGA configuration bitstream input source. */
#define ALT_E_FPGA_CFG_STM (-4)
/*! The FPGA is powered off. */
#define ALT_E_FPGA_PWR_OFF (-5)
/*! The SoC does not currently control the FPGA. */
#define ALT_E_FPGA_NO_SOC_CTRL (-6)
/*! The FPGA is not in USER mode. */
#define ALT_E_FPGA_NOT_USER_MODE (-7)
/*! An argument violates a range constraint. */
#define ALT_E_ARG_RANGE (-8)
/*! A bad argument value was passed. */
#define ALT_E_BAD_ARG (-9)
/*! The operation is invalid or illegal. */
#define ALT_E_BAD_OPERATION (-10)
/*! An invalid option was selected. */
#define ALT_E_INV_OPTION (-11)
/*! An operation or response timeout period expired. */
#define ALT_E_TMO (-12)
/*! The argument value is reserved or unavailable. */
#define ALT_E_RESERVED (-13)
/*! A clock is not enabled or violates an operational constraint. */
#define ALT_E_BAD_CLK (-14)
/*! The version ID is invalid. */
#define ALT_E_BAD_VERSION (-15)
/*! The buffer does not contain enough free space for the operation. */
#define ALT_E_BUF_OVF (-20)
/*!
* Indicates a FALSE condition.
*/
#define ALT_E_FALSE (0)
/*!
* Indicates a TRUE condition.
*/
#define ALT_E_TRUE (1)
/* Note, additional positive status codes may be defined to return
* a TRUE condition with additional information */
/* Some other useful definitions */
/*!
* Specifies the current major and minor revision of the HWLibs. The
* MS four decimal digits specify the Altera ACDS release number, the
* LS two decimal digits specify minor revisions of the HWLibs, if any.
*
* A typical use is:
* \code
* #if ALTERA_HWLIBS_VERSION_CODE >= ALT_HWLIBS_VERSION(13, 1, 0)
* \endcode
* for a dependency on the major or minor ACDS revision
* or
* \code
* #if ALTERA_HWLIBS_VERSION_CODE == ALT_HWLIBS_VERSION(13, 0, 12)
* \endcode
* for a dependency on the hwlibs revision
*
*/
#define ALT_HWLIBS_VERSION(a,b,c) (((a)*10000)+((b)*100)+(c))
#define ALTERA_HWLIBS_VERSION_CODE ALT_HWLIBS_VERSION(ALTERA_ACDS_MAJOR_REV, \
ALTERA_ACDS_MINOR_REV, ALTERA_HWLIBS_REV)
/*!
* Allow some parts of the documentation to be hidden by setting to zero
*/
#define ALTERA_INTERNAL_ONLY_DOCS 1
/*!
* Provide base address of MPU address space
*/
#ifndef ALT_HPS_ADDR
#define ALT_HPS_ADDR 0
#endif
/*!
* These constants are sometimes useful:
*/
#define ALT_MILLISECS_IN_A_SEC 1000
#define ALT_MICROSECS_IN_A_SEC 1000000
#define ALT_NANOSECS_IN_A_SEC 1000000000
#define ALT_TWO_TO_POW0 (1)
#define ALT_TWO_TO_POW1 (1<<1)
#define ALT_TWO_TO_POW2 (1<<2)
#define ALT_TWO_TO_POW3 (1<<3)
#define ALT_TWO_TO_POW4 (1<<4)
#define ALT_TWO_TO_POW5 (1<<5)
#define ALT_TWO_TO_POW6 (1<<6)
#define ALT_TWO_TO_POW7 (1<<7)
#define ALT_TWO_TO_POW8 (1<<8)
#define ALT_TWO_TO_POW9 (1<<9)
#define ALT_TWO_TO_POW10 (1<<10)
#define ALT_TWO_TO_POW11 (1<<11)
#define ALT_TWO_TO_POW12 (1<<12)
#define ALT_TWO_TO_POW13 (1<<13)
#define ALT_TWO_TO_POW14 (1<<14)
#define ALT_TWO_TO_POW15 (1<<15)
#define ALT_TWO_TO_POW16 (1<<16)
#define ALT_TWO_TO_POW17 (1<<17)
#define ALT_TWO_TO_POW18 (1<<18)
#define ALT_TWO_TO_POW19 (1<<19)
#define ALT_TWO_TO_POW20 (1<<20)
#define ALT_TWO_TO_POW21 (1<<21)
#define ALT_TWO_TO_POW22 (1<<22)
#define ALT_TWO_TO_POW23 (1<<23)
#define ALT_TWO_TO_POW24 (1<<24)
#define ALT_TWO_TO_POW25 (1<<25)
#define ALT_TWO_TO_POW26 (1<<26)
#define ALT_TWO_TO_POW27 (1<<27)
#define ALT_TWO_TO_POW28 (1<<28)
#define ALT_TWO_TO_POW29 (1<<29)
#define ALT_TWO_TO_POW30 (1<<30)
#define ALT_TWO_TO_POW31 (1<<31)
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __HWLIB_H__ */

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/*******************************************************************************
* *
* Copyright 2013 Altera Corporation. All Rights Reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following conditions are met: *
* *
* 1. Redistributions of source code must retain the above copyright notice, *
* this list of conditions and the following disclaimer. *
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, *
* this list of conditions and the following disclaimer in the documentation *
* and/or other materials provided with the distribution. *
* *
* 3. The name of the author may not be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
* *
*******************************************************************************/
/* Altera - ALT_DAP */
#ifndef __ALTERA_ALT_DAP_H__
#define __ALTERA_ALT_DAP_H__
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*
* Component : DAP Module Address Space - ALT_DAP
* DAP Module Address Space
*
* Address space allocated to the DAP. For detailed information about the use of
* this address space,
* [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/index.html]click
* here[/url] to access the ARM documentation for the DAP.
*
*/
/*
* Register : Empty - reg
*
* Placeholder
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------
* [31:0] | RW | Unknown | Empty
*
*/
/*
* Field : Empty - fld
*
* Placeholder
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_DAP_REG_FLD register field. */
#define ALT_DAP_REG_FLD_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_DAP_REG_FLD register field. */
#define ALT_DAP_REG_FLD_MSB 31
/* The width in bits of the ALT_DAP_REG_FLD register field. */
#define ALT_DAP_REG_FLD_WIDTH 32
/* The mask used to set the ALT_DAP_REG_FLD register field value. */
#define ALT_DAP_REG_FLD_SET_MSK 0xffffffff
/* The mask used to clear the ALT_DAP_REG_FLD register field value. */
#define ALT_DAP_REG_FLD_CLR_MSK 0x00000000
/* The reset value of the ALT_DAP_REG_FLD register field is UNKNOWN. */
#define ALT_DAP_REG_FLD_RESET 0x0
/* Extracts the ALT_DAP_REG_FLD field value from a register. */
#define ALT_DAP_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_DAP_REG_FLD register field value suitable for setting the register. */
#define ALT_DAP_REG_FLD_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_DAP_REG.
*/
struct ALT_DAP_REG_s
{
uint32_t fld : 32; /* Empty */
};
/* The typedef declaration for register ALT_DAP_REG. */
typedef volatile struct ALT_DAP_REG_s ALT_DAP_REG_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_DAP_REG register from the beginning of the component. */
#define ALT_DAP_REG_OFST 0x0
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register group ALT_DAP.
*/
struct ALT_DAP_s
{
volatile ALT_DAP_REG_t reg; /* ALT_DAP_REG */
};
/* The typedef declaration for register group ALT_DAP. */
typedef volatile struct ALT_DAP_s ALT_DAP_t;
/* The struct declaration for the raw register contents of register group ALT_DAP. */
struct ALT_DAP_raw_s
{
volatile uint32_t reg; /* ALT_DAP_REG */
};
/* The typedef declaration for the raw register contents of register group ALT_DAP. */
typedef volatile struct ALT_DAP_raw_s ALT_DAP_raw_t;
#endif /* __ASSEMBLY__ */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_ALT_DAP_H__ */

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FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_dmanonsecure.h
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/*******************************************************************************
* *
* Copyright 2013 Altera Corporation. All Rights Reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following conditions are met: *
* *
* 1. Redistributions of source code must retain the above copyright notice, *
* this list of conditions and the following disclaimer. *
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, *
* this list of conditions and the following disclaimer in the documentation *
* and/or other materials provided with the distribution. *
* *
* 3. The name of the author may not be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
* *
*******************************************************************************/
/* Altera - ALT_DMANONSECURE */
#ifndef __ALTERA_ALT_DMANONSECURE_H__
#define __ALTERA_ALT_DMANONSECURE_H__
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*
* Component : nonsecure DMA Module Address Space - ALT_DMANONSECURE
* nonsecure DMA Module Address Space
*
* Address space allocated to the nonsecure DMA. For detailed information about the
* use of this address space,
* [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424b/index.html]click
* here[/url] to access the ARM documentation for the DMA-330.
*
*/
/*
* Register : Empty - reg
*
* Placeholder
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------
* [31:0] | RW | Unknown | Empty
*
*/
/*
* Field : Empty - fld
*
* Placeholder
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_DMANONSECURE_REG_FLD register field. */
#define ALT_DMANONSECURE_REG_FLD_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_DMANONSECURE_REG_FLD register field. */
#define ALT_DMANONSECURE_REG_FLD_MSB 31
/* The width in bits of the ALT_DMANONSECURE_REG_FLD register field. */
#define ALT_DMANONSECURE_REG_FLD_WIDTH 32
/* The mask used to set the ALT_DMANONSECURE_REG_FLD register field value. */
#define ALT_DMANONSECURE_REG_FLD_SET_MSK 0xffffffff
/* The mask used to clear the ALT_DMANONSECURE_REG_FLD register field value. */
#define ALT_DMANONSECURE_REG_FLD_CLR_MSK 0x00000000
/* The reset value of the ALT_DMANONSECURE_REG_FLD register field is UNKNOWN. */
#define ALT_DMANONSECURE_REG_FLD_RESET 0x0
/* Extracts the ALT_DMANONSECURE_REG_FLD field value from a register. */
#define ALT_DMANONSECURE_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_DMANONSECURE_REG_FLD register field value suitable for setting the register. */
#define ALT_DMANONSECURE_REG_FLD_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_DMANONSECURE_REG.
*/
struct ALT_DMANONSECURE_REG_s
{
uint32_t fld : 32; /* Empty */
};
/* The typedef declaration for register ALT_DMANONSECURE_REG. */
typedef volatile struct ALT_DMANONSECURE_REG_s ALT_DMANONSECURE_REG_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_DMANONSECURE_REG register from the beginning of the component. */
#define ALT_DMANONSECURE_REG_OFST 0x0
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register group ALT_DMANONSECURE.
*/
struct ALT_DMANONSECURE_s
{
volatile ALT_DMANONSECURE_REG_t reg; /* ALT_DMANONSECURE_REG */
};
/* The typedef declaration for register group ALT_DMANONSECURE. */
typedef volatile struct ALT_DMANONSECURE_s ALT_DMANONSECURE_t;
/* The struct declaration for the raw register contents of register group ALT_DMANONSECURE. */
struct ALT_DMANONSECURE_raw_s
{
volatile uint32_t reg; /* ALT_DMANONSECURE_REG */
};
/* The typedef declaration for the raw register contents of register group ALT_DMANONSECURE. */
typedef volatile struct ALT_DMANONSECURE_raw_s ALT_DMANONSECURE_raw_t;
#endif /* __ASSEMBLY__ */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_ALT_DMANONSECURE_H__ */

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/*******************************************************************************
* *
* Copyright 2013 Altera Corporation. All Rights Reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following conditions are met: *
* *
* 1. Redistributions of source code must retain the above copyright notice, *
* this list of conditions and the following disclaimer. *
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, *
* this list of conditions and the following disclaimer in the documentation *
* and/or other materials provided with the distribution. *
* *
* 3. The name of the author may not be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
* *
*******************************************************************************/
/* Altera - ALT_DMASECURE */
#ifndef __ALTERA_ALT_DMASECURE_H__
#define __ALTERA_ALT_DMASECURE_H__
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*
* Component : secure DMA Module Address Space - ALT_DMASECURE
* secure DMA Module Address Space
*
* Address space allocated to the secure DMA. For detailed information about the
* use of this address space,
* [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424b/index.html]click
* here[/url] to access the ARM documentation for the DMA-330.
*
*/
/*
* Register : Empty - reg
*
* Placeholder
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------
* [31:0] | RW | Unknown | Empty
*
*/
/*
* Field : Empty - fld
*
* Placeholder
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_DMASECURE_REG_FLD register field. */
#define ALT_DMASECURE_REG_FLD_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_DMASECURE_REG_FLD register field. */
#define ALT_DMASECURE_REG_FLD_MSB 31
/* The width in bits of the ALT_DMASECURE_REG_FLD register field. */
#define ALT_DMASECURE_REG_FLD_WIDTH 32
/* The mask used to set the ALT_DMASECURE_REG_FLD register field value. */
#define ALT_DMASECURE_REG_FLD_SET_MSK 0xffffffff
/* The mask used to clear the ALT_DMASECURE_REG_FLD register field value. */
#define ALT_DMASECURE_REG_FLD_CLR_MSK 0x00000000
/* The reset value of the ALT_DMASECURE_REG_FLD register field is UNKNOWN. */
#define ALT_DMASECURE_REG_FLD_RESET 0x0
/* Extracts the ALT_DMASECURE_REG_FLD field value from a register. */
#define ALT_DMASECURE_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_DMASECURE_REG_FLD register field value suitable for setting the register. */
#define ALT_DMASECURE_REG_FLD_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_DMASECURE_REG.
*/
struct ALT_DMASECURE_REG_s
{
uint32_t fld : 32; /* Empty */
};
/* The typedef declaration for register ALT_DMASECURE_REG. */
typedef volatile struct ALT_DMASECURE_REG_s ALT_DMASECURE_REG_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_DMASECURE_REG register from the beginning of the component. */
#define ALT_DMASECURE_REG_OFST 0x0
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register group ALT_DMASECURE.
*/
struct ALT_DMASECURE_s
{
volatile ALT_DMASECURE_REG_t reg; /* ALT_DMASECURE_REG */
};
/* The typedef declaration for register group ALT_DMASECURE. */
typedef volatile struct ALT_DMASECURE_s ALT_DMASECURE_t;
/* The struct declaration for the raw register contents of register group ALT_DMASECURE. */
struct ALT_DMASECURE_raw_s
{
volatile uint32_t reg; /* ALT_DMASECURE_REG */
};
/* The typedef declaration for the raw register contents of register group ALT_DMASECURE. */
typedef volatile struct ALT_DMASECURE_raw_s ALT_DMASECURE_raw_t;
#endif /* __ASSEMBLY__ */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_ALT_DMASECURE_H__ */

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/*******************************************************************************
* *
* Copyright 2013 Altera Corporation. All Rights Reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following conditions are met: *
* *
* 1. Redistributions of source code must retain the above copyright notice, *
* this list of conditions and the following disclaimer. *
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, *
* this list of conditions and the following disclaimer in the documentation *
* and/or other materials provided with the distribution. *
* *
* 3. The name of the author may not be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
* *
*******************************************************************************/
/* Altera - ALT_FPGAMGRDATA */
#ifndef __ALTERA_ALT_FPGAMGRDATA_H__
#define __ALTERA_ALT_FPGAMGRDATA_H__
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*
* Component : FPGA Manager Module Configuration Data - ALT_FPGAMGRDATA
* FPGA Manager Module Configuration Data
*
* Registers in the FPGA Manager module accessible via its AXI slave
*
*/
/*
* Register : Write Data Register - data
*
* Used to send configuration image to FPGA.
*
* The DATA register accepts 4 bytes of the configuration image on each write. The
* configuration image byte-stream is converted into a 4-byte word with little-
* endian ordering. If the configuration image is not an integer multiple of 4
* bytes, software should pad the configuration image with extra zero bytes to make
* it an integer multiple of 4 bytes.
*
* The FPGA Manager converts the DATA to 16 bits wide when writing CB.DATA for
* partial reconfiguration.
*
* The FPGA Manager waits to transmit the data to the CB until the FPGA is able to
* receive it. For a full configuration, the FPGA Manager waits until the FPGA
* exits the Reset Phase and enters the Configuration Phase. For a partial
* reconfiguration, the FPGA Manager waits until the CB.PR_READY signal indicates
* that the FPGA is ready.
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:-----------------
* [31:0] | RW | Unknown | Write Data Value
*
*/
/*
* Field : Write Data Value - value
*
* Accepts configuration image to be sent to CB when the HPS configures the FPGA.
* Software normally just writes this register. If software reads this register, it
* returns the value 0 and replies with an AXI SLVERR error.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_FPGAMGRDATA_DATA_VALUE register field. */
#define ALT_FPGAMGRDATA_DATA_VALUE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_FPGAMGRDATA_DATA_VALUE register field. */
#define ALT_FPGAMGRDATA_DATA_VALUE_MSB 31
/* The width in bits of the ALT_FPGAMGRDATA_DATA_VALUE register field. */
#define ALT_FPGAMGRDATA_DATA_VALUE_WIDTH 32
/* The mask used to set the ALT_FPGAMGRDATA_DATA_VALUE register field value. */
#define ALT_FPGAMGRDATA_DATA_VALUE_SET_MSK 0xffffffff
/* The mask used to clear the ALT_FPGAMGRDATA_DATA_VALUE register field value. */
#define ALT_FPGAMGRDATA_DATA_VALUE_CLR_MSK 0x00000000
/* The reset value of the ALT_FPGAMGRDATA_DATA_VALUE register field is UNKNOWN. */
#define ALT_FPGAMGRDATA_DATA_VALUE_RESET 0x0
/* Extracts the ALT_FPGAMGRDATA_DATA_VALUE field value from a register. */
#define ALT_FPGAMGRDATA_DATA_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_FPGAMGRDATA_DATA_VALUE register field value suitable for setting the register. */
#define ALT_FPGAMGRDATA_DATA_VALUE_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_FPGAMGRDATA_DATA.
*/
struct ALT_FPGAMGRDATA_DATA_s
{
uint32_t value : 32; /* Write Data Value */
};
/* The typedef declaration for register ALT_FPGAMGRDATA_DATA. */
typedef volatile struct ALT_FPGAMGRDATA_DATA_s ALT_FPGAMGRDATA_DATA_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_FPGAMGRDATA_DATA register from the beginning of the component. */
#define ALT_FPGAMGRDATA_DATA_OFST 0x0
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register group ALT_FPGAMGRDATA.
*/
struct ALT_FPGAMGRDATA_s
{
volatile ALT_FPGAMGRDATA_DATA_t data; /* ALT_FPGAMGRDATA_DATA */
};
/* The typedef declaration for register group ALT_FPGAMGRDATA. */
typedef volatile struct ALT_FPGAMGRDATA_s ALT_FPGAMGRDATA_t;
/* The struct declaration for the raw register contents of register group ALT_FPGAMGRDATA. */
struct ALT_FPGAMGRDATA_raw_s
{
volatile uint32_t data; /* ALT_FPGAMGRDATA_DATA */
};
/* The typedef declaration for the raw register contents of register group ALT_FPGAMGRDATA. */
typedef volatile struct ALT_FPGAMGRDATA_raw_s ALT_FPGAMGRDATA_raw_t;
#endif /* __ASSEMBLY__ */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_ALT_FPGAMGRDATA_H__ */

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/*******************************************************************************
* *
* Copyright 2013 Altera Corporation. All Rights Reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following conditions are met: *
* *
* 1. Redistributions of source code must retain the above copyright notice, *
* this list of conditions and the following disclaimer. *
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, *
* this list of conditions and the following disclaimer in the documentation *
* and/or other materials provided with the distribution. *
* *
* 3. The name of the author may not be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
* *
*******************************************************************************/
/* Altera - ALT_LWFPGASLVS */
#ifndef __ALTERA_ALT_LWFPGASLVS_H__
#define __ALTERA_ALT_LWFPGASLVS_H__
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*
* Component : FPGA Slaves Accessed Via Lightweight HPS2FPGA AXI Bridge - ALT_LWFPGASLVS
* FPGA Slaves Accessed Via Lightweight HPS2FPGA AXI Bridge
*
*
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_ALT_LWFPGASLVS_H__ */

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/*******************************************************************************
* *
* Copyright 2013 Altera Corporation. All Rights Reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following conditions are met: *
* *
* 1. Redistributions of source code must retain the above copyright notice, *
* this list of conditions and the following disclaimer. *
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, *
* this list of conditions and the following disclaimer in the documentation *
* and/or other materials provided with the distribution. *
* *
* 3. The name of the author may not be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
* *
*******************************************************************************/
/* Altera - ALT_MPUL2 */
#ifndef __ALTERA_ALT_MPUL2_H__
#define __ALTERA_ALT_MPUL2_H__
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*
* Component : MPU L2 cache controller Module Address Space - ALT_MPUL2
* MPU L2 cache controller Module Address Space
*
* Address space allocated to the MPU L2 cache controller. For detailed information
* about the use of this address space,
* [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246e/index.html]click
* here[/url] to access the ARM documentation for the L2C-301.
*
*/
/*
* Register : Empty - reg
*
* Placeholder
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------
* [31:0] | RW | Unknown | Empty
*
*/
/*
* Field : Empty - fld
*
* Placeholder
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_MPUL2_REG_FLD register field. */
#define ALT_MPUL2_REG_FLD_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_MPUL2_REG_FLD register field. */
#define ALT_MPUL2_REG_FLD_MSB 31
/* The width in bits of the ALT_MPUL2_REG_FLD register field. */
#define ALT_MPUL2_REG_FLD_WIDTH 32
/* The mask used to set the ALT_MPUL2_REG_FLD register field value. */
#define ALT_MPUL2_REG_FLD_SET_MSK 0xffffffff
/* The mask used to clear the ALT_MPUL2_REG_FLD register field value. */
#define ALT_MPUL2_REG_FLD_CLR_MSK 0x00000000
/* The reset value of the ALT_MPUL2_REG_FLD register field is UNKNOWN. */
#define ALT_MPUL2_REG_FLD_RESET 0x0
/* Extracts the ALT_MPUL2_REG_FLD field value from a register. */
#define ALT_MPUL2_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_MPUL2_REG_FLD register field value suitable for setting the register. */
#define ALT_MPUL2_REG_FLD_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_MPUL2_REG.
*/
struct ALT_MPUL2_REG_s
{
uint32_t fld : 32; /* Empty */
};
/* The typedef declaration for register ALT_MPUL2_REG. */
typedef volatile struct ALT_MPUL2_REG_s ALT_MPUL2_REG_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_MPUL2_REG register from the beginning of the component. */
#define ALT_MPUL2_REG_OFST 0x0
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register group ALT_MPUL2.
*/
struct ALT_MPUL2_s
{
volatile ALT_MPUL2_REG_t reg; /* ALT_MPUL2_REG */
};
/* The typedef declaration for register group ALT_MPUL2. */
typedef volatile struct ALT_MPUL2_s ALT_MPUL2_t;
/* The struct declaration for the raw register contents of register group ALT_MPUL2. */
struct ALT_MPUL2_raw_s
{
volatile uint32_t reg; /* ALT_MPUL2_REG */
};
/* The typedef declaration for the raw register contents of register group ALT_MPUL2. */
typedef volatile struct ALT_MPUL2_raw_s ALT_MPUL2_raw_t;
#endif /* __ASSEMBLY__ */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_ALT_MPUL2_H__ */

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/*******************************************************************************
* *
* Copyright 2013 Altera Corporation. All Rights Reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following conditions are met: *
* *
* 1. Redistributions of source code must retain the above copyright notice, *
* this list of conditions and the following disclaimer. *
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, *
* this list of conditions and the following disclaimer in the documentation *
* and/or other materials provided with the distribution. *
* *
* 3. The name of the author may not be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
* *
*******************************************************************************/
/* Altera - ALT_MPUSCU */
#ifndef __ALTERA_ALT_MPUSCU_H__
#define __ALTERA_ALT_MPUSCU_H__
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*
* Component : MPU SCU Module Address Space - ALT_MPUSCU
* MPU SCU Module Address Space
*
* Address space allocated to the MPU SCU. For detailed information about the use
* of this address space,
* [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407f/index.html]click
* here[/url] to access the ARM documentation for the Cortex-A9 MPCore.
*
*/
/*
* Register : Empty - reg
*
* Placeholder
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------
* [31:0] | RW | Unknown | Empty
*
*/
/*
* Field : Empty - fld
*
* Placeholder
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_MPUSCU_REG_FLD register field. */
#define ALT_MPUSCU_REG_FLD_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_MPUSCU_REG_FLD register field. */
#define ALT_MPUSCU_REG_FLD_MSB 31
/* The width in bits of the ALT_MPUSCU_REG_FLD register field. */
#define ALT_MPUSCU_REG_FLD_WIDTH 32
/* The mask used to set the ALT_MPUSCU_REG_FLD register field value. */
#define ALT_MPUSCU_REG_FLD_SET_MSK 0xffffffff
/* The mask used to clear the ALT_MPUSCU_REG_FLD register field value. */
#define ALT_MPUSCU_REG_FLD_CLR_MSK 0x00000000
/* The reset value of the ALT_MPUSCU_REG_FLD register field is UNKNOWN. */
#define ALT_MPUSCU_REG_FLD_RESET 0x0
/* Extracts the ALT_MPUSCU_REG_FLD field value from a register. */
#define ALT_MPUSCU_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_MPUSCU_REG_FLD register field value suitable for setting the register. */
#define ALT_MPUSCU_REG_FLD_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_MPUSCU_REG.
*/
struct ALT_MPUSCU_REG_s
{
uint32_t fld : 32; /* Empty */
};
/* The typedef declaration for register ALT_MPUSCU_REG. */
typedef volatile struct ALT_MPUSCU_REG_s ALT_MPUSCU_REG_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_MPUSCU_REG register from the beginning of the component. */
#define ALT_MPUSCU_REG_OFST 0x0
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register group ALT_MPUSCU.
*/
struct ALT_MPUSCU_s
{
volatile ALT_MPUSCU_REG_t reg; /* ALT_MPUSCU_REG */
};
/* The typedef declaration for register group ALT_MPUSCU. */
typedef volatile struct ALT_MPUSCU_s ALT_MPUSCU_t;
/* The struct declaration for the raw register contents of register group ALT_MPUSCU. */
struct ALT_MPUSCU_raw_s
{
volatile uint32_t reg; /* ALT_MPUSCU_REG */
};
/* The typedef declaration for the raw register contents of register group ALT_MPUSCU. */
typedef volatile struct ALT_MPUSCU_raw_s ALT_MPUSCU_raw_t;
#endif /* __ASSEMBLY__ */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_ALT_MPUSCU_H__ */

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/*******************************************************************************
* *
* Copyright 2013 Altera Corporation. All Rights Reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following conditions are met: *
* *
* 1. Redistributions of source code must retain the above copyright notice, *
* this list of conditions and the following disclaimer. *
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, *
* this list of conditions and the following disclaimer in the documentation *
* and/or other materials provided with the distribution. *
* *
* 3. The name of the author may not be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
* *
*******************************************************************************/
/* Altera - ALT_NANDDATA */
#ifndef __ALTERA_ALT_NANDDATA_H__
#define __ALTERA_ALT_NANDDATA_H__
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*
* Component : NAND Controller Module Data (AXI Slave) - ALT_NANDDATA
* NAND Controller Module Data (AXI Slave)
*
*
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_ALT_NANDDATA_H__ */

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/*******************************************************************************
* *
* Copyright 2013 Altera Corporation. All Rights Reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following conditions are met: *
* *
* 1. Redistributions of source code must retain the above copyright notice, *
* this list of conditions and the following disclaimer. *
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, *
* this list of conditions and the following disclaimer in the documentation *
* and/or other materials provided with the distribution. *
* *
* 3. The name of the author may not be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
* *
*******************************************************************************/
/* Altera - ALT_OCRAM */
#ifndef __ALTERA_ALT_OCRAM_H__
#define __ALTERA_ALT_OCRAM_H__
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*
* Component : On-chip RAM Module - ALT_OCRAM
* On-chip RAM Module
*
*
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_ALT_OCRAM_H__ */

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/*******************************************************************************
* *
* Copyright 2013 Altera Corporation. All Rights Reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following conditions are met: *
* *
* 1. Redistributions of source code must retain the above copyright notice, *
* this list of conditions and the following disclaimer. *
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, *
* this list of conditions and the following disclaimer in the documentation *
* and/or other materials provided with the distribution. *
* *
* 3. The name of the author may not be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
* *
*******************************************************************************/
/* Altera - ALT_QSPIDATA */
#ifndef __ALTERA_ALT_QSPIDATA_H__
#define __ALTERA_ALT_QSPIDATA_H__
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*
* Component : QSPI Flash Module Data (AHB Slave) - ALT_QSPIDATA
* QSPI Flash Module Data (AHB Slave)
*
*
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_ALT_QSPIDATA_H__ */

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/*******************************************************************************
* *
* Copyright 2013 Altera Corporation. All Rights Reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following conditions are met: *
* *
* 1. Redistributions of source code must retain the above copyright notice, *
* this list of conditions and the following disclaimer. *
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, *
* this list of conditions and the following disclaimer in the documentation *
* and/or other materials provided with the distribution. *
* *
* 3. The name of the author may not be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
* *
*******************************************************************************/
/* Altera - ALT_ROM */
#ifndef __ALTERA_ALT_ROM_H__
#define __ALTERA_ALT_ROM_H__
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*
* Component : Boot ROM Module - ALT_ROM
* Boot ROM Module
*
*
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_ALT_ROM_H__ */

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/*******************************************************************************
* *
* Copyright 2013 Altera Corporation. All Rights Reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following conditions are met: *
* *
* 1. Redistributions of source code must retain the above copyright notice, *
* this list of conditions and the following disclaimer. *
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, *
* this list of conditions and the following disclaimer in the documentation *
* and/or other materials provided with the distribution. *
* *
* 3. The name of the author may not be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
* *
*******************************************************************************/
/* Altera - ALT_SCANMGR */
#ifndef __ALTERA_ALT_SCANMGR_H__
#define __ALTERA_ALT_SCANMGR_H__
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*
* Component : Scan Manager Module Registers - ALT_SCANMGR
* Scan Manager Module Registers
*
* Registers in the Scan Manager module.
*
* These registers are implemented by an ARM JTAG-AP module from the ARM DAP. Some
* register and field names have been changed to match the usage in the Scan
* Manager. If modified, the corresponding names from the ARM documentation are
* provided. Only registers and fields that are relevant to the JTAG-AP use in the
* Scan Manager are listed.
*
*/
/*
* Register : Control/Status Word Register - stat
*
* Consist of control bit and status information.
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:--------|:-------------------------------------
* [0] | ??? | 0x0 | *UNDEFINED*
* [1] | RW | 0x0 | Reset output to the FPGA JTAG
* [2] | ??? | 0x0 | *UNDEFINED*
* [3] | R | Unknown | Ignore
* [23:4] | ??? | 0x0 | *UNDEFINED*
* [26:24] | R | 0x0 | Response FIFO Outstanding Byte Count
* [27] | ??? | 0x0 | *UNDEFINED*
* [30:28] | R | 0x0 | Command FIFO Outstanding Byte Count
* [31] | R | 0x0 | Scan-Chain Engine Active
*
*/
/*
* Field : Reset output to the FPGA JTAG - trst
*
* Specifies the value of the nTRST signal driven to the FPGA JTAG only. The FPGA
* JTAG scan-chain must be enabled via the EN register to drive the value specified
* in this field. The nTRST signal is driven with the inverted value of this
* field.The nTRST signal is active low so, when this bit is set to 1, FPGA JTAG is
* reset.
*
* The name of this field in ARM documentation is TRST_OUT.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:-------------------------------------------------
* ALT_SCANMGR_STAT_TRST_E_DONT_RST_FPGA_JTAG | 0x0 | Don't reset FPGA JTAG.
* ALT_SCANMGR_STAT_TRST_E_RST_FPGA_JTAG | 0x1 | Reset FPGA JTAG. Must have the FPGA JTAG scan-
* : | | chain enabled in the EN register to take effect.
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_SCANMGR_STAT_TRST
*
* Don't reset FPGA JTAG.
*/
#define ALT_SCANMGR_STAT_TRST_E_DONT_RST_FPGA_JTAG 0x0
/*
* Enumerated value for register field ALT_SCANMGR_STAT_TRST
*
* Reset FPGA JTAG. Must have the FPGA JTAG scan-chain enabled in the EN register
* to take effect.
*/
#define ALT_SCANMGR_STAT_TRST_E_RST_FPGA_JTAG 0x1
/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_STAT_TRST register field. */
#define ALT_SCANMGR_STAT_TRST_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_STAT_TRST register field. */
#define ALT_SCANMGR_STAT_TRST_MSB 1
/* The width in bits of the ALT_SCANMGR_STAT_TRST register field. */
#define ALT_SCANMGR_STAT_TRST_WIDTH 1
/* The mask used to set the ALT_SCANMGR_STAT_TRST register field value. */
#define ALT_SCANMGR_STAT_TRST_SET_MSK 0x00000002
/* The mask used to clear the ALT_SCANMGR_STAT_TRST register field value. */
#define ALT_SCANMGR_STAT_TRST_CLR_MSK 0xfffffffd
/* The reset value of the ALT_SCANMGR_STAT_TRST register field. */
#define ALT_SCANMGR_STAT_TRST_RESET 0x0
/* Extracts the ALT_SCANMGR_STAT_TRST field value from a register. */
#define ALT_SCANMGR_STAT_TRST_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_SCANMGR_STAT_TRST register field value suitable for setting the register. */
#define ALT_SCANMGR_STAT_TRST_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : Ignore - ignore
*
* Ignore this field. Its value is undefined (may be 0 or 1).
*
* The name of this field in ARM documentation is PORTCONNECTED.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_STAT_IGNORE register field. */
#define ALT_SCANMGR_STAT_IGNORE_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_STAT_IGNORE register field. */
#define ALT_SCANMGR_STAT_IGNORE_MSB 3
/* The width in bits of the ALT_SCANMGR_STAT_IGNORE register field. */
#define ALT_SCANMGR_STAT_IGNORE_WIDTH 1
/* The mask used to set the ALT_SCANMGR_STAT_IGNORE register field value. */
#define ALT_SCANMGR_STAT_IGNORE_SET_MSK 0x00000008
/* The mask used to clear the ALT_SCANMGR_STAT_IGNORE register field value. */
#define ALT_SCANMGR_STAT_IGNORE_CLR_MSK 0xfffffff7
/* The reset value of the ALT_SCANMGR_STAT_IGNORE register field is UNKNOWN. */
#define ALT_SCANMGR_STAT_IGNORE_RESET 0x0
/* Extracts the ALT_SCANMGR_STAT_IGNORE field value from a register. */
#define ALT_SCANMGR_STAT_IGNORE_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_SCANMGR_STAT_IGNORE register field value suitable for setting the register. */
#define ALT_SCANMGR_STAT_IGNORE_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : Response FIFO Outstanding Byte Count - rfifocnt
*
* Response FIFO outstanding byte count. Returns the number of bytes of response
* data available in the Response FIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_STAT_RFIFOCNT register field. */
#define ALT_SCANMGR_STAT_RFIFOCNT_LSB 24
/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_STAT_RFIFOCNT register field. */
#define ALT_SCANMGR_STAT_RFIFOCNT_MSB 26
/* The width in bits of the ALT_SCANMGR_STAT_RFIFOCNT register field. */
#define ALT_SCANMGR_STAT_RFIFOCNT_WIDTH 3
/* The mask used to set the ALT_SCANMGR_STAT_RFIFOCNT register field value. */
#define ALT_SCANMGR_STAT_RFIFOCNT_SET_MSK 0x07000000
/* The mask used to clear the ALT_SCANMGR_STAT_RFIFOCNT register field value. */
#define ALT_SCANMGR_STAT_RFIFOCNT_CLR_MSK 0xf8ffffff
/* The reset value of the ALT_SCANMGR_STAT_RFIFOCNT register field. */
#define ALT_SCANMGR_STAT_RFIFOCNT_RESET 0x0
/* Extracts the ALT_SCANMGR_STAT_RFIFOCNT field value from a register. */
#define ALT_SCANMGR_STAT_RFIFOCNT_GET(value) (((value) & 0x07000000) >> 24)
/* Produces a ALT_SCANMGR_STAT_RFIFOCNT register field value suitable for setting the register. */
#define ALT_SCANMGR_STAT_RFIFOCNT_SET(value) (((value) << 24) & 0x07000000)
/*
* Field : Command FIFO Outstanding Byte Count - wfifocnt
*
* Command FIFO outstanding byte count. Returns the number of command bytes held in
* the Command FIFO that have yet to be processed by the Scan-Chain Engine.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_STAT_WFIFOCNT register field. */
#define ALT_SCANMGR_STAT_WFIFOCNT_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_STAT_WFIFOCNT register field. */
#define ALT_SCANMGR_STAT_WFIFOCNT_MSB 30
/* The width in bits of the ALT_SCANMGR_STAT_WFIFOCNT register field. */
#define ALT_SCANMGR_STAT_WFIFOCNT_WIDTH 3
/* The mask used to set the ALT_SCANMGR_STAT_WFIFOCNT register field value. */
#define ALT_SCANMGR_STAT_WFIFOCNT_SET_MSK 0x70000000
/* The mask used to clear the ALT_SCANMGR_STAT_WFIFOCNT register field value. */
#define ALT_SCANMGR_STAT_WFIFOCNT_CLR_MSK 0x8fffffff
/* The reset value of the ALT_SCANMGR_STAT_WFIFOCNT register field. */
#define ALT_SCANMGR_STAT_WFIFOCNT_RESET 0x0
/* Extracts the ALT_SCANMGR_STAT_WFIFOCNT field value from a register. */
#define ALT_SCANMGR_STAT_WFIFOCNT_GET(value) (((value) & 0x70000000) >> 28)
/* Produces a ALT_SCANMGR_STAT_WFIFOCNT register field value suitable for setting the register. */
#define ALT_SCANMGR_STAT_WFIFOCNT_SET(value) (((value) << 28) & 0x70000000)
/*
* Field : Scan-Chain Engine Active - active
*
* Indicates if the Scan-Chain Engine is processing commands from the Command FIFO
* or not.
*
* The Scan-Chain Engine is only guaranteed to be inactive if both the ACTIVE and
* WFIFOCNT fields are zero.
*
* The name of this field in ARM documentation is SERACTV.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------------------------
* ALT_SCANMGR_STAT_ACT_E_POSSIBLY_INACT | 0x0 | The Scan-Chain Engine may or may not be
* : | | processing commands from the Command FIFO. The
* : | | Scan-Chain Engine is only guaranteed to be
* : | | inactive if both this ACTIVE field and the
* : | | WFIFOCNT fields are both zero.
* ALT_SCANMGR_STAT_ACT_E_ACT | 0x1 | The Scan-Chain Engine is processing commands
* : | | from the Command FIFO.
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_SCANMGR_STAT_ACT
*
* The Scan-Chain Engine may or may not be processing commands from the Command
* FIFO. The Scan-Chain Engine is only guaranteed to be inactive if both this
* ACTIVE field and the WFIFOCNT fields are both zero.
*/
#define ALT_SCANMGR_STAT_ACT_E_POSSIBLY_INACT 0x0
/*
* Enumerated value for register field ALT_SCANMGR_STAT_ACT
*
* The Scan-Chain Engine is processing commands from the Command FIFO.
*/
#define ALT_SCANMGR_STAT_ACT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_STAT_ACT register field. */
#define ALT_SCANMGR_STAT_ACT_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_STAT_ACT register field. */
#define ALT_SCANMGR_STAT_ACT_MSB 31
/* The width in bits of the ALT_SCANMGR_STAT_ACT register field. */
#define ALT_SCANMGR_STAT_ACT_WIDTH 1
/* The mask used to set the ALT_SCANMGR_STAT_ACT register field value. */
#define ALT_SCANMGR_STAT_ACT_SET_MSK 0x80000000
/* The mask used to clear the ALT_SCANMGR_STAT_ACT register field value. */
#define ALT_SCANMGR_STAT_ACT_CLR_MSK 0x7fffffff
/* The reset value of the ALT_SCANMGR_STAT_ACT register field. */
#define ALT_SCANMGR_STAT_ACT_RESET 0x0
/* Extracts the ALT_SCANMGR_STAT_ACT field value from a register. */
#define ALT_SCANMGR_STAT_ACT_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_SCANMGR_STAT_ACT register field value suitable for setting the register. */
#define ALT_SCANMGR_STAT_ACT_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_SCANMGR_STAT.
*/
struct ALT_SCANMGR_STAT_s
{
uint32_t : 1; /* *UNDEFINED* */
uint32_t trst : 1; /* Reset output to the FPGA JTAG */
uint32_t : 1; /* *UNDEFINED* */
const uint32_t ignore : 1; /* Ignore */
uint32_t : 20; /* *UNDEFINED* */
const uint32_t rfifocnt : 3; /* Response FIFO Outstanding Byte Count */
uint32_t : 1; /* *UNDEFINED* */
const uint32_t wfifocnt : 3; /* Command FIFO Outstanding Byte Count */
const uint32_t active : 1; /* Scan-Chain Engine Active */
};
/* The typedef declaration for register ALT_SCANMGR_STAT. */
typedef volatile struct ALT_SCANMGR_STAT_s ALT_SCANMGR_STAT_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_SCANMGR_STAT register from the beginning of the component. */
#define ALT_SCANMGR_STAT_OFST 0x0
/*
* Register : Scan-Chain Enable Register - en
*
* This register is used to enable one of the 5 scan-chains (0-3 and 7). Only one
* scan-chain must be enabled at a time. A scan-chain is enabled by writing its
* corresponding enable field.
*
* Software must use the System Manager to put the corresponding I/O scan-chain
* into the frozen state before attempting to send I/O configuration data to the
* I/O scan-chain.
*
* Software must only write to this register when the Scan-Chain Engine is
* inactive.Writing this field at any other time has unpredictable results. This
* means that before writing to this field, software must read the STAT register
* and check that the ACTIVE and WFIFOCNT fields are both zero.
*
* The name of this register in ARM documentation is PSEL.
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:----------------------------
* [0] | RW | 0x0 | I/O Scan-Chain 0 Enable
* [1] | RW | 0x0 | I/O Scan-Chain 1 Enable
* [2] | RW | 0x0 | I/O Scan-Chain 2 Enable
* [3] | RW | 0x0 | I/O Scan-Chain 3 Enable
* [6:4] | ??? | 0x0 | *UNDEFINED*
* [7] | RW | 0x0 | FPGA JTAG Scan-Chain Enable
* [31:8] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : I/O Scan-Chain 0 Enable - ioscanchain0
*
* Used to enable or disable I/O Scan-Chain 0
*
* The name of this field in ARM documentation is PSEL0.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------
* ALT_SCANMGR_EN_IOSCANCHAIN0_E_DIS | 0x0 | Disable scan-chain
* ALT_SCANMGR_EN_IOSCANCHAIN0_E_EN | 0x1 | Enable scan-chain
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN0
*
* Disable scan-chain
*/
#define ALT_SCANMGR_EN_IOSCANCHAIN0_E_DIS 0x0
/*
* Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN0
*
* Enable scan-chain
*/
#define ALT_SCANMGR_EN_IOSCANCHAIN0_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN0 register field. */
#define ALT_SCANMGR_EN_IOSCANCHAIN0_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN0 register field. */
#define ALT_SCANMGR_EN_IOSCANCHAIN0_MSB 0
/* The width in bits of the ALT_SCANMGR_EN_IOSCANCHAIN0 register field. */
#define ALT_SCANMGR_EN_IOSCANCHAIN0_WIDTH 1
/* The mask used to set the ALT_SCANMGR_EN_IOSCANCHAIN0 register field value. */
#define ALT_SCANMGR_EN_IOSCANCHAIN0_SET_MSK 0x00000001
/* The mask used to clear the ALT_SCANMGR_EN_IOSCANCHAIN0 register field value. */
#define ALT_SCANMGR_EN_IOSCANCHAIN0_CLR_MSK 0xfffffffe
/* The reset value of the ALT_SCANMGR_EN_IOSCANCHAIN0 register field. */
#define ALT_SCANMGR_EN_IOSCANCHAIN0_RESET 0x0
/* Extracts the ALT_SCANMGR_EN_IOSCANCHAIN0 field value from a register. */
#define ALT_SCANMGR_EN_IOSCANCHAIN0_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_SCANMGR_EN_IOSCANCHAIN0 register field value suitable for setting the register. */
#define ALT_SCANMGR_EN_IOSCANCHAIN0_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : I/O Scan-Chain 1 Enable - ioscanchain1
*
* Used to enable or disable I/O Scan-Chain 1
*
* The name of this field in ARM documentation is PSEL1.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------
* ALT_SCANMGR_EN_IOSCANCHAIN1_E_DIS | 0x0 | Disable scan-chain
* ALT_SCANMGR_EN_IOSCANCHAIN1_E_EN | 0x1 | Enable scan-chain
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN1
*
* Disable scan-chain
*/
#define ALT_SCANMGR_EN_IOSCANCHAIN1_E_DIS 0x0
/*
* Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN1
*
* Enable scan-chain
*/
#define ALT_SCANMGR_EN_IOSCANCHAIN1_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN1 register field. */
#define ALT_SCANMGR_EN_IOSCANCHAIN1_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN1 register field. */
#define ALT_SCANMGR_EN_IOSCANCHAIN1_MSB 1
/* The width in bits of the ALT_SCANMGR_EN_IOSCANCHAIN1 register field. */
#define ALT_SCANMGR_EN_IOSCANCHAIN1_WIDTH 1
/* The mask used to set the ALT_SCANMGR_EN_IOSCANCHAIN1 register field value. */
#define ALT_SCANMGR_EN_IOSCANCHAIN1_SET_MSK 0x00000002
/* The mask used to clear the ALT_SCANMGR_EN_IOSCANCHAIN1 register field value. */
#define ALT_SCANMGR_EN_IOSCANCHAIN1_CLR_MSK 0xfffffffd
/* The reset value of the ALT_SCANMGR_EN_IOSCANCHAIN1 register field. */
#define ALT_SCANMGR_EN_IOSCANCHAIN1_RESET 0x0
/* Extracts the ALT_SCANMGR_EN_IOSCANCHAIN1 field value from a register. */
#define ALT_SCANMGR_EN_IOSCANCHAIN1_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_SCANMGR_EN_IOSCANCHAIN1 register field value suitable for setting the register. */
#define ALT_SCANMGR_EN_IOSCANCHAIN1_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : I/O Scan-Chain 2 Enable - ioscanchain2
*
* Used to enable or disable I/O Scan-Chain 2
*
* The name of this field in ARM documentation is PSEL2.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------
* ALT_SCANMGR_EN_IOSCANCHAIN2_E_DIS | 0x0 | Disable scan-chain
* ALT_SCANMGR_EN_IOSCANCHAIN2_E_EN | 0x1 | Enable scan-chain
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN2
*
* Disable scan-chain
*/
#define ALT_SCANMGR_EN_IOSCANCHAIN2_E_DIS 0x0
/*
* Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN2
*
* Enable scan-chain
*/
#define ALT_SCANMGR_EN_IOSCANCHAIN2_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN2 register field. */
#define ALT_SCANMGR_EN_IOSCANCHAIN2_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN2 register field. */
#define ALT_SCANMGR_EN_IOSCANCHAIN2_MSB 2
/* The width in bits of the ALT_SCANMGR_EN_IOSCANCHAIN2 register field. */
#define ALT_SCANMGR_EN_IOSCANCHAIN2_WIDTH 1
/* The mask used to set the ALT_SCANMGR_EN_IOSCANCHAIN2 register field value. */
#define ALT_SCANMGR_EN_IOSCANCHAIN2_SET_MSK 0x00000004
/* The mask used to clear the ALT_SCANMGR_EN_IOSCANCHAIN2 register field value. */
#define ALT_SCANMGR_EN_IOSCANCHAIN2_CLR_MSK 0xfffffffb
/* The reset value of the ALT_SCANMGR_EN_IOSCANCHAIN2 register field. */
#define ALT_SCANMGR_EN_IOSCANCHAIN2_RESET 0x0
/* Extracts the ALT_SCANMGR_EN_IOSCANCHAIN2 field value from a register. */
#define ALT_SCANMGR_EN_IOSCANCHAIN2_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_SCANMGR_EN_IOSCANCHAIN2 register field value suitable for setting the register. */
#define ALT_SCANMGR_EN_IOSCANCHAIN2_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : I/O Scan-Chain 3 Enable - ioscanchain3
*
* Used to enable or disable I/O Scan-Chain 3
*
* The name of this field in ARM documentation is PSEL3.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------
* ALT_SCANMGR_EN_IOSCANCHAIN3_E_DIS | 0x0 | Disable scan-chain
* ALT_SCANMGR_EN_IOSCANCHAIN3_E_EN | 0x1 | Enable scan-chain
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN3
*
* Disable scan-chain
*/
#define ALT_SCANMGR_EN_IOSCANCHAIN3_E_DIS 0x0
/*
* Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN3
*
* Enable scan-chain
*/
#define ALT_SCANMGR_EN_IOSCANCHAIN3_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN3 register field. */
#define ALT_SCANMGR_EN_IOSCANCHAIN3_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN3 register field. */
#define ALT_SCANMGR_EN_IOSCANCHAIN3_MSB 3
/* The width in bits of the ALT_SCANMGR_EN_IOSCANCHAIN3 register field. */
#define ALT_SCANMGR_EN_IOSCANCHAIN3_WIDTH 1
/* The mask used to set the ALT_SCANMGR_EN_IOSCANCHAIN3 register field value. */
#define ALT_SCANMGR_EN_IOSCANCHAIN3_SET_MSK 0x00000008
/* The mask used to clear the ALT_SCANMGR_EN_IOSCANCHAIN3 register field value. */
#define ALT_SCANMGR_EN_IOSCANCHAIN3_CLR_MSK 0xfffffff7
/* The reset value of the ALT_SCANMGR_EN_IOSCANCHAIN3 register field. */
#define ALT_SCANMGR_EN_IOSCANCHAIN3_RESET 0x0
/* Extracts the ALT_SCANMGR_EN_IOSCANCHAIN3 field value from a register. */
#define ALT_SCANMGR_EN_IOSCANCHAIN3_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_SCANMGR_EN_IOSCANCHAIN3 register field value suitable for setting the register. */
#define ALT_SCANMGR_EN_IOSCANCHAIN3_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : FPGA JTAG Scan-Chain Enable - fpgajtag
*
* Used to enable or disable FPGA JTAG scan-chain.Software must use the System
* Manager to enable the Scan Manager to drive the FPGA JTAG before attempting to
* communicate with the FPGA JTAG via the Scan Manager.
*
* The name of this field in ARM documentation is PSEL7.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------|:------|:-------------------
* ALT_SCANMGR_EN_FPGAJTAG_E_DIS | 0x0 | Disable scan-chain
* ALT_SCANMGR_EN_FPGAJTAG_E_EN | 0x1 | Enable scan-chain
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_SCANMGR_EN_FPGAJTAG
*
* Disable scan-chain
*/
#define ALT_SCANMGR_EN_FPGAJTAG_E_DIS 0x0
/*
* Enumerated value for register field ALT_SCANMGR_EN_FPGAJTAG
*
* Enable scan-chain
*/
#define ALT_SCANMGR_EN_FPGAJTAG_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_EN_FPGAJTAG register field. */
#define ALT_SCANMGR_EN_FPGAJTAG_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_EN_FPGAJTAG register field. */
#define ALT_SCANMGR_EN_FPGAJTAG_MSB 7
/* The width in bits of the ALT_SCANMGR_EN_FPGAJTAG register field. */
#define ALT_SCANMGR_EN_FPGAJTAG_WIDTH 1
/* The mask used to set the ALT_SCANMGR_EN_FPGAJTAG register field value. */
#define ALT_SCANMGR_EN_FPGAJTAG_SET_MSK 0x00000080
/* The mask used to clear the ALT_SCANMGR_EN_FPGAJTAG register field value. */
#define ALT_SCANMGR_EN_FPGAJTAG_CLR_MSK 0xffffff7f
/* The reset value of the ALT_SCANMGR_EN_FPGAJTAG register field. */
#define ALT_SCANMGR_EN_FPGAJTAG_RESET 0x0
/* Extracts the ALT_SCANMGR_EN_FPGAJTAG field value from a register. */
#define ALT_SCANMGR_EN_FPGAJTAG_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_SCANMGR_EN_FPGAJTAG register field value suitable for setting the register. */
#define ALT_SCANMGR_EN_FPGAJTAG_SET(value) (((value) << 7) & 0x00000080)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_SCANMGR_EN.
*/
struct ALT_SCANMGR_EN_s
{
uint32_t ioscanchain0 : 1; /* I/O Scan-Chain 0 Enable */
uint32_t ioscanchain1 : 1; /* I/O Scan-Chain 1 Enable */
uint32_t ioscanchain2 : 1; /* I/O Scan-Chain 2 Enable */
uint32_t ioscanchain3 : 1; /* I/O Scan-Chain 3 Enable */
uint32_t : 3; /* *UNDEFINED* */
uint32_t fpgajtag : 1; /* FPGA JTAG Scan-Chain Enable */
uint32_t : 24; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_SCANMGR_EN. */
typedef volatile struct ALT_SCANMGR_EN_s ALT_SCANMGR_EN_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_SCANMGR_EN register from the beginning of the component. */
#define ALT_SCANMGR_EN_OFST 0x4
/*
* Register : FIFO Single Byte Register - fifosinglebyte
*
* Writes to the FIFO Single Byte Register write a single byte value to the command
* FIFO. If the command FIFO is full, the APB write operation is stalled until the
* command FIFO is not full.
*
* Reads from the Single Byte FIFO Register read a single byte value from the
* command FIFO. If the command FIFO is empty, the APB read operation is stalled
* until the command FIFO is not empty.
*
* See the ARM documentation for a description of the read and write values.
*
* The name of this register in ARM documentation is BWFIFO1 for writes and BRFIFO1
* for reads.
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------
* [7:0] | RW | Unknown | Single Byte Value
* [31:8] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : Single Byte Value - value
*
* Transfers single byte value to/from command FIFO
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field. */
#define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field. */
#define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_MSB 7
/* The width in bits of the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field. */
#define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_WIDTH 8
/* The mask used to set the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field value. */
#define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_SET_MSK 0x000000ff
/* The mask used to clear the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field value. */
#define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_CLR_MSK 0xffffff00
/* The reset value of the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field is UNKNOWN. */
#define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_RESET 0x0
/* Extracts the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE field value from a register. */
#define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
/* Produces a ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field value suitable for setting the register. */
#define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_SET(value) (((value) << 0) & 0x000000ff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_SCANMGR_FIFOSINGLEBYTE.
*/
struct ALT_SCANMGR_FIFOSINGLEBYTE_s
{
uint32_t value : 8; /* Single Byte Value */
uint32_t : 24; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_SCANMGR_FIFOSINGLEBYTE. */
typedef volatile struct ALT_SCANMGR_FIFOSINGLEBYTE_s ALT_SCANMGR_FIFOSINGLEBYTE_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_SCANMGR_FIFOSINGLEBYTE register from the beginning of the component. */
#define ALT_SCANMGR_FIFOSINGLEBYTE_OFST 0x10
/*
* Register : FIFO Double Byte Register - fifodoublebyte
*
* Writes to the FIFO Double Byte Register write a double byte value to the command
* FIFO. If the command FIFO is full, the APB write operation is stalled until the
* command FIFO is not full.
*
* Reads from the Double Byte FIFO Register read a double byte value from the
* command FIFO. If the command FIFO is empty, the APB read operation is stalled
* until the command FIFO is not empty.
*
* See the ARM documentation for a description of the read and write values.
*
* The name of this register in ARM documentation is BWFIFO2 for writes and BRFIFO2
* for reads.
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:--------|:------------------
* [15:0] | RW | Unknown | Double Byte Value
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : Double Byte Value - value
*
* Transfers double byte value to/from command FIFO
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field. */
#define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field. */
#define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_MSB 15
/* The width in bits of the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field. */
#define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_WIDTH 16
/* The mask used to set the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field value. */
#define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field value. */
#define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_CLR_MSK 0xffff0000
/* The reset value of the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field is UNKNOWN. */
#define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_RESET 0x0
/* Extracts the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE field value from a register. */
#define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field value suitable for setting the register. */
#define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_SCANMGR_FIFODOUBLEBYTE.
*/
struct ALT_SCANMGR_FIFODOUBLEBYTE_s
{
uint32_t value : 16; /* Double Byte Value */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_SCANMGR_FIFODOUBLEBYTE. */
typedef volatile struct ALT_SCANMGR_FIFODOUBLEBYTE_s ALT_SCANMGR_FIFODOUBLEBYTE_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_SCANMGR_FIFODOUBLEBYTE register from the beginning of the component. */
#define ALT_SCANMGR_FIFODOUBLEBYTE_OFST 0x14
/*
* Register : FIFO Triple Byte Register - fifotriplebyte
*
* Writes to the FIFO Triple Byte Register write a triple byte value to the command
* FIFO. If the command FIFO is full, the APB write operation is stalled until the
* command FIFO is not full.
*
* Reads from the Triple Byte FIFO Register read a triple byte value from the
* command FIFO. If the command FIFO is empty, the APB read operation is stalled
* until the command FIFO is not empty.
*
* See the ARM documentation for a description of the read and write values.
*
* The name of this register in ARM documentation is BWFIFO3 for writes and BRFIFO3
* for reads.
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:--------|:------------------
* [23:0] | RW | Unknown | Triple Byte Value
* [31:24] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : Triple Byte Value - value
*
* Transfers triple byte value to/from command FIFO
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field. */
#define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field. */
#define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_MSB 23
/* The width in bits of the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field. */
#define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_WIDTH 24
/* The mask used to set the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field value. */
#define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_SET_MSK 0x00ffffff
/* The mask used to clear the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field value. */
#define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_CLR_MSK 0xff000000
/* The reset value of the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field is UNKNOWN. */
#define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_RESET 0x0
/* Extracts the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE field value from a register. */
#define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_GET(value) (((value) & 0x00ffffff) >> 0)
/* Produces a ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field value suitable for setting the register. */
#define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_SET(value) (((value) << 0) & 0x00ffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_SCANMGR_FIFOTRIPLEBYTE.
*/
struct ALT_SCANMGR_FIFOTRIPLEBYTE_s
{
uint32_t value : 24; /* Triple Byte Value */
uint32_t : 8; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_SCANMGR_FIFOTRIPLEBYTE. */
typedef volatile struct ALT_SCANMGR_FIFOTRIPLEBYTE_s ALT_SCANMGR_FIFOTRIPLEBYTE_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_SCANMGR_FIFOTRIPLEBYTE register from the beginning of the component. */
#define ALT_SCANMGR_FIFOTRIPLEBYTE_OFST 0x18
/*
* Register : FIFO Quad Byte Register - fifoquadbyte
*
* Writes to the FIFO Quad Byte Register write a quad byte value to the command
* FIFO. If the command FIFO is full, the APB write operation is stalled until the
* command FIFO is not full.
*
* Reads from the Quad Byte FIFO Register read a quad byte value from the command
* FIFO. If the command FIFO is empty, the APB read operation is stalled until the
* command FIFO is not empty.
*
* See the ARM documentation for a description of the read and write values.
*
* The name of this register in ARM documentation is BWFIFO4 for writes and BRFIFO4
* for reads.
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:----------------
* [31:0] | RW | Unknown | Quad Byte Value
*
*/
/*
* Field : Quad Byte Value - value
*
* Transfers quad byte value to/from command FIFO
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field. */
#define ALT_SCANMGR_FIFOQUADBYTE_VALUE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field. */
#define ALT_SCANMGR_FIFOQUADBYTE_VALUE_MSB 31
/* The width in bits of the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field. */
#define ALT_SCANMGR_FIFOQUADBYTE_VALUE_WIDTH 32
/* The mask used to set the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field value. */
#define ALT_SCANMGR_FIFOQUADBYTE_VALUE_SET_MSK 0xffffffff
/* The mask used to clear the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field value. */
#define ALT_SCANMGR_FIFOQUADBYTE_VALUE_CLR_MSK 0x00000000
/* The reset value of the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field is UNKNOWN. */
#define ALT_SCANMGR_FIFOQUADBYTE_VALUE_RESET 0x0
/* Extracts the ALT_SCANMGR_FIFOQUADBYTE_VALUE field value from a register. */
#define ALT_SCANMGR_FIFOQUADBYTE_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_SCANMGR_FIFOQUADBYTE_VALUE register field value suitable for setting the register. */
#define ALT_SCANMGR_FIFOQUADBYTE_VALUE_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_SCANMGR_FIFOQUADBYTE.
*/
struct ALT_SCANMGR_FIFOQUADBYTE_s
{
uint32_t value : 32; /* Quad Byte Value */
};
/* The typedef declaration for register ALT_SCANMGR_FIFOQUADBYTE. */
typedef volatile struct ALT_SCANMGR_FIFOQUADBYTE_s ALT_SCANMGR_FIFOQUADBYTE_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_SCANMGR_FIFOQUADBYTE register from the beginning of the component. */
#define ALT_SCANMGR_FIFOQUADBYTE_OFST 0x1c
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register group ALT_SCANMGR.
*/
struct ALT_SCANMGR_s
{
volatile ALT_SCANMGR_STAT_t stat; /* ALT_SCANMGR_STAT */
volatile ALT_SCANMGR_EN_t en; /* ALT_SCANMGR_EN */
volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */
volatile ALT_SCANMGR_FIFOSINGLEBYTE_t fifosinglebyte; /* ALT_SCANMGR_FIFOSINGLEBYTE */
volatile ALT_SCANMGR_FIFODOUBLEBYTE_t fifodoublebyte; /* ALT_SCANMGR_FIFODOUBLEBYTE */
volatile ALT_SCANMGR_FIFOTRIPLEBYTE_t fifotriplebyte; /* ALT_SCANMGR_FIFOTRIPLEBYTE */
volatile ALT_SCANMGR_FIFOQUADBYTE_t fifoquadbyte; /* ALT_SCANMGR_FIFOQUADBYTE */
};
/* The typedef declaration for register group ALT_SCANMGR. */
typedef volatile struct ALT_SCANMGR_s ALT_SCANMGR_t;
/* The struct declaration for the raw register contents of register group ALT_SCANMGR. */
struct ALT_SCANMGR_raw_s
{
volatile uint32_t stat; /* ALT_SCANMGR_STAT */
volatile uint32_t en; /* ALT_SCANMGR_EN */
volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */
volatile uint32_t fifosinglebyte; /* ALT_SCANMGR_FIFOSINGLEBYTE */
volatile uint32_t fifodoublebyte; /* ALT_SCANMGR_FIFODOUBLEBYTE */
volatile uint32_t fifotriplebyte; /* ALT_SCANMGR_FIFOTRIPLEBYTE */
volatile uint32_t fifoquadbyte; /* ALT_SCANMGR_FIFOQUADBYTE */
};
/* The typedef declaration for the raw register contents of register group ALT_SCANMGR. */
typedef volatile struct ALT_SCANMGR_raw_s ALT_SCANMGR_raw_t;
#endif /* __ASSEMBLY__ */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_ALT_SCANMGR_H__ */

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/*******************************************************************************
* *
* Copyright 2013 Altera Corporation. All Rights Reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following conditions are met: *
* *
* 1. Redistributions of source code must retain the above copyright notice, *
* this list of conditions and the following disclaimer. *
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, *
* this list of conditions and the following disclaimer in the documentation *
* and/or other materials provided with the distribution. *
* *
* 3. The name of the author may not be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
* *
*******************************************************************************/
/* Altera - ALT_STM */
#ifndef __ALTERA_ALT_STM_H__
#define __ALTERA_ALT_STM_H__
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*
* Component : STM Module Address Space - ALT_STM
* STM Module Address Space
*
* Address space allocated to the STM. For detailed information about the use of
* this address space, [url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm
* .doc.ddi0444b/index.html]click here[/url] to access the ARM documentation for
* the CoreSight STM-101.
*
*/
/*
* Register : Empty - reg
*
* Placeholder
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------
* [31:0] | RW | Unknown | Empty
*
*/
/*
* Field : Empty - fld
*
* Placeholder
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_STM_REG_FLD register field. */
#define ALT_STM_REG_FLD_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_STM_REG_FLD register field. */
#define ALT_STM_REG_FLD_MSB 31
/* The width in bits of the ALT_STM_REG_FLD register field. */
#define ALT_STM_REG_FLD_WIDTH 32
/* The mask used to set the ALT_STM_REG_FLD register field value. */
#define ALT_STM_REG_FLD_SET_MSK 0xffffffff
/* The mask used to clear the ALT_STM_REG_FLD register field value. */
#define ALT_STM_REG_FLD_CLR_MSK 0x00000000
/* The reset value of the ALT_STM_REG_FLD register field is UNKNOWN. */
#define ALT_STM_REG_FLD_RESET 0x0
/* Extracts the ALT_STM_REG_FLD field value from a register. */
#define ALT_STM_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_STM_REG_FLD register field value suitable for setting the register. */
#define ALT_STM_REG_FLD_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_STM_REG.
*/
struct ALT_STM_REG_s
{
uint32_t fld : 32; /* Empty */
};
/* The typedef declaration for register ALT_STM_REG. */
typedef volatile struct ALT_STM_REG_s ALT_STM_REG_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_STM_REG register from the beginning of the component. */
#define ALT_STM_REG_OFST 0x0
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register group ALT_STM.
*/
struct ALT_STM_s
{
volatile ALT_STM_REG_t reg; /* ALT_STM_REG */
};
/* The typedef declaration for register group ALT_STM. */
typedef volatile struct ALT_STM_s ALT_STM_t;
/* The struct declaration for the raw register contents of register group ALT_STM. */
struct ALT_STM_raw_s
{
volatile uint32_t reg; /* ALT_STM_REG */
};
/* The typedef declaration for the raw register contents of register group ALT_STM. */
typedef volatile struct ALT_STM_raw_s ALT_STM_raw_t;
#endif /* __ASSEMBLY__ */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_ALT_STM_H__ */

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/*******************************************************************************
* *
* Copyright 2013 Altera Corporation. All Rights Reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following conditions are met: *
* *
* 1. Redistributions of source code must retain the above copyright notice, *
* this list of conditions and the following disclaimer. *
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, *
* this list of conditions and the following disclaimer in the documentation *
* and/or other materials provided with the distribution. *
* *
* 3. The name of the author may not be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
* *
*******************************************************************************/
/* Altera - ALT_TMR */
#ifndef __ALTERA_ALT_TMR_H__
#define __ALTERA_ALT_TMR_H__
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*
* Component : Timer Module - ALT_TMR
* Timer Module
*
* Registers in the timer module. The timer IP core supports multiple timers but it
* is configured for just one timer. The term Timer1 refers to this one timer in
* the IP core and not the module instance.
*
*/
/*
* Register : Timer1 Load Count Register - timer1loadcount
*
* Used to load counter value into Timer1
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:----------------
* [31:0] | RW | 0x0 | Timer1LoadCount
*
*/
/*
* Field : Timer1LoadCount - timer1loadcount
*
* Value to be loaded into Timer1. This is the value from which counting commences.
* Any value written to this register is loaded into the associated timer.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field. */
#define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field. */
#define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_MSB 31
/* The width in bits of the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field. */
#define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_WIDTH 32
/* The mask used to set the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field value. */
#define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_SET_MSK 0xffffffff
/* The mask used to clear the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field value. */
#define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_CLR_MSK 0x00000000
/* The reset value of the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field. */
#define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_RESET 0x0
/* Extracts the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT field value from a register. */
#define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field value suitable for setting the register. */
#define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_TMR_TMR1LDCOUNT.
*/
struct ALT_TMR_TMR1LDCOUNT_s
{
uint32_t timer1loadcount : 32; /* Timer1LoadCount */
};
/* The typedef declaration for register ALT_TMR_TMR1LDCOUNT. */
typedef volatile struct ALT_TMR_TMR1LDCOUNT_s ALT_TMR_TMR1LDCOUNT_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_TMR_TMR1LDCOUNT register from the beginning of the component. */
#define ALT_TMR_TMR1LDCOUNT_OFST 0x0
/* The address of the ALT_TMR_TMR1LDCOUNT register. */
#define ALT_TMR_TMR1LDCOUNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1LDCOUNT_OFST))
/*
* Register : Timer1 Current Value Register - timer1currentval
*
* Provides current value of Timer1
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:---------------------
* [31:0] | R | 0x0 | Timer1 Current Value
*
*/
/*
* Field : Timer1 Current Value - timer1currentval
*
* Current value of Timer1.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field. */
#define ALT_TMR_TMR1CURVAL_TMR1CURVAL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field. */
#define ALT_TMR_TMR1CURVAL_TMR1CURVAL_MSB 31
/* The width in bits of the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field. */
#define ALT_TMR_TMR1CURVAL_TMR1CURVAL_WIDTH 32
/* The mask used to set the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field value. */
#define ALT_TMR_TMR1CURVAL_TMR1CURVAL_SET_MSK 0xffffffff
/* The mask used to clear the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field value. */
#define ALT_TMR_TMR1CURVAL_TMR1CURVAL_CLR_MSK 0x00000000
/* The reset value of the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field. */
#define ALT_TMR_TMR1CURVAL_TMR1CURVAL_RESET 0x0
/* Extracts the ALT_TMR_TMR1CURVAL_TMR1CURVAL field value from a register. */
#define ALT_TMR_TMR1CURVAL_TMR1CURVAL_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_TMR_TMR1CURVAL_TMR1CURVAL register field value suitable for setting the register. */
#define ALT_TMR_TMR1CURVAL_TMR1CURVAL_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_TMR_TMR1CURVAL.
*/
struct ALT_TMR_TMR1CURVAL_s
{
const uint32_t timer1currentval : 32; /* Timer1 Current Value */
};
/* The typedef declaration for register ALT_TMR_TMR1CURVAL. */
typedef volatile struct ALT_TMR_TMR1CURVAL_s ALT_TMR_TMR1CURVAL_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_TMR_TMR1CURVAL register from the beginning of the component. */
#define ALT_TMR_TMR1CURVAL_OFST 0x4
/* The address of the ALT_TMR_TMR1CURVAL register. */
#define ALT_TMR_TMR1CURVAL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1CURVAL_OFST))
/*
* Register : Timer1 Control Register - timer1controlreg
*
* This register controls enabling, operating mode (free-running or user-defined-
* count), and interrupt mask of Timer1. You can program this register to enable or
* disable Timer1 and to control its mode of operation.
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:----------------------
* [0] | RW | 0x0 | Timer1 Enable
* [1] | RW | 0x0 | Timer1 Mode
* [2] | RW | 0x0 | Timer1 Interrupt Mask
* [31:3] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : Timer1 Enable - timer1_enable
*
* Timer1 enable/disable bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:----------------
* ALT_TMR_TMR1CTLREG_TMR1_EN_E_DISD | 0x0 | Timer1 Disabled
* ALT_TMR_TMR1CTLREG_TMR1_EN_E_END | 0x1 | Timer1 Enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_EN
*
* Timer1 Disabled
*/
#define ALT_TMR_TMR1CTLREG_TMR1_EN_E_DISD 0x0
/*
* Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_EN
*
* Timer1 Enabled
*/
#define ALT_TMR_TMR1CTLREG_TMR1_EN_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CTLREG_TMR1_EN register field. */
#define ALT_TMR_TMR1CTLREG_TMR1_EN_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CTLREG_TMR1_EN register field. */
#define ALT_TMR_TMR1CTLREG_TMR1_EN_MSB 0
/* The width in bits of the ALT_TMR_TMR1CTLREG_TMR1_EN register field. */
#define ALT_TMR_TMR1CTLREG_TMR1_EN_WIDTH 1
/* The mask used to set the ALT_TMR_TMR1CTLREG_TMR1_EN register field value. */
#define ALT_TMR_TMR1CTLREG_TMR1_EN_SET_MSK 0x00000001
/* The mask used to clear the ALT_TMR_TMR1CTLREG_TMR1_EN register field value. */
#define ALT_TMR_TMR1CTLREG_TMR1_EN_CLR_MSK 0xfffffffe
/* The reset value of the ALT_TMR_TMR1CTLREG_TMR1_EN register field. */
#define ALT_TMR_TMR1CTLREG_TMR1_EN_RESET 0x0
/* Extracts the ALT_TMR_TMR1CTLREG_TMR1_EN field value from a register. */
#define ALT_TMR_TMR1CTLREG_TMR1_EN_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_TMR_TMR1CTLREG_TMR1_EN register field value suitable for setting the register. */
#define ALT_TMR_TMR1CTLREG_TMR1_EN_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : Timer1 Mode - timer1_mode
*
* Sets operating mode.
*
* NOTE: You must set the timer1loadcount register to all ones before enabling the
* timer in free-running mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------
* ALT_TMR_TMR1CTLREG_TMR1_MOD_E_FREERUN | 0x0 | Free-running mode
* ALT_TMR_TMR1CTLREG_TMR1_MOD_E_USEDEF | 0x1 | User-defined count mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_MOD
*
* Free-running mode
*/
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_E_FREERUN 0x0
/*
* Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_MOD
*
* User-defined count mode
*/
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_E_USEDEF 0x1
/* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field. */
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field. */
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_MSB 1
/* The width in bits of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field. */
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_WIDTH 1
/* The mask used to set the ALT_TMR_TMR1CTLREG_TMR1_MOD register field value. */
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_SET_MSK 0x00000002
/* The mask used to clear the ALT_TMR_TMR1CTLREG_TMR1_MOD register field value. */
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field. */
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_RESET 0x0
/* Extracts the ALT_TMR_TMR1CTLREG_TMR1_MOD field value from a register. */
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_TMR_TMR1CTLREG_TMR1_MOD register field value suitable for setting the register. */
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : Timer1 Interrupt Mask - timer1_interrupt_mask
*
* Timer1 interrupt mask
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:-------------------------------
* ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_NOTMSKED | 0x0 | interrupt not masked (enabled)
* ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_MSKED | 0x1 | interrupt masked (disabled)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_INT_MSK
*
* interrupt not masked (enabled)
*/
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_NOTMSKED 0x0
/*
* Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_INT_MSK
*
* interrupt masked (disabled)
*/
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_MSKED 0x1
/* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field. */
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field. */
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_MSB 2
/* The width in bits of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field. */
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_WIDTH 1
/* The mask used to set the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field value. */
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field value. */
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field. */
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_RESET 0x0
/* Extracts the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK field value from a register. */
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field value suitable for setting the register. */
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_SET(value) (((value) << 2) & 0x00000004)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_TMR_TMR1CTLREG.
*/
struct ALT_TMR_TMR1CTLREG_s
{
uint32_t timer1_enable : 1; /* Timer1 Enable */
uint32_t timer1_mode : 1; /* Timer1 Mode */
uint32_t timer1_interrupt_mask : 1; /* Timer1 Interrupt Mask */
uint32_t : 29; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_TMR_TMR1CTLREG. */
typedef volatile struct ALT_TMR_TMR1CTLREG_s ALT_TMR_TMR1CTLREG_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_TMR_TMR1CTLREG register from the beginning of the component. */
#define ALT_TMR_TMR1CTLREG_OFST 0x8
/* The address of the ALT_TMR_TMR1CTLREG register. */
#define ALT_TMR_TMR1CTLREG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1CTLREG_OFST))
/*
* Register : Timer1 End-of-Interrupt Register - timer1eoi
*
* Clears Timer1 interrupt when read.
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:------------------------
* [0] | R | 0x0 | Timer1 End of Interrupt
* [31:1] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : Timer1 End of Interrupt - timer1eoi
*
* Reading from this register clears the interrupt from Timer1 and returns 0.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1EOI_TMR1EOI register field. */
#define ALT_TMR_TMR1EOI_TMR1EOI_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1EOI_TMR1EOI register field. */
#define ALT_TMR_TMR1EOI_TMR1EOI_MSB 0
/* The width in bits of the ALT_TMR_TMR1EOI_TMR1EOI register field. */
#define ALT_TMR_TMR1EOI_TMR1EOI_WIDTH 1
/* The mask used to set the ALT_TMR_TMR1EOI_TMR1EOI register field value. */
#define ALT_TMR_TMR1EOI_TMR1EOI_SET_MSK 0x00000001
/* The mask used to clear the ALT_TMR_TMR1EOI_TMR1EOI register field value. */
#define ALT_TMR_TMR1EOI_TMR1EOI_CLR_MSK 0xfffffffe
/* The reset value of the ALT_TMR_TMR1EOI_TMR1EOI register field. */
#define ALT_TMR_TMR1EOI_TMR1EOI_RESET 0x0
/* Extracts the ALT_TMR_TMR1EOI_TMR1EOI field value from a register. */
#define ALT_TMR_TMR1EOI_TMR1EOI_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_TMR_TMR1EOI_TMR1EOI register field value suitable for setting the register. */
#define ALT_TMR_TMR1EOI_TMR1EOI_SET(value) (((value) << 0) & 0x00000001)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_TMR_TMR1EOI.
*/
struct ALT_TMR_TMR1EOI_s
{
const uint32_t timer1eoi : 1; /* Timer1 End of Interrupt */
uint32_t : 31; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_TMR_TMR1EOI. */
typedef volatile struct ALT_TMR_TMR1EOI_s ALT_TMR_TMR1EOI_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_TMR_TMR1EOI register from the beginning of the component. */
#define ALT_TMR_TMR1EOI_OFST 0xc
/* The address of the ALT_TMR_TMR1EOI register. */
#define ALT_TMR_TMR1EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1EOI_OFST))
/*
* Register : Timer1 Interrupt Status Register - timer1intstat
*
* Provides the interrupt status of Timer1 after masking.
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:------------------------
* [0] | R | 0x0 | Timer1 Interrupt Status
* [31:1] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : Timer1 Interrupt Status - timer1intstat
*
* Provides the interrupt status for Timer1. The status reported is after the
* interrupt mask has been applied. Reading from this register does not clear any
* active interrupts.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-------------------------------
* ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_E_INACT | 0x0 | Timer1 interrupt is not active
* ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_E_ACT | 0x1 | Timer1 interrupt is active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_TMR_TMR1INTSTAT_TMR1INTSTAT
*
* Timer1 interrupt is not active
*/
#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_E_INACT 0x0
/*
* Enumerated value for register field ALT_TMR_TMR1INTSTAT_TMR1INTSTAT
*
* Timer1 interrupt is active
*/
#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field. */
#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field. */
#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_MSB 0
/* The width in bits of the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field. */
#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_WIDTH 1
/* The mask used to set the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field value. */
#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_SET_MSK 0x00000001
/* The mask used to clear the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field value. */
#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_CLR_MSK 0xfffffffe
/* The reset value of the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field. */
#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_RESET 0x0
/* Extracts the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT field value from a register. */
#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field value suitable for setting the register. */
#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_SET(value) (((value) << 0) & 0x00000001)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_TMR_TMR1INTSTAT.
*/
struct ALT_TMR_TMR1INTSTAT_s
{
const uint32_t timer1intstat : 1; /* Timer1 Interrupt Status */
uint32_t : 31; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_TMR_TMR1INTSTAT. */
typedef volatile struct ALT_TMR_TMR1INTSTAT_s ALT_TMR_TMR1INTSTAT_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_TMR_TMR1INTSTAT register from the beginning of the component. */
#define ALT_TMR_TMR1INTSTAT_OFST 0x10
/* The address of the ALT_TMR_TMR1INTSTAT register. */
#define ALT_TMR_TMR1INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1INTSTAT_OFST))
/*
* Register : Timers Interrupt Status Register - timersintstat
*
* Provides the interrupt status for all timers after masking. Because there is
* only Timer1 in this module instance, this status is the same as timer1intstat.
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:------------------------
* [0] | R | 0x0 | Timers Interrupt Status
* [31:1] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : Timers Interrupt Status - timersintstat
*
* Provides the interrupt status for Timer1. Because there is only Timer1 in this
* module instance, this status is the same as timer1intstat. The status reported
* is after the interrupt mask has been applied. Reading from this register does
* not clear any active interrupts.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-------------------------
* ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_E_INACT | 0x0 | timer_intr is not active
* ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_E_ACT | 0x1 | timer_intr is active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_TMR_TMRSINTSTAT_TMRSINTSTAT
*
* timer_intr is not active
*/
#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_E_INACT 0x0
/*
* Enumerated value for register field ALT_TMR_TMRSINTSTAT_TMRSINTSTAT
*
* timer_intr is active
*/
#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field. */
#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field. */
#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_MSB 0
/* The width in bits of the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field. */
#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_WIDTH 1
/* The mask used to set the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field value. */
#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_SET_MSK 0x00000001
/* The mask used to clear the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field value. */
#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_CLR_MSK 0xfffffffe
/* The reset value of the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field. */
#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_RESET 0x0
/* Extracts the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT field value from a register. */
#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field value suitable for setting the register. */
#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_SET(value) (((value) << 0) & 0x00000001)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_TMR_TMRSINTSTAT.
*/
struct ALT_TMR_TMRSINTSTAT_s
{
const uint32_t timersintstat : 1; /* Timers Interrupt Status */
uint32_t : 31; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_TMR_TMRSINTSTAT. */
typedef volatile struct ALT_TMR_TMRSINTSTAT_s ALT_TMR_TMRSINTSTAT_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_TMR_TMRSINTSTAT register from the beginning of the component. */
#define ALT_TMR_TMRSINTSTAT_OFST 0xa0
/* The address of the ALT_TMR_TMRSINTSTAT register. */
#define ALT_TMR_TMRSINTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMRSINTSTAT_OFST))
/*
* Register : Timers End-of-Interrupt Register - timerseoi
*
* Clears Timer1 interrupt when read. Because there is only Timer1 in this module
* instance, reading this register has the same effect as reading timer1eoi.
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:------------------------
* [0] | R | 0x0 | Timers End-of-Interrupt
* [31:1] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : Timers End-of-Interrupt - timerseoi
*
* Reading from this register clears the interrupt all timers and returns 0.
* Because there is only Timer1 in this module instance, reading this register has
* the same effect as reading timer1eoi.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_TMR_TMRSEOI_TMRSEOI register field. */
#define ALT_TMR_TMRSEOI_TMRSEOI_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_TMR_TMRSEOI_TMRSEOI register field. */
#define ALT_TMR_TMRSEOI_TMRSEOI_MSB 0
/* The width in bits of the ALT_TMR_TMRSEOI_TMRSEOI register field. */
#define ALT_TMR_TMRSEOI_TMRSEOI_WIDTH 1
/* The mask used to set the ALT_TMR_TMRSEOI_TMRSEOI register field value. */
#define ALT_TMR_TMRSEOI_TMRSEOI_SET_MSK 0x00000001
/* The mask used to clear the ALT_TMR_TMRSEOI_TMRSEOI register field value. */
#define ALT_TMR_TMRSEOI_TMRSEOI_CLR_MSK 0xfffffffe
/* The reset value of the ALT_TMR_TMRSEOI_TMRSEOI register field. */
#define ALT_TMR_TMRSEOI_TMRSEOI_RESET 0x0
/* Extracts the ALT_TMR_TMRSEOI_TMRSEOI field value from a register. */
#define ALT_TMR_TMRSEOI_TMRSEOI_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_TMR_TMRSEOI_TMRSEOI register field value suitable for setting the register. */
#define ALT_TMR_TMRSEOI_TMRSEOI_SET(value) (((value) << 0) & 0x00000001)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_TMR_TMRSEOI.
*/
struct ALT_TMR_TMRSEOI_s
{
const uint32_t timerseoi : 1; /* Timers End-of-Interrupt */
uint32_t : 31; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_TMR_TMRSEOI. */
typedef volatile struct ALT_TMR_TMRSEOI_s ALT_TMR_TMRSEOI_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_TMR_TMRSEOI register from the beginning of the component. */
#define ALT_TMR_TMRSEOI_OFST 0xa4
/* The address of the ALT_TMR_TMRSEOI register. */
#define ALT_TMR_TMRSEOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMRSEOI_OFST))
/*
* Register : Timers Raw Interrupt Status Register - timersrawintstat
*
* Provides the interrupt status for all timers before masking. Note that there is
* only Timer1 in this module instance.
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:----------------------------
* [0] | R | 0x0 | Timers Raw Interrupt Status
* [31:1] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : Timers Raw Interrupt Status - timersrawintstat
*
* Provides the interrupt status for Timer1. Because there is only Timer1 in this
* module instance, this status is the same as timer1intstat. The status reported
* is before the interrupt mask has been applied. Reading from this register does
* not clear any active interrupts.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:-------------------------------
* ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_E_INACT | 0x0 | Timer1 interrupt is not active
* ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_E_ACT | 0x1 | Timer1 interrupt is active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT
*
* Timer1 interrupt is not active
*/
#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_E_INACT 0x0
/*
* Enumerated value for register field ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT
*
* Timer1 interrupt is active
*/
#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field. */
#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field. */
#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_MSB 0
/* The width in bits of the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field. */
#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_WIDTH 1
/* The mask used to set the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field value. */
#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_SET_MSK 0x00000001
/* The mask used to clear the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field value. */
#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_CLR_MSK 0xfffffffe
/* The reset value of the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field. */
#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_RESET 0x0
/* Extracts the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT field value from a register. */
#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field value suitable for setting the register. */
#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_SET(value) (((value) << 0) & 0x00000001)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_TMR_TMRSRAWINTSTAT.
*/
struct ALT_TMR_TMRSRAWINTSTAT_s
{
const uint32_t timersrawintstat : 1; /* Timers Raw Interrupt Status */
uint32_t : 31; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_TMR_TMRSRAWINTSTAT. */
typedef volatile struct ALT_TMR_TMRSRAWINTSTAT_s ALT_TMR_TMRSRAWINTSTAT_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_TMR_TMRSRAWINTSTAT register from the beginning of the component. */
#define ALT_TMR_TMRSRAWINTSTAT_OFST 0xa8
/* The address of the ALT_TMR_TMRSRAWINTSTAT register. */
#define ALT_TMR_TMRSRAWINTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMRSRAWINTSTAT_OFST))
/*
* Register : Timers Component Version Register - timerscompversion
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:-----------|:-------------------------
* [31:0] | R | 0x3230352a | Timers Component Version
*
*/
/*
* Field : Timers Component Version - timerscompversion
*
* Current revision number of the timers component.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field. */
#define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field. */
#define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_MSB 31
/* The width in bits of the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field. */
#define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_WIDTH 32
/* The mask used to set the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field value. */
#define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_SET_MSK 0xffffffff
/* The mask used to clear the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field value. */
#define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_CLR_MSK 0x00000000
/* The reset value of the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field. */
#define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_RESET 0x3230352a
/* Extracts the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER field value from a register. */
#define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field value suitable for setting the register. */
#define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_TMR_TMRSCOMPVER.
*/
struct ALT_TMR_TMRSCOMPVER_s
{
const uint32_t timerscompversion : 32; /* Timers Component Version */
};
/* The typedef declaration for register ALT_TMR_TMRSCOMPVER. */
typedef volatile struct ALT_TMR_TMRSCOMPVER_s ALT_TMR_TMRSCOMPVER_t;
#endif /* __ASSEMBLY__ */
/* The byte offset of the ALT_TMR_TMRSCOMPVER register from the beginning of the component. */
#define ALT_TMR_TMRSCOMPVER_OFST 0xac
/* The address of the ALT_TMR_TMRSCOMPVER register. */
#define ALT_TMR_TMRSCOMPVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMRSCOMPVER_OFST))
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register group ALT_TMR.
*/
struct ALT_TMR_s
{
volatile ALT_TMR_TMR1LDCOUNT_t timer1loadcount; /* ALT_TMR_TMR1LDCOUNT */
volatile ALT_TMR_TMR1CURVAL_t timer1currentval; /* ALT_TMR_TMR1CURVAL */
volatile ALT_TMR_TMR1CTLREG_t timer1controlreg; /* ALT_TMR_TMR1CTLREG */
volatile ALT_TMR_TMR1EOI_t timer1eoi; /* ALT_TMR_TMR1EOI */
volatile ALT_TMR_TMR1INTSTAT_t timer1intstat; /* ALT_TMR_TMR1INTSTAT */
volatile uint32_t _pad_0x14_0x9f[35]; /* *UNDEFINED* */
volatile ALT_TMR_TMRSINTSTAT_t timersintstat; /* ALT_TMR_TMRSINTSTAT */
volatile ALT_TMR_TMRSEOI_t timerseoi; /* ALT_TMR_TMRSEOI */
volatile ALT_TMR_TMRSRAWINTSTAT_t timersrawintstat; /* ALT_TMR_TMRSRAWINTSTAT */
volatile ALT_TMR_TMRSCOMPVER_t timerscompversion; /* ALT_TMR_TMRSCOMPVER */
volatile uint32_t _pad_0xb0_0x100[20]; /* *UNDEFINED* */
};
/* The typedef declaration for register group ALT_TMR. */
typedef volatile struct ALT_TMR_s ALT_TMR_t;
/* The struct declaration for the raw register contents of register group ALT_TMR. */
struct ALT_TMR_raw_s
{
volatile uint32_t timer1loadcount; /* ALT_TMR_TMR1LDCOUNT */
volatile uint32_t timer1currentval; /* ALT_TMR_TMR1CURVAL */
volatile uint32_t timer1controlreg; /* ALT_TMR_TMR1CTLREG */
volatile uint32_t timer1eoi; /* ALT_TMR_TMR1EOI */
volatile uint32_t timer1intstat; /* ALT_TMR_TMR1INTSTAT */
volatile uint32_t _pad_0x14_0x9f[35]; /* *UNDEFINED* */
volatile uint32_t timersintstat; /* ALT_TMR_TMRSINTSTAT */
volatile uint32_t timerseoi; /* ALT_TMR_TMRSEOI */
volatile uint32_t timersrawintstat; /* ALT_TMR_TMRSRAWINTSTAT */
volatile uint32_t timerscompversion; /* ALT_TMR_TMRSCOMPVER */
volatile uint32_t _pad_0xb0_0x100[20]; /* *UNDEFINED* */
};
/* The typedef declaration for the raw register contents of register group ALT_TMR. */
typedef volatile struct ALT_TMR_raw_s ALT_TMR_raw_t;
#endif /* __ASSEMBLY__ */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_ALT_TMR_H__ */

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
/*! \file Altera - ALT_SOCAL */
#ifndef __ALTERA_SOCAL_H__
#define __ALTERA_SOCAL_H__
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#include <cstddef>
#include <cstdbool>
#include <cstdint>
#else /* __cplusplus */
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#endif /* __cplusplus */
#endif /* __ASSEMBLY__ */
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*!
* \addtogroup ALT_SOCAL_UTIL SoCAL Utilities
*
* This file contains utility and support functions for the Altera SoCAL.
* @{
*/
#ifdef __ASSEMBLY__
#define ALT_CAST(type, ptr) ptr
#else /* __ASSEMBLY__ */
/*! Cast the pointer to specified pointer type.
*
* Note: This macro expands to \e ptr value only for assembler language
* targets.
*
* \param type The pointer type to cast to
* \param ptr The pointer to apply the type cast to
*/
#define ALT_CAST(type, ptr) ((type) (ptr))
#endif /* __ASSEMBLY__ */
/*!
* \addtogroup ALT_SOCAL_UTIL_RW_FUNC SoCAL Memory Read/Write Utilities
*
* This section implements read and write functionality for various
* memory untis. The memory unit terms used for these functions are
* consistent with those used in the ARM Architecture Reference Manual
* ARMv7-A and ARMv7-R edition manual. The terms used for units of memory are:
*
* Unit of Memory | Abbreviation | Size in Bits
* :---------------|:-------------|:------------:
* Byte | byte | 8
* Half Word | hword | 16
* Word | word | 32
* Double Word | dword | 64
*
* @{
*/
/*! Write the 8 bit byte to the destination address in device memory.
* \param dest - Write destination pointer address
* \param src - 8 bit data byte to write to memory
*/
#define alt_write_byte(dest, src) (*ALT_CAST(volatile uint8_t *, (dest)) = (src))
/*! Read and return the 8 bit byte from the source address in device memory.
* \param src Read source pointer address
* \returns 8 bit data byte value
*/
#define alt_read_byte(src) (*ALT_CAST(volatile uint8_t *, (src)))
/*! Write the 16 bit half word to the destination address in device memory.
* \param dest - Write destination pointer address
* \param src - 16 bit data half word to write to memory
*/
#define alt_write_hword(dest, src) (*ALT_CAST(volatile uint16_t *, (dest)) = (src))
/*! Read and return the 16 bit half word from the source address in device memory.
* \param src Read source pointer address
* \returns 16 bit data half word value
*/
#define alt_read_hword(src) (*ALT_CAST(volatile uint16_t *, (src)))
/*! Write the 32 bit word to the destination address in device memory.
* \param dest - Write destination pointer address
* \param src - 32 bit data word to write to memory
*/
#define alt_write_word(dest, src) (*ALT_CAST(volatile uint32_t *, (dest)) = (src))
/*! Read and return the 32 bit word from the source address in device memory.
* \param src Read source pointer address
* \returns 32 bit data word value
*/
#define alt_read_word(src) (*ALT_CAST(volatile uint32_t *, (src)))
/*! Write the 64 bit double word to the destination address in device memory.
* \param dest - Write destination pointer address
* \param src - 64 bit data double word to write to memory
*/
#define alt_write_dword(dest, src) (*ALT_CAST(volatile uint64_t *, (dest)) = (src))
/*! Read and return the 64 bit double word from the source address in device memory.
* \param src Read source pointer address
* \returns 64 bit data double word value
*/
#define alt_read_dword(src) (*ALT_CAST(volatile uint64_t *, (src)))
/*! @} */
/*!
* \addtogroup ALT_SOCAL_UTIL_SC_FUNC SoCAL Memory Bit Set/Clr/XOR/Replace Utilities
*
* This section implements useful macros to set, clear, change, and replace
* selected bits within a word in memory or a memory-mapped register.
* @{
*
*/
/*! Set selected bits in the 8 bit byte at the destination address in device memory.
* \param dest - Destination pointer address
* \param bits - Bits to set in destination byte
*/
#define alt_setbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) | (bits)))
/*! Clear selected bits in the 8 bit byte at the destination address in device memory.
* \param dest - Destination pointer address
* \param bits - Bits to clear in destination byte
*/
#define alt_clrbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) & ~(bits)))
/*! Change or toggle selected bits in the 8 bit byte at the destination address in device memory.
* \param dest - Destination pointer address
* \param bits - Bits to change in destination byte
*/
#define alt_xorbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) ^ (bits)))
/*! Replace selected bits in the 8 bit byte at the destination address in device memory.
* \param dest - Destination pointer address
* \param msk - Bits to replace in destination byte
* \param src - Source bits to write to cleared bits in destination byte
*/
#define alt_replbits_byte(dest, msk, src) (alt_write_byte(dest,(alt_read_byte(dest) & ~(msk)) | ((src) & (msk))))
/*! Set selected bits in the 16 bit halfword at the destination address in device memory.
* \param dest - Destination pointer address
* \param bits - Bits to set in destination halfword
*/
#define alt_setbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) | (bits)))
/*! Clear selected bits in the 16 bit halfword at the destination address in device memory.
* \param dest - Destination pointer address
* \param bits - Bits to clear in destination halfword
*/
#define alt_clrbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) & ~(bits)))
/*! Change or toggle selected bits in the 16 bit halfword at the destination address in device memory.
* \param dest - Destination pointer address
* \param bits - Bits to change in destination halfword
*/
#define alt_xorbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) ^ (bits)))
/*! Replace selected bits in the 16 bit halfword at the destination address in device memory.
* \param dest - Destination pointer address
* \param msk - Bits to replace in destination halfword
* \param src - Source bits to write to cleared bits in destination halfword
*/
#define alt_replbits_hword(dest, msk, src) (alt_write_hword(dest,(alt_read_hword(dest) & ~(msk)) | ((src) & (msk))))
/*! Set selected bits in the 32 bit word at the destination address in device memory.
* \param dest - Destination pointer address
* \param bits - Bits to set in destination word
*/
#define alt_setbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) | (bits)))
/*! Clear selected bits in the 32 bit word at the destination address in device memory.
* \param dest - Destination pointer address
* \param bits - Bits to clear in destination word
*/
#define alt_clrbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) & ~(bits)))
/*! Change or toggle selected bits in the 32 bit word at the destination address in device memory.
* \param dest - Destination pointer address
* \param bits - Bits to change in destination word
*/
#define alt_xorbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) ^ (bits)))
/*! Replace selected bits in the 32 bit word at the destination address in device memory.
* \param dest - Destination pointer address
* \param msk - Bits to replace in destination word
* \param src - Source bits to write to cleared bits in destination word
*/
#define alt_replbits_word(dest, msk, src) (alt_write_word(dest,(alt_read_word(dest) & ~(msk)) | ((src) & (msk))))
/*! Set selected bits in the 64 bit doubleword at the destination address in device memory.
* \param dest - Destination pointer address
* \param bits - Bits to set in destination doubleword
*/
#define alt_setbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) | (bits)))
/*! Clear selected bits in the 64 bit doubleword at the destination address in device memory.
* \param dest - Destination pointer address
* \param bits - Bits to clear in destination doubleword
*/
#define alt_clrbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) & ~(bits)))
/*! Change or toggle selected bits in the 64 bit doubleword at the destination address in device memory.
* \param dest - Destination pointer address
* \param bits - Bits to change in destination doubleword
*/
#define alt_xorbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) ^ (bits)))
/*! Replace selected bits in the 64 bit doubleword at the destination address in device memory.
* \param dest - Destination pointer address
* \param msk - Bits to replace in destination doubleword
* \param src - Source bits to write to cleared bits in destination word
*/
#define alt_replbits_dword(dest, msk, src) (alt_write_dword(dest,(alt_read_dword(dest) & ~(msk)) | ((src) & (msk))))
/*! @} */
/*! @} */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_SOCAL_H__ */

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#include "alt_cache.h"
#include "socal/hps.h"
#include "socal/socal.h"
#include "cache_support.h"
//#include "boot_support.h"
ALT_STATUS_CODE cache_init(void) {
ALT_STATUS_CODE status = ALT_E_SUCCESS;
//
// The 13.1 release of alt_cache.c does not appear to initialize the L2
// cache latency registers properly so we'll do that here.
//
configure_L2_ram_latency();
//
// Enable the shared attribute override enable bit in the L2 aux control register
//
enable_shared_attribute_override_enable();
status = alt_cache_system_enable();
// BOOT_CHECK_STATUS;
return status;
}
ALT_STATUS_CODE cache_uninit(void) {
return alt_cache_system_disable();
}
void enable_shared_attribute_override_enable(void) {
bool l2_enabled = alt_cache_l2_is_enabled();
if (l2_enabled)
{
alt_cache_l2_disable();
}
alt_setbits_word(ALT_MPUL2_AUX_CONTROL_ADDR, SHARED_ATTRIBUTE_OVERRIDE_ENABLE_MASK);
if (l2_enabled)
{
alt_cache_l2_enable();
}
}
void configure_L2_ram_latency(void) {
bool l2_enabled = alt_cache_l2_is_enabled();
if (l2_enabled)
{
alt_cache_l2_disable();
}
alt_write_word(ALT_MPUL2_TAG_RAM_CONTROL_ADDR, ALT_MPUL2_TAG_RAM_CONTROL_VALUE);
alt_write_word(ALT_MPUL2_DATA_RAM_CONTROL_ADDR, ALT_MPUL2_DATA_RAM_CONTROL_VALUE);
if (l2_enabled)
{
alt_cache_l2_enable();
}
}
/* md5sum:ec3ba66ee5cff385248a93a050de2432 2013-09-28 20:48:16 */

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FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/fpga_support.c
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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#include "alt_fpga_manager.h"
#include "fpga_support.h"
#define printf( ... )
ALT_STATUS_CODE fpga_init(void) {
// Program the FPGA
uint32_t status = ALT_E_SUCCESS;
uint32_t i;
// This is the symbol name for the SOF file contents linked in.
extern char _binary_soc_system_dc_rbf_start;
extern char _binary_soc_system_dc_rbf_end;
// Use the above symbols to extract the FPGA image information.
const char * fpga_image = &_binary_soc_system_dc_rbf_start;
const uint32_t fpga_image_size = &_binary_soc_system_dc_rbf_end - &_binary_soc_system_dc_rbf_start;
// Trace the FPGA image information.
printf("INFO: FPGA Image binary at %p.\n", fpga_image);
printf("INFO: FPGA Image size is %u bytes.\n", (unsigned int)fpga_image_size);
// Try the full configuration a few times.
const uint32_t full_config_retry = 5;
for (i = 0; i < full_config_retry; ++i)
{
status = alt_fpga_configure(fpga_image, fpga_image_size);
if (status == ALT_E_SUCCESS)
{
printf("INFO: alt_fpga_configure() successful on the %u of %u retry(s).\n",
(unsigned int)(i + 1),
(unsigned int)full_config_retry);
break;
}
}
if (status == ALT_E_SUCCESS)
{
printf("INFO: Setup of FPGA successful.\n\n");
}
else
{
printf("ERROR: Setup of FPGA return non-SUCCESS %d.\n\n", (int)status);
}
return status;
}
/* md5sum:e268b2157060033c39e9ea2c5068165f 2013-09-28 20:48:16 */

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef CACHE_SUPPORT_H_
#define CACHE_SUPPORT_H_
#include "hwlib.h"
#define ALT_MPUL2_AUX_CONTROL_OFST 0x104
#define ALT_MPUL2_TAG_RAM_CONTROL_OFST 0x108
#define ALT_MPUL2_DATA_RAM_CONTROL_OFST 0x10c
#define ALT_MPUL2_AUX_CONTROL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_AUX_CONTROL_OFST))
#define ALT_MPUL2_TAG_RAM_CONTROL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_TAG_RAM_CONTROL_OFST))
#define ALT_MPUL2_DATA_RAM_CONTROL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_DATA_RAM_CONTROL_OFST))
#define ALT_MPUL2_TAG_RAM_CONTROL_VALUE 0x00000000
#define ALT_MPUL2_DATA_RAM_CONTROL_VALUE 0x00000010
#define SHARED_ATTRIBUTE_OVERRIDE_ENABLE_MASK 0x00400000
ALT_STATUS_CODE cache_init(void);
ALT_STATUS_CODE cache_uninit(void);
void enable_shared_attribute_override_enable(void);
void configure_L2_ram_latency(void);
#endif /* CACHE_SUPPORT_H_ */
/* md5sum:58fb245f969aec44340df388edf9806b 2013-09-28 20:48:16 */

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef FPGA_SUPPORT_H_
#define FPGA_SUPPORT_H_
#include "hwlib.h"
extern char _binary_soc_system_rbf_start;
extern char _binary_soc_system_rbf_end;
ALT_STATUS_CODE fpga_init(void);
#endif /* FPGA_SUPPORT_H_ */
/* md5sum:887b9ebee4569ce8bd823342a5ce847e 2013-09-28 20:48:16 */

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef MMU_SUPPORT_H_
#define MMU_SUPPORT_H_
#include "hwlib.h"
ALT_STATUS_CODE mmu_init(void);
ALT_STATUS_CODE mmu_uninit(void);
#endif /* MMU_SUPPORT_H_ */
/* md5sum:dfae487bb7fe641d39c46b8c06396d48 2013-09-28 20:48:16 */

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#include "alt_mmu.h"
#include "mmu_support.h"
//#include "boot_support.h"
#define ARRAY_COUNT(array) (sizeof(array) / sizeof(array[0]))
static uint32_t __attribute__ ((aligned (0x4000))) mmu_pt_storage[4096];
static void * mmu_pt_alloc(const size_t size, void * context) {
return context;
}
ALT_STATUS_CODE mmu_init(void) {
//
// Populate the page table with sections (1 MiB regions).
//
ALT_MMU_MEM_REGION_t regions[] =
{
// Cacheable Memory area: 1 GiB
{
.va = (void *)0x00000000,
.pa = (void *)0x00000000,
.size = 0x40000000,
.access = ALT_MMU_AP_FULL_ACCESS,
.attributes = ALT_MMU_ATTR_WBA,
.shareable = ALT_MMU_TTB_S_NON_SHAREABLE,
.execute = ALT_MMU_TTB_XN_DISABLE,
.security = ALT_MMU_TTB_NS_SECURE
},
// Non-cacheable Memory area: 1 GiB
{
.va = (void *)0x40000000,
.pa = (void *)0x00000000,
.size = 0x40000000,
.access = ALT_MMU_AP_FULL_ACCESS,
.attributes = ALT_MMU_ATTR_NC,
.shareable = ALT_MMU_TTB_S_SHAREABLE,
.execute = ALT_MMU_TTB_XN_DISABLE,
.security = ALT_MMU_TTB_NS_SECURE
},
// Device area: Everything else
{
.va = (void *)0x80000000,
.pa = (void *)0x40000000,
.size = 0x40000000,
.access = ALT_MMU_AP_NO_ACCESS,
.attributes = ALT_MMU_ATTR_FAULT,
.shareable = ALT_MMU_TTB_S_SHAREABLE,
.execute = ALT_MMU_TTB_XN_ENABLE,
.security = ALT_MMU_TTB_NS_SECURE
},
// Device area: Everything else
{
.va = (void *)0xC0000000,
.pa = (void *)0xC0000000,
.size = 0x40000000,
.access = ALT_MMU_AP_FULL_ACCESS,
.attributes = ALT_MMU_ATTR_DEVICE,
.shareable = ALT_MMU_TTB_S_SHAREABLE,
.execute = ALT_MMU_TTB_XN_ENABLE,
.security = ALT_MMU_TTB_NS_SECURE
}
};
ALT_STATUS_CODE status = ALT_E_SUCCESS;
uint32_t * ttb1 = NULL;
status |= alt_mmu_init();
// BOOT_CHECK_STATUS;
size_t reqsize = alt_mmu_va_space_storage_required(regions,
ARRAY_COUNT(regions));
if (reqsize > sizeof(mmu_pt_storage))
status = ALT_E_ERROR;
// BOOT_CHECK_STATUS;
status |= alt_mmu_va_space_create(&ttb1, regions, ARRAY_COUNT(regions), mmu_pt_alloc, mmu_pt_storage);
// BOOT_CHECK_STATUS;
status |= alt_mmu_va_space_enable(ttb1);
// BOOT_CHECK_STATUS;
return status;
}
ALT_STATUS_CODE mmu_uninit(void) {
return alt_mmu_disable();
}
/* md5sum:4fc6b96893e8e619490fad33b17c96d7 2013-09-28 20:48:16 */

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