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Fix build error for MSP430 and Cortex A with IAR (#937)

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* fix whitespace in asm macros

* Revert formatting ARM_CA5_No_GIC and ARM_CA9
pull/935/head^2
Jeff Tenney 1 year ago committed by GitHub
parent 58f0d36e76
commit 5544c78299
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 243 additions and 341 deletions
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165
portable/IAR/ARM_CA5_No_GIC/portASM.h
Unescape Escape View File

@ -1,30 +1,30 @@
;/* ;/*
* ; * FreeRTOS Kernel <DEVELOPMENT BRANCH> ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
* ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* ; * ; *
* ; * SPDX-License-Identifier: MIT ; * SPDX-License-Identifier: MIT
* ; * ; *
* ; * Permission is hereby granted, free of charge, to any person obtaining a copy of ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
* ; * this software and associated documentation files (the "Software"), to deal in ; * this software and associated documentation files (the "Software"), to deal in
* ; * the Software without restriction, including without limitation the rights to ; * the Software without restriction, including without limitation the rights to
* ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* ; * the Software, and to permit persons to whom the Software is furnished to do so, ; * the Software, and to permit persons to whom the Software is furnished to do so,
* ; * subject to the following conditions: ; * subject to the following conditions:
* ; * ; *
* ; * The above copyright notice and this permission notice shall be included in all ; * The above copyright notice and this permission notice shall be included in all
* ; * copies or substantial portions of the Software. ; * copies or substantial portions of the Software.
* ; * ; *
* ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* ; * ; *
* ; * https://www.FreeRTOS.org ; * https://www.FreeRTOS.org
* ; * https://github.com/FreeRTOS ; * https://github.com/FreeRTOS
* ; * ; *
* ; */ ; */
EXTERN vTaskSwitchContext EXTERN vTaskSwitchContext
EXTERN ulCriticalNesting EXTERN ulCriticalNesting
@ -34,58 +34,35 @@ EXTERN ulAsmAPIPriorityMask
portSAVE_CONTEXT macro portSAVE_CONTEXT macro
; ; Save the LR and SPSR onto the system mode stack before switching to
Save the LR and SPSR onto the system mode stack before switching to ; system mode to save the remaining system mode registers
;
system mode to save the remaining system mode registers
SRSDB sp!, #SYS_MODE SRSDB sp!, #SYS_MODE
CPS #SYS_MODE CPS #SYS_MODE
PUSH { PUSH {R0-R12, R14}
R0 - R12, R14
}
; ; Push the critical nesting count
Push the critical nesting count
LDR R2, =ulCriticalNesting LDR R2, =ulCriticalNesting
LDR R1, [R2] LDR R1, [R2]
PUSH { PUSH {R1}
R1
} ; Does the task have a floating point context that needs saving? If
; ulPortTaskHasFPUContext is 0 then no.
;
Does the task have a floating point context that needs saving ? If
;
ulPortTaskHasFPUContext is 0 then no.
LDR R2, =ulPortTaskHasFPUContext LDR R2, =ulPortTaskHasFPUContext
LDR R3, [R2] LDR R3, [R2]
CMP R3, #0 CMP R3, #0
; ; Save the floating point context, if any
Save the floating point context,
if any
FMRXNE R1, FPSCR FMRXNE R1, FPSCR
VPUSHNE { VPUSHNE {D0-D15}
D0 - D15
}
#if configFPU_D32 == 1 #if configFPU_D32 == 1
VPUSHNE { VPUSHNE {D16-D31}
D16 - D31
}
#endif ; configFPU_D32 #endif ; configFPU_D32
PUSHNE { PUSHNE {R1}
R1
} ; Save ulPortTaskHasFPUContext itself
PUSH {R3}
;
Save ulPortTaskHasFPUContext itself ; Save the stack pointer in the TCB
PUSH {
R3
}
;
Save the stack pointer in the TCB
LDR R0, =pxCurrentTCB LDR R0, =pxCurrentTCB
LDR R1, [R0] LDR R1, [R0]
STR SP, [R1] STR SP, [R1]
@ -96,63 +73,37 @@ endm
portRESTORE_CONTEXT macro portRESTORE_CONTEXT macro
; ; Set the SP to point to the stack of the task being restored.
Set the SP to point to the stack of the task being restored.
LDR R0, =pxCurrentTCB LDR R0, =pxCurrentTCB
LDR R1, [R0] LDR R1, [R0]
LDR SP, [R1] LDR SP, [R1]
; ; Is there a floating point context to restore? If the restored
Is there a floating point context to restore ? If the restored ; ulPortTaskHasFPUContext is zero then no.
;
ulPortTaskHasFPUContext is zero then no.
LDR R0, =ulPortTaskHasFPUContext LDR R0, =ulPortTaskHasFPUContext
POP { POP {R1}
R1
}
STR R1, [R0] STR R1, [R0]
CMP R1, #0 CMP R1, #0
; ; Restore the floating point context, if any
Restore the floating point context, POPNE {R0}
if any
POPNE {
R0
}
#if configFPU_D32 == 1 #if configFPU_D32 == 1
VPOPNE { VPOPNE {D16-D31}
D16 - D31
}
#endif ; configFPU_D32 #endif ; configFPU_D32
VPOPNE { VPOPNE {D0-D15}
D0 - D15
}
VMSRNE FPSCR, R0 VMSRNE FPSCR, R0
; ; Restore the critical section nesting depth
Restore the critical section nesting depth
LDR R0, =ulCriticalNesting LDR R0, =ulCriticalNesting
POP { POP {R1}
R1
}
STR R1, [R0] STR R1, [R0]
; ; Restore all system mode registers other than the SP (which is already
Restore all system mode registers other than the SP( which is already ; being used)
; POP {R0-R12, R14}
being used )
POP
{
R0 - R12, R14
}
Return to the task code, loading CPSR on the way.CPSR has the interrupt
;
enable bit set appropriately
for the task about to execute. ; Return to the task code, loading CPSR on the way. CPSR has the interrupt
; enable bit set appropriately for the task about to execute.
RFEIA sp! RFEIA sp!
endm endm

165
portable/IAR/ARM_CA9/portASM.h
Unescape Escape View File

@ -1,30 +1,30 @@
;/* ;/*
* ; * FreeRTOS Kernel <DEVELOPMENT BRANCH> ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
* ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* ; * ; *
* ; * SPDX-License-Identifier: MIT ; * SPDX-License-Identifier: MIT
* ; * ; *
* ; * Permission is hereby granted, free of charge, to any person obtaining a copy of ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
* ; * this software and associated documentation files (the "Software"), to deal in ; * this software and associated documentation files (the "Software"), to deal in
* ; * the Software without restriction, including without limitation the rights to ; * the Software without restriction, including without limitation the rights to
* ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* ; * the Software, and to permit persons to whom the Software is furnished to do so, ; * the Software, and to permit persons to whom the Software is furnished to do so,
* ; * subject to the following conditions: ; * subject to the following conditions:
* ; * ; *
* ; * The above copyright notice and this permission notice shall be included in all ; * The above copyright notice and this permission notice shall be included in all
* ; * copies or substantial portions of the Software. ; * copies or substantial portions of the Software.
* ; * ; *
* ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* ; * ; *
* ; * https://www.FreeRTOS.org ; * https://www.FreeRTOS.org
* ; * https://github.com/FreeRTOS ; * https://github.com/FreeRTOS
* ; * ; *
* ; */ ; */
EXTERN vTaskSwitchContext EXTERN vTaskSwitchContext
EXTERN ulCriticalNesting EXTERN ulCriticalNesting
@ -34,56 +34,33 @@ EXTERN ulAsmAPIPriorityMask
portSAVE_CONTEXT macro portSAVE_CONTEXT macro
; ; Save the LR and SPSR onto the system mode stack before switching to
Save the LR and SPSR onto the system mode stack before switching to ; system mode to save the remaining system mode registers
;
system mode to save the remaining system mode registers
SRSDB sp!, #SYS_MODE SRSDB sp!, #SYS_MODE
CPS #SYS_MODE CPS #SYS_MODE
PUSH { PUSH {R0-R12, R14}
R0 - R12, R14
}
; ; Push the critical nesting count
Push the critical nesting count
LDR R2, =ulCriticalNesting LDR R2, =ulCriticalNesting
LDR R1, [R2] LDR R1, [R2]
PUSH { PUSH {R1}
R1
} ; Does the task have a floating point context that needs saving? If
; ulPortTaskHasFPUContext is 0 then no.
;
Does the task have a floating point context that needs saving ? If
;
ulPortTaskHasFPUContext is 0 then no.
LDR R2, =ulPortTaskHasFPUContext LDR R2, =ulPortTaskHasFPUContext
LDR R3, [R2] LDR R3, [R2]
CMP R3, #0 CMP R3, #0
; ; Save the floating point context, if any
Save the floating point context,
if any
FMRXNE R1, FPSCR FMRXNE R1, FPSCR
VPUSHNE { VPUSHNE {D0-D15}
D0 - D15 VPUSHNE {D16-D31}
} PUSHNE {R1}
VPUSHNE { ; Save ulPortTaskHasFPUContext itself
D16 - D31 PUSH {R3}
}
PUSHNE { ; Save the stack pointer in the TCB
R1
}
;
Save ulPortTaskHasFPUContext itself
PUSH {
R3
}
;
Save the stack pointer in the TCB
LDR R0, =pxCurrentTCB LDR R0, =pxCurrentTCB
LDR R1, [R0] LDR R1, [R0]
STR SP, [R1] STR SP, [R1]
@ -94,67 +71,41 @@ endm
portRESTORE_CONTEXT macro portRESTORE_CONTEXT macro
; ; Set the SP to point to the stack of the task being restored.
Set the SP to point to the stack of the task being restored.
LDR R0, =pxCurrentTCB LDR R0, =pxCurrentTCB
LDR R1, [R0] LDR R1, [R0]
LDR SP, [R1] LDR SP, [R1]
; ; Is there a floating point context to restore? If the restored
Is there a floating point context to restore ? If the restored ; ulPortTaskHasFPUContext is zero then no.
;
ulPortTaskHasFPUContext is zero then no.
LDR R0, =ulPortTaskHasFPUContext LDR R0, =ulPortTaskHasFPUContext
POP { POP {R1}
R1
}
STR R1, [R0] STR R1, [R0]
CMP R1, #0 CMP R1, #0
; ; Restore the floating point context, if any
Restore the floating point context, POPNE {R0}
VPOPNE {D16-D31}
if any VPOPNE {D0-D15}
POPNE {
R0
}
VPOPNE {
D16 - D31
}
VPOPNE {
D0 - D15
}
VMSRNE FPSCR, R0 VMSRNE FPSCR, R0
; ; Restore the critical section nesting depth
Restore the critical section nesting depth
LDR R0, =ulCriticalNesting LDR R0, =ulCriticalNesting
POP { POP {R1}
R1
}
STR R1, [R0] STR R1, [R0]
; ; Ensure the priority mask is correct for the critical nesting depth
Ensure the priority mask is correct
for the critical nesting depth
LDR R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS LDR R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS
CMP R1, #0 CMP R1, #0
MOVEQ R4, #255 MOVEQ R4, #255
LDRNE R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) LDRNE R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )
STR R4, [r2] STR R4, [r2]
; ; Restore all system mode registers other than the SP (which is already
Restore all system mode registers other than the SP( which is already ; being used)
; POP {R0-R12, R14}
being used )
POP
{
R0 - R12, R14
}
Return to the task code, loading CPSR on the way. ; Return to the task code, loading CPSR on the way.
RFEIA sp! RFEIA sp!
endm endm

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