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@ -83,7 +83,7 @@ const unsigned portLONG ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;
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/* Each task maintains its own interrupt status in the critical nesting
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variable. */
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unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;
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static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;
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/*
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* Setup the timer to generate the tick interrupts.
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@ -118,8 +118,7 @@ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE
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*pxTopOfStack = 0; /* LR */
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pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
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pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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*pxTopOfStack = 0x00000000; /* uxCriticalNesting. */
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pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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return pxTopOfStack;
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}
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@ -131,9 +130,7 @@ void vPortSVCHandler( void )
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" ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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" ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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" ldmia r0!, {r1, r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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" ldr r2, uxCriticalNestingConst2 \n" /* Restore the critical nesting count used by the task. */
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" str r1, [r2] \n"
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" ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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" msr psp, r0 \n" /* Restore the task stack pointer. */
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" mov r0, #0 \n"
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" msr basepri, r0 \n"
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@ -142,7 +139,6 @@ void vPortSVCHandler( void )
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" \n"
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" .align 2 \n"
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"pxCurrentTCBConst2: .word pxCurrentTCB \n"
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"uxCriticalNestingConst2: .word uxCriticalNesting \n"
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);
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}
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/*-----------------------------------------------------------*/
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@ -154,6 +150,9 @@ void vPortStartFirstTask( unsigned long ulValue )
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( void ) ulValue;
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asm volatile(
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" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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" ldr r0, [r0] \n"
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" ldr r0, [r0] \n"
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" msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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" svc 0 \n" /* System call to start first task. */
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);
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@ -173,6 +172,9 @@ portBASE_TYPE xPortStartScheduler( void )
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here already. */
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prvSetupTimerInterrupt();
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/* Initialise the critical nesting count ready for the first task. */
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uxCriticalNesting = 0;
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/* Start the first task. */
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vPortStartFirstTask( *((unsigned portLONG *) 0 ) );
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@ -192,10 +194,6 @@ void vPortYieldFromISR( void )
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{
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/* Set a PendSV to request a context switch. */
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*(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;
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/* This function is also called in response to a Yield(), so we want
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the yield to occur immediately. */
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portENABLE_INTERRUPTS();
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}
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/*-----------------------------------------------------------*/
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@ -227,35 +225,26 @@ void xPortPendSVHandler( void )
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" ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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" ldr r2, [r3] \n"
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" \n"
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" ldr r1, uxCriticalNestingConst \n" /* Save the remaining registers and the critical nesting count onto the task stack. */
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" ldr r1, [r1] \n"
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" stmdb r0!, {r1,r4-r11} \n"
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" stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */
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" str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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" \n"
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" stmdb sp!, {r3, r14} \n"
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" mov r0, %0 \n"
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" msr basepri, r0 \n"
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" bl vTaskSwitchContext \n"
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" mov r0, #0 \n"
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" msr basepri, r0 \n"
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" ldmia sp!, {r3, r14} \n"
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" \n" /* Restore the context, including the critical nesting count. */
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" ldr r1, [r3] \n"
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" ldr r2, uxCriticalNestingConst \n"
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" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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" ldmia r0!, {r1, r4-r11} \n" /* Pop the registers and the critical nesting count. */
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" str r1, [r2] \n" /* Save the new critical nesting value into ulCriticalNesting. */
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" ldmia r0!, {r4-r11} \n" /* Pop the registers. */
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" msr psp, r0 \n"
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" orr r14, #0xd \n"
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" \n" /* Exit with interrupts in the state required by the task. */
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" cbnz r1, sv_disable_interrupts \n" /* If the nesting count is greater than 0 we need to exit with interrupts masked. */
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" bx r14 \n"
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" \n"
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"sv_disable_interrupts: \n"
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" ldr r1, =ulKernelPriority \n"
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" ldr r1, [r1] \n"
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" msr basepri, r1 \n"
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" bx r14 \n"
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" \n"
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" .align 2 \n"
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"pxCurrentTCBConst: .word pxCurrentTCB \n"
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"uxCriticalNestingConst: .word uxCriticalNesting \n"
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::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
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);
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}
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/*-----------------------------------------------------------*/
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@ -267,7 +256,11 @@ void xPortSysTickHandler( void )
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*(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;
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#endif
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portSET_INTERRUPT_MASK_FROM_ISR();
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{
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vTaskIncrementTick();
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}
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portCLEAR_INTERRUPT_MASK_FROM_ISR();
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}
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/*-----------------------------------------------------------*/
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