Work-in-progress check in of MicroBlaze Kintex7 demo.
Richard Barry
10 years ago
parent
96e72413f7
commit
3012d9b94d
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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<storageModule moduleId="org.eclipse.cdt.core.settings">
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<cconfiguration id="org.eclipse.cdt.core.default.config.1741365255">
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<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1741365255" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
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<externalSettings/>
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<extensions/>
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</storageModule>
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<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
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</cconfiguration>
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</storageModule>
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<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
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</cproject>
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@ -0,0 +1,76 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<projectDescription>
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<name>BSP</name>
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<comment>Created by SDK v2014.4</comment>
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<projects>
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<project>Hardware</project>
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</projects>
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<buildSpec>
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<buildCommand>
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<name>org.eclipse.cdt.make.core.makeBuilder</name>
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<arguments>
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<dictionary>
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||||||
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<key>org.eclipse.cdt.core.errorOutputParser</key>
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<value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.append_environment</key>
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<value>true</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.build.arguments</key>
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<value></value>
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</dictionary>
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||||||
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<dictionary>
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||||||
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<key>org.eclipse.cdt.make.core.build.command</key>
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<value>make</value>
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</dictionary>
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<dictionary>
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||||||
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<key>org.eclipse.cdt.make.core.build.target.auto</key>
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<value>all</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.build.target.clean</key>
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<value>clean</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.build.target.inc</key>
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<value>all</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
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<value>true</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
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<value>true</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.enableFullBuild</key>
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<value>true</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
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<value>true</value>
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</dictionary>
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<dictionary>
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||||||
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<key>org.eclipse.cdt.make.core.environment</key>
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<value></value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.stopOnError</key>
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<value>false</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
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<value>true</value>
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</dictionary>
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</arguments>
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</buildCommand>
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</buildSpec>
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<natures>
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<nature>com.xilinx.sdk.sw.SwProjectNature</nature>
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<nature>org.eclipse.cdt.core.cnature</nature>
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<nature>org.eclipse.cdt.make.core.makeNature</nature>
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</natures>
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</projectDescription>
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@ -0,0 +1,3 @@
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THIRPARTY=false
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PROCESSOR=microblaze_0
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MSS_FILE=system.mss
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# Makefile generated by Xilinx.
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PROCESSOR = microblaze_0
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LIBRARIES = ${PROCESSOR}/lib/libxil.a
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BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
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SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
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ifneq (,$(findstring win,$(RDI_PLATFORM)))
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SHELL = CMD
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endif
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all: libs
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@echo 'Finished building libraries'
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include: $(addsuffix /make.include,$(SUBDIRS))
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libs: $(addsuffix /make.libs,$(SUBDIRS))
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$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
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cp -f $< $@
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%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
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@echo "Running Make include in $(subst /make.include,,$@)"
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$(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v9.4 -mhard-float -mlittle-endian -mno-xl-soft-div -mno-xl-soft-mul -mxl-barrel-shift -mxl-float-convert -mxl-float-sqrt -mxl-multiply-high -mxl-pattern-compare" "EXTRA_COMPILER_FLAGS=-g -ffunction-sections -fdata-sections"
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%/make.libs: include
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@echo "Running Make libs in $(subst /make.libs,,$@)"
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$(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v9.4 -mhard-float -mlittle-endian -mno-xl-soft-div -mno-xl-soft-mul -mxl-barrel-shift -mxl-float-convert -mxl-float-sqrt -mxl-multiply-high -mxl-pattern-compare" "EXTRA_COMPILER_FLAGS=-g -ffunction-sections -fdata-sections"
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clean:
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rm -f ${PROCESSOR}/lib/libxil.a
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@ -0,0 +1,78 @@
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PARAMETER NAME = C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\MicroBlaze_Kintex7_EthernetLite\BSP\system.mss
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PARAMETER VERSION = 2.2.0
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BEGIN OS
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PARAMETER OS_NAME = standalone
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PARAMETER OS_VER = 4.2
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PARAMETER PROC_INSTANCE = microblaze_0
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PARAMETER stdin = axi_uartlite_0
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PARAMETER stdout = axi_uartlite_0
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END
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BEGIN PROCESSOR
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PARAMETER DRIVER_NAME = cpu
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PARAMETER DRIVER_VER = 2.2
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PARAMETER HW_INSTANCE = microblaze_0
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END
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BEGIN DRIVER
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PARAMETER DRIVER_NAME = emaclite
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PARAMETER DRIVER_VER = 4.0
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PARAMETER HW_INSTANCE = axi_ethernetlite_0
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END
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BEGIN DRIVER
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PARAMETER DRIVER_NAME = gpio
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PARAMETER DRIVER_VER = 4.0
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PARAMETER HW_INSTANCE = axi_gpio_0
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END
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BEGIN DRIVER
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PARAMETER DRIVER_NAME = intc
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PARAMETER DRIVER_VER = 3.2
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PARAMETER HW_INSTANCE = axi_intc_0
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END
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BEGIN DRIVER
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PARAMETER DRIVER_NAME = tmrctr
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PARAMETER DRIVER_VER = 3.0
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PARAMETER HW_INSTANCE = axi_timer_0
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END
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BEGIN DRIVER
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PARAMETER DRIVER_NAME = uartlite
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PARAMETER DRIVER_VER = 3.0
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PARAMETER HW_INSTANCE = axi_uartlite_0
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END
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BEGIN DRIVER
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PARAMETER DRIVER_NAME = bram
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PARAMETER DRIVER_VER = 4.0
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PARAMETER HW_INSTANCE = microblaze_0_local_memory_dlmb_bram_if_cntlr
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END
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BEGIN DRIVER
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PARAMETER DRIVER_NAME = bram
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PARAMETER DRIVER_VER = 4.0
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PARAMETER HW_INSTANCE = microblaze_0_local_memory_ilmb_bram_if_cntlr
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END
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BEGIN DRIVER
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PARAMETER DRIVER_NAME = mig_7series
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PARAMETER DRIVER_VER = 2.0
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PARAMETER HW_INSTANCE = mig_7series_0
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END
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BEGIN LIBRARY
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PARAMETER LIBRARY_NAME = lwip140
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PARAMETER LIBRARY_VER = 2.3
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PARAMETER PROC_INSTANCE = microblaze_0
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END
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@ -0,0 +1,68 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<projectDescription>
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<name>Hardware</name>
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<comment>Created by SDK v2014.4</comment>
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<projects>
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</projects>
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<buildSpec>
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</buildSpec>
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<natures>
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<nature>com.xilinx.sdk.hw.HwProject</nature>
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</natures>
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<filteredResources>
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<filter>
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<id>1421760060412</id>
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<name></name>
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<type>6</type>
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<matcher>
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<id>org.eclipse.ui.ide.multiFilter</id>
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<arguments>1.0-name-matches-false-false-*.xml</arguments>
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</matcher>
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</filter>
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<filter>
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<id>1421760060422</id>
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<name></name>
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<type>6</type>
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<matcher>
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<id>org.eclipse.ui.ide.multiFilter</id>
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<arguments>1.0-name-matches-false-false-*.svd</arguments>
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</matcher>
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</filter>
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<filter>
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<id>1421760060432</id>
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<name></name>
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<type>6</type>
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<matcher>
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<id>org.eclipse.ui.ide.multiFilter</id>
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<arguments>1.0-name-matches-false-false-*.hwh</arguments>
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</matcher>
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</filter>
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<filter>
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<id>1421760060432</id>
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<name></name>
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<type>6</type>
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<matcher>
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<id>org.eclipse.ui.ide.multiFilter</id>
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<arguments>1.0-name-matches-false-false-*.bit</arguments>
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</matcher>
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</filter>
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<filter>
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<id>1421760060442</id>
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<name></name>
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<type>6</type>
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<matcher>
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<id>org.eclipse.ui.ide.multiFilter</id>
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<arguments>1.0-name-matches-false-false-*.bmm</arguments>
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</matcher>
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</filter>
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<filter>
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<id>1421760060442</id>
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<name></name>
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<type>6</type>
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<matcher>
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<id>org.eclipse.ui.ide.multiFilter</id>
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<arguments>1.0-name-matches-false-false-*.mmi</arguments>
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</matcher>
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</filter>
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</filteredResources>
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</projectDescription>
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,360 @@
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################################################################
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# This is a generated script based on design: base_microblaze_design
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2014.4
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
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return 1
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}
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################################################################
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# START
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################################################################
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# To test this script, run the following commands from Vivado Tcl console:
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# source base_microblaze_design_script.tcl
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# If you do not already have a project created,
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# you can create a project using the following command:
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# create_project project_1 myproj -part xc7k325tffg900-2
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# set_property BOARD_PART xilinx.com:kc705:part0:1.1 [current_project]
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# CHANGE DESIGN NAME HERE
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set design_name base_microblaze_design
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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# create_bd_design $design_name
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# CHECKING IF PROJECT EXISTS
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if { [get_projects -quiet] eq "" } {
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puts "ERROR: Please open or create a project!"
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return 1
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}
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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# USE CASES:
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# 1) Design_name not set
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set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
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set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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# USE CASES:
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# 2): Current design opened AND is empty AND names same.
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# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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puts "INFO: Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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# 5) Current design opened AND has components AND same names.
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set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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# USE CASES:
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# 6) Current opened design, has components, but diff names, design_name exists in project.
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# 7) No opened design, design_name exists in project.
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||||||
|
set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||||
|
set nRet 2
|
||||||
|
|
||||||
|
} else {
|
||||||
|
# USE CASES:
|
||||||
|
# 8) No opened design, design_name not in project.
|
||||||
|
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||||
|
|
||||||
|
puts "INFO: Currently there is no design <$design_name> in project, so creating one..."
|
||||||
|
|
||||||
|
create_bd_design $design_name
|
||||||
|
|
||||||
|
puts "INFO: Making design <$design_name> as current_bd_design."
|
||||||
|
current_bd_design $design_name
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."
|
||||||
|
|
||||||
|
if { $nRet != 0 } {
|
||||||
|
puts $errMsg
|
||||||
|
return $nRet
|
||||||
|
}
|
||||||
|
|
||||||
|
##################################################################
|
||||||
|
# DESIGN PROCs
|
||||||
|
##################################################################
|
||||||
|
|
||||||
|
|
||||||
|
# Hierarchical cell: microblaze_0_local_memory
|
||||||
|
proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } {
|
||||||
|
|
||||||
|
if { $parentCell eq "" || $nameHier eq "" } {
|
||||||
|
puts "ERROR: create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!"
|
||||||
|
return
|
||||||
|
}
|
||||||
|
|
||||||
|
# Get object for parentCell
|
||||||
|
set parentObj [get_bd_cells $parentCell]
|
||||||
|
if { $parentObj == "" } {
|
||||||
|
puts "ERROR: Unable to find parent cell <$parentCell>!"
|
||||||
|
return
|
||||||
|
}
|
||||||
|
|
||||||
|
# Make sure parentObj is hier blk
|
||||||
|
set parentType [get_property TYPE $parentObj]
|
||||||
|
if { $parentType ne "hier" } {
|
||||||
|
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
|
||||||
|
return
|
||||||
|
}
|
||||||
|
|
||||||
|
# Save current instance; Restore later
|
||||||
|
set oldCurInst [current_bd_instance .]
|
||||||
|
|
||||||
|
# Set parent object as current
|
||||||
|
current_bd_instance $parentObj
|
||||||
|
|
||||||
|
# Create cell and set as current instance
|
||||||
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
||||||
|
current_bd_instance $hier_obj
|
||||||
|
|
||||||
|
# Create interface pins
|
||||||
|
create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB
|
||||||
|
create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB
|
||||||
|
|
||||||
|
# Create pins
|
||||||
|
create_bd_pin -dir I -type clk LMB_Clk
|
||||||
|
create_bd_pin -dir I -from 0 -to 0 -type rst LMB_Rst
|
||||||
|
|
||||||
|
# Create instance: dlmb_bram_if_cntlr, and set properties
|
||||||
|
set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ]
|
||||||
|
set_property -dict [ list CONFIG.C_ECC {0} ] $dlmb_bram_if_cntlr
|
||||||
|
|
||||||
|
# Create instance: dlmb_v10, and set properties
|
||||||
|
set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ]
|
||||||
|
|
||||||
|
# Create instance: ilmb_bram_if_cntlr, and set properties
|
||||||
|
set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ]
|
||||||
|
set_property -dict [ list CONFIG.C_ECC {0} ] $ilmb_bram_if_cntlr
|
||||||
|
|
||||||
|
# Create instance: ilmb_v10, and set properties
|
||||||
|
set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ]
|
||||||
|
|
||||||
|
# Create instance: lmb_bram, and set properties
|
||||||
|
set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 lmb_bram ]
|
||||||
|
set_property -dict [ list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller} ] $lmb_bram
|
||||||
|
|
||||||
|
# Create interface connections
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M]
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0]
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA]
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M]
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0]
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB]
|
||||||
|
|
||||||
|
# Create port connections
|
||||||
|
connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk]
|
||||||
|
connect_bd_net -net microblaze_0_LMB_Rst [get_bd_pins LMB_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst]
|
||||||
|
|
||||||
|
# Restore current instance
|
||||||
|
current_bd_instance $oldCurInst
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
# Procedure to create entire design; Provide argument to make
|
||||||
|
# procedure reusable. If parentCell is "", will use root.
|
||||||
|
proc create_root_design { parentCell } {
|
||||||
|
|
||||||
|
if { $parentCell eq "" } {
|
||||||
|
set parentCell [get_bd_cells /]
|
||||||
|
}
|
||||||
|
|
||||||
|
# Get object for parentCell
|
||||||
|
set parentObj [get_bd_cells $parentCell]
|
||||||
|
if { $parentObj == "" } {
|
||||||
|
puts "ERROR: Unable to find parent cell <$parentCell>!"
|
||||||
|
return
|
||||||
|
}
|
||||||
|
|
||||||
|
# Make sure parentObj is hier blk
|
||||||
|
set parentType [get_property TYPE $parentObj]
|
||||||
|
if { $parentType ne "hier" } {
|
||||||
|
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
|
||||||
|
return
|
||||||
|
}
|
||||||
|
|
||||||
|
# Save current instance; Restore later
|
||||||
|
set oldCurInst [current_bd_instance .]
|
||||||
|
|
||||||
|
# Set parent object as current
|
||||||
|
current_bd_instance $parentObj
|
||||||
|
|
||||||
|
|
||||||
|
# Create interface ports
|
||||||
|
set ddr3_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3_sdram ]
|
||||||
|
set led_8bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 led_8bits ]
|
||||||
|
set mdio_mdc [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio_mdc ]
|
||||||
|
set mii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mii_rtl:1.0 mii ]
|
||||||
|
set rs232_uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 rs232_uart ]
|
||||||
|
set sys_diff_clock [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_diff_clock ]
|
||||||
|
|
||||||
|
# Create ports
|
||||||
|
set reset [ create_bd_port -dir I -type rst reset ]
|
||||||
|
set_property -dict [ list CONFIG.POLARITY {ACTIVE_HIGH} ] $reset
|
||||||
|
|
||||||
|
# Create instance: axi_ethernetlite_0, and set properties
|
||||||
|
set axi_ethernetlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernetlite:3.0 axi_ethernetlite_0 ]
|
||||||
|
set_property -dict [ list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc} CONFIG.MII_BOARD_INTERFACE {mii} CONFIG.USE_BOARD_FLOW {true} ] $axi_ethernetlite_0
|
||||||
|
|
||||||
|
# Create instance: axi_gpio_0, and set properties
|
||||||
|
set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
|
||||||
|
set_property -dict [ list CONFIG.GPIO_BOARD_INTERFACE {led_8bits} CONFIG.USE_BOARD_FLOW {true} ] $axi_gpio_0
|
||||||
|
|
||||||
|
# Create instance: axi_intc_0, and set properties
|
||||||
|
set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ]
|
||||||
|
|
||||||
|
# Create instance: axi_mem_intercon, and set properties
|
||||||
|
set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ]
|
||||||
|
set_property -dict [ list CONFIG.NUM_MI {1} CONFIG.NUM_SI {2} ] $axi_mem_intercon
|
||||||
|
|
||||||
|
# Create instance: axi_timer_0, and set properties
|
||||||
|
set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
|
||||||
|
|
||||||
|
# Create instance: axi_uartlite_0, and set properties
|
||||||
|
set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
|
||||||
|
set_property -dict [ list CONFIG.C_BAUDRATE {115200} CONFIG.UARTLITE_BOARD_INTERFACE {rs232_uart} CONFIG.USE_BOARD_FLOW {true} ] $axi_uartlite_0
|
||||||
|
|
||||||
|
# Create instance: mdm_1, and set properties
|
||||||
|
set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ]
|
||||||
|
|
||||||
|
# Create instance: microblaze_0, and set properties
|
||||||
|
set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.4 microblaze_0 ]
|
||||||
|
set_property -dict [ list CONFIG.C_CACHE_BYTE_SIZE {32768} \
|
||||||
|
CONFIG.C_DCACHE_BYTE_SIZE {32768} CONFIG.C_DCACHE_LINE_LEN {8} \
|
||||||
|
CONFIG.C_DCACHE_USE_WRITEBACK {1} CONFIG.C_DCACHE_VICTIMS {8} \
|
||||||
|
CONFIG.C_DEBUG_ENABLED {1} CONFIG.C_DIV_ZERO_EXCEPTION {1} \
|
||||||
|
CONFIG.C_D_AXI {1} CONFIG.C_D_LMB {1} \
|
||||||
|
CONFIG.C_FPU_EXCEPTION {1} CONFIG.C_ICACHE_LINE_LEN {8} \
|
||||||
|
CONFIG.C_ICACHE_STREAMS {1} CONFIG.C_ICACHE_VICTIMS {8} \
|
||||||
|
CONFIG.C_ILL_OPCODE_EXCEPTION {1} CONFIG.C_I_LMB {1} \
|
||||||
|
CONFIG.C_M_AXI_D_BUS_EXCEPTION {1} CONFIG.C_M_AXI_I_BUS_EXCEPTION {1} \
|
||||||
|
CONFIG.C_NUMBER_OF_PC_BRK {8} CONFIG.C_NUMBER_OF_RD_ADDR_BRK {2} \
|
||||||
|
CONFIG.C_NUMBER_OF_WR_ADDR_BRK {2} CONFIG.C_OPCODE_0x0_ILLEGAL {1} \
|
||||||
|
CONFIG.C_TRACE {1} CONFIG.C_UNALIGNED_EXCEPTIONS {1} \
|
||||||
|
CONFIG.C_USE_BARREL {1} CONFIG.C_USE_BRANCH_TARGET_CACHE {1} \
|
||||||
|
CONFIG.C_USE_DCACHE {1} CONFIG.C_USE_DIV {1} \
|
||||||
|
CONFIG.C_USE_FPU {2} CONFIG.C_USE_HW_MUL {2} \
|
||||||
|
CONFIG.C_USE_ICACHE {1} CONFIG.C_USE_MSR_INSTR {1} \
|
||||||
|
CONFIG.C_USE_PCMP_INSTR {1} CONFIG.C_USE_REORDER_INSTR {1} \
|
||||||
|
CONFIG.C_USE_STACK_PROTECTION {1} CONFIG.G_TEMPLATE_LIST {2} \
|
||||||
|
CONFIG.G_USE_EXCEPTIONS {1} ] $microblaze_0
|
||||||
|
|
||||||
|
# Create instance: microblaze_0_axi_periph, and set properties
|
||||||
|
set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ]
|
||||||
|
set_property -dict [ list CONFIG.NUM_MI {5} CONFIG.NUM_SI {1} ] $microblaze_0_axi_periph
|
||||||
|
|
||||||
|
# Create instance: microblaze_0_local_memory
|
||||||
|
create_hier_cell_microblaze_0_local_memory [current_bd_instance .] microblaze_0_local_memory
|
||||||
|
|
||||||
|
# Create instance: mig_7series_0, and set properties
|
||||||
|
set mig_7series_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 mig_7series_0 ]
|
||||||
|
set_property -dict [ list CONFIG.BOARD_MIG_PARAM {ddr3_sdram} CONFIG.RESET_BOARD_INTERFACE {reset} ] $mig_7series_0
|
||||||
|
|
||||||
|
# Create instance: rst_clk_wiz_1_100M, and set properties
|
||||||
|
set rst_clk_wiz_1_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_1_100M ]
|
||||||
|
set_property -dict [ list CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.USE_BOARD_FLOW {true} ] $rst_clk_wiz_1_100M
|
||||||
|
|
||||||
|
# Create instance: xlconcat_0, and set properties
|
||||||
|
set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
|
||||||
|
set_property -dict [ list CONFIG.NUM_PORTS {3} ] $xlconcat_0
|
||||||
|
|
||||||
|
# Create interface connections
|
||||||
|
connect_bd_intf_net -intf_net SYS_CLK_1 [get_bd_intf_ports sys_diff_clock] [get_bd_intf_pins mig_7series_0/SYS_CLK]
|
||||||
|
connect_bd_intf_net -intf_net axi_ethernetlite_0_MDIO [get_bd_intf_ports mdio_mdc] [get_bd_intf_pins axi_ethernetlite_0/MDIO]
|
||||||
|
connect_bd_intf_net -intf_net axi_ethernetlite_0_MII [get_bd_intf_ports mii] [get_bd_intf_pins axi_ethernetlite_0/MII]
|
||||||
|
connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports led_8bits] [get_bd_intf_pins axi_gpio_0/GPIO]
|
||||||
|
connect_bd_intf_net -intf_net axi_intc_0_interrupt [get_bd_intf_pins axi_intc_0/interrupt] [get_bd_intf_pins microblaze_0/INTERRUPT]
|
||||||
|
connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins mig_7series_0/S_AXI]
|
||||||
|
connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_ports rs232_uart] [get_bd_intf_pins axi_uartlite_0/UART]
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_M_AXI_DC [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins microblaze_0/M_AXI_DC]
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_M_AXI_DP [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI]
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_M_AXI_IC [get_bd_intf_pins axi_mem_intercon/S01_AXI] [get_bd_intf_pins microblaze_0/M_AXI_IC]
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_axi_periph_M00_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI]
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_axi_periph_M01_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI]
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_axi_periph_M02_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI]
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_axi_periph_M03_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M03_AXI]
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_axi_periph_M04_AXI [get_bd_intf_pins axi_ethernetlite_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M04_AXI]
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG]
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB]
|
||||||
|
connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB]
|
||||||
|
connect_bd_intf_net -intf_net mig_7series_0_DDR3 [get_bd_intf_ports ddr3_sdram] [get_bd_intf_pins mig_7series_0/DDR3]
|
||||||
|
|
||||||
|
# Create port connections
|
||||||
|
connect_bd_net -net axi_ethernetlite_0_ip2intc_irpt [get_bd_pins axi_ethernetlite_0/ip2intc_irpt] [get_bd_pins xlconcat_0/In2]
|
||||||
|
connect_bd_net -net axi_timer_0_interrupt [get_bd_pins axi_timer_0/interrupt] [get_bd_pins xlconcat_0/In0]
|
||||||
|
connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins xlconcat_0/In1]
|
||||||
|
connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_clk_wiz_1_100M/mb_debug_sys_rst]
|
||||||
|
connect_bd_net -net microblaze_0_Clk [get_bd_pins axi_ethernetlite_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_mem_intercon/S01_ACLK] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/M03_ACLK] [get_bd_pins microblaze_0_axi_periph/M04_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins rst_clk_wiz_1_100M/slowest_sync_clk]
|
||||||
|
connect_bd_net -net mig_7series_0_mmcm_locked [get_bd_pins mig_7series_0/mmcm_locked] [get_bd_pins rst_clk_wiz_1_100M/dcm_locked]
|
||||||
|
connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_pins mig_7series_0/ui_clk_sync_rst] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in]
|
||||||
|
connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins mig_7series_0/sys_rst]
|
||||||
|
connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/LMB_Rst] [get_bd_pins rst_clk_wiz_1_100M/bus_struct_reset]
|
||||||
|
connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_clk_wiz_1_100M/interconnect_aresetn]
|
||||||
|
connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins rst_clk_wiz_1_100M/mb_reset]
|
||||||
|
connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins axi_ethernetlite_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_mem_intercon/S01_ARESETN] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/M03_ARESETN] [get_bd_pins microblaze_0_axi_periph/M04_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins mig_7series_0/aresetn] [get_bd_pins rst_clk_wiz_1_100M/peripheral_aresetn]
|
||||||
|
connect_bd_net -net xlconcat_0_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins xlconcat_0/dout]
|
||||||
|
|
||||||
|
# Create address segments
|
||||||
|
create_bd_addr_seg -range 0x10000 -offset 0x40E00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_ethernetlite_0/S_AXI/Reg] SEG_axi_ethernetlite_0_Reg
|
||||||
|
create_bd_addr_seg -range 0x10000 -offset 0x40000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg
|
||||||
|
create_bd_addr_seg -range 0x10000 -offset 0x41200000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_intc_0/s_axi/Reg] SEG_axi_intc_0_Reg
|
||||||
|
create_bd_addr_seg -range 0x10000 -offset 0x41C00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] SEG_axi_timer_0_Reg
|
||||||
|
create_bd_addr_seg -range 0x10000 -offset 0x40600000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg
|
||||||
|
create_bd_addr_seg -range 0x40000 -offset 0x0 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] SEG_dlmb_bram_if_cntlr_Mem
|
||||||
|
create_bd_addr_seg -range 0x40000 -offset 0x0 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] SEG_ilmb_bram_if_cntlr_Mem
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr
|
||||||
|
|
||||||
|
|
||||||
|
# Restore current instance
|
||||||
|
current_bd_instance $oldCurInst
|
||||||
|
|
||||||
|
save_bd_design
|
||||||
|
}
|
||||||
|
# End of create_root_design()
|
||||||
|
|
||||||
|
|
||||||
|
##################################################################
|
||||||
|
# MAIN FLOW
|
||||||
|
##################################################################
|
||||||
|
|
||||||
|
create_root_design ""
|
||||||
|
|
||||||
|
|
||||||
Binary file not shown.
@ -0,0 +1,334 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<MemInfo Version="1" Minor="0">
|
||||||
|
<Processor Endianness="Little" InstPath="base_microblaze_design_i/microblaze_0">
|
||||||
|
<AddressSpace Name="base_microblaze_design_i_microblaze_0.base_microblaze_design_i_microblaze_0_local_memory_dlmb_bram_if_cntlr" Begin="0" End="262143">
|
||||||
|
<BusBlock>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X1Y4">
|
||||||
|
<DataWidth MSB="7" LSB="7"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X1Y8">
|
||||||
|
<DataWidth MSB="6" LSB="6"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X0Y8">
|
||||||
|
<DataWidth MSB="5" LSB="5"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X4Y0">
|
||||||
|
<DataWidth MSB="4" LSB="4"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X1Y12">
|
||||||
|
<DataWidth MSB="3" LSB="3"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X2Y5">
|
||||||
|
<DataWidth MSB="2" LSB="2"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X3Y17">
|
||||||
|
<DataWidth MSB="1" LSB="1"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X3Y6">
|
||||||
|
<DataWidth MSB="0" LSB="0"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X2Y1">
|
||||||
|
<DataWidth MSB="15" LSB="15"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X2Y3">
|
||||||
|
<DataWidth MSB="14" LSB="14"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X6Y7">
|
||||||
|
<DataWidth MSB="13" LSB="13"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X5Y2">
|
||||||
|
<DataWidth MSB="12" LSB="12"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X2Y13">
|
||||||
|
<DataWidth MSB="11" LSB="11"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X4Y13">
|
||||||
|
<DataWidth MSB="10" LSB="10"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X5Y0">
|
||||||
|
<DataWidth MSB="9" LSB="9"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X4Y2">
|
||||||
|
<DataWidth MSB="8" LSB="8"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X5Y8">
|
||||||
|
<DataWidth MSB="23" LSB="23"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X2Y7">
|
||||||
|
<DataWidth MSB="22" LSB="22"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X1Y10">
|
||||||
|
<DataWidth MSB="21" LSB="21"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X4Y7">
|
||||||
|
<DataWidth MSB="20" LSB="20"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X2Y11">
|
||||||
|
<DataWidth MSB="19" LSB="19"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X3Y0">
|
||||||
|
<DataWidth MSB="18" LSB="18"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X6Y11">
|
||||||
|
<DataWidth MSB="17" LSB="17"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X3Y2">
|
||||||
|
<DataWidth MSB="16" LSB="16"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X1Y6">
|
||||||
|
<DataWidth MSB="31" LSB="31"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X2Y9">
|
||||||
|
<DataWidth MSB="30" LSB="30"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X4Y15">
|
||||||
|
<DataWidth MSB="29" LSB="29"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X6Y3">
|
||||||
|
<DataWidth MSB="28" LSB="28"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X3Y15">
|
||||||
|
<DataWidth MSB="27" LSB="27"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X5Y13">
|
||||||
|
<DataWidth MSB="26" LSB="26"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X6Y9">
|
||||||
|
<DataWidth MSB="25" LSB="25"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X6Y5">
|
||||||
|
<DataWidth MSB="24" LSB="24"/>
|
||||||
|
<AddressRange Begin="0" End="32767"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
</BusBlock>
|
||||||
|
<BusBlock>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X1Y5">
|
||||||
|
<DataWidth MSB="7" LSB="7"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X1Y9">
|
||||||
|
<DataWidth MSB="6" LSB="6"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X0Y9">
|
||||||
|
<DataWidth MSB="5" LSB="5"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X4Y1">
|
||||||
|
<DataWidth MSB="4" LSB="4"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X1Y13">
|
||||||
|
<DataWidth MSB="3" LSB="3"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X2Y6">
|
||||||
|
<DataWidth MSB="2" LSB="2"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X3Y18">
|
||||||
|
<DataWidth MSB="1" LSB="1"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X3Y7">
|
||||||
|
<DataWidth MSB="0" LSB="0"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X2Y2">
|
||||||
|
<DataWidth MSB="15" LSB="15"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X2Y4">
|
||||||
|
<DataWidth MSB="14" LSB="14"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X6Y8">
|
||||||
|
<DataWidth MSB="13" LSB="13"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X5Y3">
|
||||||
|
<DataWidth MSB="12" LSB="12"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X2Y14">
|
||||||
|
<DataWidth MSB="11" LSB="11"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X4Y14">
|
||||||
|
<DataWidth MSB="10" LSB="10"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X5Y1">
|
||||||
|
<DataWidth MSB="9" LSB="9"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X4Y3">
|
||||||
|
<DataWidth MSB="8" LSB="8"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X5Y9">
|
||||||
|
<DataWidth MSB="23" LSB="23"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X2Y8">
|
||||||
|
<DataWidth MSB="22" LSB="22"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X1Y11">
|
||||||
|
<DataWidth MSB="21" LSB="21"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X4Y8">
|
||||||
|
<DataWidth MSB="20" LSB="20"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X2Y12">
|
||||||
|
<DataWidth MSB="19" LSB="19"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X3Y1">
|
||||||
|
<DataWidth MSB="18" LSB="18"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X6Y12">
|
||||||
|
<DataWidth MSB="17" LSB="17"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X3Y3">
|
||||||
|
<DataWidth MSB="16" LSB="16"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X1Y7">
|
||||||
|
<DataWidth MSB="31" LSB="31"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X2Y10">
|
||||||
|
<DataWidth MSB="30" LSB="30"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X4Y16">
|
||||||
|
<DataWidth MSB="29" LSB="29"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X6Y4">
|
||||||
|
<DataWidth MSB="28" LSB="28"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X3Y16">
|
||||||
|
<DataWidth MSB="27" LSB="27"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X5Y14">
|
||||||
|
<DataWidth MSB="26" LSB="26"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X6Y10">
|
||||||
|
<DataWidth MSB="25" LSB="25"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
<BitLane MemType="RAMB32" Placement="X6Y6">
|
||||||
|
<DataWidth MSB="24" LSB="24"/>
|
||||||
|
<AddressRange Begin="32768" End="65535"/>
|
||||||
|
<Parity ON="false" NumBits="0"/>
|
||||||
|
</BitLane>
|
||||||
|
</BusBlock>
|
||||||
|
</AddressSpace>
|
||||||
|
</Processor>
|
||||||
|
<Config>
|
||||||
|
<Option Name="Part" Val="xc7k325tffg900-2"/>
|
||||||
|
</Config>
|
||||||
|
</MemInfo>
|
||||||
@ -0,0 +1,14 @@
|
|||||||
|
<?xml version="1.0"?>
|
||||||
|
<Project Version="1" Minor="0">
|
||||||
|
<BUILD_NUMBER Name="1071353"/>
|
||||||
|
<FULL_BUILD Name="SW Build 1071353 on Tue Nov 18 18:29:27 MST 2014"/>
|
||||||
|
<MODE Name="Post-Bitstream"/>
|
||||||
|
<SYSTEMINFO BOARD="xilinx.com:kc705:part0:1.1" ARCH="kintex7" PACKAGE="ffg900" DEVICE="7k325t" SPEED="-2" LUT="" FF="" BRAM="" DSP=""/>
|
||||||
|
<HIERARCHY Name="base_microblaze_design_i"/>
|
||||||
|
<File Type="HW_HANDOFF" Name="base_microblaze_design.hwh" ModTime="1421754940"/>
|
||||||
|
<File Type="BIT" Name="base_microblaze_design_wrapper.bit" ModTime="1421759776"/>
|
||||||
|
<File Type="BMM" Name="base_microblaze_design_wrapper.mmi" ModTime="1421759676"/>
|
||||||
|
<File Type="BD_TCL" Name="base_microblaze_design_bd.tcl" ModTime="1421754940"/>
|
||||||
|
<USEDRESOURCES LUT="" FF="" BRAM="" DSP=""/>
|
||||||
|
</Project>
|
||||||
|
|
||||||
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Loading…
Reference in New Issue