Update header files to include CMSIS files.
Richard Barry
16 years ago
parent
fe9d735641
commit
ec5827a601
@ -0,0 +1,109 @@
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/*
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* @file: EthDev.h
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* @purpose: Ethernet Device Definitions
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* @version: V1.10
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* @date: 24. Feb. 2009
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*----------------------------------------------------------------------------
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*
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* Copyright (C) 2009 ARM Limited. All rights reserved.
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*
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* ARM Limited (ARM) is supplying this software for use with Cortex-M3
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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*/
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#ifndef _ETHDEV__H
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#define _ETHDEV__H
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#ifndef NULL
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#define NULL 0
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#endif
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/*----------------------------------------------------------------------------
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Ethernet Device Defines
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*----------------------------------------------------------------------------*/
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#define EthDev_ADDR_SIZE 6 /*!< Ethernet Address size in bytes */
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#define EthDev_MTU_SIZE 1514 /*!< Maximum Transmission Unit */
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/*----------------------------------------------------------------------------
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Ethernet Device Configuration and Control Command Defines
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*----------------------------------------------------------------------------*/
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typedef enum {
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EthDev_LINK_DOWN = 0, /*!< Ethernet link not established */
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EthDev_LINK_UP = 1, /*!< Ethernet link established */
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} EthDev_LINK;
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typedef enum {
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EthDev_SPEED_10M = 0, /*!< 10.0 Mbps link speed */
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EthDev_SPEED_100M = 1, /*!< 100.0 Mbps link speed */
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EthDev_SPEED_1000M = 2, /*!< 1.0 Gbps link speed */
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} EthDev_SPEED;
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typedef enum {
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EthDev_DUPLEX_HALF = 0, /*!< Link half duplex */
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EthDev_DUPLEX_FULL = 1, /*!< Link full duplex */
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} EthDev_DUPLEX;
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typedef enum {
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EthDev_MODE_AUTO = 0,
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EthDev_MODE_10M_FULL = 1,
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EthDev_MODE_10M_HALF = 2,
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EthDev_MODE_100M_FULL = 3,
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EthDev_MODE_100M_HALF = 4,
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EthDev_MODE_1000M_FULL = 5,
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EthDev_MODE_1000M_HALF = 6,
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} EthDev_MODE;
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typedef struct {
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EthDev_LINK Link : 1;
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EthDev_DUPLEX Duplex : 1;
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EthDev_SPEED Speed : 2;
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} EthDev_STATUS;
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/*----------------------------------------------------------------------------
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Ethernet Device IO Block Structure
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*----------------------------------------------------------------------------*/
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typedef struct {
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/* Initialized by the user application before call to Init. */
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EthDev_MODE Mode;
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unsigned char HwAddr[EthDev_ADDR_SIZE];
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void *(*RxFrame) (int size);
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void (*RxFrameReady) (int size);
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/* Initialized by Ethernet driver. */
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int (*Init) (void);
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int (*UnInit) (void);
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int (*SetMCFilter)(int NumHwAddr, unsigned char *pHwAddr);
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int (*TxFrame) (void *pData, int size);
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void (*Lock) (void);
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void (*UnLock) (void);
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EthDev_STATUS (*LinkChk) (void);
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} EthDev_IOB;
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// prototypes
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portBASE_TYPE Init_EMAC(void);
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unsigned short ReadFrameBE_EMAC(void);
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void CopyToFrame_EMAC(void *Source, unsigned int Size);
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void CopyFromFrame_EMAC(void *Dest, unsigned short Size);
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void DummyReadFrame_EMAC(unsigned short Size);
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unsigned short StartReadFrame(void);
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void EndReadFrame(void);
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unsigned int CheckFrameReceived(void);
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void RequestSend(void);
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unsigned int Rdy4Tx(void);
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void DoSend_EMAC(unsigned short FrameSize);
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void vEMACWaitForInput( void );
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unsigned int uiGetEMACRxData( unsigned char *ucBuffer );
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#endif
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@ -1,465 +0,0 @@
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/******************************************************************
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***** *****
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***** Ver.: 1.0 *****
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***** Date: 07/05/2001 *****
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***** Auth: Andreas Dannenberg *****
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***** HTWK Leipzig *****
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***** university of applied sciences *****
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***** Germany *****
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***** Func: ethernet packet-driver for use with LAN- *****
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***** controller CS8900 from Crystal/Cirrus Logic *****
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***** *****
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***** Keil: Module modified for use with Philips *****
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***** LPC2378 EMAC Ethernet controller *****
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***** *****
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******************************************************************/
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/* Adapted from file originally written by Andreas Dannenberg. Supplied with permission. */
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#include "FreeRTOS.h"
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#include "semphr.h"
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#include "task.h"
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#include "emac.h"
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#include "LPC17xx_defs.h"
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#define configPINSEL2_VALUE 0x50150105
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/* The semaphore used to wake the uIP task when data arives. */
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xSemaphoreHandle xEMACSemaphore = NULL;
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static unsigned short *rptr;
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static unsigned short *tptr;
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static unsigned short SwapBytes( unsigned short Data )
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{
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return( Data >> 8 ) | ( Data << 8 );
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}
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// Keil: function added to write PHY
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int write_PHY( int PhyReg, int Value )
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{
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unsigned int tout;
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const unsigned int uiMaxTime = 10;
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MAC_MADR = DP83848C_DEF_ADR | PhyReg;
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MAC_MWTD = Value;
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/* Wait utill operation completed */
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tout = 0;
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for( tout = 0; tout < uiMaxTime; tout++ )
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{
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if( (MAC_MIND & MIND_BUSY) == 0 )
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{
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break;
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}
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vTaskDelay( 2 );
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}
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if( tout < uiMaxTime )
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{
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return pdPASS;
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}
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else
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{
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return pdFAIL;
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}
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}
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// Keil: function added to read PHY
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unsigned short read_PHY( unsigned char PhyReg, portBASE_TYPE *pxStatus )
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{
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unsigned int tout;
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const unsigned int uiMaxTime = 10;
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MAC_MADR = DP83848C_DEF_ADR | PhyReg;
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MAC_MCMD = MCMD_READ;
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/* Wait until operation completed */
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tout = 0;
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for( tout = 0; tout < uiMaxTime; tout++ )
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{
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if( (MAC_MIND & MIND_BUSY) == 0 )
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{
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break;
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}
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vTaskDelay( 2 );
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}
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MAC_MCMD = 0;
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if( tout >= uiMaxTime )
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{
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*pxStatus = pdFAIL;
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}
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return( MAC_MRDD );
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}
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// Keil: function added to initialize Rx Descriptors
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void rx_descr_init( void )
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{
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unsigned int i;
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for( i = 0; i < NUM_RX_FRAG; i++ )
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{
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RX_DESC_PACKET( i ) = RX_BUF( i );
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RX_DESC_CTRL( i ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 );
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RX_STAT_INFO( i ) = 0;
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RX_STAT_HASHCRC( i ) = 0;
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}
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/* Set EMAC Receive Descriptor Registers. */
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MAC_RXDESCRIPTOR = RX_DESC_BASE;
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MAC_RXSTATUS = RX_STAT_BASE;
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MAC_RXDESCRIPTORNUM = NUM_RX_FRAG - 1;
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/* Rx Descriptors Point to 0 */
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MAC_RXCONSUMEINDEX = 0;
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}
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// Keil: function added to initialize Tx Descriptors
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void tx_descr_init( void )
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{
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unsigned int i;
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for( i = 0; i < NUM_TX_FRAG; i++ )
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{
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TX_DESC_PACKET( i ) = TX_BUF( i );
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TX_DESC_CTRL( i ) = 0;
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TX_STAT_INFO( i ) = 0;
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}
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/* Set EMAC Transmit Descriptor Registers. */
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MAC_TXDESCRIPTOR = TX_DESC_BASE;
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MAC_TXSTATUS = TX_STAT_BASE;
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MAC_TXDESCRIPTORNUM = NUM_TX_FRAG - 1;
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/* Tx Descriptors Point to 0 */
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MAC_TXPRODUCEINDEX = 0;
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}
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// configure port-pins for use with LAN-controller,
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// reset it and send the configuration-sequence
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portBASE_TYPE Init_EMAC( void )
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{
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portBASE_TYPE xReturn = pdPASS;
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// Keil: function modified to access the EMAC
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// Initializes the EMAC ethernet controller
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volatile unsigned int regv, tout, id1, id2;
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/* Enable P1 Ethernet Pins. */
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PINSEL2 = configPINSEL2_VALUE;
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PINSEL3 = ( PINSEL3 &~0x0000000F ) | 0x00000005;
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/* Power Up the EMAC controller. */
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PCONP |= PCONP_PCENET;
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vTaskDelay( 2 );
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/* Reset all EMAC internal modules. */
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MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
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MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
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/* A short delay after reset. */
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vTaskDelay( 2 );
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/* Initialize MAC control registers. */
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MAC_MAC1 = MAC1_PASS_ALL;
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MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
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MAC_MAXF = ETH_MAX_FLEN;
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MAC_CLRT = CLRT_DEF;
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MAC_IPGR = IPGR_DEF;
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/* Enable Reduced MII interface. */
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MAC_COMMAND = CR_RMII | CR_PASS_RUNT_FRM;
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/* Reset Reduced MII Logic. */
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MAC_SUPP = SUPP_RES_RMII;
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vTaskDelay( 2 );
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MAC_SUPP = 0;
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/* Put the PHY in reset mode */
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write_PHY( PHY_REG_BMCR, 0x8000 );
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xReturn = write_PHY( PHY_REG_BMCR, 0x8000 );
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/* Wait for hardware reset to end. */
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for( tout = 0; tout < 100; tout++ )
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{
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vTaskDelay( 10 );
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regv = read_PHY( PHY_REG_BMCR, &xReturn );
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if( !(regv & 0x8000) )
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{
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/* Reset complete */
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break;
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}
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}
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/* Check if this is a DP83848C PHY. */
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id1 = read_PHY( PHY_REG_IDR1, &xReturn );
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id2 = read_PHY( PHY_REG_IDR2, &xReturn );
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if( ((id1 << 16) | (id2 & 0xFFF0)) == DP83848C_ID )
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{
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/* Set the Ethernet MAC Address registers */
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MAC_SA0 = ( emacETHADDR0 << 8 ) | emacETHADDR1;
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MAC_SA1 = ( emacETHADDR2 << 8 ) | emacETHADDR3;
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MAC_SA2 = ( emacETHADDR4 << 8 ) | emacETHADDR5;
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/* Initialize Tx and Rx DMA Descriptors */
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rx_descr_init();
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tx_descr_init();
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/* Receive Broadcast and Perfect Match Packets */
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MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
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/* Create the semaphore used ot wake the uIP task. */
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vSemaphoreCreateBinary( xEMACSemaphore );
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/* Configure the PHY device */
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/* Use autonegotiation about the link speed. */
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if( write_PHY(PHY_REG_BMCR, PHY_AUTO_NEG) )
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{
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/* Wait to complete Auto_Negotiation. */
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for( tout = 0; tout < 10; tout++ )
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{
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vTaskDelay( 100 );
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regv = read_PHY( PHY_REG_BMSR, &xReturn );
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if( regv & 0x0020 )
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{
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/* Autonegotiation Complete. */
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break;
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}
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}
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}
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}
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else
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{
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xReturn = pdFAIL;
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}
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/* Check the link status. */
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if( xReturn == pdPASS )
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{
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xReturn = pdFAIL;
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for( tout = 0; tout < 10; tout++ )
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{
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vTaskDelay( 100 );
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regv = read_PHY( PHY_REG_STS, &xReturn );
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if( regv & 0x0001 )
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{
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/* Link is on. */
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xReturn = pdPASS;
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break;
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}
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}
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}
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if( xReturn == pdPASS )
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{
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/* Configure Full/Half Duplex mode. */
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if( regv & 0x0004 )
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{
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/* Full duplex is enabled. */
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MAC_MAC2 |= MAC2_FULL_DUP;
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MAC_COMMAND |= CR_FULL_DUP;
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MAC_IPGT = IPGT_FULL_DUP;
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}
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else
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{
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/* Half duplex mode. */
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MAC_IPGT = IPGT_HALF_DUP;
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}
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/* Configure 100MBit/10MBit mode. */
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if( regv & 0x0002 )
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{
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/* 10MBit mode. */
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MAC_SUPP = 0;
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}
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else
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{
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/* 100MBit mode. */
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MAC_SUPP = SUPP_SPEED;
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}
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/* Reset all interrupts */
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MAC_INTCLEAR = 0xFFFF;
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/* Enable receive and transmit mode of MAC Ethernet core */
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MAC_COMMAND |= ( CR_RX_EN | CR_TX_EN );
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MAC_MAC1 |= MAC1_REC_EN;
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}
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return xReturn;
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}
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// reads a word in little-endian byte order from RX_BUFFER
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unsigned short ReadFrame_EMAC( void )
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{
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return( *rptr++ );
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}
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// reads a word in big-endian byte order from RX_FRAME_PORT
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// (useful to avoid permanent byte-swapping while reading
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// TCP/IP-data)
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unsigned short ReadFrameBE_EMAC( void )
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{
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unsigned short ReturnValue;
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ReturnValue = SwapBytes( *rptr++ );
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return( ReturnValue );
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}
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// copies bytes from frame port to MCU-memory
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// NOTES: * an odd number of byte may only be transfered
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// if the frame is read to the end!
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// * MCU-memory MUST start at word-boundary
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void CopyFromFrame_EMAC( void *Dest, unsigned short Size )
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{
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unsigned short *piDest; // Keil: Pointer added to correct expression
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piDest = Dest; // Keil: Line added
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while( Size > 1 )
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{
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*piDest++ = ReadFrame_EMAC();
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Size -= 2;
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}
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if( Size )
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{ // check for leftover byte...
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*( unsigned char * ) piDest = ( char ) ReadFrame_EMAC(); // the LAN-Controller will return 0
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} // for the highbyte
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}
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// does a dummy read on frame-I/O-port
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// NOTE: only an even number of bytes is read!
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void DummyReadFrame_EMAC( unsigned short Size ) // discards an EVEN number of bytes
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{ // from RX-fifo
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while( Size > 1 )
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{
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ReadFrame_EMAC();
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Size -= 2;
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}
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}
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// Reads the length of the received ethernet frame and checks if the
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// destination address is a broadcast message or not
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// returns the frame length
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unsigned short StartReadFrame( void )
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{
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unsigned short RxLen;
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unsigned int idx;
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idx = MAC_RXCONSUMEINDEX;
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RxLen = ( RX_STAT_INFO(idx) & RINFO_SIZE ) - 3;
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rptr = ( unsigned short * ) RX_DESC_PACKET( idx );
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return( RxLen );
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}
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void EndReadFrame( void )
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{
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unsigned int idx;
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/* DMA free packet. */
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idx = MAC_RXCONSUMEINDEX;
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if( ++idx == NUM_RX_FRAG )
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{
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idx = 0;
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}
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MAC_RXCONSUMEINDEX = idx;
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}
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unsigned int CheckFrameReceived( void )
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{
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// Packet received ?
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if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX )
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{ // more packets received ?
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return( 1 );
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}
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else
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{
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return( 0 );
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}
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}
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unsigned int uiGetEMACRxData( unsigned char *ucBuffer )
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{
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unsigned int uiLen = 0;
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if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX )
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{
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uiLen = StartReadFrame();
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CopyFromFrame_EMAC( ucBuffer, uiLen );
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EndReadFrame();
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}
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return uiLen;
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}
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// requests space in EMAC memory for storing an outgoing frame
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void RequestSend( void )
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{
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unsigned int idx;
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idx = MAC_TXPRODUCEINDEX;
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tptr = ( unsigned short * ) TX_DESC_PACKET( idx );
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}
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|
||||
// check if ethernet controller is ready to accept the
|
||||
// frame we want to send
|
||||
unsigned int Rdy4Tx( void )
|
||||
{
|
||||
return( 1 ); // the ethernet controller transmits much faster
|
||||
} // than the CPU can load its buffers
|
||||
|
||||
// writes a word in little-endian byte order to TX_BUFFER
|
||||
void WriteFrame_EMAC( unsigned short Data )
|
||||
{
|
||||
*tptr++ = Data;
|
||||
}
|
||||
|
||||
// copies bytes from MCU-memory to frame port
|
||||
// NOTES: * an odd number of byte may only be transfered
|
||||
// if the frame is written to the end!
|
||||
// * MCU-memory MUST start at word-boundary
|
||||
void CopyToFrame_EMAC( void *Source, unsigned int Size )
|
||||
{
|
||||
unsigned short *piSource;
|
||||
|
||||
piSource = Source;
|
||||
Size = ( Size + 1 ) & 0xFFFE; // round Size up to next even number
|
||||
while( Size > 0 )
|
||||
{
|
||||
WriteFrame_EMAC( *piSource++ );
|
||||
Size -= 2;
|
||||
}
|
||||
}
|
||||
|
||||
void DoSend_EMAC( unsigned short FrameSize )
|
||||
{
|
||||
unsigned int idx;
|
||||
|
||||
idx = MAC_TXPRODUCEINDEX;
|
||||
TX_DESC_CTRL( idx ) = FrameSize | TCTRL_LAST;
|
||||
if( ++idx == NUM_TX_FRAG )
|
||||
{
|
||||
idx = 0;
|
||||
}
|
||||
|
||||
MAC_TXPRODUCEINDEX = idx;
|
||||
}
|
||||
|
||||
void vEMAC_ISR( void )
|
||||
{
|
||||
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
|
||||
|
||||
/* Clear the interrupt. */
|
||||
MAC_INTCLEAR = 0xffff;
|
||||
|
||||
/* Ensure the uIP task is not blocked as data has arrived. */
|
||||
xSemaphoreGiveFromISR( xEMACSemaphore, &xHigherPriorityTaskWoken );
|
||||
|
||||
portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
|
||||
}
|
||||
Loading…
Reference in New Issue