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Update polarfire project to latest RISC-V port with vector mode support (#791)

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* Update PolarFire Project to support vector mode.l

* Update vector alignments.

* Update file headers.

* Code review changes

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
pull/788/head^2
Ming Yue 3 years ago committed by GitHub
parent 449c7b29ca
commit cc8c0266a8
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 125 additions and 3 deletions
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4
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/.settings/language.settings.xml
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@ -5,10 +5,10 @@
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-651266087234227896" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1167646644509623642" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
</extension>
</configuration>
</project>
</project>

26
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/main.c
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@ -20,7 +20,7 @@
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://aws.amazon.com/freertos
* https://github.com/FreeRTOS
*
*/
@ -60,8 +60,22 @@
or 0 to run the more comprehensive test and demo application. */
#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
/* Set to 1 to use direct mode and set to 0 to use vectored mode.
VECTOR MODE=Direct --> all traps into machine mode cause the pc to be set to the
vector base address (BASE) in the mtvec register.
VECTOR MODE=Vectored --> all synchronous exceptions into machine mode cause the
pc to be set to the BASE, whereas interrupts cause the pc to be set to the
address BASE plus four times the interrupt cause number.
*/
#define mainVECTOR_MODE_DIRECT 0
/*-----------------------------------------------------------*/
extern void freertos_risc_v_trap_handler( void );
extern void freertos_vector_table( void );
/*
* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
* main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
@ -121,6 +135,16 @@ static void prvSetupHardware( void )
mss_config_clk_rst( MSS_PERIPH_GPIO2, ( uint8_t )MPFS_HAL_FIRST_HART, PERIPHERAL_ON );
MSS_GPIO_config( GPIO2_LO, MSS_GPIO_16, MSS_GPIO_OUTPUT_MODE ); /* Red Led (LED1). */
MSS_GPIO_config( GPIO2_LO, MSS_GPIO_18, MSS_GPIO_OUTPUT_MODE ); /* Yellow Led (LED3). */
#if( mainVECTOR_MODE_DIRECT == 1 )
{
__asm__ volatile( "csrw mtvec, %0" :: "r"( freertos_risc_v_trap_handler ) );
}
#else
{
__asm__ volatile( "csrw mtvec, %0" :: "r"( ( uintptr_t )freertos_vector_table | 0x1 ) );
}
#endif
}
/*-----------------------------------------------------------*/

98
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/vector_table.S
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@ -0,0 +1,98 @@
/*
* FreeRTOS V202112.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
.extern freertos_risc_v_exception_handler
.extern freertos_risc_v_interrupt_handler
.extern freertos_risc_v_mtimer_interrupt_handler
.balign 256, 0
.option norvc
.global freertos_vector_table
freertos_vector_table:
IRQ_0:
j freertos_risc_v_exception_handler
IRQ_1:
j freertos_risc_v_interrupt_handler
IRQ_2:
j freertos_risc_v_interrupt_handler
IRQ_3:
j freertos_risc_v_interrupt_handler
IRQ_4:
j freertos_risc_v_interrupt_handler
IRQ_5:
j freertos_risc_v_interrupt_handler
IRQ_6:
j freertos_risc_v_interrupt_handler
IRQ_7:
j freertos_risc_v_mtimer_interrupt_handler
IRQ_8:
j freertos_risc_v_interrupt_handler
IRQ_9:
j freertos_risc_v_interrupt_handler
IRQ_10:
j freertos_risc_v_interrupt_handler
IRQ_11:
j freertos_risc_v_interrupt_handler
IRQ_12:
j freertos_risc_v_interrupt_handler
IRQ_13:
j freertos_risc_v_interrupt_handler
IRQ_14:
j freertos_risc_v_interrupt_handler
IRQ_15:
j freertos_risc_v_interrupt_handler
IRQ_LC0:
j freertos_risc_v_interrupt_handler
IRQ_LC1:
j freertos_risc_v_interrupt_handler
IRQ_LC2:
j freertos_risc_v_interrupt_handler
IRQ_LC3:
j freertos_risc_v_interrupt_handler
IRQ_LC4:
j freertos_risc_v_interrupt_handler
IRQ_LC5:
j freertos_risc_v_interrupt_handler
IRQ_LC6:
j freertos_risc_v_interrupt_handler
IRQ_LC7:
j freertos_risc_v_interrupt_handler
IRQ_LC8:
j freertos_risc_v_interrupt_handler
IRQ_LC9:
j freertos_risc_v_interrupt_handler
IRQ_LC10:
j freertos_risc_v_interrupt_handler
IRQ_LC11:
j freertos_risc_v_interrupt_handler
IRQ_LC12:
j freertos_risc_v_interrupt_handler
IRQ_LC13:
j freertos_risc_v_interrupt_handler
IRQ_LC14:
j freertos_risc_v_interrupt_handler
IRQ_LC15:
j freertos_risc_v_interrupt_handler
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