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Demo projects for nRF9160-DK (#784)

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* Add demo projects for nRF9160-DK

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
pull/794/head
Gaurav-Aggarwal-AWS 3 years ago committed by GitHub
parent 4255ac5c28
commit 449c7b29ca
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
188 changed files with 523132 additions and 15 deletions
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2
.github/scripts/core_checker.py vendored
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@ -73,6 +73,7 @@ FREERTOS_IGNORED_EXTENSIONS = [
'.dtd',
'.dts',
'.elf',
'.emProject',
'.env_conf',
'.ewd',
'.ewp',
@ -257,6 +258,7 @@ FREERTOS_IGNORED_PATTERNS = [
r'.*mbedtls_config\.h.*',
r'.*mbedtls_config\.h.*',
r'.*CMSIS.*',
r'.*/Nordic_Code/*',
r'.*/makefile',
r'.*/Makefile',
r'.*/printf-stdarg\.c.*',

3
FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/.gitignore vendored
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Output/
*.emSession
*.jlink

169
FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Config/FreeRTOSConfig.h
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/*
* FreeRTOS V202112.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/******************************************************************************
See http://www.freertos.org/a00110.html for an explanation of the
definitions contained in this file.
******************************************************************************/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
* https://www.FreeRTOS.org/a00110.html
*----------------------------------------------------------*/
extern uint32_t SystemCoreClock;
/* Cortex M33 port configuration. */
#define configENABLE_MPU 1
#define configENABLE_FPU 1
#define configENABLE_TRUSTZONE 0
/* This part has 16 MPU regions. */
#define configTOTAL_MPU_REGIONS 16
/* Run FreeRTOS on the secure side and never jump to the non-secure side. */
#define configRUN_FREERTOS_SECURE_ONLY 1
/* Constants related to the behaviour or the scheduler. */
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
#define configUSE_PREEMPTION 1
#define configUSE_TIME_SLICING 1
#define configMAX_PRIORITIES ( 5 )
#define configIDLE_SHOULD_YIELD 1
#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */
/* Constants that describe the hardware and memory usage. */
#define configCPU_CLOCK_HZ SystemCoreClock
#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 256 )
#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )
#define configMAX_TASK_NAME_LEN ( 12 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) )
/* Constants that build features in or out. */
#define configUSE_MUTEXES 1
#define configUSE_TICKLESS_IDLE 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_NEWLIB_REENTRANT 0
#define configUSE_CO_ROUTINES 0
#define configUSE_COUNTING_SEMAPHORES 1
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_QUEUE_SETS 0
#define configUSE_TASK_NOTIFICATIONS 1
#define configUSE_TRACE_FACILITY 1
/* Constants that define which hook (callback) functions should be used. */
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configUSE_MALLOC_FAILED_HOOK 0
/* Constants provided for debugging and optimisation assistance. */
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
#define configQUEUE_REGISTRY_SIZE 0
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 3 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
/* Set the following definitions to 1 to include the API function, or zero
* to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is
* only necessary if the linker does not automatically remove functions that are
* not referenced anyway. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_uxTaskGetStackHighWaterMark 0
#define INCLUDE_xTaskGetIdleTaskHandle 0
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTaskResumeFromISR 0
#define INCLUDE_xTaskGetCurrentTaskHandle 1
#define INCLUDE_xTaskGetSchedulerState 0
#define INCLUDE_xSemaphoreGetMutexHolder 0
#define INCLUDE_xTimerPendFunctionCall 1
/* This demo makes use of one or more example stats formatting functions. These
* format the raw data provided by the uxTaskGetSystemState() function in to
* human readable ASCII form. See the notes in the implementation of vTaskList()
* within FreeRTOS/Source/tasks.c for limitations. */
#define configUSE_STATS_FORMATTING_FUNCTIONS 1
/* Dimensions a buffer that can be used by the FreeRTOS+CLI command interpreter.
* See the FreeRTOS+CLI documentation for more information:
* https://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */
#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048
/* Interrupt priority configuration follows...................... */
/* Use the system definition, if there is one. */
#ifdef __NVIC_PRIO_BITS
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 3 /* 8 priority levels. */
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
* function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07
/* The highest interrupt priority that can be used by any interrupt service
* routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT
* CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A
* HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values). */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* Interrupt priorities used by the kernel port layer itself. These are generic
* to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
* See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )
/* Constants related to the generation of run time stats. */
#define configGENERATE_RUN_TIME_STATS 0
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
#define portGET_RUN_TIME_COUNTER_VALUE() 0
#define configTICK_RATE_HZ ( ( TickType_t ) 100 )
/* Enable static allocation. */
#define configSUPPORT_STATIC_ALLOCATION 1
#endif /* FREERTOS_CONFIG_H */

125
FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/FreeRTOSDemo.emProject
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<!DOCTYPE CrossStudio_Project_File>
<solution Name="FreeRTOSDemo" target="8" version="2">
<project Name="FreeRTOSDemo">
<configuration
LIBRARY_IO_TYPE="RTT"
Name="Common"
Target="nRF9160_xxAA"
arm_architecture="v8M_Mainline"
arm_compiler_variant="clang"
arm_core_type="Cortex-M33"
arm_endian="Little"
arm_fp_abi="Hard"
arm_fpu_type="FPv5-SP-D16"
arm_linker_heap_size="0"
arm_linker_process_stack_size="0"
arm_linker_stack_size="2048"
arm_linker_variant="GNU"
arm_rtl_variant="SEGGER"
arm_simulator_memory_simulation_parameter="ROM;0x00000000;0x00100000;RAM;0x20000000;0x0003E000"
arm_target_debug_interface_type="ADIv5"
arm_target_device_name="nRF9160_xxAA"
arm_target_interface_type="SWD"
arm_v8M_has_cmse="Yes"
build_intermediate_directory="Output/$(Configuration)/Objects/"
build_output_directory="Output/$(Configuration)/"
c_preprocessor_definitions="ARM_MATH_ARMV8MML;NRF9160_XXAA;__NRF_FAMILY;__SUPPORT_RESET_HALT_AFTER_BTL=0;INITIALIZE_USER_SECTIONS;__ARMCC_VERSION"
c_user_include_directories="$(ProjectDir)/Nordic_Code/CMSIS_5/CMSIS/Core/Include;$(ProjectDir)/Nordic_Code/nRF/Device/Include;$(ProjectDir)/Config;../../Source/include;../../Source/portable/GCC/ARM_CM33_NTZ/non_secure;../Common/ARMv8M/mpu_demo"
debug_register_definition_file="$(ProjectDir)/Nordic_Code/nRF/XML/nrf9160_Registers.xml"
debug_stack_pointer_start="__stack_end__"
debug_start_from_entry_point_symbol="No"
debug_target_connection="J-Link"
gcc_entry_point="Reset_Handler"
link_linker_script_file=""
linker_memory_map_file="$(ProjectDir)/Source/FreeRTOSDemo_MemoryMap.xml"
linker_output_format="bin"
linker_section_placement_file="$(ProjectDir)/Source/FreeRTOSDemo_Flash_Placement.xml"
macros="DeviceHeaderFile=$(PackagesDir)/nRF/Device/Include/nrf.h;DeviceLibraryIdentifier=ARMv8MMLlfsp;DeviceSystemFile=$(PackagesDir)/nRF/Device/Source/system_nrf9160.c;DeviceVectorsFile=$(PackagesDir)/nRF/Source/nrf9160_Vectors.s;DeviceFamily=nRF;Target=nRF9160_xxAA"
project_directory=""
project_type="Executable"
target_reset_script="Reset();"
target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
<folder Name="Nordic_Code">
<folder Name="CMSIS Files">
<file file_name="Nordic_Code/nRF/Device/Source/system_nrf9160.c">
<configuration
Name="Common"
default_code_section=".init"
default_const_section=".init_rodata" />
</file>
<file file_name="Nordic_Code/nRF/Device/Include/nrf.h" />
</folder>
<folder Name="Script Files">
<file file_name="Nordic_Code/nRF/Scripts/nRF_Target.js">
<configuration Name="Common" file_type="Reset Script" />
</file>
</folder>
<folder Name="System Files">
<file file_name="Nordic_Code/nRF/Source/nRF_Startup.s" />
<file file_name="Nordic_Code/nRF/Source/nrf9160_Vectors.s">
<configuration Name="Common" file_type="Assembly" />
</file>
<file file_name="Nordic_Code/nRF/Source/thumb_crt0.s" />
</folder>
</folder>
<folder Name="User">
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc" />
<file file_name="Source/main.c" />
</folder>
<folder Name="FreeRTOS">
<folder Name="include">
<file file_name="../../Source/include/atomic.h" />
<file file_name="../../Source/include/deprecated_definitions.h" />
<file file_name="../../Source/include/event_groups.h" />
<file file_name="../../Source/include/FreeRTOS.h" />
<file file_name="../../Source/include/list.h" />
<file file_name="../../Source/include/message_buffer.h" />
<file file_name="../../Source/include/mpu_prototypes.h" />
<file file_name="../../Source/include/mpu_wrappers.h" />
<file file_name="../../Source/include/portable.h" />
<file file_name="../../Source/include/projdefs.h" />
<file file_name="../../Source/include/queue.h" />
<file file_name="../../Source/include/semphr.h" />
<file file_name="../../Source/include/stack_macros.h" />
<file file_name="../../Source/include/stdint.readme" />
<file file_name="../../Source/include/stream_buffer.h" />
<file file_name="../../Source/include/task.h" />
<file file_name="../../Source/include/timers.h" />
</folder>
<folder Name="portable">
<folder Name="Common">
<file file_name="../../Source/portable/Common/mpu_wrappers.c" />
</folder>
<folder Name="GCC">
<folder Name="ARM_CM33_NTZ">
<file file_name="../../Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c" />
<file file_name="../../Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h" />
<file file_name="../../Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c" />
<file file_name="../../Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h" />
</folder>
</folder>
<folder Name="MemMang">
<file file_name="../../Source/portable/MemMang/heap_4.c" />
</folder>
</folder>
<file file_name="../../Source/event_groups.c" />
<file file_name="../../Source/list.c" />
<file file_name="../../Source/queue.c" />
<file file_name="../../Source/stream_buffer.c" />
<file file_name="../../Source/tasks.c" />
<file file_name="../../Source/timers.c" />
</folder>
<folder Name="Config">
<file file_name="Config/FreeRTOSConfig.h" />
</folder>
<folder Name="Demos">
<file file_name="../Common/ARMv8M/mpu_demo/mpu_demo.c" />
<file file_name="../Common/ARMv8M/mpu_demo/mpu_demo.h" />
</folder>
</project>
<configuration
Name="Debug"
c_preprocessor_definitions="DEBUG"
gcc_debugging_level="Level 3"
gcc_optimization_level="None" />
</solution>

283
FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Nordic_Code/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h
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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Nordic_Code/CMSIS_5/CMSIS/Core/Include/cmsis_version.h
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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.4
* @date 23. July 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.2
* @date 10. February 2020
******************************************************************************/
/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
(((BASE) & MPU_RBAR_BASE_Msk) | \
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DMB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _COMPILER_ABSTRACTION_H
#define _COMPILER_ABSTRACTION_H
/*lint ++flb "Enter library region" */
#ifndef NRF_STRING_CONCATENATE_IMPL
#define NRF_STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs
#endif
#ifndef NRF_STRING_CONCATENATE
#define NRF_STRING_CONCATENATE(lhs, rhs) NRF_STRING_CONCATENATE_IMPL(lhs, rhs)
#endif
#if defined ( __CC_ARM )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __ALIGN
#define __ALIGN(n) __align(n)
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
#ifndef __UNUSED
#define __UNUSED __attribute__((unused))
#endif
#define GET_SP() __current_sp()
#ifndef NRF_STATIC_ASSERT
#define NRF_STATIC_ASSERT(cond, msg) \
;enum { NRF_STRING_CONCATENATE(static_assert_on_line_, __LINE__) = 1 / (!!(cond)) }
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __ALIGN
#define __ALIGN(n) __attribute__((aligned(n)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __UNUSED
#define __UNUSED __attribute__((unused))
#endif
#define GET_SP() __current_sp()
#ifndef NRF_STATIC_ASSERT
#ifdef __cplusplus
#ifndef _Static_assert
#define _Static_assert static_assert
#endif
#endif
#define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg)
#endif
#elif defined ( __ICCARM__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#if (__VER__ >= 8000000)
#ifndef __ALIGN
#define __ALIGN(n) __attribute__((aligned(n)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#else
#ifndef __ALIGN
#define STRING_PRAGMA(x) _Pragma(#x)
#define __ALIGN(n) STRING_PRAGMA(data_alignment = n)
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
#endif
#ifndef __UNUSED
#define __UNUSED
#endif
#define GET_SP() __get_SP()
#ifndef NRF_STATIC_ASSERT
#define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg)
#endif
#elif defined ( __GNUC__ ) || defined ( __clang__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __ALIGN
#define __ALIGN(n) __attribute__((aligned(n)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __UNUSED
#define __UNUSED __attribute__((unused))
#endif
#define GET_SP() gcc_current_sp()
static inline unsigned int gcc_current_sp(void)
{
unsigned int stack_pointer = 0;
__asm__ __volatile__ ("mov %0, sp" : "=r"(stack_pointer));
return stack_pointer;
}
#ifndef NRF_STATIC_ASSERT
#ifdef __cplusplus
#ifndef _Static_assert
#define _Static_assert static_assert
#endif
#endif
#define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg)
#endif
#elif defined ( __TASKING__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __ALIGN
#define __ALIGN(n) __align(n)
#endif
/* Not defined for TASKING. */
#ifndef __PACKED
#define __PACKED
#endif
#ifndef __UNUSED
#define __UNUSED __attribute__((unused))
#endif
#define GET_SP() __get_MSP()
#ifndef NRF_STATIC_ASSERT
#define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg)
#endif
#endif
#define NRF_MDK_VERSION_ASSERT_AT_LEAST(major, minor, micro) \
NRF_STATIC_ASSERT( \
( \
(major < MDK_MAJOR_VERSION) || \
(major == MDK_MAJOR_VERSION && minor < MDK_MINOR_VERSION) || \
(major == MDK_MAJOR_VERSION && minor == MDK_MINOR_VERSION && micro < MDK_MICRO_VERSION) \
), "MDK version mismatch.")
#define NRF_MDK_VERSION_ASSERT_EXACT(major, minor, micro) \
NRF_STATIC_ASSERT( \
( \
(major != MDK_MAJOR_VERSION) || \
(major != MDK_MAJOR_VERSION) || \
(major != MDK_MAJOR_VERSION) \
), "MDK version mismatch.")
/*lint --flb "Leave library region" */
#endif

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF_H
#define NRF_H
/* MDK version */
#define MDK_MAJOR_VERSION 8
#define MDK_MINOR_VERSION 44
#define MDK_MICRO_VERSION 1
/* Define coprocessor domains */
#if defined (NRF5340_XXAA_APPLICATION) || defined (NRF5340_XXAA_NETWORK)
#ifndef NRF5340_XXAA
#define NRF5340_XXAA
#endif
#endif
#if defined (NRF5340_XXAA_APPLICATION)
#ifndef NRF_APPLICATION
#define NRF_APPLICATION
#endif
#endif
#if defined (NRF5340_XXAA_NETWORK)
#ifndef NRF_NETWORK
#define NRF_NETWORK
#endif
#endif
/* Apply compatibility macros for old nRF5340 macros */
#if defined(NRF5340_XXAA)
#if defined (NRF_APPLICATION)
#ifndef NRF5340_XXAA_APPLICATION
#define NRF5340_XXAA_APPLICATION
#endif
#endif
#if defined (NRF_NETWORK)
#ifndef NRF5340_XXAA_NETWORK
#define NRF5340_XXAA_NETWORK
#endif
#endif
#endif
/* Define NRF51_SERIES for common use in nRF51 series devices. Only if not previously defined. */
#if defined (NRF51) ||\
defined (NRF51422_XXAA) ||\
defined (NRF51422_XXAB) ||\
defined (NRF51422_XXAC) ||\
defined (NRF51801_XXAB) ||\
defined (NRF51802_XXAA) ||\
defined (NRF51822_XXAA) ||\
defined (NRF51822_XXAB) ||\
defined (NRF51822_XXAC) ||\
defined (NRF51824_XXAA)
#ifndef NRF51_SERIES
#define NRF51_SERIES
#endif
#ifndef NRF51
#define NRF51
#endif
#endif
/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */
#if defined (NRF52)
#ifndef NRF52832_XXAA
#define NRF52832_XXAA
#endif
#endif
/* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */
#if defined (NRF52805_XXAA) || defined (NRF52810_XXAA) || defined (NRF52811_XXAA) || defined (NRF52820_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52833_XXAA) || defined (NRF52840_XXAA)
#ifndef NRF52_SERIES
#define NRF52_SERIES
#endif
#endif
/* Define NRF53_SERIES for common use in nRF53 series devices. */
#if defined (NRF5340_XXAA)
#ifndef NRF53_SERIES
#define NRF53_SERIES
#endif
#endif
/* Define NRF91_SERIES for common use in nRF91 series devices. */
#if defined (NRF9160_XXAA)
#ifndef NRF91_SERIES
#define NRF91_SERIES
#endif
#endif
/* Device selection for device includes. */
#if defined (NRF51)
#include "nrf51.h"
#include "nrf51_bitfields.h"
#include "nrf51_deprecated.h"
#elif defined (NRF52805_XXAA)
#include "nrf52805.h"
#include "nrf52805_bitfields.h"
#include "nrf51_to_nrf52810.h"
#include "nrf52_to_nrf52810.h"
#include "nrf52810_to_nrf52811.h"
#elif defined (NRF52810_XXAA)
#include "nrf52810.h"
#include "nrf52810_bitfields.h"
#include "nrf51_to_nrf52810.h"
#include "nrf52_to_nrf52810.h"
#include "nrf52810_name_change.h"
#elif defined (NRF52811_XXAA)
#include "nrf52811.h"
#include "nrf52811_bitfields.h"
#include "nrf51_to_nrf52810.h"
#include "nrf52_to_nrf52810.h"
#include "nrf52810_to_nrf52811.h"
#elif defined (NRF52820_XXAA)
#include "nrf52820.h"
#include "nrf52820_bitfields.h"
#include "nrf51_to_nrf52.h"
#include "nrf52_to_nrf52833.h"
#include "nrf52833_to_nrf52820.h"
#elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB)
#include "nrf52.h"
#include "nrf52_bitfields.h"
#include "nrf51_to_nrf52.h"
#include "nrf52_name_change.h"
#elif defined (NRF52833_XXAA)
#include "nrf52833.h"
#include "nrf52833_bitfields.h"
#include "nrf52_to_nrf52833.h"
#include "nrf51_to_nrf52.h"
#elif defined (NRF52840_XXAA)
#include "nrf52840.h"
#include "nrf52840_bitfields.h"
#include "nrf51_to_nrf52840.h"
#include "nrf52_to_nrf52840.h"
#elif defined (NRF5340_XXAA)
#if defined(NRF_APPLICATION)
#include "nrf5340_application.h"
#include "nrf5340_application_bitfields.h"
#include "nrf5340_application_name_change.h"
/* Address of locations in RAM that will be used to store a NS-accessible version of FICR */
#if !defined(NRF_FICR_NS)
#define NRF_FICR_NS_BASE 0x2007F000
#define NRF_FICR_NS ((NRF_FICR_Type*) NRF_FICR_NS_BASE)
#endif
#elif defined (NRF_NETWORK)
#include "nrf5340_network.h"
#include "nrf5340_network_bitfields.h"
#include "nrf5340_network_name_change.h"
#endif
#elif defined (NRF9160_XXAA)
#include "nrf9160.h"
#include "nrf9160_bitfields.h"
#include "nrf9160_name_change.h"
/* Address of locations in RAM that will be used to store a NS-accessible version of FICR */
#if !defined(NRF_FICR_NS)
#define NRF_FICR_NS_BASE 0x2003E000
#define NRF_FICR_NS ((NRF_FICR_Type*) NRF_FICR_NS_BASE)
#endif
#else
#error "Device must be defined. See nrf.h."
#endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52820_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF5340_XXAA_APPLICATION, NRF5340_XXAA_NETWORK, NRF9160_XXAA */
#include "compiler_abstraction.h"
#endif /* NRF_H */

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
/* This file is deprecated */
#ifndef _NRF51422_PERIPHERALS_H
#define _NRF51422_PERIPHERALS_H
/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 1
#define P0_PIN_NUM 32
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
/* MPU and BPROT */
#define BPROT_PRESENT
#define BPROT_REGIONS_SIZE 4096
#define BPROT_REGIONS_NUM 64
/* Radio */
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
#define AAR_MAX_IRK_NUM 8
/* AES Electronic CodeBook mode encryption */
#define ECB_PRESENT
#define ECB_COUNT 1
/* AES CCM mode encryption */
#define CCM_PRESENT
#define CCM_COUNT 1
/* Peripheral to Peripheral Interconnect */
#define PPI_PRESENT
#define PPI_COUNT 1
#define PPI_CH_NUM 16
#define PPI_FIXED_CH_NUM 12
#define PPI_GROUP_NUM 4
/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 3
#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 16
#define TIMER2_MAX_SIZE 16
#define TIMER0_CC_NUM 4
#define TIMER1_CC_NUM 4
#define TIMER2_CC_NUM 4
/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 2
#define RTC0_CC_NUM 3
#define RTC1_CC_NUM 4
/* RNG */
#define RNG_PRESENT
#define RNG_COUNT 1
/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 1
/* Temperature Sensor */
#define TEMP_PRESENT
#define TEMP_COUNT 1
/* Serial Peripheral Interface Master */
#define SPI_PRESENT
#define SPI_COUNT 2
/* Serial Peripheral Interface Slave with DMA */
#define SPIS_PRESENT
#define SPIS_COUNT 1
#define SPIS1_EASYDMA_MAXCNT_SIZE 8
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2
/* Universal Asynchronous Receiver-Transmitter */
#define UART_PRESENT
#define UART_COUNT 1
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 1
/* Analog to Digital Converter */
#define ADC_PRESENT
#define ADC_COUNT 1
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
#define GPIOTE_CH_NUM 4
/* Low Power Comparator */
#define LPCOMP_PRESENT
#define LPCOMP_COUNT 1
#define LPCOMP_REFSEL_RESOLUTION 8
#endif // _NRF51422_PERIPHERALS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
/* This file is deprecated */
#ifndef _NRF51801_PERIPHERALS_H
#define _NRF51801_PERIPHERALS_H
/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 1
#define P0_PIN_NUM 32
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
/* MPU and BPROT */
#define BPROT_PRESENT
#define BPROT_REGIONS_SIZE 4096
#define BPROT_REGIONS_NUM 64
/* Radio */
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
#define AAR_MAX_IRK_NUM 8
/* AES Electronic CodeBook mode encryption */
#define ECB_PRESENT
#define ECB_COUNT 1
/* AES CCM mode encryption */
#define CCM_PRESENT
#define CCM_COUNT 1
/* Peripheral to Peripheral Interconnect */
#define PPI_PRESENT
#define PPI_COUNT 1
#define PPI_CH_NUM 16
#define PPI_FIXED_CH_NUM 12
#define PPI_GROUP_NUM 4
/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 3
#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 16
#define TIMER2_MAX_SIZE 16
#define TIMER0_CC_NUM 4
#define TIMER1_CC_NUM 4
#define TIMER2_CC_NUM 4
/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 2
#define RTC0_CC_NUM 3
#define RTC1_CC_NUM 4
/* RNG */
#define RNG_PRESENT
#define RNG_COUNT 1
/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 1
/* Temperature Sensor */
#define TEMP_PRESENT
#define TEMP_COUNT 1
/* Serial Peripheral Interface Master */
#define SPI_PRESENT
#define SPI_COUNT 2
/* Serial Peripheral Interface Slave with DMA */
#define SPIS_PRESENT
#define SPIS_COUNT 1
#define SPIS1_EASYDMA_MAXCNT_SIZE 8
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2
/* Universal Asynchronous Receiver-Transmitter */
#define UART_PRESENT
#define UART_COUNT 1
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 1
/* Analog to Digital Converter */
#define ADC_PRESENT
#define ADC_COUNT 1
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
#define GPIOTE_CH_NUM 4
/* Low Power Comparator */
#define LPCOMP_PRESENT
#define LPCOMP_COUNT 1
#define LPCOMP_REFSEL_RESOLUTION 8
#endif // _NRF51801_PERIPHERALS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
/* This file is deprecated */
#ifndef _NRF51802_PERIPHERALS_H
#define _NRF51802_PERIPHERALS_H
/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 1
#define P0_PIN_NUM 32
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
/* MPU and BPROT */
#define BPROT_PRESENT
#define BPROT_REGIONS_SIZE 4096
#define BPROT_REGIONS_NUM 64
/* Radio */
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
#define AAR_MAX_IRK_NUM 8
/* AES Electronic CodeBook mode encryption */
#define ECB_PRESENT
#define ECB_COUNT 1
/* AES CCM mode encryption */
#define CCM_PRESENT
#define CCM_COUNT 1
/* Peripheral to Peripheral Interconnect */
#define PPI_PRESENT
#define PPI_COUNT 1
#define PPI_CH_NUM 16
#define PPI_FIXED_CH_NUM 12
#define PPI_GROUP_NUM 4
/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 3
#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 16
#define TIMER2_MAX_SIZE 16
#define TIMER0_CC_NUM 4
#define TIMER1_CC_NUM 4
#define TIMER2_CC_NUM 4
/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 2
#define RTC0_CC_NUM 3
#define RTC1_CC_NUM 4
/* RNG */
#define RNG_PRESENT
#define RNG_COUNT 1
/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 1
/* Temperature Sensor */
#define TEMP_PRESENT
#define TEMP_COUNT 1
/* Serial Peripheral Interface Master */
#define SPI_PRESENT
#define SPI_COUNT 2
/* Serial Peripheral Interface Slave with DMA */
#define SPIS_PRESENT
#define SPIS_COUNT 1
#define SPIS1_EASYDMA_MAXCNT_SIZE 8
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2
/* Universal Asynchronous Receiver-Transmitter */
#define UART_PRESENT
#define UART_COUNT 1
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 1
/* Analog to Digital Converter */
#define ADC_PRESENT
#define ADC_COUNT 1
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
#define GPIOTE_CH_NUM 4
/* Low Power Comparator */
#define LPCOMP_PRESENT
#define LPCOMP_COUNT 1
#define LPCOMP_REFSEL_RESOLUTION 8
#endif // _NRF51802_PERIPHERALS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
/* This file is deprecated */
#ifndef _NRF51822_PERIPHERALS_H
#define _NRF51822_PERIPHERALS_H
/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 1
#define P0_PIN_NUM 32
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
/* MPU and BPROT */
#define BPROT_PRESENT
#define BPROT_REGIONS_SIZE 4096
#define BPROT_REGIONS_NUM 64
/* Radio */
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
#define AAR_MAX_IRK_NUM 8
/* AES Electronic CodeBook mode encryption */
#define ECB_PRESENT
#define ECB_COUNT 1
/* AES CCM mode encryption */
#define CCM_PRESENT
#define CCM_COUNT 1
/* Peripheral to Peripheral Interconnect */
#define PPI_PRESENT
#define PPI_COUNT 1
#define PPI_CH_NUM 16
#define PPI_FIXED_CH_NUM 12
#define PPI_GROUP_NUM 4
/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 3
#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 16
#define TIMER2_MAX_SIZE 16
#define TIMER0_CC_NUM 4
#define TIMER1_CC_NUM 4
#define TIMER2_CC_NUM 4
/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 2
#define RTC0_CC_NUM 3
#define RTC1_CC_NUM 4
/* RNG */
#define RNG_PRESENT
#define RNG_COUNT 1
/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 1
/* Temperature Sensor */
#define TEMP_PRESENT
#define TEMP_COUNT 1
/* Serial Peripheral Interface Master */
#define SPI_PRESENT
#define SPI_COUNT 2
/* Serial Peripheral Interface Slave with DMA */
#define SPIS_PRESENT
#define SPIS_COUNT 1
#define SPIS1_EASYDMA_MAXCNT_SIZE 8
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2
/* Universal Asynchronous Receiver-Transmitter */
#define UART_PRESENT
#define UART_COUNT 1
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 1
/* Analog to Digital Converter */
#define ADC_PRESENT
#define ADC_COUNT 1
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
#define GPIOTE_CH_NUM 4
/* Low Power Comparator */
#define LPCOMP_PRESENT
#define LPCOMP_COUNT 1
#define LPCOMP_REFSEL_RESOLUTION 8
#endif // _NRF51822_PERIPHERALS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
/* This file is deprecated */
#ifndef _NRF51824_PERIPHERALS_H
#define _NRF51824_PERIPHERALS_H
/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 1
#define P0_PIN_NUM 32
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
/* MPU and BPROT */
#define BPROT_PRESENT
#define BPROT_REGIONS_SIZE 4096
#define BPROT_REGIONS_NUM 64
/* Radio */
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
#define AAR_MAX_IRK_NUM 8
/* AES Electronic CodeBook mode encryption */
#define ECB_PRESENT
#define ECB_COUNT 1
/* AES CCM mode encryption */
#define CCM_PRESENT
#define CCM_COUNT 1
/* Peripheral to Peripheral Interconnect */
#define PPI_PRESENT
#define PPI_COUNT 1
#define PPI_CH_NUM 16
#define PPI_FIXED_CH_NUM 12
#define PPI_GROUP_NUM 4
/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 3
#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 16
#define TIMER2_MAX_SIZE 16
#define TIMER0_CC_NUM 4
#define TIMER1_CC_NUM 4
#define TIMER2_CC_NUM 4
/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 2
#define RTC0_CC_NUM 3
#define RTC1_CC_NUM 4
/* RNG */
#define RNG_PRESENT
#define RNG_COUNT 1
/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 1
/* Temperature Sensor */
#define TEMP_PRESENT
#define TEMP_COUNT 1
/* Serial Peripheral Interface Master */
#define SPI_PRESENT
#define SPI_COUNT 2
/* Serial Peripheral Interface Slave with DMA */
#define SPIS_PRESENT
#define SPIS_COUNT 1
#define SPIS1_EASYDMA_MAXCNT_SIZE 8
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2
/* Universal Asynchronous Receiver-Transmitter */
#define UART_PRESENT
#define UART_COUNT 1
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 1
/* Analog to Digital Converter */
#define ADC_PRESENT
#define ADC_COUNT 1
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
#define GPIOTE_CH_NUM 4
/* Low Power Comparator */
#define LPCOMP_PRESENT
#define LPCOMP_COUNT 1
#define LPCOMP_REFSEL_RESOLUTION 8
#endif // _NRF51824_PERIPHERALS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF51_DEPRECATED_H
#define NRF51_DEPRECATED_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and
* nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these
* macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead.
*/
/* NVMC */
/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */
#define ERASEPROTECTEDPAGE ERASEPCR0
/* LPCOMP */
/* The interrupt ISR was renamed. Adding old name to the macros. */
#define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler
#define LPCOMP_COMP_IRQn LPCOMP_IRQn
/* Corrected typo in RESULT register. */
#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
/* MPU */
/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */
#define MPU_PERR0_LPCOMP_COMP_Pos MPU_PERR0_LPCOMP_Pos
#define MPU_PERR0_LPCOMP_COMP_Msk MPU_PERR0_LPCOMP_Msk
#define MPU_PERR0_LPCOMP_COMP_InRegion1 MPU_PERR0_LPCOMP_InRegion1
#define MPU_PERR0_LPCOMP_COMP_InRegion0 MPU_PERR0_LPCOMP_InRegion0
/* POWER */
/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_OFFRAM3_Pos (19UL)
#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos)
#define POWER_RAMON_OFFRAM3_RAM3Off (0UL)
#define POWER_RAMON_OFFRAM3_RAM3On (1UL)
/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_OFFRAM2_Pos (18UL)
#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos)
#define POWER_RAMON_OFFRAM2_RAM2Off (0UL)
#define POWER_RAMON_OFFRAM2_RAM2On (1UL)
/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_ONRAM3_Pos (3UL)
#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos)
#define POWER_RAMON_ONRAM3_RAM3Off (0UL)
#define POWER_RAMON_ONRAM3_RAM3On (1UL)
/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_ONRAM2_Pos (2UL)
#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos)
#define POWER_RAMON_ONRAM2_RAM2Off (0UL)
#define POWER_RAMON_ONRAM2_RAM2On (1UL)
/* RADIO */
/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */
#define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm
/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos
#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk
#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include
#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip
/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */
#define RADIO_TEST_PLL_LOCK_Pos RADIO_TEST_PLLLOCK_Pos
#define RADIO_TEST_PLL_LOCK_Msk RADIO_TEST_PLLLOCK_Msk
#define RADIO_TEST_PLL_LOCK_Disabled RADIO_TEST_PLLLOCK_Disabled
#define RADIO_TEST_PLL_LOCK_Enabled RADIO_TEST_PLLLOCK_Enabled
/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */
#define RADIO_TEST_CONST_CARRIER_Pos RADIO_TEST_CONSTCARRIER_Pos
#define RADIO_TEST_CONST_CARRIER_Msk RADIO_TEST_CONSTCARRIER_Msk
#define RADIO_TEST_CONST_CARRIER_Disabled RADIO_TEST_CONSTCARRIER_Disabled
#define RADIO_TEST_CONST_CARRIER_Enabled RADIO_TEST_CONSTCARRIER_Enabled
/* FICR */
/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */
#define SIZERAMBLOCK0 SIZERAMBLOCKS
#define SIZERAMBLOCK1 SIZERAMBLOCKS
#define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
#define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
#define DEVICEID0 DEVICEID[0]
#define DEVICEID1 DEVICEID[1]
/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
#define ER0 ER[0]
#define ER1 ER[1]
#define ER2 ER[2]
#define ER3 ER[3]
/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
#define IR0 IR[0]
#define IR1 IR[1]
#define IR2 IR[2]
#define IR3 IR[3]
/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
#define DEVICEADDR0 DEVICEADDR[0]
#define DEVICEADDR1 DEVICEADDR[1]
/* PPI */
/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
#define TASKS_CHG0EN TASKS_CHG[0].EN
#define TASKS_CHG0DIS TASKS_CHG[0].DIS
#define TASKS_CHG1EN TASKS_CHG[1].EN
#define TASKS_CHG1DIS TASKS_CHG[1].DIS
#define TASKS_CHG2EN TASKS_CHG[2].EN
#define TASKS_CHG2DIS TASKS_CHG[2].DIS
#define TASKS_CHG3EN TASKS_CHG[3].EN
#define TASKS_CHG3DIS TASKS_CHG[3].DIS
/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
#define CH0_EEP CH[0].EEP
#define CH0_TEP CH[0].TEP
#define CH1_EEP CH[1].EEP
#define CH1_TEP CH[1].TEP
#define CH2_EEP CH[2].EEP
#define CH2_TEP CH[2].TEP
#define CH3_EEP CH[3].EEP
#define CH3_TEP CH[3].TEP
#define CH4_EEP CH[4].EEP
#define CH4_TEP CH[4].TEP
#define CH5_EEP CH[5].EEP
#define CH5_TEP CH[5].TEP
#define CH6_EEP CH[6].EEP
#define CH6_TEP CH[6].TEP
#define CH7_EEP CH[7].EEP
#define CH7_TEP CH[7].TEP
#define CH8_EEP CH[8].EEP
#define CH8_TEP CH[8].TEP
#define CH9_EEP CH[9].EEP
#define CH9_TEP CH[9].TEP
#define CH10_EEP CH[10].EEP
#define CH10_TEP CH[10].TEP
#define CH11_EEP CH[11].EEP
#define CH11_TEP CH[11].TEP
#define CH12_EEP CH[12].EEP
#define CH12_TEP CH[12].TEP
#define CH13_EEP CH[13].EEP
#define CH13_TEP CH[13].TEP
#define CH14_EEP CH[14].EEP
#define CH14_TEP CH[14].TEP
#define CH15_EEP CH[15].EEP
#define CH15_TEP CH[15].TEP
/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
#define CHG0 CHG[0]
#define CHG1 CHG[1]
#define CHG2 CHG[2]
#define CHG3 CHG[3]
/* All bitfield macros for the CHGx registers therefore changed name. */
#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included
/* SPIS */
/* nRF51 devices do not have an SPIS0, only SPIS1. SPIS0_EASYDMA_MAXCNT_SIZE was therefore renamed. */
#define SPIS0_EASYDMA_MAXCNT_SIZE SPIS1_EASYDMA_MAXCNT_SIZE
/*lint --flb "Leave library region" */
#endif /* NRF51_DEPRECATED_H */

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _NRF51_PERIPHERALS_H
#define _NRF51_PERIPHERALS_H
/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 1
#define P0_PIN_NUM 32
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
/* MPU and BPROT */
#define BPROT_PRESENT
#define BPROT_REGIONS_SIZE 4096
#define BPROT_REGIONS_NUM 64
/* Radio */
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
#define AAR_MAX_IRK_NUM 8
/* AES Electronic CodeBook mode encryption */
#define ECB_PRESENT
#define ECB_COUNT 1
/* AES CCM mode encryption */
#define CCM_PRESENT
#define CCM_COUNT 1
/* Peripheral to Peripheral Interconnect */
#define PPI_PRESENT
#define PPI_COUNT 1
#define PPI_CH_NUM 16
#define PPI_FIXED_CH_NUM 12
#define PPI_GROUP_NUM 4
/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 3
#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 16
#define TIMER2_MAX_SIZE 16
#define TIMER0_CC_NUM 4
#define TIMER1_CC_NUM 4
#define TIMER2_CC_NUM 4
/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 2
#define RTC0_CC_NUM 3
#define RTC1_CC_NUM 4
/* RNG */
#define RNG_PRESENT
#define RNG_COUNT 1
/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 1
/* Temperature Sensor */
#define TEMP_PRESENT
#define TEMP_COUNT 1
/* Serial Peripheral Interface Master */
#define SPI_PRESENT
#define SPI_COUNT 2
/* Serial Peripheral Interface Slave with DMA */
#define SPIS_PRESENT
#define SPIS_COUNT 1
#define SPIS1_EASYDMA_MAXCNT_SIZE 8
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2
/* Universal Asynchronous Receiver-Transmitter */
#define UART_PRESENT
#define UART_COUNT 1
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 1
/* Analog to Digital Converter */
#define ADC_PRESENT
#define ADC_COUNT 1
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
#define GPIOTE_CH_NUM 4
/* Low Power Comparator */
#define LPCOMP_PRESENT
#define LPCOMP_COUNT 1
#define LPCOMP_REFSEL_RESOLUTION 8
#endif // _NRF51_PERIPHERALS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _NRF52805_PERIPHERALS_H
#define _NRF52805_PERIPHERALS_H
/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
#define POWER_FEATURE_RAM_REGISTERS_COUNT 3
/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1
/* Systick timer */
#define SYSTICK_PRESENT
#define SYSTICK_COUNT 1
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 1
#define P0_PIN_NUM 32
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
/* MPU and BPROT */
#define BPROT_PRESENT
#define BPROT_REGIONS_SIZE 4096
#define BPROT_REGIONS_NUM 48
/* Radio */
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_EASYDMA_MAXCNT_SIZE 8
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
#define AAR_MAX_IRK_NUM 16
/* AES Electronic CodeBook mode encryption */
#define ECB_PRESENT
#define ECB_COUNT 1
/* AES CCM mode encryption */
#define CCM_PRESENT
#define CCM_COUNT 1
/* Peripheral to Peripheral Interconnect */
#define PPI_PRESENT
#define PPI_COUNT 1
#define PPI_CH_NUM 10
#define PPI_FIXED_CH_NUM 12
#define PPI_GROUP_NUM 6
#define PPI_FEATURE_FORKS_PRESENT
/* Event Generator Unit */
#define EGU_PRESENT
#define EGU_COUNT 2
#define EGU0_CH_NUM 16
#define EGU1_CH_NUM 16
/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 3
#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 32
#define TIMER2_MAX_SIZE 32
#define TIMER0_CC_NUM 4
#define TIMER1_CC_NUM 4
#define TIMER2_CC_NUM 4
/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 2
#define RTC0_CC_NUM 3
#define RTC1_CC_NUM 4
/* RNG */
#define RNG_PRESENT
#define RNG_COUNT 1
/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 1
/* Temperature Sensor */
#define TEMP_PRESENT
#define TEMP_COUNT 1
/* Serial Peripheral Interface Master */
#define SPI_PRESENT
#define SPI_COUNT 1
/* Serial Peripheral Interface Master with DMA */
#define SPIM_PRESENT
#define SPIM_COUNT 1
#define SPIM0_MAX_DATARATE 8
#define SPIM1_MAX_DATARATE 8
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM0_FEATURE_DCX_PRESENT 0
#define SPIM1_FEATURE_DCX_PRESENT 0
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
#define SPIM1_FEATURE_RXDELAY_PRESENT 0
#define SPIM0_EASYDMA_MAXCNT_SIZE 14
#define SPIM1_EASYDMA_MAXCNT_SIZE 14
/* Serial Peripheral Interface Slave with DMA*/
#define SPIS_PRESENT
#define SPIS_COUNT 1
#define SPIS0_EASYDMA_MAXCNT_SIZE 14
#define SPIS1_EASYDMA_MAXCNT_SIZE 14
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 1
/* Two Wire Interface Master with DMA */
#define TWIM_PRESENT
#define TWIM_COUNT 1
#define TWIM0_EASYDMA_MAXCNT_SIZE 14
/* Two Wire Interface Slave with DMA */
#define TWIS_PRESENT
#define TWIS_COUNT 1
#define TWIS0_EASYDMA_MAXCNT_SIZE 14
/* Universal Asynchronous Receiver-Transmitter */
#define UART_PRESENT
#define UART_COUNT 1
/* Universal Asynchronous Receiver-Transmitter with DMA */
#define UARTE_PRESENT
#define UARTE_COUNT 1
#define UARTE0_EASYDMA_MAXCNT_SIZE 14
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 1
/* Successive Approximation Analog to Digital Converter */
#define SAADC_PRESENT
#define SAADC_COUNT 1
#define SAADC_EASYDMA_MAXCNT_SIZE 15
#define SAADC_CH_NUM 8
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
#define GPIOTE_CH_NUM 8
#define GPIOTE_FEATURE_SET_PRESENT
#define GPIOTE_FEATURE_CLR_PRESENT
#endif // _NRF52805_PERIPHERALS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF52810_NAME_CHANGE_H
#define NRF52810_NAME_CHANGE_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the updates made to nrf52810.h and
* nrf52810_bitfields.h. The macros defined in this file were available previously. Do not use these
* macros on purpose. Use the ones defined in nrf52810.h and nrf52810_bitfields.h instead.
*/
/* IRQ */
/* Changes of interrupt names */
#define SPIM0_SPIS0_IRQn SPIM0_SPIS0_SPI0_IRQn
#define TWIM0_TWIS0_IRQn TWIM0_TWIS0_TWI0_IRQn
#define UARTE0_IRQn UARTE0_UART0_IRQn
#define SPIM0_SPIS0_IRQHandler SPIM0_SPIS0_SPI0_IRQHandler
#define TWIM0_TWIS0_IRQHandler TWIM0_TWIS0_TWI0_IRQHandler
#define UARTE0_IRQHandler UARTE0_UART0_IRQHandler
/*lint --flb "Leave library region" */
#endif /* NRF52810_NAME_CHANGE_H */

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _NRF52810_PERIPHERALS_H
#define _NRF52810_PERIPHERALS_H
/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
#define POWER_FEATURE_RAM_REGISTERS_COUNT 3
/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1
/* Systick timer */
#define SYSTICK_PRESENT
#define SYSTICK_COUNT 1
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 1
#define P0_PIN_NUM 32
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
/* MPU and BPROT */
#define BPROT_PRESENT
#define BPROT_REGIONS_SIZE 4096
#define BPROT_REGIONS_NUM 48
/* Radio */
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_EASYDMA_MAXCNT_SIZE 8
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
#define AAR_MAX_IRK_NUM 16
/* AES Electronic CodeBook mode encryption */
#define ECB_PRESENT
#define ECB_COUNT 1
/* AES CCM mode encryption */
#define CCM_PRESENT
#define CCM_COUNT 1
/* Peripheral to Peripheral Interconnect */
#define PPI_PRESENT
#define PPI_COUNT 1
#define PPI_CH_NUM 20
#define PPI_FIXED_CH_NUM 12
#define PPI_GROUP_NUM 6
#define PPI_FEATURE_FORKS_PRESENT
/* Event Generator Unit */
#define EGU_PRESENT
#define EGU_COUNT 2
#define EGU0_CH_NUM 16
#define EGU1_CH_NUM 16
/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 3
#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 32
#define TIMER2_MAX_SIZE 32
#define TIMER0_CC_NUM 4
#define TIMER1_CC_NUM 4
#define TIMER2_CC_NUM 4
/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 2
#define RTC0_CC_NUM 3
#define RTC1_CC_NUM 4
/* RNG */
#define RNG_PRESENT
#define RNG_COUNT 1
/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 1
/* Temperature Sensor */
#define TEMP_PRESENT
#define TEMP_COUNT 1
/* Serial Peripheral Interface Master */
#define SPI_PRESENT
#define SPI_COUNT 1
/* Serial Peripheral Interface Master with DMA */
#define SPIM_PRESENT
#define SPIM_COUNT 1
#define SPIM0_MAX_DATARATE 8
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM0_FEATURE_DCX_PRESENT 0
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
#define SPIM0_EASYDMA_MAXCNT_SIZE 10
/* Serial Peripheral Interface Slave with DMA*/
#define SPIS_PRESENT
#define SPIS_COUNT 1
#define SPIS0_EASYDMA_MAXCNT_SIZE 10
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 1
/* Two Wire Interface Master with DMA */
#define TWIM_PRESENT
#define TWIM_COUNT 1
#define TWIM0_EASYDMA_MAXCNT_SIZE 10
/* Two Wire Interface Slave with DMA */
#define TWIS_PRESENT
#define TWIS_COUNT 1
#define TWIS0_EASYDMA_MAXCNT_SIZE 10
/* Universal Asynchronous Receiver-Transmitter */
#define UART_PRESENT
#define UART_COUNT 1
/* Universal Asynchronous Receiver-Transmitter with DMA */
#define UARTE_PRESENT
#define UARTE_COUNT 1
#define UARTE0_EASYDMA_MAXCNT_SIZE 10
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 1
/* Successive Approximation Analog to Digital Converter */
#define SAADC_PRESENT
#define SAADC_COUNT 1
#define SAADC_EASYDMA_MAXCNT_SIZE 15
#define SAADC_CH_NUM 8
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
#define GPIOTE_CH_NUM 8
#define GPIOTE_FEATURE_SET_PRESENT
#define GPIOTE_FEATURE_CLR_PRESENT
/* Comparator */
#define COMP_PRESENT
#define COMP_COUNT 1
/* Pulse Width Modulator */
#define PWM_PRESENT
#define PWM_COUNT 1
#define PWM0_CH_NUM 4
#define PWM0_EASYDMA_MAXCNT_SIZE 15
/* Pulse Density Modulator */
#define PDM_PRESENT
#define PDM_COUNT 1
#define PDM_EASYDMA_MAXCNT_SIZE 15
#endif // _NRF52810_PERIPHERALS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF52810_TO_NRF52811_H
#define NRF52810_TO_NRF52811_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the name changes between nRF52810 and nRF52811 devices.
* It redefines the old nRF52810 names into the new ones as long as the functionality is still supported. If the
* functionality is gone, there old names are not defined, so compilation will fail. */
/* Differences between latest nRF52810 headers and nRF52811 headers. */
/* Interrupt service routines handlers. */
#ifndef TWIM0_TWIS0_IRQHandler
#define TWIM0_TWIS0_IRQHandler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
#endif
/* Interrupt service routines index. */
#ifndef TWIM0_TWIS0_IRQn
#define TWIM0_TWIS0_IRQn TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQn
#endif
/*lint --flb "Leave library region" */
#endif /* NRF52810_TO_NRF52811_H */

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _NRF52811_PERIPHERALS_H
#define _NRF52811_PERIPHERALS_H
/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
#define POWER_FEATURE_RAM_REGISTERS_COUNT 3
/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1
/* Systick timer */
#define SYSTICK_PRESENT
#define SYSTICK_COUNT 1
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 1
#define P0_PIN_NUM 32
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
/* MPU and BPROT */
#define BPROT_PRESENT
#define BPROT_REGIONS_SIZE 4096
#define BPROT_REGIONS_NUM 48
/* Radio */
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_EASYDMA_MAXCNT_SIZE 8
#define RADIO_FEATURE_IEEE_802_15_4_PRESENT
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
#define AAR_MAX_IRK_NUM 16
/* AES Electronic CodeBook mode encryption */
#define ECB_PRESENT
#define ECB_COUNT 1
/* AES CCM mode encryption */
#define CCM_PRESENT
#define CCM_COUNT 1
/* Peripheral to Peripheral Interconnect */
#define PPI_PRESENT
#define PPI_COUNT 1
#define PPI_CH_NUM 20
#define PPI_FIXED_CH_NUM 12
#define PPI_GROUP_NUM 6
#define PPI_FEATURE_FORKS_PRESENT
/* Event Generator Unit */
#define EGU_PRESENT
#define EGU_COUNT 2
#define EGU0_CH_NUM 16
#define EGU1_CH_NUM 16
/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 3
#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 32
#define TIMER2_MAX_SIZE 32
#define TIMER0_CC_NUM 4
#define TIMER1_CC_NUM 4
#define TIMER2_CC_NUM 4
/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 2
#define RTC0_CC_NUM 3
#define RTC1_CC_NUM 4
/* RNG */
#define RNG_PRESENT
#define RNG_COUNT 1
/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 1
/* Temperature Sensor */
#define TEMP_PRESENT
#define TEMP_COUNT 1
/* Serial Peripheral Interface Master */
#define SPI_PRESENT
#define SPI_COUNT 2
/* Serial Peripheral Interface Master with DMA */
#define SPIM_PRESENT
#define SPIM_COUNT 2
#define SPIM0_MAX_DATARATE 8
#define SPIM1_MAX_DATARATE 8
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM0_FEATURE_DCX_PRESENT 0
#define SPIM1_FEATURE_DCX_PRESENT 0
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
#define SPIM1_FEATURE_RXDELAY_PRESENT 0
#define SPIM0_EASYDMA_MAXCNT_SIZE 14
#define SPIM1_EASYDMA_MAXCNT_SIZE 14
/* Serial Peripheral Interface Slave with DMA*/
#define SPIS_PRESENT
#define SPIS_COUNT 2
#define SPIS0_EASYDMA_MAXCNT_SIZE 14
#define SPIS1_EASYDMA_MAXCNT_SIZE 14
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 1
/* Two Wire Interface Master with DMA */
#define TWIM_PRESENT
#define TWIM_COUNT 1
#define TWIM0_EASYDMA_MAXCNT_SIZE 14
/* Two Wire Interface Slave with DMA */
#define TWIS_PRESENT
#define TWIS_COUNT 1
#define TWIS0_EASYDMA_MAXCNT_SIZE 14
/* Universal Asynchronous Receiver-Transmitter */
#define UART_PRESENT
#define UART_COUNT 1
/* Universal Asynchronous Receiver-Transmitter with DMA */
#define UARTE_PRESENT
#define UARTE_COUNT 1
#define UARTE0_EASYDMA_MAXCNT_SIZE 14
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 1
/* Successive Approximation Analog to Digital Converter */
#define SAADC_PRESENT
#define SAADC_COUNT 1
#define SAADC_EASYDMA_MAXCNT_SIZE 15
#define SAADC_CH_NUM 8
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
#define GPIOTE_CH_NUM 8
#define GPIOTE_FEATURE_SET_PRESENT
#define GPIOTE_FEATURE_CLR_PRESENT
/* Comparator */
#define COMP_PRESENT
#define COMP_COUNT 1
/* Pulse Width Modulator */
#define PWM_PRESENT
#define PWM_COUNT 1
#define PWM0_CH_NUM 4
#define PWM0_EASYDMA_MAXCNT_SIZE 15
/* Pulse Density Modulator */
#define PDM_PRESENT
#define PDM_COUNT 1
#define PDM_EASYDMA_MAXCNT_SIZE 15
#endif // _NRF52811_PERIPHERALS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _NRF52820_PERIPHERALS_H
#define _NRF52820_PERIPHERALS_H
/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
#define POWER_FEATURE_RAM_REGISTERS_COUNT 4
#define POWER_FEATURE_VDDH_PRESENT
/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1
/* Systick timer */
#define SYSTICK_PRESENT
#define SYSTICK_COUNT 1
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 1
#define P0_PIN_NUM (18)
#define P0_FEATURE_PINS_PRESENT (nrf52_errata_230() ? 0xF0168E3Ful : 0x7017C1FFul)
/* ACL */
#define ACL_PRESENT
#define ACL_REGIONS_COUNT 8
/* Radio */
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_EASYDMA_MAXCNT_SIZE 14
#define RADIO_FEATURE_IEEE_802_15_4_PRESENT
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
#define AAR_MAX_IRK_NUM 16
/* AES Electronic CodeBook mode encryption */
#define ECB_PRESENT
#define ECB_COUNT 1
/* AES CCM mode encryption */
#define CCM_PRESENT
#define CCM_COUNT 1
/* Peripheral to Peripheral Interconnect */
#define PPI_PRESENT
#define PPI_COUNT 1
#define PPI_CH_NUM 20
#define PPI_FIXED_CH_NUM 12
#define PPI_GROUP_NUM 6
#define PPI_FEATURE_FORKS_PRESENT
/* Event Generator Unit */
#define EGU_PRESENT
#define EGU_COUNT 6
#define EGU0_CH_NUM 16
#define EGU1_CH_NUM 16
#define EGU2_CH_NUM 16
#define EGU3_CH_NUM 16
#define EGU4_CH_NUM 16
#define EGU5_CH_NUM 16
/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 4
#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 32
#define TIMER2_MAX_SIZE 32
#define TIMER3_MAX_SIZE 32
#define TIMER0_CC_NUM 4
#define TIMER1_CC_NUM 4
#define TIMER2_CC_NUM 4
#define TIMER3_CC_NUM 6
/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 2
#define RTC0_CC_NUM 3
#define RTC1_CC_NUM 4
/* RNG */
#define RNG_PRESENT
#define RNG_COUNT 1
/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 1
/* Temperature Sensor */
#define TEMP_PRESENT
#define TEMP_COUNT 1
/* Serial Peripheral Interface Master */
#define SPI_PRESENT
#define SPI_COUNT 2
/* Serial Peripheral Interface Master with DMA */
#define SPIM_PRESENT
#define SPIM_COUNT 2
#define SPIM0_MAX_DATARATE 8
#define SPIM1_MAX_DATARATE 8
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM0_FEATURE_DCX_PRESENT 0
#define SPIM1_FEATURE_DCX_PRESENT 0
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
#define SPIM1_FEATURE_RXDELAY_PRESENT 0
#define SPIM0_EASYDMA_MAXCNT_SIZE 15
#define SPIM1_EASYDMA_MAXCNT_SIZE 15
/* Serial Peripheral Interface Slave with DMA*/
#define SPIS_PRESENT
#define SPIS_COUNT 2
#define SPIS0_EASYDMA_MAXCNT_SIZE 15
#define SPIS1_EASYDMA_MAXCNT_SIZE 15
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2
/* Two Wire Interface Master with DMA */
#define TWIM_PRESENT
#define TWIM_COUNT 2
#define TWIM0_EASYDMA_MAXCNT_SIZE 15
#define TWIM1_EASYDMA_MAXCNT_SIZE 15
/* Two Wire Interface Slave with DMA */
#define TWIS_PRESENT
#define TWIS_COUNT 2
#define TWIS0_EASYDMA_MAXCNT_SIZE 15
#define TWIS1_EASYDMA_MAXCNT_SIZE 15
/* Universal Asynchronous Receiver-Transmitter */
#define UART_PRESENT
#define UART_COUNT 1
/* Universal Asynchronous Receiver-Transmitter with DMA */
#define UARTE_PRESENT
#define UARTE_COUNT 1
#define UARTE0_EASYDMA_MAXCNT_SIZE 15
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 1
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
#define GPIOTE_CH_NUM 8
#define GPIOTE_FEATURE_SET_PRESENT
#define GPIOTE_FEATURE_CLR_PRESENT
/* Comparator */
#define COMP_PRESENT
#define COMP_COUNT 1
/* Universal Serial Bus Device */
#define USBD_PRESENT
#define USBD_COUNT 1
#define USBD_EASYDMA_MAXCNT_SIZE 7
#endif // _NRF52820_PERIPHERALS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _NRF52832_PERIPHERALS_H
#define _NRF52832_PERIPHERALS_H
/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
#if defined(NRF52832_XXAA)
#define POWER_FEATURE_RAM_REGISTERS_COUNT 8
#elif defined(NRF52832_XXAB)
#define POWER_FEATURE_RAM_REGISTERS_COUNT 4
#endif
/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1
#define NVMC_FEATURE_CACHE_PRESENT
/* Floating Point Unit */
#define FPU_PRESENT
#define FPU_COUNT 1
/* Systick timer */
#define SYSTICK_PRESENT
#define SYSTICK_COUNT 1
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
/* Memory Watch Unit */
#define MWU_PRESENT
#define MWU_COUNT 1
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 1
#define P0_PIN_NUM 32
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
/* MPU and BPROT */
#define BPROT_PRESENT
#define BPROT_REGIONS_SIZE 4096
#if defined(NRF52832_XXAA)
#define BPROT_REGIONS_NUM 128
#elif defined(NRF52832_XXAB)
#define BPROT_REGIONS_NUM 64
#endif
/* Radio */
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_EASYDMA_MAXCNT_SIZE 8
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
#define AAR_MAX_IRK_NUM 16
/* AES Electronic CodeBook mode encryption */
#define ECB_PRESENT
#define ECB_COUNT 1
/* AES CCM mode encryption */
#define CCM_PRESENT
#define CCM_COUNT 1
/* NFC Tag */
#define NFCT_PRESENT
#define NFCT_COUNT 1
#define NFCT_EASYDMA_MAXCNT_SIZE 9
/* Peripheral to Peripheral Interconnect */
#define PPI_PRESENT
#define PPI_COUNT 1
#define PPI_CH_NUM 20
#define PPI_FIXED_CH_NUM 12
#define PPI_GROUP_NUM 6
#define PPI_FEATURE_FORKS_PRESENT
/* Event Generator Unit */
#define EGU_PRESENT
#define EGU_COUNT 6
#define EGU0_CH_NUM 16
#define EGU1_CH_NUM 16
#define EGU2_CH_NUM 16
#define EGU3_CH_NUM 16
#define EGU4_CH_NUM 16
#define EGU5_CH_NUM 16
/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 5
#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 32
#define TIMER2_MAX_SIZE 32
#define TIMER3_MAX_SIZE 32
#define TIMER4_MAX_SIZE 32
#define TIMER0_CC_NUM 4
#define TIMER1_CC_NUM 4
#define TIMER2_CC_NUM 4
#define TIMER3_CC_NUM 6
#define TIMER4_CC_NUM 6
/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 3
#define RTC0_CC_NUM 3
#define RTC1_CC_NUM 4
#define RTC2_CC_NUM 4
/* RNG */
#define RNG_PRESENT
#define RNG_COUNT 1
/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 1
/* Temperature Sensor */
#define TEMP_PRESENT
#define TEMP_COUNT 1
/* Serial Peripheral Interface Master */
#define SPI_PRESENT
#define SPI_COUNT 3
/* Serial Peripheral Interface Master with DMA */
#define SPIM_PRESENT
#define SPIM_COUNT 3
#define SPIM0_MAX_DATARATE 8
#define SPIM1_MAX_DATARATE 8
#define SPIM2_MAX_DATARATE 8
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM0_FEATURE_DCX_PRESENT 0
#define SPIM1_FEATURE_DCX_PRESENT 0
#define SPIM2_FEATURE_DCX_PRESENT 0
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
#define SPIM1_FEATURE_RXDELAY_PRESENT 0
#define SPIM2_FEATURE_RXDELAY_PRESENT 0
#define SPIM0_EASYDMA_MAXCNT_SIZE 8
#define SPIM1_EASYDMA_MAXCNT_SIZE 8
#define SPIM2_EASYDMA_MAXCNT_SIZE 8
/* Serial Peripheral Interface Slave with DMA*/
#define SPIS_PRESENT
#define SPIS_COUNT 3
#define SPIS0_EASYDMA_MAXCNT_SIZE 8
#define SPIS1_EASYDMA_MAXCNT_SIZE 8
#define SPIS2_EASYDMA_MAXCNT_SIZE 8
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2
/* Two Wire Interface Master with DMA */
#define TWIM_PRESENT
#define TWIM_COUNT 2
#define TWIM0_EASYDMA_MAXCNT_SIZE 8
#define TWIM1_EASYDMA_MAXCNT_SIZE 8
/* Two Wire Interface Slave with DMA */
#define TWIS_PRESENT
#define TWIS_COUNT 2
#define TWIS0_EASYDMA_MAXCNT_SIZE 8
#define TWIS1_EASYDMA_MAXCNT_SIZE 8
/* Universal Asynchronous Receiver-Transmitter */
#define UART_PRESENT
#define UART_COUNT 1
/* Universal Asynchronous Receiver-Transmitter with DMA */
#define UARTE_PRESENT
#define UARTE_COUNT 1
#define UARTE0_EASYDMA_MAXCNT_SIZE 8
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 1
/* Successive Approximation Analog to Digital Converter */
#define SAADC_PRESENT
#define SAADC_COUNT 1
#define SAADC_EASYDMA_MAXCNT_SIZE 15
#define SAADC_CH_NUM 8
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
#define GPIOTE_CH_NUM 8
#define GPIOTE_FEATURE_SET_PRESENT
#define GPIOTE_FEATURE_CLR_PRESENT
/* Low Power Comparator */
#define LPCOMP_PRESENT
#define LPCOMP_COUNT 1
#define LPCOMP_REFSEL_RESOLUTION 16
#define LPCOMP_FEATURE_HYST_PRESENT
/* Comparator */
#define COMP_PRESENT
#define COMP_COUNT 1
/* Pulse Width Modulator */
#define PWM_PRESENT
#define PWM_COUNT 3
#define PWM0_CH_NUM 4
#define PWM1_CH_NUM 4
#define PWM2_CH_NUM 4
#define PWM0_EASYDMA_MAXCNT_SIZE 15
#define PWM1_EASYDMA_MAXCNT_SIZE 15
#define PWM2_EASYDMA_MAXCNT_SIZE 15
/* Pulse Density Modulator */
#define PDM_PRESENT
#define PDM_COUNT 1
#define PDM_EASYDMA_MAXCNT_SIZE 15
/* Inter-IC Sound Interface */
#define I2S_PRESENT
#define I2S_COUNT 1
#define I2S_EASYDMA_MAXCNT_SIZE 14
#endif // _NRF52832_PERIPHERALS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _NRF52833_PERIPHERALS_H
#define _NRF52833_PERIPHERALS_H
/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1
#define CLOCK_FEATURE_LFXO_EXTENDED_DEBOUNCE_PRESENT
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
#define POWER_FEATURE_RAM_REGISTERS_COUNT 9
#define POWER_FEATURE_VDDH_PRESENT
/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1
#define NVMC_FEATURE_CACHE_PRESENT
/* Floating Point Unit */
#define FPU_PRESENT
#define FPU_COUNT 1
/* Systick timer */
#define SYSTICK_PRESENT
#define SYSTICK_COUNT 1
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
/* Memory Watch Unit */
#define MWU_PRESENT
#define MWU_COUNT 1
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 2
#define P0_PIN_NUM 32
#define P1_PIN_NUM 10
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
#define P1_FEATURE_PINS_PRESENT 0x000003FFUL
/* ACL */
#define ACL_PRESENT
#define ACL_REGIONS_COUNT 8
/* Radio */
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_EASYDMA_MAXCNT_SIZE 8
#define RADIO_FEATURE_IEEE_802_15_4_PRESENT
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
#define AAR_MAX_IRK_NUM 16
/* AES Electronic CodeBook mode encryption */
#define ECB_PRESENT
#define ECB_COUNT 1
/* AES CCM mode encryption */
#define CCM_PRESENT
#define CCM_COUNT 1
/* NFC Tag */
#define NFCT_PRESENT
#define NFCT_COUNT 1
#define NFCT_EASYDMA_MAXCNT_SIZE 9
/* Peripheral to Peripheral Interconnect */
#define PPI_PRESENT
#define PPI_COUNT 1
#define PPI_CH_NUM 20
#define PPI_FIXED_CH_NUM 12
#define PPI_GROUP_NUM 6
#define PPI_FEATURE_FORKS_PRESENT
/* Event Generator Unit */
#define EGU_PRESENT
#define EGU_COUNT 6
#define EGU0_CH_NUM 16
#define EGU1_CH_NUM 16
#define EGU2_CH_NUM 16
#define EGU3_CH_NUM 16
#define EGU4_CH_NUM 16
#define EGU5_CH_NUM 16
/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 5
#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 32
#define TIMER2_MAX_SIZE 32
#define TIMER3_MAX_SIZE 32
#define TIMER4_MAX_SIZE 32
#define TIMER0_CC_NUM 4
#define TIMER1_CC_NUM 4
#define TIMER2_CC_NUM 4
#define TIMER3_CC_NUM 6
#define TIMER4_CC_NUM 6
/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 3
#define RTC0_CC_NUM 3
#define RTC1_CC_NUM 4
#define RTC2_CC_NUM 4
/* RNG */
#define RNG_PRESENT
#define RNG_COUNT 1
/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 1
/* Temperature Sensor */
#define TEMP_PRESENT
#define TEMP_COUNT 1
/* Serial Peripheral Interface Master */
#define SPI_PRESENT
#define SPI_COUNT 3
/* Serial Peripheral Interface Master with DMA */
#define SPIM_PRESENT
#define SPIM_COUNT 4
#define SPIM0_MAX_DATARATE 8
#define SPIM1_MAX_DATARATE 8
#define SPIM2_MAX_DATARATE 8
#define SPIM3_MAX_DATARATE 32
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM3_FEATURE_HARDWARE_CSN_PRESENT 1
#define SPIM0_FEATURE_DCX_PRESENT 0
#define SPIM1_FEATURE_DCX_PRESENT 0
#define SPIM2_FEATURE_DCX_PRESENT 0
#define SPIM3_FEATURE_DCX_PRESENT 1
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
#define SPIM1_FEATURE_RXDELAY_PRESENT 0
#define SPIM2_FEATURE_RXDELAY_PRESENT 0
#define SPIM3_FEATURE_RXDELAY_PRESENT 1
#define SPIM0_EASYDMA_MAXCNT_SIZE 16
#define SPIM1_EASYDMA_MAXCNT_SIZE 16
#define SPIM2_EASYDMA_MAXCNT_SIZE 16
#define SPIM3_EASYDMA_MAXCNT_SIZE 16
/* Serial Peripheral Interface Slave with DMA*/
#define SPIS_PRESENT
#define SPIS_COUNT 3
#define SPIS0_EASYDMA_MAXCNT_SIZE 16
#define SPIS1_EASYDMA_MAXCNT_SIZE 16
#define SPIS2_EASYDMA_MAXCNT_SIZE 16
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2
/* Two Wire Interface Master with DMA */
#define TWIM_PRESENT
#define TWIM_COUNT 2
#define TWIM0_EASYDMA_MAXCNT_SIZE 16
#define TWIM1_EASYDMA_MAXCNT_SIZE 16
/* Two Wire Interface Slave with DMA */
#define TWIS_PRESENT
#define TWIS_COUNT 2
#define TWIS0_EASYDMA_MAXCNT_SIZE 16
#define TWIS1_EASYDMA_MAXCNT_SIZE 16
/* Universal Asynchronous Receiver-Transmitter */
#define UART_PRESENT
#define UART_COUNT 1
#define UART0_FEATURE_ODD_PARITY_PRESENT
/* Universal Asynchronous Receiver-Transmitter with DMA */
#define UARTE_PRESENT
#define UARTE_COUNT 2
#define UARTE0_EASYDMA_MAXCNT_SIZE 16
#define UARTE1_EASYDMA_MAXCNT_SIZE 16
#define UARTE0_FEATURE_ODD_PARITY_PRESENT
#define UARTE1_FEATURE_ODD_PARITY_PRESENT
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 1
/* Successive Approximation Analog to Digital Converter */
#define SAADC_PRESENT
#define SAADC_COUNT 1
#define SAADC_EASYDMA_MAXCNT_SIZE 15
#define SAADC_CH_NUM 8
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
#define GPIOTE_CH_NUM 8
#define GPIOTE_FEATURE_SET_PRESENT
#define GPIOTE_FEATURE_CLR_PRESENT
/* Low Power Comparator */
#define LPCOMP_PRESENT
#define LPCOMP_COUNT 1
#define LPCOMP_REFSEL_RESOLUTION 16
#define LPCOMP_FEATURE_HYST_PRESENT
/* Comparator */
#define COMP_PRESENT
#define COMP_COUNT 1
/* Pulse Width Modulator */
#define PWM_PRESENT
#define PWM_COUNT 4
#define PWM0_CH_NUM 4
#define PWM1_CH_NUM 4
#define PWM2_CH_NUM 4
#define PWM3_CH_NUM 4
#define PWM0_EASYDMA_MAXCNT_SIZE 15
#define PWM1_EASYDMA_MAXCNT_SIZE 15
#define PWM2_EASYDMA_MAXCNT_SIZE 15
#define PWM3_EASYDMA_MAXCNT_SIZE 15
/* Pulse Density Modulator */
#define PDM_PRESENT
#define PDM_COUNT 1
#define PDM_EASYDMA_MAXCNT_SIZE 15
/* Inter-IC Sound Interface */
#define I2S_PRESENT
#define I2S_COUNT 1
#define I2S_EASYDMA_MAXCNT_SIZE 14
/* Universal Serial Bus Device */
#define USBD_PRESENT
#define USBD_COUNT 1
#define USBD_EASYDMA_MAXCNT_SIZE 7
#endif // _NRF52833_PERIPHERALS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF52833_TO_NRF52820_H
#define NRF52833_TO_NRF52820_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the name changes between nRF52833 and nRF52820 devices.
* It redefines the old nRF52833 names into the new ones as long as the functionality is still supported. If the
* functionality is gone, there old names are not defined, so compilation will fail. */
/* Differences between latest nRF52833 headers and nRF52820 headers. */
#endif /* NRF52833_TO_NRF52820_H */

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _NRF52840_PERIPHERALS_H
#define _NRF52840_PERIPHERALS_H
/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
#define POWER_FEATURE_RAM_REGISTERS_COUNT 9
#define POWER_FEATURE_VDDH_PRESENT
#define POWER_FEATURE_VDDH_DCDC_PRESENT
/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1
#define NVMC_FEATURE_CACHE_PRESENT
/* Floating Point Unit */
#define FPU_PRESENT
#define FPU_COUNT 1
/* Systick timer */
#define SYSTICK_PRESENT
#define SYSTICK_COUNT 1
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
/* Memory Watch Unit */
#define MWU_PRESENT
#define MWU_COUNT 1
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 2
#define P0_PIN_NUM 32
#define P1_PIN_NUM 16
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
#define P1_FEATURE_PINS_PRESENT 0x0000FFFFUL
/* ACL */
#define ACL_PRESENT
#define ACL_REGIONS_COUNT 8
/* Radio */
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_EASYDMA_MAXCNT_SIZE 8
#define RADIO_FEATURE_IEEE_802_15_4_PRESENT
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
#define AAR_MAX_IRK_NUM 16
/* AES Electronic CodeBook mode encryption */
#define ECB_PRESENT
#define ECB_COUNT 1
/* AES CCM mode encryption */
#define CCM_PRESENT
#define CCM_COUNT 1
/* NFC Tag */
#define NFCT_PRESENT
#define NFCT_COUNT 1
#define NFCT_EASYDMA_MAXCNT_SIZE 9
/* Peripheral to Peripheral Interconnect */
#define PPI_PRESENT
#define PPI_COUNT 1
#define PPI_CH_NUM 20
#define PPI_FIXED_CH_NUM 12
#define PPI_GROUP_NUM 6
#define PPI_FEATURE_FORKS_PRESENT
/* Event Generator Unit */
#define EGU_PRESENT
#define EGU_COUNT 6
#define EGU0_CH_NUM 16
#define EGU1_CH_NUM 16
#define EGU2_CH_NUM 16
#define EGU3_CH_NUM 16
#define EGU4_CH_NUM 16
#define EGU5_CH_NUM 16
/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 5
#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 32
#define TIMER2_MAX_SIZE 32
#define TIMER3_MAX_SIZE 32
#define TIMER4_MAX_SIZE 32
#define TIMER0_CC_NUM 4
#define TIMER1_CC_NUM 4
#define TIMER2_CC_NUM 4
#define TIMER3_CC_NUM 6
#define TIMER4_CC_NUM 6
/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 3
#define RTC0_CC_NUM 3
#define RTC1_CC_NUM 4
#define RTC2_CC_NUM 4
/* RNG */
#define RNG_PRESENT
#define RNG_COUNT 1
/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 1
/* Temperature Sensor */
#define TEMP_PRESENT
#define TEMP_COUNT 1
/* Serial Peripheral Interface Master */
#define SPI_PRESENT
#define SPI_COUNT 3
/* Serial Peripheral Interface Master with DMA */
#define SPIM_PRESENT
#define SPIM_COUNT 4
#define SPIM0_MAX_DATARATE 8
#define SPIM1_MAX_DATARATE 8
#define SPIM2_MAX_DATARATE 8
#define SPIM3_MAX_DATARATE 32
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM3_FEATURE_HARDWARE_CSN_PRESENT 1
#define SPIM0_FEATURE_DCX_PRESENT 0
#define SPIM1_FEATURE_DCX_PRESENT 0
#define SPIM2_FEATURE_DCX_PRESENT 0
#define SPIM3_FEATURE_DCX_PRESENT 1
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
#define SPIM1_FEATURE_RXDELAY_PRESENT 0
#define SPIM2_FEATURE_RXDELAY_PRESENT 0
#define SPIM3_FEATURE_RXDELAY_PRESENT 1
#define SPIM0_EASYDMA_MAXCNT_SIZE 16
#define SPIM1_EASYDMA_MAXCNT_SIZE 16
#define SPIM2_EASYDMA_MAXCNT_SIZE 16
#define SPIM3_EASYDMA_MAXCNT_SIZE 16
/* Serial Peripheral Interface Slave with DMA*/
#define SPIS_PRESENT
#define SPIS_COUNT 3
#define SPIS0_EASYDMA_MAXCNT_SIZE 16
#define SPIS1_EASYDMA_MAXCNT_SIZE 16
#define SPIS2_EASYDMA_MAXCNT_SIZE 16
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2
/* Two Wire Interface Master with DMA */
#define TWIM_PRESENT
#define TWIM_COUNT 2
#define TWIM0_EASYDMA_MAXCNT_SIZE 16
#define TWIM1_EASYDMA_MAXCNT_SIZE 16
/* Two Wire Interface Slave with DMA */
#define TWIS_PRESENT
#define TWIS_COUNT 2
#define TWIS0_EASYDMA_MAXCNT_SIZE 16
#define TWIS1_EASYDMA_MAXCNT_SIZE 16
/* Universal Asynchronous Receiver-Transmitter */
#define UART_PRESENT
#define UART_COUNT 1
/* Universal Asynchronous Receiver-Transmitter with DMA */
#define UARTE_PRESENT
#define UARTE_COUNT 2
#define UARTE0_EASYDMA_MAXCNT_SIZE 16
#define UARTE1_EASYDMA_MAXCNT_SIZE 16
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 1
/* Successive Approximation Analog to Digital Converter */
#define SAADC_PRESENT
#define SAADC_COUNT 1
#define SAADC_EASYDMA_MAXCNT_SIZE 15
#define SAADC_CH_NUM 8
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
#define GPIOTE_CH_NUM 8
#define GPIOTE_FEATURE_SET_PRESENT
#define GPIOTE_FEATURE_CLR_PRESENT
/* Low Power Comparator */
#define LPCOMP_PRESENT
#define LPCOMP_COUNT 1
#define LPCOMP_REFSEL_RESOLUTION 16
#define LPCOMP_FEATURE_HYST_PRESENT
/* Comparator */
#define COMP_PRESENT
#define COMP_COUNT 1
/* Pulse Width Modulator */
#define PWM_PRESENT
#define PWM_COUNT 4
#define PWM0_CH_NUM 4
#define PWM1_CH_NUM 4
#define PWM2_CH_NUM 4
#define PWM3_CH_NUM 4
#define PWM0_EASYDMA_MAXCNT_SIZE 15
#define PWM1_EASYDMA_MAXCNT_SIZE 15
#define PWM2_EASYDMA_MAXCNT_SIZE 15
#define PWM3_EASYDMA_MAXCNT_SIZE 15
/* Pulse Density Modulator */
#define PDM_PRESENT
#define PDM_COUNT 1
#define PDM_EASYDMA_MAXCNT_SIZE 15
/* Inter-IC Sound Interface */
#define I2S_PRESENT
#define I2S_COUNT 1
#define I2S_EASYDMA_MAXCNT_SIZE 14
/* Universal Serial Bus Device */
#define USBD_PRESENT
#define USBD_COUNT 1
#define USBD_EASYDMA_MAXCNT_SIZE 7
/* ARM TrustZone Cryptocell 310 */
#define CRYPTOCELL_PRESENT
#define CRYPTOCELL_COUNT 1
/* Quad SPI */
#define QSPI_PRESENT
#define QSPI_COUNT 1
#define QSPI_EASYDMA_MAXCNT_SIZE 20
#endif // _NRF52840_PERIPHERALS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF52_NAME_CHANGE_H
#define NRF52_NAME_CHANGE_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and
* nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these
* macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead.
*/
/* I2S */
/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled
#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled
#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master
#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave
#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled
#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled
#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled
#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled
#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled
#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled
#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit
#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit
#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit
#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left
#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right
#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned
#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left
#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right
/* LPCOMP */
/* Corrected typo in RESULT register. */
#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
/*lint --flb "Leave library region" */
#endif /* NRF52_NAME_CHANGE_H */

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF52_TO_NRF52810_H
#define NRF52_TO_NRF52810_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52810 devices.
* It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the
* functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
* from the nrf52_namechange.h file. */
/* Differences between latest nRF52 headers and nRF52810 headers. */
/* Interrupt service routines handlers. Note that handlers SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler and
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler are not redefined since functionality is not equivalent. */
#ifndef COMP_LPCOMP_IRQHandler
#define COMP_LPCOMP_IRQHandler COMP_IRQHandler
#endif
#ifndef SWI2_EGU2_IRQHandler
#define SWI2_EGU2_IRQHandler SWI2_IRQHandler
#endif
#ifndef SWI3_EGU3_IRQHandler
#define SWI3_EGU3_IRQHandler SWI3_IRQHandler
#endif
#ifndef SWI4_EGU4_IRQHandler
#define SWI4_EGU4_IRQHandler SWI4_IRQHandler
#endif
#ifndef SWI5_EGU5_IRQHandler
#define SWI5_EGU5_IRQHandler SWI5_IRQHandler
#endif
/* Interrupt service routines index. Note that indexes SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn and
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn are not redefined since functionality is not equivalent. */
#ifndef COMP_LPCOMP_IRQn
#define COMP_LPCOMP_IRQn COMP_IRQn
#endif
#ifndef SWI2_EGU2_IRQn
#define SWI2_EGU2_IRQn SWI2_IRQn
#endif
#ifndef SWI3_EGU3_IRQn
#define SWI3_EGU3_IRQn SWI3_IRQn
#endif
#ifndef SWI4_EGU4_IRQn
#define SWI4_EGU4_IRQn SWI4_IRQn
#endif
#ifndef SWI5_EGU5_IRQn
#define SWI5_EGU5_IRQn SWI5_IRQn
#endif
/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */
/* I2S */
/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
#ifndef I2S_ENABLE_ENABLE_DISABLE
#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled
#endif
#ifndef I2S_ENABLE_ENABLE_ENABLE
#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled
#endif
#ifndef I2S_CONFIG_MODE_MODE_MASTER
#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master
#endif
#ifndef I2S_CONFIG_MODE_MODE_SLAVE
#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave
#endif
#ifndef I2S_CONFIG_RXEN_RXEN_DISABLE
#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled
#endif
#ifndef I2S_CONFIG_RXEN_RXEN_ENABLE
#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled
#endif
#ifndef I2S_CONFIG_TXEN_TXEN_DISABLE
#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled
#endif
#ifndef I2S_CONFIG_TXEN_TXEN_ENABLE
#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled
#endif
#ifndef I2S_CONFIG_MCKEN_MCKEN_DISABLE
#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled
#endif
#ifndef I2S_CONFIG_MCKEN_MCKEN_ENABLE
#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled
#endif
#ifndef I2S_CONFIG_SWIDTH_SWIDTH_8BIT
#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit
#endif
#ifndef I2S_CONFIG_SWIDTH_SWIDTH_16BIT
#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit
#endif
#ifndef I2S_CONFIG_SWIDTH_SWIDTH_24BIT
#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit
#endif
#ifndef I2S_CONFIG_ALIGN_ALIGN_LEFT
#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left
#endif
#ifndef I2S_CONFIG_ALIGN_ALIGN_RIGHT
#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right
#endif
#ifndef I2S_CONFIG_FORMAT_FORMAT_ALIGNED
#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned
#endif
#ifndef I2S_CONFIG_CHANNELS_CHANNELS_STEREO
#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
#endif
#ifndef I2S_CONFIG_CHANNELS_CHANNELS_LEFT
#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left
#endif
#ifndef I2S_CONFIG_CHANNELS_CHANNELS_RIGHT
#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right
#endif
/* LPCOMP */
/* Corrected typo in RESULT register. */
#ifndef LPCOMP_RESULT_RESULT_Bellow
#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
#endif
/*lint --flb "Leave library region" */
#endif /* NRF52_TO_NRF52810_H */

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF52_TO_NRF52833_H
#define NRF52_TO_NRF52833_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52840 devices.
* It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the
* functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
* from the nrf52_namechange.h file. */
/* Differences between latest nRF52 headers and nRF52840 headers. */
/* UART */
/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */
#ifndef PSELRTS
#define PSELRTS PSEL.RTS
#endif
#ifndef PSELTXD
#define PSELTXD PSEL.TXD
#endif
#ifndef PSELCTS
#define PSELCTS PSEL.CTS
#endif
#ifndef PSELRXD
#define PSELRXD PSEL.RXD
#endif
/* TWI */
/* The registers PSELSCL, PSELSDA were restructured into a struct. */
#ifndef PSELSCL
#define PSELSCL PSEL.SCL
#endif
#ifndef PSELSDA
#define PSELSDA PSEL.SDA
#endif
/* LPCOMP */
/* The hysteresis control enumerated values has changed name for nRF52833 devices. */
#ifndef LPCOMP_HYST_HYST_NoHyst
#define LPCOMP_HYST_HYST_NoHyst LPCOMP_HYST_HYST_Disabled
#endif
#ifndef LPCOMP_HYST_HYST_Hyst50mV
#define LPCOMP_HYST_HYST_Hyst50mV LPCOMP_HYST_HYST_Enabled
#endif
/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */
/* I2S */
/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
#ifndef I2S_ENABLE_ENABLE_DISABLE
#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled
#endif
#ifndef I2S_ENABLE_ENABLE_ENABLE
#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled
#endif
#ifndef I2S_CONFIG_MODE_MODE_MASTER
#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master
#endif
#ifndef I2S_CONFIG_MODE_MODE_SLAVE
#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave
#endif
#ifndef I2S_CONFIG_RXEN_RXEN_DISABLE
#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled
#endif
#ifndef I2S_CONFIG_RXEN_RXEN_ENABLE
#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled
#endif
#ifndef I2S_CONFIG_TXEN_TXEN_DISABLE
#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled
#endif
#ifndef I2S_CONFIG_TXEN_TXEN_ENABLE
#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled
#endif
#ifndef I2S_CONFIG_MCKEN_MCKEN_DISABLE
#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled
#endif
#ifndef I2S_CONFIG_MCKEN_MCKEN_ENABLE
#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled
#endif
#ifndef I2S_CONFIG_SWIDTH_SWIDTH_8BIT
#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit
#endif
#ifndef I2S_CONFIG_SWIDTH_SWIDTH_16BIT
#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit
#endif
#ifndef I2S_CONFIG_SWIDTH_SWIDTH_24BIT
#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit
#endif
#ifndef I2S_CONFIG_ALIGN_ALIGN_LEFT
#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left
#endif
#ifndef I2S_CONFIG_ALIGN_ALIGN_RIGHT
#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right
#endif
#ifndef I2S_CONFIG_FORMAT_FORMAT_ALIGNED
#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned
#endif
#ifndef I2S_CONFIG_CHANNELS_CHANNELS_STEREO
#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
#endif
#ifndef I2S_CONFIG_CHANNELS_CHANNELS_LEFT
#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left
#endif
#ifndef I2S_CONFIG_CHANNELS_CHANNELS_RIGHT
#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right
#endif
/* LPCOMP */
/* Corrected typo in RESULT register. */
#ifndef LPCOMP_RESULT_RESULT_Bellow
#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
#endif
/*lint --flb "Leave library region" */
#endif /* NRF52_TO_NRF52833_H */

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF52_TO_NRF52840_H
#define NRF52_TO_NRF52840_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52840 devices.
* It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the
* functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
* from the nrf52_namechange.h file. */
/* Differences between latest nRF52 headers and nRF52840 headers. */
/* UART */
/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */
#ifndef PSELRTS
#define PSELRTS PSEL.RTS
#endif
#ifndef PSELTXD
#define PSELTXD PSEL.TXD
#endif
#ifndef PSELCTS
#define PSELCTS PSEL.CTS
#endif
#ifndef PSELRXD
#define PSELRXD PSEL.RXD
#endif
/* TWI */
/* The registers PSELSCL, PSELSDA were restructured into a struct. */
#ifndef PSELSCL
#define PSELSCL PSEL.SCL
#endif
#ifndef PSELSDA
#define PSELSDA PSEL.SDA
#endif
/* LPCOMP */
/* The hysteresis control enumerated values has changed name for nRF52840 devices. */
#ifndef LPCOMP_HYST_HYST_NoHyst
#define LPCOMP_HYST_HYST_NoHyst LPCOMP_HYST_HYST_Disabled
#endif
#ifndef LPCOMP_HYST_HYST_Hyst50mV
#define LPCOMP_HYST_HYST_Hyst50mV LPCOMP_HYST_HYST_Enabled
#endif
/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */
/* I2S */
/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
#ifndef I2S_ENABLE_ENABLE_DISABLE
#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled
#endif
#ifndef I2S_ENABLE_ENABLE_ENABLE
#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled
#endif
#ifndef I2S_CONFIG_MODE_MODE_MASTER
#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master
#endif
#ifndef I2S_CONFIG_MODE_MODE_SLAVE
#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave
#endif
#ifndef I2S_CONFIG_RXEN_RXEN_DISABLE
#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled
#endif
#ifndef I2S_CONFIG_RXEN_RXEN_ENABLE
#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled
#endif
#ifndef I2S_CONFIG_TXEN_TXEN_DISABLE
#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled
#endif
#ifndef I2S_CONFIG_TXEN_TXEN_ENABLE
#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled
#endif
#ifndef I2S_CONFIG_MCKEN_MCKEN_DISABLE
#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled
#endif
#ifndef I2S_CONFIG_MCKEN_MCKEN_ENABLE
#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled
#endif
#ifndef I2S_CONFIG_SWIDTH_SWIDTH_8BIT
#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit
#endif
#ifndef I2S_CONFIG_SWIDTH_SWIDTH_16BIT
#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit
#endif
#ifndef I2S_CONFIG_SWIDTH_SWIDTH_24BIT
#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit
#endif
#ifndef I2S_CONFIG_ALIGN_ALIGN_LEFT
#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left
#endif
#ifndef I2S_CONFIG_ALIGN_ALIGN_RIGHT
#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right
#endif
#ifndef I2S_CONFIG_FORMAT_FORMAT_ALIGNED
#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned
#endif
#ifndef I2S_CONFIG_CHANNELS_CHANNELS_STEREO
#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
#endif
#ifndef I2S_CONFIG_CHANNELS_CHANNELS_LEFT
#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left
#endif
#ifndef I2S_CONFIG_CHANNELS_CHANNELS_RIGHT
#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right
#endif
/* LPCOMP */
/* Corrected typo in RESULT register. */
#ifndef LPCOMP_RESULT_RESULT_Bellow
#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
#endif
/*lint --flb "Leave library region" */
#endif /* NRF51_TO_NRF52840_H */

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF5340_APPLICATION_NAME_CHANGE_H
#define NRF5340_APPLICATION_NAME_CHANGE_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the updates made to nrf5340_application.h and
* nrf5340_application_bitfields.h. The macros defined in this file were available previously. Do not use these
* macros on purpose. Use the ones defined in nrf5340_application.h and nrf5340_application_bitfields.h instead.
*/
/* The serial box interrupt ISRs were renamed. Adding old names as macros. */
#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler SERIAL0_IRQHandler
#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn SERIAL0_IRQn
#define SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler SERIAL1_IRQHandler
#define SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn SERIAL1_IRQn
#define SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler SERIAL2_IRQHandler
#define SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn SERIAL2_IRQn
#define SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler SERIAL3_IRQHandler
#define SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn SERIAL3_IRQn
/*lint --flb "Leave library region" */
#endif /* NRF5340_APPLICATION_NAME_CHANGE_H */

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _NRF5340_PERIPHERALS_H
#define _NRF5340_PERIPHERALS_H
/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1
#define CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1
/* NVM instruction and data cache */
#define CACHE_PRESENT
#define CACHE_COUNT 1
/* Memory Protection Unit */
#define MPU_REGION_NUM 8
/* Regulators Peripheral */
#define REGULATORS_PRESENT
#define REGULATORS_COUNT 1
#define REGULATORS_FEATURE_VDDH_PRESENT
/* USB Regulator Peripheral */
#define USBREG_PRESENT
#define USBREG_COUNT 1
/* Volatile Memory Controller Peripheral */
#define VMC_PRESENT
#define VMC_COUNT 1
#define VMC_FEATURE_RAM_REGISTERS_PRESENT
#define VMC_FEATURE_RAM_REGISTERS_COUNT 8
/* Floating Point Unit */
#define FPU_PRESENT
#define FPU_COUNT 1
/* Systick timer */
#define SYSTICK_PRESENT
#define SYSTICK_COUNT 1
/* Inter-Processor Communication */
#define IPC_PRESENT
#define IPC_COUNT 1
#define IPC_CH_NUM 16
#define IPC_CONF_NUM 16
#define IPC_GPMEM_NUM 2
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 2
#define P0_PIN_NUM 32
#define P1_PIN_NUM 16
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
#define P1_FEATURE_PINS_PRESENT 0x0000FFFFUL
/* NFC Tag */
#define NFCT_PRESENT
#define NFCT_COUNT 1
#define NFCT_EASYDMA_MAXCNT_SIZE 9
/* Distributed Peripheral to Peripheral Interconnect */
#define DPPI_PRESENT
#define DPPI_COUNT 1
#define DPPI_CH_NUM 32
#define DPPI_GROUP_NUM 6
/* Event Generator Unit */
#define EGU_PRESENT
#define EGU_COUNT 6
#define EGU0_CH_NUM 16
#define EGU1_CH_NUM 16
#define EGU2_CH_NUM 16
#define EGU3_CH_NUM 16
#define EGU4_CH_NUM 16
#define EGU5_CH_NUM 16
/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 3
#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 32
#define TIMER2_MAX_SIZE 32
#define TIMER0_CC_NUM 6
#define TIMER1_CC_NUM 6
#define TIMER2_CC_NUM 6
/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 2
#define RTC0_CC_NUM 4
#define RTC1_CC_NUM 4
/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 2
/* Serial Peripheral Interface Master with DMA */
#define SPIM_PRESENT
#define SPIM_COUNT 5
#define SPIM0_MAX_DATARATE 8
#define SPIM1_MAX_DATARATE 8
#define SPIM2_MAX_DATARATE 8
#define SPIM3_MAX_DATARATE 8
#define SPIM4_MAX_DATARATE 32
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM3_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM4_FEATURE_HARDWARE_CSN_PRESENT 1
#define SPIM0_FEATURE_DCX_PRESENT 0
#define SPIM1_FEATURE_DCX_PRESENT 0
#define SPIM2_FEATURE_DCX_PRESENT 0
#define SPIM3_FEATURE_DCX_PRESENT 0
#define SPIM4_FEATURE_DCX_PRESENT 1
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
#define SPIM1_FEATURE_RXDELAY_PRESENT 0
#define SPIM2_FEATURE_RXDELAY_PRESENT 0
#define SPIM3_FEATURE_RXDELAY_PRESENT 0
#define SPIM4_FEATURE_RXDELAY_PRESENT 1
#define SPIM0_EASYDMA_MAXCNT_SIZE 16
#define SPIM1_EASYDMA_MAXCNT_SIZE 16
#define SPIM2_EASYDMA_MAXCNT_SIZE 16
#define SPIM3_EASYDMA_MAXCNT_SIZE 16
#define SPIM4_EASYDMA_MAXCNT_SIZE 16
/* Serial Peripheral Interface Slave with DMA*/
#define SPIS_PRESENT
#define SPIS_COUNT 4
#define SPIS0_EASYDMA_MAXCNT_SIZE 16
#define SPIS1_EASYDMA_MAXCNT_SIZE 16
#define SPIS2_EASYDMA_MAXCNT_SIZE 16
#define SPIS3_EASYDMA_MAXCNT_SIZE 16
/* Two Wire Interface Master with DMA */
#define TWIM_PRESENT
#define TWIM_COUNT 4
#define TWIM0_EASYDMA_MAXCNT_SIZE 16
#define TWIM1_EASYDMA_MAXCNT_SIZE 16
#define TWIM2_EASYDMA_MAXCNT_SIZE 16
#define TWIM3_EASYDMA_MAXCNT_SIZE 16
/* Two Wire Interface Slave with DMA */
#define TWIS_PRESENT
#define TWIS_COUNT 4
#define TWIS0_EASYDMA_MAXCNT_SIZE 16
#define TWIS1_EASYDMA_MAXCNT_SIZE 16
#define TWIS2_EASYDMA_MAXCNT_SIZE 16
#define TWIS3_EASYDMA_MAXCNT_SIZE 16
/* Universal Asynchronous Receiver-Transmitter with DMA */
#define UARTE_PRESENT
#define UARTE_COUNT 4
#define UARTE0_EASYDMA_MAXCNT_SIZE 16
#define UARTE1_EASYDMA_MAXCNT_SIZE 16
#define UARTE2_EASYDMA_MAXCNT_SIZE 16
#define UARTE3_EASYDMA_MAXCNT_SIZE 16
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 2
/* Successive Approximation Analog to Digital Converter */
#define SAADC_PRESENT
#define SAADC_COUNT 1
#define SAADC_CH_NUM 8
#define SAADC_EASYDMA_MAXCNT_SIZE 15
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 2
#define GPIOTE_CH_NUM 8
#define GPIOTE_FEATURE_SET_PRESENT
#define GPIOTE_FEATURE_CLR_PRESENT
/* Low Power Comparator */
#define LPCOMP_PRESENT
#define LPCOMP_COUNT 1
#define LPCOMP_REFSEL_RESOLUTION 16
#define LPCOMP_FEATURE_HYST_PRESENT
/* Comparator */
#define COMP_PRESENT
#define COMP_COUNT 1
/* Pulse Width Modulator */
#define PWM_PRESENT
#define PWM_COUNT 4
#define PWM0_CH_NUM 4
#define PWM1_CH_NUM 4
#define PWM2_CH_NUM 4
#define PWM3_CH_NUM 4
#define PWM0_EASYDMA_MAXCNT_SIZE 15
#define PWM1_EASYDMA_MAXCNT_SIZE 15
#define PWM2_EASYDMA_MAXCNT_SIZE 15
#define PWM3_EASYDMA_MAXCNT_SIZE 15
/* ARM TrustZone Cryptocell 310 */
#define CRYPTOCELL_PRESENT
#define CRYPTOCELL_COUNT 1
/* Quad SPI */
#define QSPI_PRESENT
#define QSPI_COUNT 1
#define QSPI_EASYDMA_MAXCNT_SIZE 20
/* Mutex*/
#define MUTEX_PRESENT
#define MUTEX_COUNT 1
/* Key management Unit */
#define KMU_PRESENT
#define KMU_COUNT 1
/* Pulse density modulation */
#define PDM_PRESENT
#define PDM_COUNT 1
/* Secure Peripheral Unit */
#define SPU_PRESENT
#define SPU_COUNT 1
#define SPU_RAMREGION_SIZE 0x2000ul
/* Inter-IC Sound Interface */
#define I2S_PRESENT
#define I2S_COUNT 1
#define I2S_EASYDMA_MAXCNT_SIZE 14
/* Universal Serial Bus Device */
#define USBD_PRESENT
#define USBD_COUNT 1
#define USBD_EASYDMA_MAXCNT_SIZE 7
/* Oscillators */
#define OSCILLATORS_PRESENT
#define OSCILLATORS_COUNT 1
#endif // _NRF5340_PERIPHERALS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF5340_NETWORK_NAME_CHANGE_H
#define NRF5340_NETWORK_NAME_CHANGE_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the updates made to nrf5340_network.h and
* nrf5340_network_bitfields.h. The macros defined in this file were available previously. Do not use these
* macros on purpose. Use the ones defined in nrf5340_network.h and nrf5340_network_bitfields.h instead.
*/
/* The serial box interrupt ISRs were renamed. Adding old names as macros. */
#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler SERIAL0_IRQHandler
#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn SERIAL0_IRQn
/*lint --flb "Leave library region" */
#endif /* NRF5340_NETWORK_NAME_CHANGE_H */

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _NRF5340_NETWORK_PERIPHERALS_H
#define _NRF5340_NETWORK_PERIPHERALS_H
/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1
#define NVMC_FEATURE_CACHE_PRESENT
/* Voltage request peripheral */
#define VREQCTRL_PRESENT
#define VREQCTRL_COUNT 1
/* Volatile Memory Controller Peripheral */
#define VMC_PRESENT
#define VMC_COUNT 1
#define VMC_FEATURE_RAM_REGISTERS_PRESENT
#define VMC_FEATURE_RAM_REGISTERS_COUNT 4
/* Systick timer */
#define SYSTICK_PRESENT
#define SYSTICK_COUNT 1
/* Inter-Processor Communication */
#define IPC_PRESENT
#define IPC_COUNT 1
#define IPC_CH_NUM 16
#define IPC_CONF_NUM 16
#define IPC_GPMEM_NUM 2
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 2
#define P0_PIN_NUM 32
#define P1_PIN_NUM 16
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
#define P1_FEATURE_PINS_PRESENT 0x0000FFFFUL
/* ACL */
#define ACL_PRESENT
#define ACL_REGIONS_COUNT 8
/* Radio */
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_EASYDMA_MAXCNT_SIZE 9
#define RADIO_FEATURE_IEEE_802_15_4_PRESENT
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_0dBm
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
#define AAR_MAX_IRK_NUM 16
/* AES Electronic CodeBook mode encryption */
#define ECB_PRESENT
#define ECB_COUNT 1
/* AES CCM mode encryption */
#define CCM_PRESENT
#define CCM_COUNT 1
/* Distributed Peripheral to Peripheral Interconnect */
#define DPPI_PRESENT
#define DPPI_COUNT 1
#define DPPI_CH_NUM 32
#define DPPI_GROUP_NUM 6
/* Event Generator Unit */
#define EGU_PRESENT
#define EGU_COUNT 1
#define EGU0_CH_NUM 16
/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 3
#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 32
#define TIMER2_MAX_SIZE 32
#define TIMER0_CC_NUM 8
#define TIMER1_CC_NUM 8
#define TIMER2_CC_NUM 8
/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 2
#define RTC0_CC_NUM 4
#define RTC1_CC_NUM 4
/* RNG */
#define RNG_PRESENT
#define RNG_COUNT 1
/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 1
/* Temperature Sensor */
#define TEMP_PRESENT
#define TEMP_COUNT 1
/* Universal Asynchronous Receiver-Transmitter with DMA */
#define UARTE_PRESENT
#define UARTE_COUNT 1
#define UARTE0_EASYDMA_MAXCNT_SIZE 16
/* Serial Peripheral Interface Master with DMA */
#define SPIM_PRESENT
#define SPIM_COUNT 1
#define SPIM0_MAX_DATARATE 8
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM0_FEATURE_DCX_PRESENT 0
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
#define SPIM0_EASYDMA_MAXCNT_SIZE 16
/* Serial Peripheral Interface Slave with DMA*/
#define SPIS_PRESENT
#define SPIS_COUNT 1
#define SPIS0_EASYDMA_MAXCNT_SIZE 16
/* Two Wire Interface Master with DMA */
#define TWIM_PRESENT
#define TWIM_COUNT 1
#define TWIM0_EASYDMA_MAXCNT_SIZE 16
/* Two Wire Interface Slave with DMA */
#define TWIS_PRESENT
#define TWIS_COUNT 1
#define TWIS0_EASYDMA_MAXCNT_SIZE 16
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
#define GPIOTE_CH_NUM 8
#define GPIOTE_FEATURE_SET_PRESENT
#define GPIOTE_FEATURE_CLR_PRESENT
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 4
/* Mutex*/
#define MUTEX_PRESENT
#define MUTEX_COUNT 1
#endif // _NRF5340_NETWORK_PERIPHERALS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF9160_NAME_CHANGE_H
#define NRF9160_NAME_CHANGE_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the updates made to nrf9160.h and
* nrf9160_bitfields.h. The macros defined in this file were available previously. Do not use these
* macros on purpose. Use the ones defined in nrf9160.h and nrf9160_bitfields.h instead.
*/
/* SAADC enums */
/* Changes to enum names in SAADC */
#define SAADC_CH_PSELP_PSELP_VDD SAADC_CH_PSELP_PSELP_VDDGPIO
#define SAADC_CH_PSELP_PSELN_VDD SAADC_CH_PSELP_PSELN_VDDGPIO
/* CTRLAP PERI Fields */
#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Pos CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos
#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Msk CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk
#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Unlocked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked
#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Locked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked
/*lint --flb "Leave library region" */
#endif /* NRF9160_NAME_CHANGE_H */

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _NRF9160_PERIPHERALS_H
#define _NRF9160_PERIPHERALS_H
/* UICR */
#define UICR_KEYSLOT_COUNT 128
/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1
#define NVMC_FEATURE_CACHE_PRESENT
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 1
#define P0_PIN_NUM 32
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
/* Distributed Peripheral to Peripheral Interconnect */
#define DPPI_PRESENT
#define DPPI_COUNT 1
#define DPPI_CH_NUM 16
#define DPPI_GROUP_NUM 6
/* Event Generator Unit */
#define EGU_PRESENT
#define EGU_COUNT 6
#define EGU0_CH_NUM 16
#define EGU1_CH_NUM 16
#define EGU2_CH_NUM 16
#define EGU3_CH_NUM 16
#define EGU4_CH_NUM 16
#define EGU5_CH_NUM 16
/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 3
#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 32
#define TIMER2_MAX_SIZE 32
#define TIMER0_CC_NUM 6
#define TIMER1_CC_NUM 6
#define TIMER2_CC_NUM 6
/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 2
#define RTC0_CC_NUM 4
#define RTC1_CC_NUM 4
/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 1
/* Serial Peripheral Interface Master with DMA */
#define SPIM_PRESENT
#define SPIM_COUNT 4
#define SPIM0_MAX_DATARATE 8
#define SPIM1_MAX_DATARATE 8
#define SPIM2_MAX_DATARATE 8
#define SPIM3_MAX_DATARATE 8
#define SPIM0_EASYDMA_MAXCNT_SIZE 13
#define SPIM1_EASYDMA_MAXCNT_SIZE 13
#define SPIM2_EASYDMA_MAXCNT_SIZE 13
#define SPIM3_EASYDMA_MAXCNT_SIZE 13
/* Serial Peripheral Interface Slave with DMA*/
#define SPIS_PRESENT
#define SPIS_COUNT 4
#define SPIS0_EASYDMA_MAXCNT_SIZE 13
#define SPIS1_EASYDMA_MAXCNT_SIZE 13
#define SPIS2_EASYDMA_MAXCNT_SIZE 13
#define SPIS3_EASYDMA_MAXCNT_SIZE 13
/* Two Wire Interface Master with DMA */
#define TWIM_PRESENT
#define TWIM_COUNT 4
#define TWIM0_EASYDMA_MAXCNT_SIZE 13
#define TWIM1_EASYDMA_MAXCNT_SIZE 13
#define TWIM2_EASYDMA_MAXCNT_SIZE 13
#define TWIM3_EASYDMA_MAXCNT_SIZE 13
/* Two Wire Interface Slave with DMA */
#define TWIS_PRESENT
#define TWIS_COUNT 4
#define TWIS0_EASYDMA_MAXCNT_SIZE 13
#define TWIS1_EASYDMA_MAXCNT_SIZE 13
#define TWIS2_EASYDMA_MAXCNT_SIZE 13
#define TWIS3_EASYDMA_MAXCNT_SIZE 13
/* Universal Asynchronous Receiver-Transmitter with DMA */
#define UARTE_PRESENT
#define UARTE_COUNT 4
#define UARTE0_EASYDMA_MAXCNT_SIZE 13
#define UARTE1_EASYDMA_MAXCNT_SIZE 13
#define UARTE2_EASYDMA_MAXCNT_SIZE 13
#define UARTE3_EASYDMA_MAXCNT_SIZE 13
/* Successive Approximation Analog to Digital Converter */
#define SAADC_PRESENT
#define SAADC_COUNT 1
#define SAADC_CH_NUM 8
#define SAADC_EASYDMA_MAXCNT_SIZE 15
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 2
#define GPIOTE_CH_NUM 8
#define GPIOTE_FEATURE_SET_PRESENT
#define GPIOTE_FEATURE_CLR_PRESENT
/* Pulse Width Modulator */
#define PWM_PRESENT
#define PWM_COUNT 4
#define PWM_CH_NUM 4
#define PWM_EASYDMA_MAXCNT_SIZE 15
/* Pulse Density Modulator */
#define PDM_PRESENT
#define PDM_COUNT 1
#define PDM_EASYDMA_MAXCNT_SIZE 15
/* Inter-IC Sound Interface */
#define I2S_PRESENT
#define I2S_COUNT 1
#define I2S_EASYDMA_MAXCNT_SIZE 14
/* Inter Processor Communication */
#define IPC_PRESENT
#define IPC_COUNT 1
#define IPC_CH_NUM 8
#define IPC_CONF_NUM 8
#define IPC_GPMEM_NUM 4
/* FPU */
#define FPU_PRESENT
#define FPU_COUNT 1
/* SPU */
#define SPU_PRESENT
#define SPU_COUNT 1
#define SPU_RAMREGION_SIZE 0x2000ul
/* CRYPTOCELL */
#define CRYPTOCELL_PRESENT
#define CRYPTOCELL_COUNT 1
/* KMU */
#define KMU_PRESENT
#define KMU_COUNT 1
#define KMU_KEYSLOT_PRESENT
/* MAGPIO */
#define MAGPIO_PRESENT
#define MAGPIO_COUNT 1
#define MAGPIO_PIN_NUM 3
/* REGULATORS */
#define REGULATORS_PRESENT
#define REGULATORS_COUNT 1
#endif // _NRF9160_PERIPHERALS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF_ERRATAS_H
#define NRF_ERRATAS_H
#include "nrf.h"
/* Check MDK version to make sure we have the required macros */
NRF_MDK_VERSION_ASSERT_AT_LEAST(8,34,0);
/*lint ++flb "Enter library region */
#include "nrf51_erratas.h"
#include "nrf52_erratas.h"
#include "nrf53_erratas.h"
#include "nrf91_erratas.h"
/*lint --flb "Leave library region" */
#endif // NRF_ERRATAS_H

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/*
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF_PERIPHERALS_H__
#define NRF_PERIPHERALS_H__
/*lint ++flb "Enter library region */
#if defined(NRF51)
#include "nrf51_peripherals.h"
#elif defined (NRF52805_XXAA)
#include "nrf52805_peripherals.h"
#elif defined(NRF52810_XXAA)
#include "nrf52810_peripherals.h"
#elif defined(NRF52811_XXAA)
#include "nrf52811_peripherals.h"
#elif defined(NRF52820_XXAA)
#include "nrf52820_peripherals.h"
#elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB)
#include "nrf52832_peripherals.h"
#elif defined (NRF52833_XXAA)
#include "nrf52833_peripherals.h"
#elif defined(NRF52840_XXAA)
#include "nrf52840_peripherals.h"
#elif defined (NRF5340_XXAA_APPLICATION)
#include "nrf5340_application_peripherals.h"
#elif defined (NRF5340_XXAA_NETWORK)
#include "nrf5340_network_peripherals.h"
#elif defined(NRF9160_XXAA)
#include "nrf9160_peripherals.h"
#else
#error "Device must be defined. See nrf.h."
#endif
/*lint --flb "Leave library region" */
#endif // NRF_PERIPHERALS_H__

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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
#ifndef SYSTEM_NRF_H
#define SYSTEM_NRF_H
#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF_H */

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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
#ifndef SYSTEM_NRF51_H
#define SYSTEM_NRF51_H
#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF51_H */

63
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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
#ifndef SYSTEM_NRF52_H
#define SYSTEM_NRF52_H
#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF52_H */

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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
#ifndef SYSTEM_NRF52805_H
#define SYSTEM_NRF52805_H
#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF52805_H */

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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
#ifndef SYSTEM_NRF52810_H
#define SYSTEM_NRF52810_H
#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF52810_H */

63
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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
#ifndef SYSTEM_NRF52811_H
#define SYSTEM_NRF52811_H
#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF52811_H */

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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
#ifndef SYSTEM_NRF52820_H
#define SYSTEM_NRF52820_H
#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF52820_H */

63
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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
#ifndef SYSTEM_NRF52833_H
#define SYSTEM_NRF52833_H
#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF52833_H */

63
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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
#ifndef SYSTEM_NRF52840_H
#define SYSTEM_NRF52840_H
#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF52840_H */

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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
#ifndef SYSTEM_NRF52_APPROTECT_H
#define SYSTEM_NRF52_APPROTECT_H
#include "nrf.h"
#include "nrf52_erratas.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Function that handles firmware-driven enabling or disabling of APPROTECT on devices where it is supported.
If ENABLE_APPROTECT is defined, the FW will lock the fw branch of the APPROTECT mechanism,
preventing it from being opened.
Otherwise, the fw branch state is loaded from UICR, emulating the legacy APPROTECT behavior.
The same mechanism is implemented for SECURE APPROTECT, with the macros
ENABLE_SECURE_APPROTECT and ENABLE_SECURE_APPROTECT_USER_HANDLING. */
static inline void nrf52_handle_approtect(void)
{
#if NRF52_CONFIGURATION_249_PRESENT
#if defined (ENABLE_APPROTECT)
if (nrf52_configuration_249())
{
/* Prevent processor from unlocking APPROTECT soft branch after this point. */
NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force;
}
#else
if (nrf52_configuration_249())
{
/* Load APPROTECT soft branch from UICR.
If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */
NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT;
}
#endif
#endif
}
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_NRF52_APPROTECT_H */

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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
#ifndef SYSTEM_NRF5340_APPLICATION_H
#define SYSTEM_NRF5340_APPLICATION_H
#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF5340_APPLICATION_H */

63
FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Nordic_Code/nRF/Device/Include/system_nrf5340_network.h
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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
#ifndef SYSTEM_NRF5340_NETWORK_H
#define SYSTEM_NRF5340_NETWORK_H
#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF5340_NETWORK_H */

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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
#ifndef SYSTEM_NRF53_APPROTECT_H
#define SYSTEM_NRF53_APPROTECT_H
#include "nrf.h"
#include "nrf53_erratas.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Function that handles firmware-driven enabling or disabling of APPROTECT on devices where it is supported.
If ENABLE_APPROTECT is defined, the FW will lock the fw branch of the APPROTECT mechanism,
preventing it from being opened.
If ENABLE_APPROTECT_USER_HANDLING is defined, the FW will not write to the fw branch of the APPROTECT mechanism.
This allows later stages of the fw to handle APPROTECT,
for example to implement authenticated debug.
Otherwise, the fw branch state is loaded from UICR.
The same mechanism is implemented for SECURE APPROTECT, with the macros
ENABLE_SECURE_APPROTECT and ENABLE_SECURE_APPROTECT_USER_HANDLING. */
static inline void nrf53_handle_approtect(void)
{
#if defined(NRF_APPLICATION)
#if defined (ENABLE_APPROTECT)
/* Prevent processor from unlocking APPROTECT soft branch after this point. */
NRF_CTRLAP_S->APPROTECT.LOCK = CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked;
#elif defined (ENABLE_APPROTECT_USER_HANDLING)
/* Do nothing, allow user code to handle APPROTECT. Use this if you want to enable authenticated debug. */
#else
/* Load APPROTECT soft branch from UICR.
If UICR->APPROTECT is disabled, CTRLAP->APPROTECT will be disabled. */
NRF_CTRLAP_S->APPROTECT.DISABLE = NRF_UICR_S->APPROTECT;
#endif
/* Secure APPROTECT is only available for Application core. */
#if defined (ENABLE_SECURE_APPROTECT)
/* Prevent processor from unlocking SECURE APPROTECT soft branch after this point. */
NRF_CTRLAP_S->SECUREAPPROTECT.LOCK = CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Locked;
#elif defined (ENABLE_SECURE_APPROTECT_USER_HANDLING)
/* Do nothing, allow user code to handle SECURE APPROTECT. Use this if you want to enable authenticated debug. */
#else
/* Load SECURE APPROTECT soft branch from UICR.
If UICR->SECUREAPPROTECT is disabled, CTRLAP->SECUREAPPROTECT will be disabled. */
NRF_CTRLAP_S->SECUREAPPROTECT.DISABLE = NRF_UICR_S->SECUREAPPROTECT;
#endif
#endif
#if defined(NRF_NETWORK)
#if defined (ENABLE_APPROTECT)
/* Prevent processor from unlocking APPROTECT soft branch after this point. */
NRF_CTRLAP_NS->APPROTECT.LOCK = CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked;
#elif defined (ENABLE_APPROTECT_USER_HANDLING)
/* Do nothing, allow user code to handle APPROTECT. Use this if you want to enable authenticated debug. */
#else
/* Load APPROTECT soft branch from UICR.
If UICR->APPROTECT is disabled, CTRLAP->APPROTECT will be disabled. */
NRF_CTRLAP_NS->APPROTECT.DISABLE = NRF_UICR_NS->APPROTECT;
#endif
#endif
}
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_NRF5_APPROTECT_H */

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FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Nordic_Code/nRF/Device/Include/system_nrf9160.h
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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
#ifndef SYSTEM_NRF9160_H
#define SYSTEM_NRF9160_H
#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF9160_H */

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FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Nordic_Code/nRF/Device/Source/system_nrf9160.c
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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
/* NOTE: Template files (including this one) are application specific and therefore expected to
be copied into the application project folder prior to its use! */
#include <stdint.h>
#include <stdbool.h>
#include "nrf.h"
#include "nrf_peripherals.h"
#include "nrf91_erratas.h"
#include "system_nrf9160.h"
/*lint ++flb "Enter library region" */
void SystemStoreFICRNS();
#define __SYSTEM_CLOCK (64000000UL) /*!< nRF9160 Application core uses a fixed System Clock Frequency of 64MHz */
#define TRACE_PIN_CNF_VALUE ( (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | \
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | \
(GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) | \
(GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | \
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) )
#define TRACE_TRACECLK_PIN (21)
#define TRACE_TRACEDATA0_PIN (22)
#define TRACE_TRACEDATA1_PIN (23)
#define TRACE_TRACEDATA2_PIN (24)
#define TRACE_TRACEDATA3_PIN (25)
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
#elif defined ( __ICCARM__ )
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK;
#elif defined ( __GNUC__ )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
#endif
/* Global values used used in Secure mode SystemInit. */
#if !defined(NRF_TRUSTZONE_NONSECURE)
/* Global values used by UICR erase fix algorithm. */
static uint32_t uicr_erased_value;
static uint32_t uicr_new_value;
#endif
/* Errata are only handled in secure mode since they usually need access to FICR. */
#if !defined(NRF_TRUSTZONE_NONSECURE)
static bool uicr_HFXOSRC_erased(void);
static bool uicr_HFXOCNT_erased(void);
static bool is_empty_word(uint32_t const volatile * word);
#endif
void SystemCoreClockUpdate(void)
{
SystemCoreClock = __SYSTEM_CLOCK;
}
void SystemInit(void)
{
#if !defined(NRF_TRUSTZONE_NONSECURE)
/* Perform Secure-mode initialization routines. */
/* Set all ARM SAU regions to NonSecure if TrustZone extensions are enabled.
* Nordic SPU should handle Secure Attribution tasks */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
#endif
/* Workaround for Errata 6 "POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf91_errata_6()){
NRF_POWER_S->EVENTS_SLEEPENTER = (POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos);
NRF_POWER_S->EVENTS_SLEEPEXIT = (POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos);
}
/* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf91_errata_14()){
*((volatile uint32_t *)0x50004A38) = 0x01ul;
NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
}
/* Workaround for Errata 15 "REGULATORS: LDO mode at startup" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf91_errata_15()){
NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
}
/* Workaround for Errata 20 "RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf91_errata_20()){
*((volatile uint32_t *)0x5003AEE4) = 0xE;
}
/* Workaround for Errata 31 "XOSC32k Startup Failure" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf91_errata_31()){
*((volatile uint32_t *)0x5000470Cul) = 0x0;
*((volatile uint32_t *)0x50004710ul) = 0x1;
}
#if !defined(NRF_SKIP_FICR_NS_COPY_TO_RAM)
SystemStoreFICRNS();
#endif
/* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
until one ADDR is not initialized. */
for (uint32_t index = 0; index < 256ul && !is_empty_word(&NRF_FICR_S->TRIMCNF[index].ADDR); index++){
#if defined ( __ICCARM__ )
#pragma diag_suppress=Pa082
#endif
*(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
#if defined ( __ICCARM__ )
#pragma diag_default=Pa082
#endif
}
/* Set UICR->HFXOSRC and UICR->HFXOCNT to working defaults if UICR was erased */
if (uicr_HFXOSRC_erased() || uicr_HFXOCNT_erased()) {
/* Wait for pending NVMC operations to finish */
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
/* Enable write mode in NVMC */
NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen;
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
if (uicr_HFXOSRC_erased()){
/* Write default value to UICR->HFXOSRC */
uicr_erased_value = NRF_UICR_S->HFXOSRC;
uicr_new_value = (uicr_erased_value & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO;
NRF_UICR_S->HFXOSRC = uicr_new_value;
__DSB();
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
}
if (uicr_HFXOCNT_erased()){
/* Write default value to UICR->HFXOCNT */
uicr_erased_value = NRF_UICR_S->HFXOCNT;
uicr_new_value = (uicr_erased_value & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20;
NRF_UICR_S->HFXOCNT = uicr_new_value;
__DSB();
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
}
/* Enable read mode in NVMC */
NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren;
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
/* Reset to apply clock select update */
NVIC_SystemReset();
}
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
Specification to see which ones). */
#if defined (ENABLE_TRACE)
// Enable Trace And Debug peripheral
NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk;
NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk;
// Set up Trace pads SPU firewall
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACECLK_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA0_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA1_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA2_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA3_PIN);
// Configure trace port pads
NRF_P0_S->PIN_CNF[TRACE_TRACECLK_PIN] = TRACE_PIN_CNF_VALUE;
NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE;
NRF_P0_S->PIN_CNF[TRACE_TRACEDATA1_PIN] = TRACE_PIN_CNF_VALUE;
NRF_P0_S->PIN_CNF[TRACE_TRACEDATA2_PIN] = TRACE_PIN_CNF_VALUE;
NRF_P0_S->PIN_CNF[TRACE_TRACEDATA3_PIN] = TRACE_PIN_CNF_VALUE;
// Select trace pins
NRF_TAD_S->PSEL.TRACECLK = TRACE_TRACECLK_PIN;
NRF_TAD_S->PSEL.TRACEDATA0 = TRACE_TRACEDATA0_PIN;
NRF_TAD_S->PSEL.TRACEDATA1 = TRACE_TRACEDATA1_PIN;
NRF_TAD_S->PSEL.TRACEDATA2 = TRACE_TRACEDATA2_PIN;
NRF_TAD_S->PSEL.TRACEDATA3 = TRACE_TRACEDATA3_PIN;
// Set trace port speed to 32 MHz
NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz;
*((volatile uint32_t *)(0xE0053000ul)) = 0x00000001ul;
*((volatile uint32_t *)(0xE005AFB0ul)) = 0xC5ACCE55ul;
*((volatile uint32_t *)(0xE005A000ul)) &= 0xFFFFFF00ul;
*((volatile uint32_t *)(0xE005A004ul)) = 0x00000009ul;
*((volatile uint32_t *)(0xE005A000ul)) = 0x00000303ul;
*((volatile uint32_t *)(0xE005AFB0ul)) = 0x00000000ul;
*((volatile uint32_t *)(0xE005BFB0ul)) = 0xC5ACCE55ul;
*((volatile uint32_t *)(0xE005B000ul)) &= 0xFFFFFF00ul;
*((volatile uint32_t *)(0xE005B004ul)) = 0x00003000ul;
*((volatile uint32_t *)(0xE005B000ul)) = 0x00000308ul;
*((volatile uint32_t *)(0xE005BFB0ul)) = 0x00000000ul;
*((volatile uint32_t *)(0xE0058FB0ul)) = 0xC5ACCE55ul;
*((volatile uint32_t *)(0xE0058000ul)) = 0x00000000ul;
*((volatile uint32_t *)(0xE0058004ul)) = 0x00000000ul;
*((volatile uint32_t *)(0xE0058FB0ul)) = 0x00000000ul;
/* Rom table does not list ETB, or TPIU base addresses.
* Some debug probes may require manual configuration of these peripherals to enable tracing.
* ETB_BASE = 0xE0051000
* TPIU_BASE = 0xE0054000
*/
#endif
/* Allow Non-Secure code to run FPU instructions.
* If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */
SCB->NSACR |= (3UL << 10);
#endif
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
#if (__FPU_USED == 1)
SCB->CPACR |= (3UL << 20) | (3UL << 22);
__DSB();
__ISB();
#endif
SystemCoreClockUpdate();
}
#if !defined(NRF_TRUSTZONE_NONSECURE)
bool uicr_HFXOCNT_erased()
{
if (is_empty_word(&NRF_UICR_S->HFXOCNT)) {
return true;
}
return false;
}
bool uicr_HFXOSRC_erased()
{
uint32_t HFXOSRC_readout = NRF_UICR_S->HFXOSRC;
__DSB();
if ((HFXOSRC_readout & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) {
return true;
}
return false;
}
bool is_empty_word(uint32_t const volatile * word)
{
uint32_t val = *word;
__DSB();
return val == 0xFFFFFFFFul;
}
#endif
/* Workaround to allow NS code to access FICR. Override NRF_FICR_NS to move FICR_NS buffer. */
#define FICR_SIZE 0x1000ul
#define RAM_BASE 0x20000000ul
#define RAM_END 0x2FFFFFFFul
/* Copy FICR_S to FICR_NS RAM region */
void SystemStoreFICRNS()
{
if ((uint32_t)NRF_FICR_NS < RAM_BASE || (uint32_t)NRF_FICR_NS + FICR_SIZE > RAM_END)
{
/* FICR_NS is not in RAM. */
return;
}
/* Copy FICR to NS-accessible RAM block. */
volatile uint32_t * from = (volatile uint32_t *)((uint32_t)NRF_FICR_S + (FICR_SIZE - sizeof(uint32_t)));
volatile uint32_t * to = (volatile uint32_t *)((uint32_t)NRF_FICR_NS + (FICR_SIZE - sizeof(uint32_t)));
volatile uint32_t * copy_from_end = (volatile uint32_t *)NRF_FICR_S;
while (from >= copy_from_end)
{
*(to--) = *(from--);
}
/* Make RAM region NS. */
uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE;
__DSB();
NRF_SPU_S->RAMREGION[ram_region].PERM &= ~(1 << SPU_RAMREGION_PERM_SECATTR_Pos);
}
/* Block write and execute access to FICR RAM region */
void SystemLockFICRNS()
{
if ((uint32_t)NRF_FICR_NS < RAM_BASE || (uint32_t)NRF_FICR_NS + FICR_SIZE > RAM_END)
{
/* FICR_NS is not in RAM. */
return;
}
uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE;
__DSB();
NRF_SPU_S->RAMREGION[ram_region].PERM &=
~(
(1 << SPU_RAMREGION_PERM_WRITE_Pos) |
(1 << SPU_RAMREGION_PERM_EXECUTE_Pos)
);
NRF_SPU_S->RAMREGION[ram_region].PERM |= 1 << SPU_RAMREGION_PERM_LOCK_Pos;
}
/*lint --flb "Leave library region" */

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FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Nordic_Code/nRF/Scripts/nRF_Target.js
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/*********************************************************************
* SEGGER Microcontroller GmbH *
* The Embedded Experts *
**********************************************************************
* *
* (c) 2014 - 2021 SEGGER Microcontroller GmbH *
* *
* www.segger.com Support: support@segger.com *
* *
**********************************************************************
* *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or *
* without modification, are permitted provided that the following *
* condition is met: *
* *
* - Redistributions of source code must retain the above copyright *
* notice, this condition and the following disclaimer. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
* DAMAGE. *
* *
*********************************************************************/
function Reset() {
TargetInterface.resetAndStop();
}
function EnableTrace(traceInterfaceType) {
// TODO: Enable trace
}

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/*********************************************************************
* SEGGER Microcontroller GmbH *
* The Embedded Experts *
**********************************************************************
* *
* (c) 2014 - 2021 SEGGER Microcontroller GmbH *
* *
* www.segger.com Support: support@segger.com *
* *
**********************************************************************
* *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or *
* without modification, are permitted provided that the following *
* condition is met: *
* *
* - Redistributions of source code must retain the above copyright *
* notice, this condition and the following disclaimer. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
* DAMAGE. *
* *
**********************************************************************
-------------------------- END-OF-HEADER -----------------------------
File : nRF_Startup.s
Purpose : Startup and exception handlers for nRF devices.
Additional information:
Preprocessor Definitions
__NO_SYSTEM_INIT
If defined,
SystemInit is not called.
If not defined,
SystemInit is called.
SystemInit is usually supplied by the CMSIS files.
This file declares a weak implementation as fallback.
__SUPPORT_RESET_HALT_AFTER_BTL
If != 0 (default)
Support J-Link's reset strategy Reset and Halt After Bootloader.
https://wiki.segger.com/Reset_and_Halt_After_Bootloader
If == 0,
Disable support for Reset and Halt After Bootloader.
__NO_SYSTEM_CLK_UPDATE
If defined,
SystemCoreClockUpdate is not automatically called.
Should be defined if SystemCoreClockUpdate must not be called before main().
If not defined,
SystemCoreClockUpdate is called before the application entry point.
__MEMORY_INIT
If defined,
MemoryInit is called after SystemInit.
void MemoryInit(void) can be implemented to enable external
memory controllers.
__VECTORS_IN_RAM
If defined,
the vector table will be copied from Flash to RAM,
and the vector table offset register is adjusted.
__VTOR_CONFIG
If defined,
the vector table offset register is set to point to the
application's vector table.
__NO_FPU_ENABLE
If defined, the FPU is explicitly not enabled,
even if the compiler could use floating point operations.
__SOFTFP__
Defined by the build system.
If not defined, the FPU is enabled for floating point operations.
*/
.syntax unified
#ifndef __SUPPORT_RESET_HALT_AFTER_BTL
#define __SUPPORT_RESET_HALT_AFTER_BTL 1
#endif
/*********************************************************************
*
* Global functions
*
**********************************************************************
*/
/*********************************************************************
*
* Reset_Handler
*
* Function description
* Exception handler for reset.
* Generic bringup of a Cortex-M system.
*
* Additional information
* The stack pointer is expected to be initialized by hardware,
* i.e. read from vectortable[0].
* For manual initialization add
* ldr R0, =__stack_end__
* mov SP, R0
*/
.global reset_handler
.global Reset_Handler
.equ reset_handler, Reset_Handler
.section .init.Reset_Handler, "ax"
.balign 2
.thumb_func
Reset_Handler:
#if __SUPPORT_RESET_HALT_AFTER_BTL != 0
//
// Perform a dummy read access from address 0x00000008 followed by two nop's
// This is needed to support J-Links reset strategy: Reset and Halt After Bootloader.
// https://wiki.segger.com/Reset_and_Halt_After_Bootloader
//
movs R0, #8
ldr R0, [R0]
nop
nop
#endif
#ifndef __NO_SYSTEM_INIT
//
// Call SystemInit
//
bl SystemInit
#endif
#ifdef __MEMORY_INIT
//
// Call MemoryInit
//
bl MemoryInit
#endif
#ifdef __VECTORS_IN_RAM
//
// Copy vector table (from Flash) to RAM
//
ldr R0, =__vectors_start__
ldr R1, =__vectors_end__
ldr R2, =__vectors_ram_start__
1:
cmp R0, R1
beq 2f
ldr R3, [R0]
str R3, [R2]
adds R0, R0, #4
adds R2, R2, #4
b 1b
2:
#endif
#if defined(__VTOR_CONFIG) || defined(__VECTORS_IN_RAM)
//
// Configure vector table offset register
//
#ifdef __ARM_ARCH_6M__
ldr R0, =0xE000ED08 // VTOR_REG
#else
movw R0, 0xED08 // VTOR_REG
movt R0, 0xE000
#endif
#ifdef __VECTORS_IN_RAM
ldr R1, =_vectors_ram
#else
ldr R1, =_vectors
#endif
str R1, [R0]
#endif
#if !defined(__SOFTFP__) && !defined(__NO_FPU_ENABLE)
//
// Enable CP11 and CP10 with CPACR |= (0xf<<20)
//
movw R0, 0xED88 // CPACR
movt R0, 0xE000
ldr R1, [R0]
orrs R1, R1, #(0xf << 20)
str R1, [R0]
#endif
//
// Call runtime initialization, which calls main().
//
bl _start
//
// Weak only declaration of SystemInit enables Linker to replace bl SystemInit with a NOP,
// when there is no strong definition of SystemInit.
//
.weak SystemInit
//
// Place SystemCoreClockUpdate in .init_array
// to be called after runtime initialization
//
#if !defined(__NO_SYSTEM_INIT) && !defined(__NO_SYSTEM_CLK_UPDATE)
.section .init_array, "aw"
.balign 4
.word SystemCoreClockUpdate
#endif
/*********************************************************************
*
* HardFault_Handler
*
* Function description
* Simple exception handler for HardFault.
* In case of a HardFault caused by BKPT instruction without
* debugger attached, return execution, otherwise stay in loop.
*
* Additional information
* The stack pointer is expected to be initialized by hardware,
* i.e. read from vectortable[0].
* For manual initialization add
* ldr R0, =__stack_end__
* mov SP, R0
*/
#undef L
#define L(label) .LHardFault_Handler_##label
.weak HardFault_Handler
.section .init.HardFault_Handler, "ax"
.balign 2
.thumb_func
HardFault_Handler:
//
// Check if HardFault is caused by BKPT instruction
//
ldr R1, =0xE000ED2C // Load NVIC_HFSR
ldr R2, [R1]
cmp R2, #0 // Check NVIC_HFSR[31]
L(hfLoop):
bmi L(hfLoop) // Not set? Stay in HardFault Handler.
//
// Continue execution after BKPT instruction
//
#if defined(__thumb__) && !defined(__thumb2__)
movs R0, #4
mov R1, LR
tst R0, R1 // Check EXC_RETURN in Link register bit 2.
bne L(Uses_PSP)
mrs R0, MSP // Stacking was using MSP.
b L(Pass_StackPtr)
L(Uses_PSP):
mrs R0, PSP // Stacking was using PSP.
L(Pass_StackPtr):
#else
tst LR, #4 // Check EXC_RETURN[2] in link register to get the return stack
ite eq
mrseq R0, MSP // Frame stored on MSP
mrsne R0, PSP // Frame stored on PSP
#endif
//
// Reset HardFault Status
//
#if defined(__thumb__) && !defined(__thumb2__)
movs R3, #1
lsls R3, R3, #31
orrs R2, R3
str R2, [R1]
#else
orr R2, R2, #0x80000000
str R2, [R1]
#endif
//
// Adjust return address
//
ldr R1, [R0, #24] // Get stored PC from stack
adds R1, #2 // Adjust PC by 2 to skip current BKPT
str R1, [R0, #24] // Write back adjusted PC to stack
//
bx LR // Return
/*************************** End of file ****************************/

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/*********************************************************************
* SEGGER Microcontroller GmbH *
* The Embedded Experts *
**********************************************************************
* *
* (c) 2014 - 2021 SEGGER Microcontroller GmbH *
* *
* www.segger.com Support: support@segger.com *
* *
**********************************************************************
* *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or *
* without modification, are permitted provided that the following *
* condition is met: *
* *
* - Redistributions of source code must retain the above copyright *
* notice, this condition and the following disclaimer. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
* DAMAGE. *
* *
**********************************************************************
-------------------------- END-OF-HEADER -----------------------------
File : nrf9160_Vectors.s
Purpose : Exception and interrupt vectors for nrf9160 devices.
Additional information:
Preprocessor Definitions
__NO_EXTERNAL_INTERRUPTS
If defined,
the vector table will contain only the internal exceptions
and interrupts.
__VECTORS_IN_RAM
If defined,
an area of RAM, large enough to store the vector table,
will be reserved.
__OPTIMIZATION_SMALL
If defined,
all weak definitions of interrupt handlers will share the
same implementation.
If not defined,
all weak definitions of interrupt handlers will be defined
with their own implementation.
*/
.syntax unified
/*********************************************************************
*
* Macros
*
**********************************************************************
*/
//
// Directly place a vector (word) in the vector table
//
.macro VECTOR Name=
.section .vectors, "ax"
.code 16
.word \Name
.endm
//
// Declare an exception handler with a weak definition
//
.macro EXC_HANDLER Name=
//
// Insert vector in vector table
//
.section .vectors, "ax"
.word \Name
//
// Insert dummy handler in init section
//
.section .init.\Name, "ax"
.thumb_func
.weak \Name
.balign 2
\Name:
1: b 1b // Endless loop
.endm
//
// Declare an interrupt handler with a weak definition
//
.macro ISR_HANDLER Name=
//
// Insert vector in vector table
//
.section .vectors, "ax"
.word \Name
//
// Insert dummy handler in init section
//
#if defined(__OPTIMIZATION_SMALL)
.section .init, "ax"
.weak \Name
.thumb_set \Name,Dummy_Handler
#else
.section .init.\Name, "ax"
.thumb_func
.weak \Name
.balign 2
\Name:
1: b 1b // Endless loop
#endif
.endm
//
// Place a reserved vector in vector table
//
.macro ISR_RESERVED
.section .vectors, "ax"
.word 0
.endm
//
// Place a reserved vector in vector table
//
.macro ISR_RESERVED_DUMMY
.section .vectors, "ax"
.word Dummy_Handler
.endm
/*********************************************************************
*
* Externals
*
**********************************************************************
*/
.extern __stack_end__
.extern Reset_Handler
.extern HardFault_Handler
/*********************************************************************
*
* Global functions
*
**********************************************************************
*/
/*********************************************************************
*
* Setup of the vector table and weak definition of interrupt handlers
*
*/
.section .vectors, "ax"
.code 16
.balign 512
.global _vectors
_vectors:
//
// Internal exceptions and interrupts
//
VECTOR __stack_end__
VECTOR Reset_Handler
EXC_HANDLER NMI_Handler
VECTOR HardFault_Handler
EXC_HANDLER MemManage_Handler
ISR_RESERVED
ISR_RESERVED
ISR_RESERVED
ISR_RESERVED
ISR_RESERVED
ISR_RESERVED
EXC_HANDLER SVC_Handler
ISR_RESERVED
ISR_RESERVED
EXC_HANDLER PendSV_Handler
EXC_HANDLER SysTick_Handler
//
// External interrupts
//
#ifndef __NO_EXTERNAL_INTERRUPTS
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_HANDLER SPU_IRQHandler
ISR_RESERVED_DUMMY
ISR_HANDLER CLOCK_POWER_IRQHandler
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_HANDLER UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
ISR_HANDLER UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
ISR_HANDLER UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
ISR_HANDLER UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
ISR_RESERVED_DUMMY
ISR_HANDLER GPIOTE0_IRQHandler
ISR_HANDLER SAADC_IRQHandler
ISR_HANDLER TIMER0_IRQHandler
ISR_HANDLER TIMER1_IRQHandler
ISR_HANDLER TIMER2_IRQHandler
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_HANDLER RTC0_IRQHandler
ISR_HANDLER RTC1_IRQHandler
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_HANDLER WDT_IRQHandler
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_HANDLER EGU0_IRQHandler
ISR_HANDLER EGU1_IRQHandler
ISR_HANDLER EGU2_IRQHandler
ISR_HANDLER EGU3_IRQHandler
ISR_HANDLER EGU4_IRQHandler
ISR_HANDLER EGU5_IRQHandler
ISR_HANDLER PWM0_IRQHandler
ISR_HANDLER PWM1_IRQHandler
ISR_HANDLER PWM2_IRQHandler
ISR_HANDLER PWM3_IRQHandler
ISR_RESERVED_DUMMY
ISR_HANDLER PDM_IRQHandler
ISR_RESERVED_DUMMY
ISR_HANDLER I2S_IRQHandler
ISR_RESERVED_DUMMY
ISR_HANDLER IPC_IRQHandler
ISR_RESERVED_DUMMY
ISR_HANDLER FPU_IRQHandler
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_HANDLER GPIOTE1_IRQHandler
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_HANDLER KMU_IRQHandler
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_RESERVED_DUMMY
ISR_HANDLER CRYPTOCELL_IRQHandler
#endif
//
.section .vectors, "ax"
_vectors_end:
#ifdef __VECTORS_IN_RAM
//
// Reserve space with the size of the vector table
// in the designated RAM section.
//
.section .vectors_ram, "ax"
.balign 512
.global _vectors_ram
_vectors_ram:
.space _vectors_end - _vectors, 0
#endif
/*********************************************************************
*
* Dummy handler to be used for reserved interrupt vectors
* and weak implementation of interrupts.
*
*/
.section .init.Dummy_Handler, "ax"
.thumb_func
.weak Dummy_Handler
.balign 2
Dummy_Handler:
1: b 1b // Endless loop
/*************************** End of file ****************************/

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// **********************************************************************
// * SEGGER Microcontroller GmbH *
// * The Embedded Experts *
// **********************************************************************
// * *
// * (c) 2014 - 2022 SEGGER Microcontroller GmbH *
// * (c) 2001 - 2022 Rowley Associates Limited *
// * *
// * www.segger.com Support: support@segger.com *
// * *
// **********************************************************************
// * *
// * All rights reserved. *
// * *
// * Redistribution and use in source and binary forms, with or *
// * without modification, are permitted provided that the following *
// * condition is met: *
// * *
// * - Redistributions of source code must retain the above copyright *
// * notice, this condition and the following disclaimer. *
// * *
// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
// * DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
// * DAMAGE. *
// * *
// **********************************************************************
//
//
// Preprocessor Definitions
// ------------------------
// APP_ENTRY_POINT
//
// Defines the application entry point function, if undefined this setting
// defaults to "main".
//
// INITIALIZE_STACK
//
// If defined, the contents of the stack will be initialized to a the
// value 0xCC.
//
// INITIALIZE_SECONDARY_SECTIONS
//
// If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
//
// INITIALIZE_TCM_SECTIONS
//
// If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections
// will be initialized.
//
// INITIALIZE_USER_SECTIONS
//
// If defined, the function InitializeUserMemorySections will be called prior
// to entering main in order to allow the user to initialize any user defined
// memory sections.
//
// FULL_LIBRARY
//
// If defined then
// - argc, argv are setup by the debug_getargs.
// - the exit symbol is defined and executes on return from main.
// - the exit symbol calls destructors, atexit functions and then debug_exit.
//
// If not defined then
// - argc and argv are zero.
// - the exit symbol is defined, executes on return from main and loops
//
// STACK_CHECK
//
// If defined will set the v8m msplim/psplim registers to the start of the stacks
//
// RETURN_FROM_CRT0
//
// If defined, carry out a return to link register on application exit.
//
#ifndef APP_ENTRY_POINT
#define APP_ENTRY_POINT main
#endif
#ifndef ARGSSPACE
#define ARGSSPACE 128
#endif
.syntax unified
.global _start
.extern APP_ENTRY_POINT
.weak exit
#ifdef INITIALIZE_USER_SECTIONS
.extern InitializeUserMemorySections
#endif
.section .init, "ax"
.code 16
.balign 2
.thumb_func
_start:
/* Set up main stack if size > 0 */
ldr r1, =__stack_end__
ldr r0, =__stack_start__
subs r2, r1, r0
beq 1f
#ifdef __ARM_EABI__
movs r2, #0x7
bics r1, r2
#endif
mov sp, r1
#ifdef RETURN_FROM_CRT0
push {lr}
#endif
#ifdef INITIALIZE_STACK
movs r2, #0xCC
ldr r0, =__stack_start__
bl memory_set
#endif
#ifdef STACK_CHECK
ldr r0, =__stack_start__
msr msplim, r0
#endif
1:
/* Set up process stack if size > 0 */
ldr r1, =__stack_process_end__
ldr r0, =__stack_process_start__
subs r2, r1, r0
beq 1f
#ifdef __ARM_EABI__
movs r2, #0x7
bics r1, r2
#endif
msr psp, r1
movs r2, #2
msr control, r2
#ifdef INITIALIZE_STACK
movs r2, #0xCC
bl memory_set
#endif
#ifdef STACK_CHECK
ldr r0, =__stack_process_start__
msr psplim, r0
#endif
1:
/* Copy initialized memory sections into RAM (if necessary). */
ldr r0, =__data_load_start__
ldr r1, =__data_start__
ldr r2, =__data_end__
bl memory_copy
ldr r0, =__text_load_start__
ldr r1, =__text_start__
ldr r2, =__text_end__
bl memory_copy
ldr r0, =__fast_load_start__
ldr r1, =__fast_start__
ldr r2, =__fast_end__
bl memory_copy
ldr r0, =__ctors_load_start__
ldr r1, =__ctors_start__
ldr r2, =__ctors_end__
bl memory_copy
ldr r0, =__dtors_load_start__
ldr r1, =__dtors_start__
ldr r2, =__dtors_end__
bl memory_copy
ldr r0, =__rodata_load_start__
ldr r1, =__rodata_start__
ldr r2, =__rodata_end__
bl memory_copy
ldr r0, =__tdata_load_start__
ldr r1, =__tdata_start__
ldr r2, =__tdata_end__
bl memory_copy
#ifdef INITIALIZE_SECONDARY_SECTIONS
ldr r0, =__data2_load_start__
ldr r1, =__data2_start__
ldr r2, =__data2_end__
bl memory_copy
ldr r0, =__text2_load_start__
ldr r1, =__text2_start__
ldr r2, =__text2_end__
bl memory_copy
ldr r0, =__rodata2_load_start__
ldr r1, =__rodata2_start__
ldr r2, =__rodata2_end__
bl memory_copy
#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
#ifdef INITIALIZE_TCM_SECTIONS
ldr r0, =__data_tcm_load_start__
ldr r1, =__data_tcm_start__
ldr r2, =__data_tcm_end__
bl memory_copy
ldr r0, =__text_tcm_load_start__
ldr r1, =__text_tcm_start__
ldr r2, =__text_tcm_end__
bl memory_copy
ldr r0, =__rodata_tcm_load_start__
ldr r1, =__rodata_tcm_start__
ldr r2, =__rodata_tcm_end__
bl memory_copy
#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
/* Zero the bss. */
ldr r0, =__bss_start__
ldr r1, =__bss_end__
movs r2, #0
bl memory_set
ldr r0, =__tbss_start__
ldr r1, =__tbss_end__
movs r2, #0
bl memory_set
#ifdef INITIALIZE_SECONDARY_SECTIONS
ldr r0, =__bss2_start__
ldr r1, =__bss2_end__
mov r2, #0
bl memory_set
#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
#ifdef INITIALIZE_TCM_SECTIONS
ldr r0, =__bss_tcm_start__
ldr r1, =__bss_tcm_end__
mov r2, #0
bl memory_set
#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
#if !defined(__HEAP_SIZE__) || (__HEAP_SIZE__)
/* Initialize the heap */
ldr r0, = __heap_start__
ldr r1, = __heap_end__
subs r1, r1, r0
cmp r1, #8
blt 1f
movs r2, #0
str r2, [r0]
str r1, [r0, #4]
1:
#endif
#ifdef INITIALIZE_USER_SECTIONS
ldr r2, =InitializeUserMemorySections
blx r2
#endif
.type start, function
start:
/* Call constructors */
ldr r0, =__ctors_start__
ldr r1, =__ctors_end__
ctor_loop:
cmp r0, r1
beq ctor_end
ldr r2, [r0]
adds r0, #4
push {r0-r1}
blx r2
pop {r0-r1}
b ctor_loop
ctor_end:
/* Setup initial call frame */
movs r0, #0
mov lr, r0
mov r12, sp
/* Jump to application entry point */
#ifdef FULL_LIBRARY
movs r0, #ARGSSPACE
ldr r1, =args
ldr r2, =debug_getargs
blx r2
ldr r1, =args
#else
movs r0, #0
movs r1, #0
#endif
ldr r2, =APP_ENTRY_POINT
blx r2
.thumb_func
exit:
#ifdef FULL_LIBRARY
mov r5, r0 // save the exit parameter/return result
/* Call destructors */
ldr r0, =__dtors_start__
ldr r1, =__dtors_end__
dtor_loop:
cmp r0, r1
beq dtor_end
ldr r2, [r0]
adds r0, #4
push {r0-r1}
blx r2
pop {r0-r1}
b dtor_loop
dtor_end:
/* Call atexit functions */
ldr r2, =_execute_at_exit_fns
blx r2
/* Call debug_exit with return result/exit parameter */
mov r0, r5
ldr r2, =debug_exit
blx r2
#endif
/* Returned from application entry point */
#ifdef RETURN_FROM_CRT0
pop {r2}
bx r2
#else
/* Loop forever */
exit_loop:
b exit_loop
#endif
.thumb_func
memory_copy:
cmp r0, r1
beq 2f
subs r2, r2, r1
beq 2f
1:
ldrb r3, [r0]
adds r0, r0, #1
strb r3, [r1]
adds r1, r1, #1
subs r2, r2, #1
bne 1b
2:
bx lr
.thumb_func
memory_set:
cmp r0, r1
beq 1f
strb r2, [r0]
adds r0, r0, #1
b memory_set
1:
bx lr
// default C/C++ library helpers
.macro HELPER helper_name
.section .text.\helper_name, "ax", %progbits
.balign 2
.weak \helper_name
.thumb_func
\helper_name:
.endm
.macro JUMPTO name
#if defined(__thumb__) && !defined(__thumb2__)
mov r12, r0
ldr r0, =\name
push {r0}
mov r0, r12
pop {pc}
#else
b \name
#endif
.endm
HELPER __aeabi_read_tp
ldr r0, =__tbss_start__-8
bx lr
HELPER abort
b .
HELPER __assert
b .
HELPER __assert_func
b .
HELPER __aeabi_assert
b .
HELPER __sync_synchronize
bx lr
HELPER __getchar
JUMPTO debug_getchar
HELPER __putchar
JUMPTO debug_putchar
HELPER __open
JUMPTO debug_fopen
HELPER __close
JUMPTO debug_fclose
HELPER __write
mov r3, r0
mov r0, r1
movs r1, #1
JUMPTO debug_fwrite
HELPER __read
mov r3, r0
mov r0, r1
movs r1, #1
JUMPTO debug_fread
HELPER __seek
push {r4, lr}
mov r4, r0
bl debug_fseek
cmp r0, #0
bne 1f
mov r0, r4
bl debug_ftell
pop {r4, pc}
1:
ldr r0, =-1
pop {r4, pc}
HELPER remove
JUMPTO debug_remove
HELPER rename
JUMPTO debug_rename
// char __user_locale_name_buffer[];
.section .bss.__user_locale_name_buffer, "aw", %nobits
.weak __user_locale_name_buffer
__user_locale_name_buffer:
.space 0x4
#ifdef FULL_LIBRARY
.bss
args:
.space ARGSSPACE
#endif
/* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
.section .stack, "wa", %nobits
.section .stack_process, "wa", %nobits
.section .heap, "wa", %nobits

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<!DOCTYPE Linker_Placement_File>
<Root name="Flash Section Placement">
<MemorySegment name="$(FLASH_NAME:FLASH_NS_PRIV);FLASH_NS_PRIV">
<ProgramSection alignment="32" load="Yes" name=".vectors" start="$(FLASH_START:)" />
<ProgramSection alignment="4" load="Yes" name="priv_functions" inputsections="*(privileged_functions)"/>
<ProgramSection alignment="4" load="Yes" runin="privileged_data_run" name="privileged_data" />
</MemorySegment>
<MemorySegment name="$(FLASH_NAME:FLASH_NS_SYSCALLS);FLASH_NS_SYSCALLS">
<ProgramSection alignment="32" load="Yes" name="freertos_system_calls" />
</MemorySegment>
<MemorySegment name="$(FLASH_NAME:FLASH_NS_UNPRIV);FLASH_NS_UNPRIV">
<ProgramSection alignment="4" load="Yes" name=".init" />
<ProgramSection alignment="4" load="Yes" name=".init_rodata" />
<ProgramSection alignment="4" load="Yes" name=".text" />
<ProgramSection alignment="4" load="Yes" name=".dtors" />
<ProgramSection alignment="4" load="Yes" name=".ctors" />
<ProgramSection alignment="4" load="Yes" name=".rodata" />
<ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
<ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
<ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
<ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
</MemorySegment>
<MemorySegment name="$(RAM_NAME:RAM_NS_PRIV);SRAM_NS_PRIV;RAM_NS_PRIV">
<ProgramSection alignment="32" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
<ProgramSection alignment="32" load="No" name="privileged_data_run" />
</MemorySegment>
<MemorySegment name="$(RAM_NAME:RAM_NS_UNPRIV);SRAM_NS_UNPRIV;RAM_NS_UNPRIV">
<ProgramSection alignment="4" load="No" name=".fast_run" />
<ProgramSection alignment="4" load="No" name=".data_run" />
<ProgramSection alignment="4" load="No" name=".bss" />
<ProgramSection alignment="4" load="No" name=".tbss" />
<ProgramSection alignment="4" load="No" name=".tdata_run" />
<ProgramSection alignment="4" load="No" name=".non_init" />
<ProgramSection alignment="8" size="__HEAPSIZE__" load="No" name=".heap" />
<ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
<ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
</MemorySegment>
</Root>

8
FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Source/FreeRTOSDemo_MemoryMap.xml
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<!DOCTYPE Board_Memory_Definition_File>
<root name="nRF9160_xxAA">
<MemorySegment name="FLASH_NS_PRIV" start="0x00000000" size="0x00020000" access="ReadOnly" />
<MemorySegment name="FLASH_NS_SYSCALLS" start="0x00020000" size="0x00008000" access="ReadOnly" />
<MemorySegment name="FLASH_NS_UNPRIV" start="0x00028000" size="0x000D8000" access="ReadOnly" />
<MemorySegment name="RAM_NS_PRIV" start="0x20000000" size="0x00010000" access="Read/Write" />
<MemorySegment name="RAM_NS_UNPRIV" start="0x20010000" size="0x0002E000" access="Read/Write" />
</root>

184
FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Source/main.c
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/*
* FreeRTOS V202112.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Standard includes. */
#include <string.h>
/* FreeRTOS include. */
#include "FreeRTOS.h"
#include "task.h"
/* Device includes. */
#include "nrf.h"
/* Demo includes. */
#include "mpu_demo.h"
/*-----------------------------------------------------------*/
/* Initialize the MPU symbols needed by the port code. */
extern uint32_t __FLASH_NS_PRIV_segment_start__[];
extern uint32_t __FLASH_NS_PRIV_segment_end__[];
extern uint32_t __FLASH_NS_SYSCALLS_segment_start__[];
extern uint32_t __FLASH_NS_SYSCALLS_segment_end__[];
extern uint32_t __FLASH_NS_UNPRIV_segment_start__[];
extern uint32_t __FLASH_NS_UNPRIV_segment_end__[];
extern uint32_t __RAM_NS_PRIV_segment_start__[];
extern uint32_t __RAM_NS_PRIV_segment_end__[];
uint32_t * __privileged_functions_start__ = __FLASH_NS_PRIV_segment_start__;
uint32_t * __privileged_functions_end__ = ( uint32_t * )( ( uint32_t )__FLASH_NS_PRIV_segment_end__ - ( uint32_t ) 1 );
uint32_t * __syscalls_flash_start__ = __FLASH_NS_SYSCALLS_segment_start__;
uint32_t * __syscalls_flash_end__ = ( uint32_t * )( ( uint32_t )__FLASH_NS_SYSCALLS_segment_end__ - ( uint32_t ) 1 );
uint32_t * __unprivileged_flash_start__ = __FLASH_NS_UNPRIV_segment_start__;
uint32_t * __unprivileged_flash_end__ = ( uint32_t * )( ( uint32_t )__FLASH_NS_UNPRIV_segment_end__ - ( uint32_t ) 1 );
uint32_t * __privileged_sram_start__ = __RAM_NS_PRIV_segment_start__;
uint32_t * __privileged_sram_end__ = ( uint32_t * )( ( uint32_t )__RAM_NS_PRIV_segment_end__ - ( uint32_t ) 1 );
/*-----------------------------------------------------------*/
/**
* @brief The mem fault handler.
*
* It calls a function called vHandleMemoryFault.
*/
void MemManage_Handler( void ) __attribute__ ( ( naked ) );
/**
* @brief Initializes the privileged_data section.
*
* Called from the startup code.
*/
void InitializeUserMemorySections( void );
/*-----------------------------------------------------------*/
/* Non-Secure main. */
int main( void )
{
/* Create tasks for the MPU Demo. */
vStartMPUDemo();
/* Start scheduler. */
vTaskStartScheduler();
/* Will not get here if the scheduler starts successfully. If you do end up
here then there wasn't enough heap memory available to start either the idle
task or the timer/daemon task. https://www.freertos.org/a00111.html */
for( ; ; )
{
}
}
/*-----------------------------------------------------------*/
void InitializeUserMemorySections( void )
{
extern uint8_t __privileged_data_load_start__[];
extern uint8_t __privileged_data_start__[];
extern uint8_t __privileged_data_end__[];
memcpy( __privileged_data_start__,
__privileged_data_load_start__,
__privileged_data_end__ - __privileged_data_start__ );
}
/*-----------------------------------------------------------*/
/* Stack overflow hook. */
void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName )
{
/* Force an assert. */
configASSERT( pcTaskName == 0 );
}
/*-----------------------------------------------------------*/
/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an
* implementation of vApplicationGetIdleTaskMemory() to provide the memory that
* is used by the Idle task. */
void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
StackType_t ** ppxIdleTaskStackBuffer,
uint32_t * pulIdleTaskStackSize )
{
/* If the buffers to be provided to the Idle task are declared inside this
* function then they must be declared static - otherwise they will be
* allocated on the stack and so not exists after this function exits. */
static StaticTask_t xIdleTaskTCB;
static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );
/* Pass out a pointer to the StaticTask_t structure in which the Idle
* task's state will be stored. */
*ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
/* Pass out the array that will be used as the Idle task's stack. */
*ppxIdleTaskStackBuffer = uxIdleTaskStack;
/* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
* Note that, as the array is necessarily of type StackType_t,
* configMINIMAL_STACK_SIZE is specified in words, not bytes. */
*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
}
/*-----------------------------------------------------------*/
/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
* application must provide an implementation of vApplicationGetTimerTaskMemory()
* to provide the memory that is used by the Timer service task. */
void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
StackType_t ** ppxTimerTaskStackBuffer,
uint32_t * pulTimerTaskStackSize )
{
/* If the buffers to be provided to the Timer task are declared inside this
* function then they must be declared static - otherwise they will be
* allocated on the stack and so not exists after this function exits. */
static StaticTask_t xTimerTaskTCB;
static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ] __attribute__( ( aligned( 32 ) ) );
/* Pass out a pointer to the StaticTask_t structure in which the Timer
* task's state will be stored. */
*ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
/* Pass out the array that will be used as the Timer task's stack. */
*ppxTimerTaskStackBuffer = uxTimerTaskStack;
/* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
* Note that, as the array is necessarily of type StackType_t,
* configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */
*pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
}
/*-----------------------------------------------------------*/
void MemManage_Handler( void )
{
__asm volatile
(
" tst lr, #4 \n"
" ite eq \n"
" mrseq r0, msp \n"
" mrsne r0, psp \n"
" ldr r1, handler_address_const \n"
" bx r1 \n"
" \n"
" .align 4 \n"
" handler_address_const: .word vHandleMemoryFault \n"
);
}
/*-----------------------------------------------------------*/

3
FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/.gitignore vendored
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Output/
*.emSession
*.jlink

166
FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/Config/FreeRTOSConfig.h
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/*
* FreeRTOS V202112.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/******************************************************************************
See http://www.freertos.org/a00110.html for an explanation of the
definitions contained in this file.
******************************************************************************/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
* https://www.FreeRTOS.org/a00110.html
*----------------------------------------------------------*/
extern uint32_t SystemCoreClock;
/* Cortex M33 port configuration. */
#define configENABLE_MPU 1
#define configENABLE_FPU 1
#define configENABLE_TRUSTZONE 1
/* This part has 16 MPU regions. */
#define configTOTAL_MPU_REGIONS 16
/* Constants related to the behaviour or the scheduler. */
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
#define configUSE_PREEMPTION 1
#define configUSE_TIME_SLICING 1
#define configMAX_PRIORITIES ( 5 )
#define configIDLE_SHOULD_YIELD 1
#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */
/* Constants that describe the hardware and memory usage. */
#define configCPU_CLOCK_HZ SystemCoreClock
#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 256 )
#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )
#define configMAX_TASK_NAME_LEN ( 12 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) )
/* Constants that build features in or out. */
#define configUSE_MUTEXES 1
#define configUSE_TICKLESS_IDLE 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_NEWLIB_REENTRANT 0
#define configUSE_CO_ROUTINES 0
#define configUSE_COUNTING_SEMAPHORES 1
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_QUEUE_SETS 0
#define configUSE_TASK_NOTIFICATIONS 1
#define configUSE_TRACE_FACILITY 1
/* Constants that define which hook (callback) functions should be used. */
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configUSE_MALLOC_FAILED_HOOK 0
/* Constants provided for debugging and optimisation assistance. */
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
#define configQUEUE_REGISTRY_SIZE 0
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 3 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
/* Set the following definitions to 1 to include the API function, or zero
* to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is
* only necessary if the linker does not automatically remove functions that are
* not referenced anyway. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_uxTaskGetStackHighWaterMark 0
#define INCLUDE_xTaskGetIdleTaskHandle 0
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTaskResumeFromISR 0
#define INCLUDE_xTaskGetCurrentTaskHandle 1
#define INCLUDE_xTaskGetSchedulerState 0
#define INCLUDE_xSemaphoreGetMutexHolder 0
#define INCLUDE_xTimerPendFunctionCall 1
/* This demo makes use of one or more example stats formatting functions. These
* format the raw data provided by the uxTaskGetSystemState() function in to
* human readable ASCII form. See the notes in the implementation of vTaskList()
* within FreeRTOS/Source/tasks.c for limitations. */
#define configUSE_STATS_FORMATTING_FUNCTIONS 1
/* Dimensions a buffer that can be used by the FreeRTOS+CLI command interpreter.
* See the FreeRTOS+CLI documentation for more information:
* https://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */
#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048
/* Interrupt priority configuration follows...................... */
/* Use the system definition, if there is one. */
#ifdef __NVIC_PRIO_BITS
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 3 /* 8 priority levels. */
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
* function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07
/* The highest interrupt priority that can be used by any interrupt service
* routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT
* CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A
* HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values). */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* Interrupt priorities used by the kernel port layer itself. These are generic
* to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
* See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )
/* Constants related to the generation of run time stats. */
#define configGENERATE_RUN_TIME_STATS 0
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
#define portGET_RUN_TIME_COUNTER_VALUE() 0
#define configTICK_RATE_HZ ( ( TickType_t ) 100 )
/* Enable static allocation. */
#define configSUPPORT_STATIC_ALLOCATION 1
#endif /* FREERTOS_CONFIG_H */

218
FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/FreeRTOSDemo.emProject
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<!DOCTYPE CrossStudio_Project_File>
<solution Name="FreeRTOSDemo" target="8" version="2">
<project Name="FreeRTOSDemo_s">
<configuration
LIBRARY_IO_TYPE="RTT"
Name="Common"
Target="nRF9160_xxAA"
arm_architecture="v8M_Mainline"
arm_compiler_variant="clang"
arm_core_type="Cortex-M33"
arm_endian="Little"
arm_fp_abi="Hard"
arm_fpu_type="FPv5-SP-D16"
arm_linker_cmse_import_library_file_name="$(OutDir)/FreeRTOSDemo_s_cmse.lib"
arm_linker_heap_size="0"
arm_linker_process_stack_size="0"
arm_linker_stack_size="2048"
arm_linker_variant="GNU"
arm_rtl_variant="SEGGER"
arm_simulator_memory_simulation_parameter="ROM;0x00000000;0x00100000;RAM;0x20000000;0x0003E000"
arm_target_debug_interface_type="ADIv5"
arm_target_device_name="nRF9160_xxAA"
arm_target_interface_type="SWD"
arm_v8M_has_cmse="Yes"
build_intermediate_directory="Output/$(ProjectName)/$(Configuration)/Objects/"
build_output_directory="Output/$(ProjectName)/$(Configuration)"
c_preprocessor_definitions="ARM_MATH_ARMV8MML;NRF9160_XXAA;__NRF_FAMILY;__SUPPORT_RESET_HALT_AFTER_BTL=0;__ARMCC_VERSION"
c_user_include_directories="$(ProjectDir)/Nordic_Code/CMSIS_5/CMSIS/Core/Include;$(ProjectDir)/Nordic_Code/nRF/Device/Include;$(ProjectDir)/Config;../../Source/portable/GCC/ARM_CM33/secure;../Common/ARMv8M/tz_demo"
debug_register_definition_file="$(ProjectDir)/Nordic_Code/nRF/XML/nrf9160_Registers.xml"
debug_stack_pointer_start="__stack_end__"
debug_start_from_entry_point_symbol="No"
debug_target_connection="J-Link"
gcc_entry_point="Reset_Handler"
link_linker_script_file=""
linker_memory_map_file="$(ProjectDir)/Secure/FreeRTOSDemo_s_MemoryMap.xml"
linker_output_format="bin"
linker_section_placement_file="$(ProjectDir)/Secure/FreeRTOSDemo_s_Flash_Placement.xml"
macros="DeviceHeaderFile=$(PackagesDir)/nRF/Device/Include/nrf.h;DeviceLibraryIdentifier=ARMv8MMLlfsp;DeviceSystemFile=$(PackagesDir)/nRF/Device/Source/system_nrf9160.c;DeviceVectorsFile=$(PackagesDir)/nRF/Source/nrf9160_Vectors.s;DeviceFamily=nRF;Target=nRF9160_xxAA"
project_directory=""
project_type="Executable"
target_reset_script="Reset();"
target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
<folder Name="Nordic_Code">
<folder Name="CMSIS Files">
<file file_name="Nordic_Code/nRF/Device/Source/system_nrf9160.c">
<configuration
Name="Common"
default_code_section=".init"
default_const_section=".init_rodata" />
</file>
<file file_name="Nordic_Code/nRF/Device/Include/nrf.h" />
</folder>
<folder Name="Script Files">
<file file_name="Nordic_Code/nRF/Scripts/nRF_Target.js">
<configuration Name="Common" file_type="Reset Script" />
</file>
</folder>
<folder Name="System Files">
<file file_name="Nordic_Code/nRF/Source/nRF_Startup.s" />
<file file_name="Nordic_Code/nRF/Source/nrf9160_Vectors.s">
<configuration Name="Common" file_type="Assembly" />
</file>
<file file_name="Nordic_Code/nRF/Source/thumb_crt0.s" />
</folder>
</folder>
<folder Name="User">
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc" />
<file file_name="Secure/main_s.c" />
</folder>
<folder Name="FreeRTOS">
<folder Name="SecureContext">
<file file_name="../../Source/portable/GCC/ARM_CM33/secure/secure_context.c" />
<file file_name="../../Source/portable/GCC/ARM_CM33/secure/secure_context.h" />
<file file_name="../../Source/portable/GCC/ARM_CM33/secure/secure_context_port.c" />
<file file_name="../../Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h" />
</folder>
<folder Name="SecureHeap">
<file file_name="../../Source/portable/GCC/ARM_CM33/secure/secure_heap.c" />
<file file_name="../../Source/portable/GCC/ARM_CM33/secure/secure_heap.h" />
</folder>
<folder Name="SecureInit">
<file file_name="../../Source/portable/GCC/ARM_CM33/secure/secure_init.c" />
<file file_name="../../Source/portable/GCC/ARM_CM33/secure/secure_init.h" />
</folder>
</folder>
<folder Name="NSCFunctions">
<file file_name="../Common/ARMv8M/tz_demo/nsc_functions.c" />
<file file_name="../Common/ARMv8M/tz_demo/nsc_functions.h" />
</folder>
<folder Name="Config">
<file file_name="Config/FreeRTOSConfig.h" />
</folder>
</project>
<configuration
Name="Debug"
c_preprocessor_definitions="DEBUG"
gcc_debugging_level="Level 3"
gcc_optimization_level="None" />
<project Name="FreeRTOSDemo_ns">
<configuration
LIBRARY_IO_TYPE="RTT"
Name="Common"
Target="nRF9160_xxAA"
arm_architecture="v8M_Mainline"
arm_compiler_variant="clang"
arm_core_type="Cortex-M33"
arm_endian="Little"
arm_fp_abi="Hard"
arm_fpu_type="FPv5-SP-D16"
arm_linker_heap_size="0"
arm_linker_process_stack_size="0"
arm_linker_stack_size="2048"
arm_linker_variant="GNU"
arm_rtl_variant="SEGGER"
arm_simulator_memory_simulation_parameter="ROM;0x00000000;0x00100000;RAM;0x20000000;0x0003E000"
arm_target_debug_interface_type="ADIv5"
arm_target_device_name="nRF9160_xxAA"
arm_target_interface_type="SWD"
arm_v8M_has_cmse="Yes"
build_intermediate_directory="Output/$(ProjectName)/$(Configuration)/Objects/"
build_output_directory="Output/$(ProjectName)/$(Configuration)"
c_preprocessor_definitions="ARM_MATH_ARMV8MML;NRF9160_XXAA;__NRF_FAMILY;NRF_TRUSTZONE_NONSECURE;__SUPPORT_RESET_HALT_AFTER_BTL=0;INITIALIZE_USER_SECTIONS;__ARMCC_VERSION"
c_user_include_directories="$(ProjectDir)/Nordic_Code/CMSIS_5/CMSIS/Core/Include;$(ProjectDir)/Nordic_Code/nRF/Device/Include;$(ProjectDir)/Config;../../Source/include;../../Source/portable/GCC/ARM_CM33/secure;../../Source/portable/GCC/ARM_CM33/non_secure;../Common/ARMv8M/tz_demo;../Common/ARMv8M/mpu_demo"
debug_register_definition_file="$(ProjectDir)/Nordic_Code/nRF/XML/nrf9160_Registers.xml"
debug_stack_pointer_start="__stack_end__"
debug_start_from_entry_point_symbol="No"
debug_target_connection="J-Link"
gcc_entry_point="Reset_Handler"
link_linker_script_file=""
linker_additional_files="$(OutDir)/../../FreeRTOSDemo_s/$(Configuration)/FreeRTOSDemo_s_cmse.lib"
linker_memory_map_file="$(ProjectDir)/NonSecure/FreeRTOSDemo_ns_MemoryMap.xml"
linker_output_format="bin"
linker_section_placement_file="$(ProjectDir)/NonSecure/FreeRTOSDemo_ns_Flash_Placement.xml"
macros="DeviceHeaderFile=$(PackagesDir)/nRF/Device/Include/nrf.h;DeviceLibraryIdentifier=ARMv8MMLlfsp;DeviceSystemFile=$(PackagesDir)/nRF/Device/Source/system_nrf9160.c;DeviceVectorsFile=$(PackagesDir)/nRF/Source/nrf9160_Vectors.s;DeviceFamily=nRF;Target=nRF9160_xxAA"
project_directory=""
project_type="Executable"
target_reset_script="Reset();"
target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
<folder Name="Nordic_Code">
<folder Name="CMSIS Files">
<file file_name="Nordic_Code/nRF/Device/Include/nrf.h" />
<file file_name="Nordic_Code/nRF/Device/Source/system_nrf9160.c">
<configuration
Name="Common"
default_code_section=".init"
default_const_section=".init_rodata" />
</file>
</folder>
<folder Name="Script Files">
<file file_name="Nordic_Code/nRF/Scripts/nRF_Target.js">
<configuration Name="Common" file_type="Reset Script" />
</file>
</folder>
<folder Name="System Files">
<file file_name="Nordic_Code/nRF/Source/nRF_Startup.s" />
<file file_name="Nordic_Code/nRF/Source/nrf9160_Vectors.s">
<configuration Name="Common" file_type="Assembly" />
</file>
<file file_name="Nordic_Code/nRF/Source/thumb_crt0.s" />
</folder>
</folder>
<folder Name="User">
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc" />
<file file_name="NonSecure/main_ns.c" />
</folder>
<folder Name="FreeRTOS">
<folder Name="include">
<file file_name="../../Source/include/atomic.h" />
<file file_name="../../Source/include/deprecated_definitions.h" />
<file file_name="../../Source/include/event_groups.h" />
<file file_name="../../Source/include/FreeRTOS.h" />
<file file_name="../../Source/include/list.h" />
<file file_name="../../Source/include/message_buffer.h" />
<file file_name="../../Source/include/mpu_prototypes.h" />
<file file_name="../../Source/include/mpu_wrappers.h" />
<file file_name="../../Source/include/portable.h" />
<file file_name="../../Source/include/projdefs.h" />
<file file_name="../../Source/include/queue.h" />
<file file_name="../../Source/include/semphr.h" />
<file file_name="../../Source/include/stack_macros.h" />
<file file_name="../../Source/include/stream_buffer.h" />
<file file_name="../../Source/include/task.h" />
<file file_name="../../Source/include/timers.h" />
</folder>
<folder Name="portable">
<folder Name="GCC">
<folder Name="ARM_CM33">
<file file_name="../../Source/portable/GCC/ARM_CM33/non_secure/portasm.c" />
<file file_name="../../Source/portable/GCC/ARM_CM33/non_secure/portasm.h" />
<file file_name="../../Source/portable/GCC/ARM_CM33/non_secure/port.c" />
<file file_name="../../Source/portable/GCC/ARM_CM33/non_secure/portmacro.h" />
</folder>
</folder>
<folder Name="MemMang">
<file file_name="../../Source/portable/MemMang/heap_4.c" />
</folder>
<folder Name="Common">
<file file_name="../../Source/portable/Common/mpu_wrappers.c" />
</folder>
</folder>
<file file_name="../../Source/event_groups.c" />
<file file_name="../../Source/list.c" />
<file file_name="../../Source/queue.c" />
<file file_name="../../Source/stream_buffer.c" />
<file file_name="../../Source/tasks.c" />
<file file_name="../../Source/timers.c" />
</folder>
<folder Name="Demos">
<file file_name="../Common/ARMv8M/mpu_demo/mpu_demo.c" />
<file file_name="../Common/ARMv8M/mpu_demo/mpu_demo.h" />
<file file_name="../Common/ARMv8M/tz_demo/tz_demo.c" />
<file file_name="../Common/ARMv8M/tz_demo/tz_demo.h" />
</folder>
<folder Name="Config">
<file file_name="Config/FreeRTOSConfig.h" />
</folder>
</project>
</solution>

38
FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/NonSecure/FreeRTOSDemo_ns_Flash_Placement.xml
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<!DOCTYPE Linker_Placement_File>
<Root name="Flash Section Placement">
<MemorySegment name="$(FLASH_NAME:FLASH_NS_PRIV);FLASH_NS_PRIV">
<ProgramSection alignment="32" load="Yes" name=".vectors" start="$(FLASH_START:)" />
<ProgramSection alignment="4" load="Yes" name="priv_functions" inputsections="*(privileged_functions)"/>
<ProgramSection alignment="4" load="Yes" runin="privileged_data_run" name="privileged_data" />
</MemorySegment>
<MemorySegment name="$(FLASH_NAME:FLASH_NS_SYSCALLS);FLASH_NS_SYSCALLS">
<ProgramSection alignment="32" load="Yes" name="freertos_system_calls" />
</MemorySegment>
<MemorySegment name="$(FLASH_NAME:FLASH_NS_UNPRIV);FLASH_NS_UNPRIV">
<ProgramSection alignment="4" load="Yes" name=".init" />
<ProgramSection alignment="4" load="Yes" name=".init_rodata" />
<ProgramSection alignment="4" load="Yes" name=".text" />
<ProgramSection alignment="4" load="Yes" name=".dtors" />
<ProgramSection alignment="4" load="Yes" name=".ctors" />
<ProgramSection alignment="4" load="Yes" name=".rodata" />
<ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
<ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
<ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
<ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
</MemorySegment>
<MemorySegment name="$(RAM_NAME:RAM_NS_PRIV);SRAM_NS_PRIV;RAM_NS_PRIV">
<ProgramSection alignment="32" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
<ProgramSection alignment="32" load="No" name="privileged_data_run" />
</MemorySegment>
<MemorySegment name="$(RAM_NAME:RAM_NS_UNPRIV);SRAM_NS_UNPRIV;RAM_NS_UNPRIV">
<ProgramSection alignment="4" load="No" name=".fast_run" />
<ProgramSection alignment="4" load="No" name=".data_run" />
<ProgramSection alignment="4" load="No" name=".bss" />
<ProgramSection alignment="4" load="No" name=".tbss" />
<ProgramSection alignment="4" load="No" name=".tdata_run" />
<ProgramSection alignment="4" load="No" name=".non_init" />
<ProgramSection alignment="8" size="__HEAPSIZE__" load="No" name=".heap" />
<ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
<ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
</MemorySegment>
</Root>

8
FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/NonSecure/FreeRTOSDemo_ns_MemoryMap.xml
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@ -0,0 +1,8 @@
<!DOCTYPE Board_Memory_Definition_File>
<root name="nRF9160_xxAA">
<MemorySegment name="FLASH_NS_PRIV" start="0x00080000" size="0x00020000" access="ReadOnly" />
<MemorySegment name="FLASH_NS_SYSCALLS" start="0x000A0000" size="0x00008000" access="ReadOnly" />
<MemorySegment name="FLASH_NS_UNPRIV" start="0x000A8000" size="0x00058000" access="ReadOnly" />
<MemorySegment name="RAM_NS_PRIV" start="0x20020000" size="0x00010000" access="Read/Write" />
<MemorySegment name="RAM_NS_UNPRIV" start="0x20030000" size="0x0000E000" access="Read/Write" />
</root>

201
FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/NonSecure/main_ns.c
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/*
* FreeRTOS V202112.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Standard includes. */
#include <string.h>
/* FreeRTOS include. */
#include "FreeRTOS.h"
#include "task.h"
/* Device includes. */
#include "nrf.h"
/* Demo includes. */
#include "tz_demo.h"
#include "mpu_demo.h"
/*-----------------------------------------------------------*/
/* Initialize the MPU symbols needed by the port code. */
extern uint32_t __FLASH_NS_PRIV_segment_start__[];
extern uint32_t __FLASH_NS_PRIV_segment_end__[];
extern uint32_t __FLASH_NS_SYSCALLS_segment_start__[];
extern uint32_t __FLASH_NS_SYSCALLS_segment_end__[];
extern uint32_t __FLASH_NS_UNPRIV_segment_start__[];
extern uint32_t __FLASH_NS_UNPRIV_segment_end__[];
extern uint32_t __RAM_NS_PRIV_segment_start__[];
extern uint32_t __RAM_NS_PRIV_segment_end__[];
uint32_t * __privileged_functions_start__ = __FLASH_NS_PRIV_segment_start__;
uint32_t * __privileged_functions_end__ = ( uint32_t * )( ( uint32_t )__FLASH_NS_PRIV_segment_end__ - ( uint32_t ) 1 );
uint32_t * __syscalls_flash_start__ = __FLASH_NS_SYSCALLS_segment_start__;
uint32_t * __syscalls_flash_end__ = ( uint32_t * )( ( uint32_t )__FLASH_NS_SYSCALLS_segment_end__ - ( uint32_t ) 1 );
uint32_t * __unprivileged_flash_start__ = __FLASH_NS_UNPRIV_segment_start__;
uint32_t * __unprivileged_flash_end__ = ( uint32_t * )( ( uint32_t )__FLASH_NS_UNPRIV_segment_end__ - ( uint32_t ) 1 );
uint32_t * __privileged_sram_start__ = __RAM_NS_PRIV_segment_start__;
uint32_t * __privileged_sram_end__ = ( uint32_t * )( ( uint32_t )__RAM_NS_PRIV_segment_end__ - ( uint32_t ) 1 );
/*-----------------------------------------------------------*/
/**
* @brief Create all demo tasks.
*/
static void prvCreateTasks( void );
/**
* @brief The mem fault handler.
*
* It calls a function called vHandleMemoryFault.
*/
void MemManage_Handler( void ) __attribute__ ( ( naked ) );
/**
* @brief Initializes the privileged_data section.
*
* Called from the startup code.
*/
void InitializeUserMemorySections( void );
/*-----------------------------------------------------------*/
/* Non-Secure main. */
int main( void )
{
/* Create tasks. */
prvCreateTasks();
/* Start scheduler. */
vTaskStartScheduler();
/* Will not get here if the scheduler starts successfully. If you do end up
here then there wasn't enough heap memory available to start either the idle
task or the timer/daemon task. https://www.freertos.org/a00111.html */
for( ; ; )
{
}
}
/*-----------------------------------------------------------*/
static void prvCreateTasks( void )
{
/* Create tasks for the MPU Demo. */
vStartMPUDemo();
/* Create tasks for the TZ Demo. */
vStartTZDemo();
}
/*-----------------------------------------------------------*/
void InitializeUserMemorySections( void )
{
extern uint8_t __privileged_data_load_start__[];
extern uint8_t __privileged_data_start__[];
extern uint8_t __privileged_data_end__[];
memcpy( __privileged_data_start__,
__privileged_data_load_start__,
__privileged_data_end__ - __privileged_data_start__ );
}
/*-----------------------------------------------------------*/
/* Stack overflow hook. */
void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName )
{
/* Force an assert. */
configASSERT( pcTaskName == 0 );
}
/*-----------------------------------------------------------*/
/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an
* implementation of vApplicationGetIdleTaskMemory() to provide the memory that
* is used by the Idle task. */
void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
StackType_t ** ppxIdleTaskStackBuffer,
uint32_t * pulIdleTaskStackSize )
{
/* If the buffers to be provided to the Idle task are declared inside this
* function then they must be declared static - otherwise they will be
* allocated on the stack and so not exists after this function exits. */
static StaticTask_t xIdleTaskTCB;
static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );
/* Pass out a pointer to the StaticTask_t structure in which the Idle
* task's state will be stored. */
*ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
/* Pass out the array that will be used as the Idle task's stack. */
*ppxIdleTaskStackBuffer = uxIdleTaskStack;
/* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
* Note that, as the array is necessarily of type StackType_t,
* configMINIMAL_STACK_SIZE is specified in words, not bytes. */
*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
}
/*-----------------------------------------------------------*/
/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
* application must provide an implementation of vApplicationGetTimerTaskMemory()
* to provide the memory that is used by the Timer service task. */
void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
StackType_t ** ppxTimerTaskStackBuffer,
uint32_t * pulTimerTaskStackSize )
{
/* If the buffers to be provided to the Timer task are declared inside this
* function then they must be declared static - otherwise they will be
* allocated on the stack and so not exists after this function exits. */
static StaticTask_t xTimerTaskTCB;
static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ] __attribute__( ( aligned( 32 ) ) );
/* Pass out a pointer to the StaticTask_t structure in which the Timer
* task's state will be stored. */
*ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
/* Pass out the array that will be used as the Timer task's stack. */
*ppxTimerTaskStackBuffer = uxTimerTaskStack;
/* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
* Note that, as the array is necessarily of type StackType_t,
* configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */
*pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
}
/*-----------------------------------------------------------*/
void MemManage_Handler( void )
{
__asm volatile
(
" tst lr, #4 \n"
" ite eq \n"
" mrseq r0, msp \n"
" mrsne r0, psp \n"
" ldr r1, handler_address_const \n"
" bx r1 \n"
" \n"
" .align 4 \n"
" handler_address_const: .word vHandleMemoryFault \n"
);
}
/*-----------------------------------------------------------*/

283
FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/Nordic_Code/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h
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@ -0,0 +1,283 @@
/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

2177
FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/Nordic_Code/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h
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