Update to IAR V5.3.
Richard Barry
16 years ago
parent
eefea4b753
commit
c82aa9b224
@ -0,0 +1,131 @@
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// ---------------------------------------------------------
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// ATMEL Microcontroller Software Support - ROUSSET -
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// ---------------------------------------------------------
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// The software is delivered "AS IS" without warranty or
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// condition of any kind, either express, implied or
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// statutory. This includes without limitation any warranty
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// or condition with respect to merchantability or fitness
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// for any particular purpose, or against the infringements of
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// intellectual property rights of others.
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// ---------------------------------------------------------
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// File: SAM9XE_FLASH.mac
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// User setup file for CSPY debugger.
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// 1.1 08/Aug/06 jpp : Creation
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//
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// $Revision: 23594 $
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//
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// ---------------------------------------------------------
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__var __mac_i;
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__var __mac_pt;
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/*********************************************************************
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*
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* execUserReset() : JTAG set initially to Full Speed
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*/
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execUserReset()
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{
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__message "------------------------------ execUserReset ---------------------------------";
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__writeMemory32(0x00000500, 0xFFFFFA00, "Memory"); // Set flash wait states
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__PllSetting(); //* Init PLL
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__PllSetting100MHz();
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__message "-------------------------------Set PC Reset ----------------------------------";
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}
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/*********************************************************************
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*
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* execUserPreload() : JTAG set initially to 32kHz
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*/
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execUserPreload()
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{
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__message "------------------------------ execUserPreload ---------------------------------";
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__hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
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__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
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__writeMemory32(0x00000500, 0xFFFFFA00, "Memory"); // Set flash wait states
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__PllSetting(); //* Init PLL
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__PllSetting100MHz();
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_InitRSTC(); //* Enable User Reset to allow execUserReset() execution
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}
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/*********************************************************************
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*
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* _InitRSTC()
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*
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* Function description
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* Initializes the RSTC (Reset controller).
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* This makes sense since the default is to not allow user resets, which makes it impossible to
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* apply a second RESET via J-Link
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*/
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_InitRSTC() {
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__writeMemory32(0xA5000001, 0xFFFFFD08,"Memory"); // Allow user reset
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}
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/*********************************************************************
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*
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* __PllSetting()
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* Function description
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* Initializes the PMC.
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* 1. Enable the Main Oscillator
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* 2. Configure PLL
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* 3. Switch Master
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*/
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__PllSetting()
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{
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if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) {
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//* Disable all PMC interrupt ( $$ JPP)
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//* AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
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//* pPmc->PMC_IDR = 0xFFFFFFFF;
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__writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory");
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//* AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
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__writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory");
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// Disable all clock only Processor clock is enabled.
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__writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory");
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// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
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__writeMemory32(0x00000001,0xFFFFFC30,"Memory");
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__sleep(10000);
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// write reset value to PLLA and PLLB
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// AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
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__writeMemory32(0x00003F00,0xFFFFFC28,"Memory");
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// AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
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__writeMemory32(0x00003F00,0xFFFFFC2C,"Memory");
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__sleep(10000);
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__message "------------------------------- PLL Enable -----------------------------------------";
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} else {
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__message " ********* Core in SLOW CLOCK mode ********* "; }
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}
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/*********************************************************************
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*
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* __PllSetting100MHz()
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* Function description
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* Set core at 200 MHz and MCK at 100 MHz
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*/
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__PllSetting100MHz()
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{
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__message "------------------------------- PLL Set at 100 MHz ----------------------------------";
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//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
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__writeMemory32(0x00004001,0xFFFFFC20,"Memory");
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__sleep(10000);
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// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
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__writeMemory32(0x00000001,0xFFFFFC30,"Memory");
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__sleep(10000);
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//* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) |
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// (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);
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__writeMemory32(0x2060BF09,0xFFFFFC28,"Memory");
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__sleep(10000);
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//* AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
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__writeMemory32(0x00000102,0xFFFFFC30,"Memory");
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__sleep(10000);
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}
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@ -0,0 +1,249 @@
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// ---------------------------------------------------------
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// ATMEL Microcontroller Software Support - ROUSSET -
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// ---------------------------------------------------------
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// The software is delivered "AS IS" without warranty or
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// condition of any kind, either express, implied or
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// statutory. This includes without limitation any warranty
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||||
// or condition with respect to merchantability or fitness
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||||
// for any particular purpose, or against the infringements of
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// intellectual property rights of others.
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// ---------------------------------------------------------
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// File: SAM9XE_SDRAM.mac
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// User setup file for CSPY debugger.
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// 1.1 08/Aug/06 jpp : Creation
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//
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// $Revision: 23594 $
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//
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// ---------------------------------------------------------
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__var __mac_i;
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__var __mac_pt;
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/*********************************************************************
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*
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* execUserReset() : JTAG set initially to Full Speed
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*/
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execUserReset()
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{
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__message "------------------------------ execUserReset ---------------------------------";
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_MapRAMAt0(); //* Set the RAM memory at 0x00200000 & 0x00000000
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__PllSetting(); //* Init PLL
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__PllSetting100MHz();
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__message "-------------------------------Set PC Reset ----------------------------------";
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}
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/*********************************************************************
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*
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* execUserPreload() : JTAG set initially to 32kHz
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*/
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execUserPreload()
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{
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__message "------------------------------ execUserPreload ---------------------------------";
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__hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
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__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
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__PllSetting(); //* Init PLL
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__PllSetting100MHz();
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__initSDRAM(); //* Init SDRAM before load
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_MapRAMAt0(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
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_InitRSTC(); //* Enable User Reset to allow execUserReset() execution
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}
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/*********************************************************************
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*
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* _InitRSTC()
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*
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* Function description
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* Initializes the RSTC (Reset controller).
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* This makes sense since the default is to not allow user resets, which makes it impossible to
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* apply a second RESET via J-Link
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*/
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_InitRSTC() {
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__writeMemory32(0xA5000001, 0xFFFFFD08,"Memory"); // Allow user reset
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}
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/*********************************************************************
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*
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* __initSDRAM()
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* Function description
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* Set SDRAM for works at 100 MHz
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*/
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__initSDRAM()
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{
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//* Configure EBI Chip select
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// pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC;
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// AT91C_CCFG_EBICSA ((AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register
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__writeMemory32(0x0001003A,0xFFFFEF1C,"Memory");
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//* Configure PIOs
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//* AT91F_PIO_CfgPeriph( AT91C_BASE_PIOC, AT91C_PC16_D16 to AT91C_PC16_D31
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// pPio->PIO_ASR = periphAEnable; AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register
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// pPio->PIO_BSR = periphBEnable;AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register
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// pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
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__writeMemory32(0xFFFF0000,0xFFFFF870,"Memory");
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__writeMemory32(0x00000000,0xFFFFF874,"Memory");
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__writeMemory32(0xFFFF0000,0xFFFFF804,"Memory");
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//* psdrc->SDRAMC_CR = AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 |
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// AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 |
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// AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 ;
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__writeMemory32(0x85227279,0xFFFFEA08,"Memory");
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__sleep(100);
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//* psdrc->SDRAMC_MR = 0x00000002; // Set PRCHG AL
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__writeMemory32(0x00000002,0xFFFFEA00,"Memory");
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//* *AT91C_SDRAM = 0x00000000; // Perform PRCHG
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__writeMemory32(0x00000000,0x20000000,"Memory");
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__sleep(100);
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//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
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__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
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//* *(AT91C_SDRAM+4) = 0x00000001; // Perform CBR
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__writeMemory32(0x00000001,0x20000010,"Memory");
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//* psdrc->SDRAMC_MR = 0x00000004; // Set 2 CBR
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__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
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//* *(AT91C_SDRAM+8) = 0x00000002; // Perform CBR
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__writeMemory32(0x00000002,0x20000020,"Memory");
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//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 3 CBR
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__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
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//* *(AT91C_SDRAM+0xc) = 0x00000003; // Perform CBR
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__writeMemory32(0x00000003,0x20000030,"Memory");
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//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 4 CBR
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__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
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//* *(AT91C_SDRAM+0x10) = 0x00000004; // Perform CBR
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__writeMemory32(0x00000004,0x20000040,"Memory");
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//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 5 CBR
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__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
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//* *(AT91C_SDRAM+0x14) = 0x00000005; // Perform CBR
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__writeMemory32(0x00000005,0x20000050,"Memory");
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//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 6 CBR
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__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
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//* *(AT91C_SDRAM+0x18) = 0x00000006; // Perform CBR
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__writeMemory32(0x00000006,0x20000060,"Memory");
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//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 7 CBR
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__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
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//* *(AT91C_SDRAM+0x1c) = 0x00000007; // Perform CBR
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__writeMemory32(0x00000007,0x20000070,"Memory");
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//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 8 CBR
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__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
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//* *(AT91C_SDRAM+0x20) = 0x00000008; // Perform CBR
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__writeMemory32(0x00000008,0x20000080,"Memory");
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//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_LMR_CMD; // Set LMR operation
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__writeMemory32(0x00000003,0xFFFFEA00,"Memory");
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//* *(AT91C_SDRAM+0x24) = 0xcafedede; // Perform LMR burst=1, lat=2
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__writeMemory32(0xCAFEDEDE,0x20000090,"Memory");
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//* psdrc->SDRAMC_TR = (AT91C_MASTER_CLOCK * 7)/1000000; // Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
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// // (F : system clock freq. MHz
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__writeMemory32(0x000002B9,0xFFFFEA04,"Memory");
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//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_NORMAL_CMD; // Set Normal mode
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__writeMemory32(0x00000000,0xFFFFEA00,"Memory");
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//* *AT91C_SDRAM = 0x00000000; // Perform Normal mode
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__writeMemory32(0x00000000,0x20000000,"Memory");
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__message "------------------------------- SDRAM Done at 100 MHz -------------------------------";
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}
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/*********************************************************************
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*
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* _MapRAMAt0()
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* Function description
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* Remap RAM at 0
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*/
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_MapRAMAt0()
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{
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// AT91C_MATRIX_MRCR ((AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register
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__mac_i=__readMemory32(0xFFFFEF00,"Memory");
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__message "----- AT91C_MATRIX_MRCR : 0x",__mac_i:%X;
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if ( ((__mac_i & 0x01) == 0) || ((__mac_i & 0x02) == 0)){
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__message "------------------------------- The Remap is NOT & REMAP ----------------------------";
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__writeMemory32(0x00000003,0xFFFFEF00,"Memory");
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__mac_i=__readMemory32(0xFFFFEF00,"Memory");
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__message "----- AT91C_MATRIX_MRCR : 0x",__mac_i:%X;
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} else {
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__message "------------------------------- The Remap is done -----------------------------------";
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}
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}
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/*********************************************************************
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*
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* __PllSetting()
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* Function description
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* Initializes the PMC.
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* 1. Enable the Main Oscillator
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* 2. Configure PLL
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* 3. Switch Master
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*/
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__PllSetting()
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{
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if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) {
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//* Disable all PMC interrupt ( $$ JPP)
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//* AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
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//* pPmc->PMC_IDR = 0xFFFFFFFF;
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__writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory");
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//* AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
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__writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory");
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// Disable all clock only Processor clock is enabled.
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__writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory");
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// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
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__writeMemory32(0x00000001,0xFFFFFC30,"Memory");
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__sleep(10000);
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// write reset value to PLLA and PLLB
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// AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
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__writeMemory32(0x00003F00,0xFFFFFC28,"Memory");
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// AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
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__writeMemory32(0x00003F00,0xFFFFFC2C,"Memory");
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__sleep(10000);
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__message "------------------------------- PLL Enable -----------------------------------------";
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} else {
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__message " ********* Core in SLOW CLOCK mode ********* "; }
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}
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/*********************************************************************
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*
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* __PllSetting100MHz()
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* Function description
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* Set core at 200 MHz and MCK at 100 MHz
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*/
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__PllSetting100MHz()
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{
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__message "------------------------------- PLL Set at 100 MHz ----------------------------------";
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//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
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__writeMemory32(0x00004001,0xFFFFFC20,"Memory");
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__sleep(10000);
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// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
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__writeMemory32(0x00000001,0xFFFFFC30,"Memory");
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__sleep(10000);
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//* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) |
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// (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);
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__writeMemory32(0x2060BF09,0xFFFFFC28,"Memory");
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__sleep(10000);
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//* AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
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__writeMemory32(0x00000102,0xFFFFFC30,"Memory");
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__sleep(10000);
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}
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@ -0,0 +1,154 @@
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// ---------------------------------------------------------
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// ATMEL Microcontroller Software Support - ROUSSET -
|
||||
// ---------------------------------------------------------
|
||||
// The software is delivered "AS IS" without warranty or
|
||||
// condition of any kind, either express, implied or
|
||||
// statutory. This includes without limitation any warranty
|
||||
// or condition with respect to merchantability or fitness
|
||||
// for any particular purpose, or against the infringements of
|
||||
// intellectual property rights of others.
|
||||
// ---------------------------------------------------------
|
||||
// File: SAM9XE_SRAM.mac
|
||||
// User setup file for CSPY debugger.
|
||||
// 1.1 08/Aug/06 jpp : Creation
|
||||
//
|
||||
// $Revision: 23594 $
|
||||
//
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// ---------------------------------------------------------
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__var __mac_i;
|
||||
__var __mac_pt;
|
||||
|
||||
/*********************************************************************
|
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*
|
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* execUserReset() : JTAG set initially to Full Speed
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*/
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execUserReset()
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{
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__message "------------------------------ execUserReset ---------------------------------";
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_MapRAMAt0(); //* Set the RAM memory at 0x00200000 & 0x00000000
|
||||
__PllSetting(); //* Init PLL
|
||||
__PllSetting100MHz();
|
||||
__message "-------------------------------Set PC Reset ----------------------------------";
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* execUserPreload() : JTAG set initially to 32kHz
|
||||
*/
|
||||
execUserPreload()
|
||||
{
|
||||
__message "------------------------------ execUserPreload ---------------------------------";
|
||||
__hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
|
||||
__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
|
||||
__PllSetting(); //* Init PLL
|
||||
__PllSetting100MHz();
|
||||
_MapRAMAt0(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
|
||||
_InitRSTC(); //* Enable User Reset to allow execUserReset() execution
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* _InitRSTC()
|
||||
*
|
||||
* Function description
|
||||
* Initializes the RSTC (Reset controller).
|
||||
* This makes sense since the default is to not allow user resets, which makes it impossible to
|
||||
* apply a second RESET via J-Link
|
||||
*/
|
||||
_InitRSTC() {
|
||||
__writeMemory32(0xA5000001, 0xFFFFFD08,"Memory"); // Allow user reset
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* _MapRAMAt0()
|
||||
* Function description
|
||||
* Remap RAM at 0
|
||||
*/
|
||||
_MapRAMAt0()
|
||||
{
|
||||
// AT91C_MATRIX_MRCR ((AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register
|
||||
__mac_i=__readMemory32(0xFFFFEF00,"Memory");
|
||||
__message "----- AT91C_MATRIX_MRCR : 0x",__mac_i:%X;
|
||||
|
||||
if ( ((__mac_i & 0x01) == 0) || ((__mac_i & 0x02) == 0)){
|
||||
__message "------------------------------- The Remap is NOT & REMAP ----------------------------";
|
||||
__writeMemory32(0x00000003,0xFFFFEF00,"Memory");
|
||||
__mac_i=__readMemory32(0xFFFFEF00,"Memory");
|
||||
__message "----- AT91C_MATRIX_MRCR : 0x",__mac_i:%X;
|
||||
} else {
|
||||
__message "------------------------------- The Remap is done -----------------------------------";
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* __PllSetting()
|
||||
* Function description
|
||||
* Initializes the PMC.
|
||||
* 1. Enable the Main Oscillator
|
||||
* 2. Configure PLL
|
||||
* 3. Switch Master
|
||||
*/
|
||||
__PllSetting()
|
||||
{
|
||||
if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) {
|
||||
//* Disable all PMC interrupt ( $$ JPP)
|
||||
//* AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
|
||||
//* pPmc->PMC_IDR = 0xFFFFFFFF;
|
||||
__writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory");
|
||||
//* AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
|
||||
__writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory");
|
||||
// Disable all clock only Processor clock is enabled.
|
||||
__writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory");
|
||||
|
||||
// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
|
||||
__writeMemory32(0x00000001,0xFFFFFC30,"Memory");
|
||||
__sleep(10000);
|
||||
|
||||
// write reset value to PLLA and PLLB
|
||||
// AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
|
||||
__writeMemory32(0x00003F00,0xFFFFFC28,"Memory");
|
||||
|
||||
// AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
|
||||
__writeMemory32(0x00003F00,0xFFFFFC2C,"Memory");
|
||||
__sleep(10000);
|
||||
|
||||
__message "------------------------------- PLL Enable -----------------------------------------";
|
||||
} else {
|
||||
__message " ********* Core in SLOW CLOCK mode ********* "; }
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* __PllSetting100MHz()
|
||||
* Function description
|
||||
* Set core at 200 MHz and MCK at 100 MHz
|
||||
*/
|
||||
__PllSetting100MHz()
|
||||
{
|
||||
|
||||
__message "------------------------------- PLL Set at 100 MHz ----------------------------------";
|
||||
|
||||
//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
|
||||
__writeMemory32(0x00004001,0xFFFFFC20,"Memory");
|
||||
__sleep(10000);
|
||||
// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
|
||||
__writeMemory32(0x00000001,0xFFFFFC30,"Memory");
|
||||
__sleep(10000);
|
||||
//* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) |
|
||||
// (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);
|
||||
__writeMemory32(0x2060BF09,0xFFFFFC28,"Memory");
|
||||
__sleep(10000);
|
||||
//* AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
|
||||
__writeMemory32(0x00000102,0xFFFFFC30,"Memory");
|
||||
__sleep(10000);
|
||||
|
||||
}
|
||||
|
||||
@ -0,0 +1,46 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_SDRAM_end__ = 0x21FFFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_startup__ = 0x100;
|
||||
define symbol __ICFEDIT_size_vectors__ = 0x100;
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_svcstack__ = 0x60;
|
||||
define symbol __ICFEDIT_size_irqstack__ = 0x60;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x10000;
|
||||
/*-Exports-*/
|
||||
export symbol __ICFEDIT_region_SDRAM_start__;
|
||||
export symbol __ICFEDIT_region_SDRAM_end__;
|
||||
export symbol __ICFEDIT_region_RAM_start__;
|
||||
export symbol __ICFEDIT_region_RAM_end__;
|
||||
export symbol __ICFEDIT_size_startup__;
|
||||
export symbol __ICFEDIT_size_vectors__;
|
||||
export symbol __ICFEDIT_size_cstack__;
|
||||
export symbol __ICFEDIT_size_svcstack__;
|
||||
export symbol __ICFEDIT_size_irqstack__;
|
||||
export symbol __ICFEDIT_size_heap__;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region STA_region = mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__];
|
||||
define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__];
|
||||
define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
|
||||
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { section .vectors };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place in STA_region { section .cstartup };
|
||||
place in VEC_region { section .vectors };
|
||||
place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
|
||||
|
||||
Loading…
Reference in New Issue