diff --git a/Demo/ARM9_AT91SAM9XE_IAR/FreeRTOSConfig.h b/Demo/ARM9_AT91SAM9XE_IAR/FreeRTOSConfig.h index d6a191e58a..77712ffdd4 100644 --- a/Demo/ARM9_AT91SAM9XE_IAR/FreeRTOSConfig.h +++ b/Demo/ARM9_AT91SAM9XE_IAR/FreeRTOSConfig.h @@ -65,12 +65,12 @@ #define configUSE_PREEMPTION 1 #define configUSE_IDLE_HOOK 0 #define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 64000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 100 ) +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) BOARD_MCK ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) #define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 190 ) #define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40000 ) ) #define configMAX_TASK_NAME_LEN ( 12 ) -#define configUSE_TRACE_FACILITY 1 +#define configUSE_TRACE_FACILITY 0 #define configUSE_16_BIT_TICKS 0 #define configIDLE_SHOULD_YIELD 0 #define configUSE_CO_ROUTINES 0 diff --git a/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek-flash.mac b/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek-flash.mac new file mode 100644 index 0000000000..54a6f1e762 --- /dev/null +++ b/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek-flash.mac @@ -0,0 +1,131 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: SAM9XE_FLASH.mac +// User setup file for CSPY debugger. +// 1.1 08/Aug/06 jpp : Creation +// +// $Revision: 23594 $ +// +// --------------------------------------------------------- +__var __mac_i; +__var __mac_pt; + +/********************************************************************* +* +* execUserReset() : JTAG set initially to Full Speed +*/ +execUserReset() +{ + __message "------------------------------ execUserReset ---------------------------------"; + __writeMemory32(0x00000500, 0xFFFFFA00, "Memory"); // Set flash wait states + __PllSetting(); //* Init PLL + __PllSetting100MHz(); + __message "-------------------------------Set PC Reset ----------------------------------"; +} + +/********************************************************************* +* +* execUserPreload() : JTAG set initially to 32kHz +*/ +execUserPreload() +{ + __message "------------------------------ execUserPreload ---------------------------------"; + __hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz) + __writeMemory32(0xD3,0x98,"Register"); //* Set CPSR + __writeMemory32(0x00000500, 0xFFFFFA00, "Memory"); // Set flash wait states + __PllSetting(); //* Init PLL + __PllSetting100MHz(); + _InitRSTC(); //* Enable User Reset to allow execUserReset() execution +} + + + +/********************************************************************* +* +* _InitRSTC() +* +* Function description +* Initializes the RSTC (Reset controller). +* This makes sense since the default is to not allow user resets, which makes it impossible to +* apply a second RESET via J-Link +*/ +_InitRSTC() { + __writeMemory32(0xA5000001, 0xFFFFFD08,"Memory"); // Allow user reset +} + + + +/********************************************************************* +* +* __PllSetting() +* Function description +* Initializes the PMC. +* 1. Enable the Main Oscillator +* 2. Configure PLL +* 3. Switch Master +*/ +__PllSetting() +{ + if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) { +//* Disable all PMC interrupt ( $$ JPP) +//* AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register +//* pPmc->PMC_IDR = 0xFFFFFFFF; + __writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory"); +//* AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register + __writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory"); +// Disable all clock only Processor clock is enabled. + __writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory"); + +// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register + __writeMemory32(0x00000001,0xFFFFFC30,"Memory"); + __sleep(10000); + +// write reset value to PLLA and PLLB +// AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register + __writeMemory32(0x00003F00,0xFFFFFC28,"Memory"); + +// AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register + __writeMemory32(0x00003F00,0xFFFFFC2C,"Memory"); + __sleep(10000); + + __message "------------------------------- PLL Enable -----------------------------------------"; + } else { + __message " ********* Core in SLOW CLOCK mode ********* "; } +} + + +/********************************************************************* +* +* __PllSetting100MHz() +* Function description +* Set core at 200 MHz and MCK at 100 MHz +*/ +__PllSetting100MHz() +{ + + __message "------------------------------- PLL Set at 100 MHz ----------------------------------"; + +//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN )); + __writeMemory32(0x00004001,0xFFFFFC20,"Memory"); + __sleep(10000); +// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register + __writeMemory32(0x00000001,0xFFFFFC30,"Memory"); + __sleep(10000); +//* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) | +// (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9); + __writeMemory32(0x2060BF09,0xFFFFFC28,"Memory"); + __sleep(10000); +//* AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;; + __writeMemory32(0x00000102,0xFFFFFC30,"Memory"); + __sleep(10000); + +} + diff --git a/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek-sdram.mac b/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek-sdram.mac new file mode 100644 index 0000000000..b493dea6bf --- /dev/null +++ b/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek-sdram.mac @@ -0,0 +1,249 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: SAM9XE_SDRAM.mac +// User setup file for CSPY debugger. +// 1.1 08/Aug/06 jpp : Creation +// +// $Revision: 23594 $ +// +// --------------------------------------------------------- +__var __mac_i; +__var __mac_pt; + +/********************************************************************* +* +* execUserReset() : JTAG set initially to Full Speed +*/ +execUserReset() +{ + __message "------------------------------ execUserReset ---------------------------------"; + _MapRAMAt0(); //* Set the RAM memory at 0x00200000 & 0x00000000 + __PllSetting(); //* Init PLL + __PllSetting100MHz(); + __message "-------------------------------Set PC Reset ----------------------------------"; +} + +/********************************************************************* +* +* execUserPreload() : JTAG set initially to 32kHz +*/ +execUserPreload() +{ + __message "------------------------------ execUserPreload ---------------------------------"; + __hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz) + __writeMemory32(0xD3,0x98,"Register"); //* Set CPSR + __PllSetting(); //* Init PLL + __PllSetting100MHz(); + __initSDRAM(); //* Init SDRAM before load + _MapRAMAt0(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000 + _InitRSTC(); //* Enable User Reset to allow execUserReset() execution +} + + + +/********************************************************************* +* +* _InitRSTC() +* +* Function description +* Initializes the RSTC (Reset controller). +* This makes sense since the default is to not allow user resets, which makes it impossible to +* apply a second RESET via J-Link +*/ +_InitRSTC() { + __writeMemory32(0xA5000001, 0xFFFFFD08,"Memory"); // Allow user reset +} + + +/********************************************************************* +* +* __initSDRAM() +* Function description +* Set SDRAM for works at 100 MHz +*/ +__initSDRAM() +{ +//* Configure EBI Chip select +// pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC; +// AT91C_CCFG_EBICSA ((AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register + __writeMemory32(0x0001003A,0xFFFFEF1C,"Memory"); + + +//* Configure PIOs +//* AT91F_PIO_CfgPeriph( AT91C_BASE_PIOC, AT91C_PC16_D16 to AT91C_PC16_D31 +// pPio->PIO_ASR = periphAEnable; AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register +// pPio->PIO_BSR = periphBEnable;AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register +// pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode + __writeMemory32(0xFFFF0000,0xFFFFF870,"Memory"); + __writeMemory32(0x00000000,0xFFFFF874,"Memory"); + __writeMemory32(0xFFFF0000,0xFFFFF804,"Memory"); + +//* psdrc->SDRAMC_CR = AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 | +// AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 | +// AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 ; + __writeMemory32(0x85227279,0xFFFFEA08,"Memory"); + __sleep(100); +//* psdrc->SDRAMC_MR = 0x00000002; // Set PRCHG AL + __writeMemory32(0x00000002,0xFFFFEA00,"Memory"); +//* *AT91C_SDRAM = 0x00000000; // Perform PRCHG + __writeMemory32(0x00000000,0x20000000,"Memory"); + __sleep(100); + + +//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR + __writeMemory32(0x00000004,0xFFFFEA00,"Memory"); + +//* *(AT91C_SDRAM+4) = 0x00000001; // Perform CBR + __writeMemory32(0x00000001,0x20000010,"Memory"); + +//* psdrc->SDRAMC_MR = 0x00000004; // Set 2 CBR + __writeMemory32(0x00000004,0xFFFFEA00,"Memory"); +//* *(AT91C_SDRAM+8) = 0x00000002; // Perform CBR + __writeMemory32(0x00000002,0x20000020,"Memory"); + +//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 3 CBR + __writeMemory32(0x00000004,0xFFFFEA00,"Memory"); +//* *(AT91C_SDRAM+0xc) = 0x00000003; // Perform CBR + __writeMemory32(0x00000003,0x20000030,"Memory"); + +//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 4 CBR + __writeMemory32(0x00000004,0xFFFFEA00,"Memory"); +//* *(AT91C_SDRAM+0x10) = 0x00000004; // Perform CBR + __writeMemory32(0x00000004,0x20000040,"Memory"); + +//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 5 CBR + __writeMemory32(0x00000004,0xFFFFEA00,"Memory"); +//* *(AT91C_SDRAM+0x14) = 0x00000005; // Perform CBR + __writeMemory32(0x00000005,0x20000050,"Memory"); + +//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 6 CBR + __writeMemory32(0x00000004,0xFFFFEA00,"Memory"); +//* *(AT91C_SDRAM+0x18) = 0x00000006; // Perform CBR + __writeMemory32(0x00000006,0x20000060,"Memory"); + +//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 7 CBR + __writeMemory32(0x00000004,0xFFFFEA00,"Memory"); +//* *(AT91C_SDRAM+0x1c) = 0x00000007; // Perform CBR + __writeMemory32(0x00000007,0x20000070,"Memory"); + +//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 8 CBR + __writeMemory32(0x00000004,0xFFFFEA00,"Memory"); +//* *(AT91C_SDRAM+0x20) = 0x00000008; // Perform CBR + __writeMemory32(0x00000008,0x20000080,"Memory"); + +//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_LMR_CMD; // Set LMR operation + __writeMemory32(0x00000003,0xFFFFEA00,"Memory"); +//* *(AT91C_SDRAM+0x24) = 0xcafedede; // Perform LMR burst=1, lat=2 + __writeMemory32(0xCAFEDEDE,0x20000090,"Memory"); + +//* psdrc->SDRAMC_TR = (AT91C_MASTER_CLOCK * 7)/1000000; // Set Refresh Timer 390 for 25MHz (TR= 15.6 * F ) +// // (F : system clock freq. MHz + + __writeMemory32(0x000002B9,0xFFFFEA04,"Memory"); + +//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_NORMAL_CMD; // Set Normal mode + __writeMemory32(0x00000000,0xFFFFEA00,"Memory"); + +//* *AT91C_SDRAM = 0x00000000; // Perform Normal mode + __writeMemory32(0x00000000,0x20000000,"Memory"); + __message "------------------------------- SDRAM Done at 100 MHz -------------------------------"; + +} + +/********************************************************************* +* +* _MapRAMAt0() +* Function description +* Remap RAM at 0 +*/ +_MapRAMAt0() +{ +// AT91C_MATRIX_MRCR ((AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register + __mac_i=__readMemory32(0xFFFFEF00,"Memory"); + __message "----- AT91C_MATRIX_MRCR : 0x",__mac_i:%X; + + if ( ((__mac_i & 0x01) == 0) || ((__mac_i & 0x02) == 0)){ + __message "------------------------------- The Remap is NOT & REMAP ----------------------------"; + __writeMemory32(0x00000003,0xFFFFEF00,"Memory"); + __mac_i=__readMemory32(0xFFFFEF00,"Memory"); + __message "----- AT91C_MATRIX_MRCR : 0x",__mac_i:%X; + } else { + __message "------------------------------- The Remap is done -----------------------------------"; + } +} + + +/********************************************************************* +* +* __PllSetting() +* Function description +* Initializes the PMC. +* 1. Enable the Main Oscillator +* 2. Configure PLL +* 3. Switch Master +*/ +__PllSetting() +{ + if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) { +//* Disable all PMC interrupt ( $$ JPP) +//* AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register +//* pPmc->PMC_IDR = 0xFFFFFFFF; + __writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory"); +//* AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register + __writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory"); +// Disable all clock only Processor clock is enabled. + __writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory"); + +// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register + __writeMemory32(0x00000001,0xFFFFFC30,"Memory"); + __sleep(10000); + +// write reset value to PLLA and PLLB +// AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register + __writeMemory32(0x00003F00,0xFFFFFC28,"Memory"); + +// AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register + __writeMemory32(0x00003F00,0xFFFFFC2C,"Memory"); + __sleep(10000); + + __message "------------------------------- PLL Enable -----------------------------------------"; + } else { + __message " ********* Core in SLOW CLOCK mode ********* "; } +} + + +/********************************************************************* +* +* __PllSetting100MHz() +* Function description +* Set core at 200 MHz and MCK at 100 MHz +*/ +__PllSetting100MHz() +{ + + __message "------------------------------- PLL Set at 100 MHz ----------------------------------"; + +//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN )); + __writeMemory32(0x00004001,0xFFFFFC20,"Memory"); + __sleep(10000); +// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register + __writeMemory32(0x00000001,0xFFFFFC30,"Memory"); + __sleep(10000); +//* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) | +// (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9); + __writeMemory32(0x2060BF09,0xFFFFFC28,"Memory"); + __sleep(10000); +//* AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;; + __writeMemory32(0x00000102,0xFFFFFC30,"Memory"); + __sleep(10000); + +} + diff --git a/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek-sram.mac b/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek-sram.mac new file mode 100644 index 0000000000..c23e7f9368 --- /dev/null +++ b/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek-sram.mac @@ -0,0 +1,154 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: SAM9XE_SRAM.mac +// User setup file for CSPY debugger. +// 1.1 08/Aug/06 jpp : Creation +// +// $Revision: 23594 $ +// +// --------------------------------------------------------- +__var __mac_i; +__var __mac_pt; + +/********************************************************************* +* +* execUserReset() : JTAG set initially to Full Speed +*/ +execUserReset() +{ + __message "------------------------------ execUserReset ---------------------------------"; + _MapRAMAt0(); //* Set the RAM memory at 0x00200000 & 0x00000000 + __PllSetting(); //* Init PLL + __PllSetting100MHz(); + __message "-------------------------------Set PC Reset ----------------------------------"; +} + +/********************************************************************* +* +* execUserPreload() : JTAG set initially to 32kHz +*/ +execUserPreload() +{ + __message "------------------------------ execUserPreload ---------------------------------"; + __hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz) + __writeMemory32(0xD3,0x98,"Register"); //* Set CPSR + __PllSetting(); //* Init PLL + __PllSetting100MHz(); + _MapRAMAt0(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000 + _InitRSTC(); //* Enable User Reset to allow execUserReset() execution +} + + + +/********************************************************************* +* +* _InitRSTC() +* +* Function description +* Initializes the RSTC (Reset controller). +* This makes sense since the default is to not allow user resets, which makes it impossible to +* apply a second RESET via J-Link +*/ +_InitRSTC() { + __writeMemory32(0xA5000001, 0xFFFFFD08,"Memory"); // Allow user reset +} + + + +/********************************************************************* +* +* _MapRAMAt0() +* Function description +* Remap RAM at 0 +*/ +_MapRAMAt0() +{ +// AT91C_MATRIX_MRCR ((AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register + __mac_i=__readMemory32(0xFFFFEF00,"Memory"); + __message "----- AT91C_MATRIX_MRCR : 0x",__mac_i:%X; + + if ( ((__mac_i & 0x01) == 0) || ((__mac_i & 0x02) == 0)){ + __message "------------------------------- The Remap is NOT & REMAP ----------------------------"; + __writeMemory32(0x00000003,0xFFFFEF00,"Memory"); + __mac_i=__readMemory32(0xFFFFEF00,"Memory"); + __message "----- AT91C_MATRIX_MRCR : 0x",__mac_i:%X; + } else { + __message "------------------------------- The Remap is done -----------------------------------"; + } +} + + +/********************************************************************* +* +* __PllSetting() +* Function description +* Initializes the PMC. +* 1. Enable the Main Oscillator +* 2. Configure PLL +* 3. Switch Master +*/ +__PllSetting() +{ + if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) { +//* Disable all PMC interrupt ( $$ JPP) +//* AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register +//* pPmc->PMC_IDR = 0xFFFFFFFF; + __writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory"); +//* AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register + __writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory"); +// Disable all clock only Processor clock is enabled. + __writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory"); + +// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register + __writeMemory32(0x00000001,0xFFFFFC30,"Memory"); + __sleep(10000); + +// write reset value to PLLA and PLLB +// AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register + __writeMemory32(0x00003F00,0xFFFFFC28,"Memory"); + +// AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register + __writeMemory32(0x00003F00,0xFFFFFC2C,"Memory"); + __sleep(10000); + + __message "------------------------------- PLL Enable -----------------------------------------"; + } else { + __message " ********* Core in SLOW CLOCK mode ********* "; } +} + + +/********************************************************************* +* +* __PllSetting100MHz() +* Function description +* Set core at 200 MHz and MCK at 100 MHz +*/ +__PllSetting100MHz() +{ + + __message "------------------------------- PLL Set at 100 MHz ----------------------------------"; + +//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN )); + __writeMemory32(0x00004001,0xFFFFFC20,"Memory"); + __sleep(10000); +// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register + __writeMemory32(0x00000001,0xFFFFFC30,"Memory"); + __sleep(10000); +//* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) | +// (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9); + __writeMemory32(0x2060BF09,0xFFFFFC28,"Memory"); + __sleep(10000); +//* AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;; + __writeMemory32(0x00000102,0xFFFFFC30,"Memory"); + __sleep(10000); + +} + diff --git a/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek.ewd b/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek.ewd index 1f004b52aa..0472a5f736 100644 --- a/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek.ewd +++ b/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek.ewd @@ -559,6 +559,19 @@ + + STLINK_ID + 2 + + 0 + 1 + 1 + + + THIRDPARTY_ID 2 @@ -1192,6 +1205,19 @@ + + STLINK_ID + 2 + + 0 + 1 + 1 + + + THIRDPARTY_ID 2 @@ -1825,6 +1851,19 @@ + + STLINK_ID + 2 + + 0 + 1 + 1 + + + THIRDPARTY_ID 2 @@ -2458,6 +2497,19 @@ + + STLINK_ID + 2 + + 0 + 1 + 1 + + + THIRDPARTY_ID 2 @@ -3091,6 +3143,19 @@ + + STLINK_ID + 2 + + 0 + 1 + 1 + + + THIRDPARTY_ID 2 @@ -3724,6 +3789,19 @@ + + STLINK_ID + 2 + + 0 + 1 + 1 + + + THIRDPARTY_ID 2 @@ -3835,7 +3913,7 @@ + + STLINK_ID + 2 + + 0 + 1 + 1 + + + THIRDPARTY_ID 2 @@ -4468,7 +4559,7 @@ + + STLINK_ID + 2 + + 0 + 1 + 1 + + + THIRDPARTY_ID 2 @@ -5101,7 +5205,7 @@ + + STLINK_ID + 2 + + 0 + 1 + 1 + + + THIRDPARTY_ID 2 diff --git a/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek.ewp b/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek.ewp index 439c355320..32b24f372f 100644 --- a/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek.ewp +++ b/Demo/ARM9_AT91SAM9XE_IAR/ewp/at91sam9xe-ek.ewp @@ -12,7 +12,7 @@ General 3 - 16 + 17 1 1 + + ICCARM 2 - 20 + 21 1 1 + @@ -546,7 +560,7 @@ ILINK 0 - 6 + 7 1 1 + @@ -795,7 +813,7 @@ General 3 - 16 + 17 1 1 + + ICCARM 2 - 20 + 21 1 1 + @@ -1329,7 +1361,7 @@ ILINK 0 - 6 + 7 1 1 + @@ -1578,7 +1614,7 @@ General 3 - 16 + 17 1 1 + + ICCARM 2 - 20 + 21 1 1 + @@ -2112,7 +2162,7 @@ ILINK 0 - 6 + 7 1 1 + @@ -2361,7 +2415,7 @@ General 3 - 16 + 17 1 1 + + ICCARM 2 - 20 + 21 1 1 + @@ -2895,7 +2963,7 @@ ILINK 0 - 6 + 7 1 1 + @@ -3144,7 +3216,7 @@ General 3 - 16 + 17 1 1 + + ICCARM 2 - 20 + 21 1 1 + @@ -3678,7 +3764,7 @@ ILINK 0 - 6 + 7 1 1 + @@ -3927,7 +4017,7 @@ General 3 - 16 + 17 1 1 + + ICCARM 2 - 20 + 21 1 1 + @@ -4461,7 +4565,7 @@ ILINK 0 - 6 + 7 1 1 + @@ -4710,7 +4818,7 @@ General 3 - 16 + 17 1 1 + + ICCARM 2 - 20 + 21 1 1 + @@ -5245,7 +5367,7 @@ ILINK 0 - 6 + 7 1 1 + @@ -5494,7 +5620,7 @@ General 3 - 16 + 17 1 1 + + ICCARM 2 - 20 + 21 1 1 + @@ -6028,7 +6169,7 @@ ILINK 0 - 6 + 7 1 1 + @@ -6277,7 +6422,7 @@ General 3 - 16 + 17 1 1 + + ICCARM 2 - 20 + 21 1 1 + @@ -6811,7 +6971,7 @@ ILINK 0 - 6 + 7 1 1 + diff --git a/Demo/ARM9_AT91SAM9XE_IAR/ewp/sdram.icf b/Demo/ARM9_AT91SAM9XE_IAR/ewp/sdram.icf new file mode 100644 index 0000000000..4fdb258191 --- /dev/null +++ b/Demo/ARM9_AT91SAM9XE_IAR/ewp/sdram.icf @@ -0,0 +1,46 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_SDRAM_end__ = 0x21FFFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x300000; +define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_startup__ = 0x100; +define symbol __ICFEDIT_size_vectors__ = 0x100; +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_svcstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x10000; +/*-Exports-*/ +export symbol __ICFEDIT_region_SDRAM_start__; +export symbol __ICFEDIT_region_SDRAM_end__; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_startup__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_svcstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region STA_region = mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__]; +define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__]; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { section .vectors }; +do not initialize { section .noinit }; + +place in STA_region { section .cstartup }; +place in VEC_region { section .vectors }; +place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP }; + diff --git a/Demo/ARM9_AT91SAM9XE_IAR/ewp/settings/at91sam9xe-ek.cspy.bat b/Demo/ARM9_AT91SAM9XE_IAR/ewp/settings/at91sam9xe-ek.cspy.bat index 4784cbeee8..4c0321479c 100644 --- a/Demo/ARM9_AT91SAM9XE_IAR/ewp/settings/at91sam9xe-ek.cspy.bat +++ b/Demo/ARM9_AT91SAM9XE_IAR/ewp/settings/at91sam9xe-ek.cspy.bat @@ -22,11 +22,11 @@ @REM but they are listed at the end of this file for reference. -"C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\bin\cspybat" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\armproc.dll" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\armjlink.dll" %1 --plugin "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\" --macro "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\ARM9_AT91SAM9XE_IAR\ewp\..\..\..\resources\at91sam9xe-ek-flash.mac" --backend -B "--endian=little" "--cpu=ARM926EJ-S" "--fpu=None" "-p" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\CONFIG\debugger\Atmel\ioAT91SAM9XE512.ddf" "--drv_verify_download" "--semihosting" "--device=AT91SAM9XE512" "-d" "jlink" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--drv_catch_exceptions=0x000" "--jlink_reset_strategy=50,0" +"C:\Devtools\IAR Systems\Embedded Workbench 5.3-EWARM-5.30.0.1162-BETA\common\bin\cspybat" "C:\Devtools\IAR Systems\Embedded Workbench 5.3-EWARM-5.30.0.1162-BETA\arm\bin\armproc.dll" "C:\Devtools\IAR Systems\Embedded Workbench 5.3-EWARM-5.30.0.1162-BETA\arm\bin\armjlink.dll" %1 --plugin "C:\Devtools\IAR Systems\Embedded Workbench 5.3-EWARM-5.30.0.1162-BETA\arm\bin\" --macro "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\ARM9_AT91SAM9XE_IAR\ewp\at91sam9xe-ek-sdram.mac" --backend -B "--endian=little" "--cpu=ARM926EJ-S" "--fpu=None" "-p" "C:\Devtools\IAR Systems\Embedded Workbench 5.3-EWARM-5.30.0.1162-BETA\arm\CONFIG\debugger\Atmel\ioAT91SAM9XE512.ddf" "--drv_verify_download" "--semihosting=none" "--device=AT91SAM9XE512" "-d" "jlink" "--drv_communication=USB0" "--jlink_speed=adaptive" "--drv_catch_exceptions=0x000" @REM Loaded plugins: -@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\armlibsupport.dll -@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\CodeCoverage\CodeCoverage.dll -@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\stack\stack.dll -@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\SymList\SymList.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 5.3-EWARM-5.30.0.1162-BETA\arm\bin\armlibsupport.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 5.3-EWARM-5.30.0.1162-BETA\common\plugins\CodeCoverage\CodeCoverage.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 5.3-EWARM-5.30.0.1162-BETA\common\plugins\stack\stack.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 5.3-EWARM-5.30.0.1162-BETA\common\plugins\SymList\SymList.dll diff --git a/Demo/ARM9_AT91SAM9XE_IAR/ewp/settings/at91sam9xe-ek.dbgdt b/Demo/ARM9_AT91SAM9XE_IAR/ewp/settings/at91sam9xe-ek.dbgdt index 22d6b995e1..4bddf5882a 100644 --- a/Demo/ARM9_AT91SAM9XE_IAR/ewp/settings/at91sam9xe-ek.dbgdt +++ b/Demo/ARM9_AT91SAM9XE_IAR/ewp/settings/at91sam9xe-ek.dbgdt @@ -3,7 +3,7 @@ - + 201342 20 1216 @@ -12,19 +12,22 @@ - 124 - 27 - 27 - 27 - + + + + + 290272727 - 1 - 0 - + + + 200100 - + + + + TabID-27883-8575 @@ -39,175 +42,33 @@ - 0 - - + + 0 TabID-5864-8578 Workspace Workspace - - at91sam9xe-ek - - + + at91sam9xe-ek - 0 - - - - - TabID-16612-8582 - Disassembly - Disassembly - - - - 0 - - + + 0 - - - TextEditor - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\Common\drivers\Atmel\at91lib\boards\at91sam9xe-ek\board_cstartup_iar.s - 0 - 125 - 4609 - 4609 - - - TextEditor - C:\E\Dev\FreeRTOS\WorkingCopy3\Source\portable\IAR\AtmelSAM9XE\port.c - 0 - 178 - 7138 - 7138 - - - TextEditor - C:\E\Dev\FreeRTOS\WorkingCopy3\Source\portable\IAR\AtmelSAM9XE\portasm.s79 - 0 - 17 - 1072 - 1072 - - - TextEditor - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\ARM9_AT91SAM9XE_IAR\ParTest\ParTest.c - 0 - 58 - 2678 - 2701 - - 3 - - TextEditor - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\Common\drivers\Atmel\at91lib\utility\led.c - 0 - 92 - 2663 - 2663 - - - 0 - - - 1000000 - 1000000 - - - 1 - + + + + + TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\ARM9_AT91SAM9XE_IAR\main.c07437723772TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\ARM9_AT91SAM9XE_IAR\ParTest\ParTest.c04529692976TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Source\tasks.c017345434454344TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\ARM9_AT91SAM9XE_IAR\FreeRTOSConfig.h06330043004TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\Common\drivers\Atmel\at91lib\boards\at91sam9xe-ek\board_cstartup_iar.s09840274027TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\Common\drivers\Atmel\at91lib\boards\at91sam9xe-ek\board_lowlevel.c07539133913TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Source\portable\MemMang\heap_3.c05329802980TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Source\portable\IAR\AtmelSAM9XE\port.c020478297829TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Source\portable\IAR\AtmelSAM9XE\portasm.s7905435435TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\Common\Minimal\flash.c09047914791TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\Common\drivers\Atmel\at91lib\peripherals\pit\pit.c04831573157TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\Common\drivers\Atmel\at91lib\boards\at91sam9xe-ek\board.h01867460746711TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\Common\drivers\Atmel\at91lib\utility\led.c079312331320100000010000001 - - - - - iaridepm.enu1 - - - - - - - debuggergui.enu1 - - - - - - - - - - -2 - -2 - 716 - 198 - -2 - -2 - 200 - 200 - 119048 - 203666 - 119048 - 731161 - - - - - - - - - - - -2 - -2 - 716 - 198 - -2 - -2 - 200 - 200 - 119048 - 203666 - 119048 - 731161 - - - - - - - - - - - -2 - -2 - 198 - 1682 - -2 - -2 - 1684 - 200 - 1002381 - 203666 - 119048 - 203666 - - - - - - - - - + + + + + + iaridepm.enu1debuggergui.enu1-2-2740364-2-2167200119286203666261429755601-2-21981402-2-214042001002857203666119286203666 diff --git a/Demo/ARM9_AT91SAM9XE_IAR/ewp/settings/at91sam9xe-ek.dni b/Demo/ARM9_AT91SAM9XE_IAR/ewp/settings/at91sam9xe-ek.dni index fadd9a7871..903e2f92ad 100644 --- a/Demo/ARM9_AT91SAM9XE_IAR/ewp/settings/at91sam9xe-ek.dni +++ b/Demo/ARM9_AT91SAM9XE_IAR/ewp/settings/at91sam9xe-ek.dni @@ -17,6 +17,10 @@ UseTrigger=1 TriggerName=main LimitSize=0 ByteLimit=50 +[DebugChecksum] +Checksum=-542088010 +[InstructionProfiling] +Enabled=_ 0 [Log file] LoggingEnabled=_ 0 LogFile=_ "" @@ -24,10 +28,15 @@ Category=_ 0 [TermIOLog] LoggingEnabled=_ 0 LogFile=_ "" +[DriverProfiling] +Enabled=0 +Source=2 +Graph=0 [Disassemble mode] mode=0 [Breakpoints] -Count=0 +Bp0=_ "STD_CODE" "{C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\ARM9_AT91SAM9XE_IAR\main.c}.96.2@1" 1 0 0 0 "" 0 "" 0 +Count=1 [TraceHelper] Enabled=0 ShowSource=1 diff --git a/Demo/ARM9_AT91SAM9XE_IAR/settings/rtosdemo.wsdt b/Demo/ARM9_AT91SAM9XE_IAR/settings/rtosdemo.wsdt index c4c8326479..2b39a96851 100644 --- a/Demo/ARM9_AT91SAM9XE_IAR/settings/rtosdemo.wsdt +++ b/Demo/ARM9_AT91SAM9XE_IAR/settings/rtosdemo.wsdt @@ -3,7 +3,7 @@ - at91sam9xe-ek/at91sam9xe512_flash + at91sam9xe-ek/at91sam9xe512_sdram @@ -12,7 +12,7 @@ - 258272727 + 242272727 @@ -20,7 +20,7 @@ 20121632481 - + 181344 @@ -32,7 +32,7 @@ Workspace - at91sam9xe-ek + at91sam9xe-ekat91sam9xe-ek/main.cat91sam9xe-ek/scheduler_source @@ -52,14 +52,14 @@ - TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\ARM9_AT91SAM9XE_IAR\main.c000000100000010000001 + TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\ARM9_AT91SAM9XE_IAR\main.c07437723772TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\ARM9_AT91SAM9XE_IAR\ParTest\ParTest.c04529692976TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Source\tasks.c017345434454344TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\ARM9_AT91SAM9XE_IAR\FreeRTOSConfig.h06330043004TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\Common\drivers\Atmel\at91lib\boards\at91sam9xe-ek\board_cstartup_iar.s09840274027TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\Common\drivers\Atmel\at91lib\boards\at91sam9xe-ek\board_lowlevel.c07539133913TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Source\portable\MemMang\heap_3.c05329802980TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Source\portable\IAR\AtmelSAM9XE\port.c020478297829TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Source\portable\IAR\AtmelSAM9XE\portasm.s7905435435TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\Common\Minimal\flash.c09047914791TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\Common\drivers\Atmel\at91lib\peripherals\pit\pit.c04831573157TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\Common\drivers\Atmel\at91lib\boards\at91sam9xe-ek\board.h01867460746711TextEditorC:\E\Dev\FreeRTOS\WorkingCopy3\Demo\Common\drivers\Atmel\at91lib\utility\led.c079312331320100000010000001 - iaridepm.enu1-2-2592332-2-2200200142857203666238571604888-2-23461402-2-214043481002857354379142857203666 + iaridepm.enu1-2-2592332-2-2200200142857203666238571604888-2-23461402-2-214043481002857354379142857203666