Remove PPC files that are in the EDK V7 format.
Richard Barry
17 years ago
parent
3fd422ff2f
commit
c2a6dc193e
@ -1,97 +0,0 @@
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/*
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FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
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This file is part of the FreeRTOS.org distribution.
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FreeRTOS.org is free software; you can redistribute it and/or modify
|
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it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
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FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
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||||
|
||||
***************************************************************************
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||||
***************************************************************************
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||||
* *
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||||
* SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
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||||
* and even write all or part of your application on your behalf. *
|
||||
* See http://www.OpenRTOS.com for details of the services we provide to *
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||||
* expedite your project. *
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* *
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***************************************************************************
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***************************************************************************
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Please ensure to read the configuration and relevant port sections of the
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||||
online documentation.
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|
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http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
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||||
|
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http://www.SafeRTOS.com - A version that is certified for use in safety
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||||
critical systems.
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||||
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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#ifndef FREERTOS_CONFIG_H
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#define FREERTOS_CONFIG_H
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/*-----------------------------------------------------------
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* Application specific definitions.
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*
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* These definitions should be adjusted for your particular hardware and
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* application requirements.
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*
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* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
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* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
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*----------------------------------------------------------*/
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#define configUSE_PREEMPTION 1
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#define configUSE_IDLE_HOOK 0
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#define configUSE_TICK_HOOK 0
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#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 250 )
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#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 100000000 ) /* Clock setup from start.asm in the demo application. */
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#define configTICK_RATE_HZ ( (portTickType) 1000 )
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#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 )
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#define configTOTAL_HEAP_SIZE ( (size_t) (80 * 1024) )
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#define configMAX_TASK_NAME_LEN ( 20 )
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#define configUSE_16_BIT_TICKS 1
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#define configIDLE_SHOULD_YIELD 1
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#define configUSE_MUTEXES 1
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#define configUSE_TRACE_FACILITY 0
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#define configCHECK_FOR_STACK_OVERFLOW 2
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/* Co-routine definitions. */
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#define configUSE_CO_ROUTINES 0
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#define configMAX_CO_ROUTINE_PRIORITIES ( 4 )
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/* Set the following definitions to 1 to include the API function, or zero
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to exclude the API function. */
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#define INCLUDE_vTaskPrioritySet 1
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#define INCLUDE_uxTaskPriorityGet 1
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#define INCLUDE_vTaskDelete 1
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#define INCLUDE_vTaskCleanUpResources 1
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#define INCLUDE_vTaskSuspend 1
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#define INCLUDE_vResumeFromISR 1
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#define INCLUDE_vTaskDelayUntil 1
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#define INCLUDE_vTaskDelay 1
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#define INCLUDE_xTaskGetSchedulerState 1
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#define INCLUDE_xTaskGetCurrentTaskHandle 1
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#define INCLUDE_uxTaskGetStackHighWaterMark 1
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#endif /* FREERTOS_CONFIG_H */
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@ -1,203 +0,0 @@
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/*******************************************************************/
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/* */
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/* This file is automatically generated by linker script generator.*/
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/* */
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/* Version: Xilinx EDK 8.2.02EDK_Im_Sp2.4 */
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/* */
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/* Copyright (c) 2004 Xilinx, Inc. All rights reserved. */
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/* */
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/* Description : PowerPC405 Linker Script */
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/* */
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/*******************************************************************/
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_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
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_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
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/* Define Memories in the system */
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MEMORY
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{
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SRAM_256Kx32_C_MEM0_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00100000
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plb_bram_if_cntlr_1 : ORIGIN = 0xFFFFF000, LENGTH = 0x00001000
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}
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/* Specify the default entry point to the program */
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ENTRY(_boot)
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STARTUP(boot.o)
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/* Define the sections, and where they are mapped in memory */
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SECTIONS
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{
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.vectors : {
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__vectors_start = .;
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*(.vectors)
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__vectors_end = .;
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.text : {
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*(.text)
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*(.text.*)
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*(.gnu.linkonce.t.*)
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.init : {
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KEEP (*(.init))
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.fini : {
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KEEP (*(.fini))
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.rodata : {
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__rodata_start = .;
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*(.rodata)
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*(.rodata.*)
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*(.gnu.linkonce.r.*)
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__rodata_end = .;
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.sdata2 : {
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__sdata2_start = .;
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*(.sdata2)
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*(.gnu.linkonce.s2.*)
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__sdata2_end = .;
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.sbss2 : {
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__sbss2_start = .;
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*(.sbss2)
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*(.gnu.linkonce.sb2.*)
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__sbss2_end = .;
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.data : {
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__data_start = .;
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d.*)
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__data_end = .;
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.got : {
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*(.got)
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.got1 : {
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*(.got1)
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.got2 : {
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*(.got2)
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.ctors : {
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__CTOR_LIST__ = .;
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___CTORS_LIST___ = .;
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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__CTOR_END__ = .;
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___CTORS_END___ = .;
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.dtors : {
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__DTOR_LIST__ = .;
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___DTORS_LIST___ = .;
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KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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__DTOR_END__ = .;
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___DTORS_END___ = .;
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.fixup : {
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__fixup_start = .;
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*(.fixup)
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__fixup_end = .;
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.eh_frame : {
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*(.eh_frame)
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.jcr : {
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*(.jcr)
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.gcc_except_table : {
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*(.gcc_except_table)
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.sdata : {
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__sdata_start = .;
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*(.sdata)
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*(.gnu.linkonce.s.*)
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__sdata_end = .;
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.sbss : {
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__sbss_start = .;
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*(.sbss)
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*(.gnu.linkonce.sb.*)
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*(.scommon)
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__sbss_end = .;
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.tdata : {
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__tdata_start = .;
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*(.tdata)
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*(.gnu.linkonce.td.*)
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__tdata_end = .;
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.tbss : {
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__tbss_start = .;
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*(.tbss)
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*(.gnu.linkonce.tb.*)
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__tbss_end = .;
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.bss : {
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__bss_start = .;
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*(.bss)
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*(.gnu.linkonce.b.*)
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||||
*(COMMON)
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. = ALIGN(4);
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__bss_end = .;
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.boot0 : {
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__boot0_start = .;
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*(.boot0)
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__boot0_end = .;
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} > plb_bram_if_cntlr_1
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.boot 0xFFFFFFFC : {
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__boot_start = .;
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*(.boot)
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__boot_end = .;
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||||
}
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||||
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/* Generate Stack and Heap Sections */
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.stack : {
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_stack_end = .;
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. += _STACK_SIZE;
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. = ALIGN(16);
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__stack = .;
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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.heap : {
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. = ALIGN(16);
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_heap_start = .;
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. += _HEAP_SIZE;
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. = ALIGN(16);
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_heap_end = .;
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} > SRAM_256Kx32_C_MEM0_BASEADDR
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}
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@ -1,653 +0,0 @@
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/*
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FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
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This file is part of the FreeRTOS.org distribution.
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FreeRTOS.org is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
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||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
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||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
***************************************************************************
|
||||
* *
|
||||
* SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
|
||||
* and even write all or part of your application on your behalf. *
|
||||
* See http://www.OpenRTOS.com for details of the services we provide to *
|
||||
* expedite your project. *
|
||||
* *
|
||||
***************************************************************************
|
||||
***************************************************************************
|
||||
|
||||
Please ensure to read the configuration and relevant port sections of the
|
||||
online documentation.
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
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/*
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* Creates all the demo application tasks, then starts the scheduler. The WEB
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* documentation provides more details of the demo application tasks.
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*
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* In addition to the standard demo tasks, the follow demo specific tasks are
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* create:
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*
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* The "Check" task. This only executes every three seconds but has the highest
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* priority so is guaranteed to get processor time. Its main function is to
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* check that all the other tasks are still operational. Most tasks maintain
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* a unique count that is incremented each time the task successfully completes
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* its function. Should any error occur within such a task the count is
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* permanently halted. The check task inspects the count of each task to ensure
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* it has changed since the last time the check task executed. If all the count
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* variables have changed all the tasks are still executing error free, and the
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* check task toggles the onboard LED. Should any task contain an error at any time
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* the LED toggle rate will change from 3 seconds to 500ms.
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*
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* The "Register Check" tasks. These tasks fill the CPU registers with known
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* values, then check that each register still contains the expected value, the
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* discovery of an unexpected value being indicative of an error in the RTOS
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* context switch mechanism. The register check tasks operate at low priority
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* so are switched in and out frequently.
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*
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Xilinx library includes. */
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#include "xcache_l.h"
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#include "xintc.h"
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/* Demo application includes. */
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#include "flash.h"
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#include "integer.h"
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#include "comtest2.h"
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#include "semtest.h"
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#include "BlockQ.h"
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#include "dynamic.h"
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#include "flop.h"
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#include "GenQTest.h"
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#include "QPeek.h"
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#include "blocktim.h"
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#include "death.h"
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#include "partest.h"
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/* Priorities assigned to the demo tasks. */
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#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
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#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 3 )
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#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
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#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 2 )
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#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 )
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#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
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#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY )
|
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/* The first LED used by the COM test and check tasks respectively. */
|
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#define mainCOM_TEST_LED ( 4 )
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#define mainCHECK_TEST_LED ( 3 )
|
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|
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/* The baud rate used by the comtest tasks is set by the hardware, so the
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baud rate parameters passed into the comtest initialisation has no effect. */
|
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#define mainBAUD_SET_IN_HARDWARE ( 0 )
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/* Delay periods used by the check task. If no errors have been found then
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||||
the check LED will toggle every mainNO_ERROR_CHECK_DELAY milliseconds. If an
|
||||
error has been found at any time then the toggle rate will increase to
|
||||
mainERROR_CHECK_DELAY milliseconds. */
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#define mainNO_ERROR_CHECK_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS )
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#define mainERROR_CHECK_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
|
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/*
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* The tasks defined within this file - described within the comments at the
|
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* head of this page.
|
||||
*/
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static void prvRegTestTask1( void *pvParameters );
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static void prvRegTestTask2( void *pvParameters );
|
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static void prvErrorChecks( void *pvParameters );
|
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/*
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* Called by the 'check' task to inspect all the standard demo tasks within
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* the system, as described within the comments at the head of this page.
|
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*/
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static portSHORT prvCheckOtherTasksAreStillRunning( void );
|
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|
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/*
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* Perform any hardware initialisation required by the demo application.
|
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*/
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static void prvSetupHardware( void );
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|
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/*-----------------------------------------------------------*/
|
||||
|
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/* xRegTestStatus will get set to pdFAIL by the regtest tasks if they
|
||||
discover an unexpected value. */
|
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static unsigned portBASE_TYPE xRegTestStatus = pdPASS;
|
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|
||||
/* Counters used to ensure the regtest tasks are still running. */
|
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static volatile unsigned portLONG ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL;
|
||||
|
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/*-----------------------------------------------------------*/
|
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|
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int main( void )
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{
|
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/* Must be called prior to installing any interrupt handlers! */
|
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vPortSetupInterruptController();
|
||||
|
||||
/* In this case prvSetupHardware() just enables the caches and and
|
||||
configures the IO ports for the LED outputs. */
|
||||
prvSetupHardware();
|
||||
|
||||
/* Start the standard demo application tasks. Note that the baud rate used
|
||||
by the comtest tasks is set by the hardware, so the baud rate parameter
|
||||
passed has no effect. */
|
||||
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
|
||||
vStartIntegerMathTasks( tskIDLE_PRIORITY );
|
||||
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_SET_IN_HARDWARE, mainCOM_TEST_LED );
|
||||
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
|
||||
vStartBlockingQueueTasks ( mainQUEUE_BLOCK_PRIORITY );
|
||||
vStartDynamicPriorityTasks();
|
||||
vStartMathTasks( tskIDLE_PRIORITY );
|
||||
vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY );
|
||||
vStartQueuePeekTasks();
|
||||
vCreateBlockTimeTasks();
|
||||
|
||||
/* Create the tasks defined within this file. */
|
||||
xTaskCreate( prvRegTestTask1, "Regtest1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
|
||||
xTaskCreate( prvRegTestTask2, "Regtest2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
|
||||
xTaskCreate( prvErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
|
||||
|
||||
/* The suicide tasks must be started last as they record the number of other
|
||||
tasks that exist within the system. The value is then used to ensure at run
|
||||
time the number of tasks that exists is within expected bounds. */
|
||||
vCreateSuicidalTasks( mainDEATH_PRIORITY );
|
||||
|
||||
/* Now start the scheduler. Following this call the created tasks should
|
||||
be executing. */
|
||||
vTaskStartScheduler( );
|
||||
|
||||
/* vTaskStartScheduler() will only return if an error occurs while the
|
||||
idle task is being created. */
|
||||
for( ;; );
|
||||
|
||||
return 0;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static portSHORT prvCheckOtherTasksAreStillRunning( void )
|
||||
{
|
||||
portBASE_TYPE lReturn = pdPASS;
|
||||
static unsigned portLONG ulLastRegTest1Counter= 0UL, ulLastRegTest2Counter = 0UL;
|
||||
|
||||
/* The demo tasks maintain a count that increments every cycle of the task
|
||||
provided that the task has never encountered an error. This function
|
||||
checks the counts maintained by the tasks to ensure they are still being
|
||||
incremented. A count remaining at the same value between calls therefore
|
||||
indicates that an error has been detected. */
|
||||
|
||||
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
if( xAreComTestTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
if( xAreBlockingQueuesStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
if( xAreMathsTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
if( xIsCreateTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
if ( xAreQueuePeekTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
/* Have the register test tasks found any errors? */
|
||||
if( xRegTestStatus != pdPASS )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
/* Are the register test tasks still looping? */
|
||||
if( ulLastRegTest1Counter == ulRegTest1Counter )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
else
|
||||
{
|
||||
ulLastRegTest1Counter = ulRegTest1Counter;
|
||||
}
|
||||
|
||||
if( ulLastRegTest2Counter == ulRegTest2Counter )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
else
|
||||
{
|
||||
ulLastRegTest2Counter = ulRegTest2Counter;
|
||||
}
|
||||
|
||||
return lReturn;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvErrorChecks( void *pvParameters )
|
||||
{
|
||||
portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY, xLastExecutionTime;
|
||||
volatile unsigned portBASE_TYPE uxFreeStack;
|
||||
|
||||
/* This call is just to demonstrate the use of the function - nothing is
|
||||
done with the value. You would expect the stack high water mark to be
|
||||
lower (the function to return a larger value) here at function entry than
|
||||
later following calls to other functions. */
|
||||
uxFreeStack = uxTaskGetStackHighWaterMark( NULL );
|
||||
|
||||
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
|
||||
works correctly. */
|
||||
xLastExecutionTime = xTaskGetTickCount();
|
||||
|
||||
/* Cycle for ever, delaying then checking all the other tasks are still
|
||||
operating without error. */
|
||||
for( ;; )
|
||||
{
|
||||
/* Again just for demo purposes - uxFreeStack should have a lower value
|
||||
here than following the call to uxTaskGetStackHighWaterMark() on the
|
||||
task entry. */
|
||||
uxFreeStack = uxTaskGetStackHighWaterMark( NULL );
|
||||
|
||||
/* Wait until it is time to check again. The time we wait here depends
|
||||
on whether an error has been detected or not. When an error is
|
||||
detected the time is shortened resulting in a faster LED flash rate. */
|
||||
vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
|
||||
|
||||
/* See if the other tasks are all ok. */
|
||||
if( prvCheckOtherTasksAreStillRunning() != pdPASS )
|
||||
{
|
||||
/* An error occurred in one of the tasks so shorten the delay
|
||||
period - which has the effect of increasing the frequency of the
|
||||
LED toggle. */
|
||||
xDelayPeriod = mainERROR_CHECK_DELAY;
|
||||
}
|
||||
|
||||
/* Flash! */
|
||||
vParTestToggleLED( mainCHECK_TEST_LED );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvSetupHardware( void )
|
||||
{
|
||||
XCache_EnableICache( 0x80000000 );
|
||||
XCache_EnableDCache( 0x80000000 );
|
||||
|
||||
/* Setup the IO port for use with the LED outputs. */
|
||||
vParTestInitialise();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void prvRegTest1Pass( void )
|
||||
{
|
||||
/* Called from the inline assembler - this cannot be static
|
||||
otherwise it can get optimised away. */
|
||||
ulRegTest1Counter++;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void prvRegTest2Pass( void )
|
||||
{
|
||||
/* Called from the inline assembler - this cannot be static
|
||||
otherwise it can get optimised away. */
|
||||
ulRegTest2Counter++;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void prvRegTestFail( void )
|
||||
{
|
||||
/* Called from the inline assembler - this cannot be static
|
||||
otherwise it can get optimised away. */
|
||||
xRegTestStatus = pdFAIL;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvRegTestTask1( void *pvParameters )
|
||||
{
|
||||
/* The first register test task as described at the top of this file. The
|
||||
values used in the registers are different to those use in the second
|
||||
register test task. Also, unlike the second register test task, this task
|
||||
yields between setting the register values and subsequently checking the
|
||||
register values. */
|
||||
asm volatile
|
||||
(
|
||||
"RegTest1Start: \n\t" \
|
||||
" \n\t" \
|
||||
" li 0, 301 \n\t" \
|
||||
" mtspr 256, 0 #USPRG0 \n\t" \
|
||||
" li 0, 501 \n\t" \
|
||||
" mtspr 8, 0 #LR \n\t" \
|
||||
" li 0, 4 \n\t" \
|
||||
" mtspr 1, 0 #XER \n\t" \
|
||||
" \n\t" \
|
||||
" li 0, 1 \n\t" \
|
||||
" li 2, 2 \n\t" \
|
||||
" li 3, 3 \n\t" \
|
||||
" li 4, 4 \n\t" \
|
||||
" li 5, 5 \n\t" \
|
||||
" li 6, 6 \n\t" \
|
||||
" li 7, 7 \n\t" \
|
||||
" li 8, 8 \n\t" \
|
||||
" li 9, 9 \n\t" \
|
||||
" li 10, 10 \n\t" \
|
||||
" li 11, 11 \n\t" \
|
||||
" li 12, 12 \n\t" \
|
||||
" li 13, 13 \n\t" \
|
||||
" li 14, 14 \n\t" \
|
||||
" li 15, 15 \n\t" \
|
||||
" li 16, 16 \n\t" \
|
||||
" li 17, 17 \n\t" \
|
||||
" li 18, 18 \n\t" \
|
||||
" li 19, 19 \n\t" \
|
||||
" li 20, 20 \n\t" \
|
||||
" li 21, 21 \n\t" \
|
||||
" li 22, 22 \n\t" \
|
||||
" li 23, 23 \n\t" \
|
||||
" li 24, 24 \n\t" \
|
||||
" li 25, 25 \n\t" \
|
||||
" li 26, 26 \n\t" \
|
||||
" li 27, 27 \n\t" \
|
||||
" li 28, 28 \n\t" \
|
||||
" li 29, 29 \n\t" \
|
||||
" li 30, 30 \n\t" \
|
||||
" li 31, 31 \n\t" \
|
||||
" \n\t" \
|
||||
" sc \n\t" \
|
||||
" nop \n\t" \
|
||||
" \n\t" \
|
||||
" cmpwi 0, 1 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 2, 2 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 3, 3 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 4, 4 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 5, 5 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 6, 6 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 7, 7 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 8, 8 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 9, 9 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 10, 10 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 11, 11 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 12, 12 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 13, 13 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 14, 14 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 15, 15 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 16, 16 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 17, 17 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 18, 18 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 19, 19 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 20, 20 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 21, 21 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 22, 22 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 23, 23 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 24, 24 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 25, 25 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 26, 26 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 27, 27 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 28, 28 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 29, 29 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 30, 30 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" cmpwi 31, 31 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" \n\t" \
|
||||
" mfspr 0, 256 #USPRG0 \n\t" \
|
||||
" cmpwi 0, 301 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" mfspr 0, 8 #LR \n\t" \
|
||||
" cmpwi 0, 501 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" mfspr 0, 1 #XER \n\t" \
|
||||
" cmpwi 0, 4 \n\t" \
|
||||
" bne RegTest1Fail \n\t" \
|
||||
" \n\t" \
|
||||
" bl prvRegTest1Pass \n\t" \
|
||||
" b RegTest1Start \n\t" \
|
||||
" \n\t" \
|
||||
"RegTest1Fail: \n\t" \
|
||||
" \n\t" \
|
||||
" \n\t" \
|
||||
" bl prvRegTestFail \n\t" \
|
||||
" b RegTest1Start \n\t" \
|
||||
);
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvRegTestTask2( void *pvParameters )
|
||||
{
|
||||
/* The second register test task as described at the top of this file.
|
||||
Note that this task fills the registers with different values to the
|
||||
first register test task. */
|
||||
asm volatile
|
||||
(
|
||||
"RegTest2Start: \n\t" \
|
||||
" \n\t" \
|
||||
" li 0, 300 \n\t" \
|
||||
" mtspr 256, 0 #USPRG0 \n\t" \
|
||||
" li 0, 500 \n\t" \
|
||||
" mtspr 8, 0 #LR \n\t" \
|
||||
" li 0, 4 \n\t" \
|
||||
" mtspr 1, 0 #XER \n\t" \
|
||||
" \n\t" \
|
||||
" li 0, 11 \n\t" \
|
||||
" li 2, 12 \n\t" \
|
||||
" li 3, 13 \n\t" \
|
||||
" li 4, 14 \n\t" \
|
||||
" li 5, 15 \n\t" \
|
||||
" li 6, 16 \n\t" \
|
||||
" li 7, 17 \n\t" \
|
||||
" li 8, 18 \n\t" \
|
||||
" li 9, 19 \n\t" \
|
||||
" li 10, 110 \n\t" \
|
||||
" li 11, 111 \n\t" \
|
||||
" li 12, 112 \n\t" \
|
||||
" li 13, 113 \n\t" \
|
||||
" li 14, 114 \n\t" \
|
||||
" li 15, 115 \n\t" \
|
||||
" li 16, 116 \n\t" \
|
||||
" li 17, 117 \n\t" \
|
||||
" li 18, 118 \n\t" \
|
||||
" li 19, 119 \n\t" \
|
||||
" li 20, 120 \n\t" \
|
||||
" li 21, 121 \n\t" \
|
||||
" li 22, 122 \n\t" \
|
||||
" li 23, 123 \n\t" \
|
||||
" li 24, 124 \n\t" \
|
||||
" li 25, 125 \n\t" \
|
||||
" li 26, 126 \n\t" \
|
||||
" li 27, 127 \n\t" \
|
||||
" li 28, 128 \n\t" \
|
||||
" li 29, 129 \n\t" \
|
||||
" li 30, 130 \n\t" \
|
||||
" li 31, 131 \n\t" \
|
||||
" \n\t" \
|
||||
" cmpwi 0, 11 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 2, 12 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 3, 13 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 4, 14 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 5, 15 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 6, 16 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 7, 17 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 8, 18 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 9, 19 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 10, 110 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 11, 111 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 12, 112 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 13, 113 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 14, 114 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 15, 115 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 16, 116 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 17, 117 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 18, 118 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 19, 119 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 20, 120 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 21, 121 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 22, 122 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 23, 123 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 24, 124 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 25, 125 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 26, 126 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 27, 127 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 28, 128 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 29, 129 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 30, 130 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" cmpwi 31, 131 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" \n\t" \
|
||||
" mfspr 0, 256 #USPRG0 \n\t" \
|
||||
" cmpwi 0, 300 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" mfspr 0, 8 #LR \n\t" \
|
||||
" cmpwi 0, 500 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" mfspr 0, 1 #XER \n\t" \
|
||||
" cmpwi 0, 4 \n\t" \
|
||||
" bne RegTest2Fail \n\t" \
|
||||
" \n\t" \
|
||||
" bl prvRegTest2Pass \n\t" \
|
||||
" b RegTest2Start \n\t" \
|
||||
" \n\t" \
|
||||
"RegTest2Fail: \n\t" \
|
||||
" \n\t" \
|
||||
" \n\t" \
|
||||
" bl prvRegTestFail \n\t" \
|
||||
" b RegTest2Start \n\t" \
|
||||
);
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* This hook function will get called if there is a suspected stack overflow.
|
||||
An overflow can cause the task name to be corrupted, in which case the task
|
||||
handle needs to be used to determine the offending task. */
|
||||
void vApplicationStackOverflowHook( xTaskHandle xTask, signed portCHAR *pcTaskName );
|
||||
void vApplicationStackOverflowHook( xTaskHandle xTask, signed portCHAR *pcTaskName )
|
||||
{
|
||||
/* The following three calls are simply to stop compiler warnings about the
|
||||
functions not being used - they are called from the inline assembly. */
|
||||
prvRegTest1Pass();
|
||||
prvRegTest2Pass();
|
||||
prvRegTestFail();
|
||||
|
||||
for( ;; );
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -1,167 +0,0 @@
|
||||
/*
|
||||
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
***************************************************************************
|
||||
* *
|
||||
* SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
|
||||
* and even write all or part of your application on your behalf. *
|
||||
* See http://www.OpenRTOS.com for details of the services we provide to *
|
||||
* expedite your project. *
|
||||
* *
|
||||
***************************************************************************
|
||||
***************************************************************************
|
||||
|
||||
Please ensure to read the configuration and relevant port sections of the
|
||||
online documentation.
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
|
||||
/* Scheduler includes. */
|
||||
#include "FreeRTOS.h"
|
||||
|
||||
/* Demo application includes. */
|
||||
#include "partest.h"
|
||||
|
||||
/* Library includes. */
|
||||
#include "xparameters.h"
|
||||
#include "xgpio_l.h"
|
||||
|
||||
/* Misc hardware specific definitions. */
|
||||
#define partstALL_AS_OUTPUT 0x00
|
||||
#define partstCHANNEL_1 0x01
|
||||
#define partstMAX_4BIT_LED 0x03
|
||||
|
||||
/* The outputs are split into two IO sections, these variables maintain the
|
||||
current value of either section. */
|
||||
static unsigned portBASE_TYPE uxCurrentOutput4Bit, uxCurrentOutput5Bit;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
/*
|
||||
* Setup the IO for the LED outputs.
|
||||
*/
|
||||
void vParTestInitialise( void )
|
||||
{
|
||||
/* Set both sets of LED's on the demo board to outputs. */
|
||||
XGpio_mSetDataDirection( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT );
|
||||
XGpio_mSetDataDirection( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT );
|
||||
|
||||
/* Start with all outputs off. */
|
||||
uxCurrentOutput4Bit = 0;
|
||||
XGpio_mSetDataReg( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, 0x00 );
|
||||
uxCurrentOutput5Bit = 0;
|
||||
XGpio_mSetDataReg( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, 0x00 );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
|
||||
{
|
||||
unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue;
|
||||
|
||||
portENTER_CRITICAL();
|
||||
{
|
||||
/* Which IO section does the LED being set/cleared belong to? The
|
||||
4 bit or 5 bit outputs? */
|
||||
if( uxLED <= partstMAX_4BIT_LED )
|
||||
{
|
||||
uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR;
|
||||
puxCurrentValue = &uxCurrentOutput4Bit;
|
||||
}
|
||||
else
|
||||
{
|
||||
uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR;
|
||||
puxCurrentValue = &uxCurrentOutput5Bit;
|
||||
uxLED -= partstMAX_4BIT_LED;
|
||||
}
|
||||
|
||||
/* Setup the bit mask accordingly. */
|
||||
uxLED = 0x01 << uxLED;
|
||||
|
||||
/* Maintain the current output value. */
|
||||
if( xValue )
|
||||
{
|
||||
*puxCurrentValue |= uxLED;
|
||||
}
|
||||
else
|
||||
{
|
||||
*puxCurrentValue &= ~uxLED;
|
||||
}
|
||||
|
||||
/* Write the value to the port. */
|
||||
XGpio_mSetDataReg( uxBaseAddress, partstCHANNEL_1, *puxCurrentValue );
|
||||
}
|
||||
portEXIT_CRITICAL();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
|
||||
{
|
||||
unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue;
|
||||
|
||||
portENTER_CRITICAL();
|
||||
{
|
||||
/* Which IO section does the LED being toggled belong to? The
|
||||
4 bit or 5 bit outputs? */
|
||||
if( uxLED <= partstMAX_4BIT_LED )
|
||||
{
|
||||
uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR;
|
||||
puxCurrentValue = &uxCurrentOutput4Bit;
|
||||
}
|
||||
else
|
||||
{
|
||||
uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR;
|
||||
puxCurrentValue = &uxCurrentOutput5Bit;
|
||||
uxLED -= partstMAX_4BIT_LED;
|
||||
}
|
||||
|
||||
/* Setup the bit mask accordingly. */
|
||||
uxLED = 0x01 << uxLED;
|
||||
|
||||
/* Maintain the current output value. */
|
||||
if( *puxCurrentValue & uxLED )
|
||||
{
|
||||
*puxCurrentValue &= ~uxLED;
|
||||
}
|
||||
else
|
||||
{
|
||||
*puxCurrentValue |= uxLED;
|
||||
}
|
||||
|
||||
/* Write the value to the port. */
|
||||
XGpio_mSetDataReg(uxBaseAddress, partstCHANNEL_1, *puxCurrentValue );
|
||||
}
|
||||
portEXIT_CRITICAL();
|
||||
}
|
||||
|
||||
|
||||
@ -1,227 +0,0 @@
|
||||
/*
|
||||
FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
***************************************************************************
|
||||
* *
|
||||
* SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
|
||||
* and even write all or part of your application on your behalf. *
|
||||
* See http://www.OpenRTOS.com for details of the services we provide to *
|
||||
* expedite your project. *
|
||||
* *
|
||||
***************************************************************************
|
||||
***************************************************************************
|
||||
|
||||
Please ensure to read the configuration and relevant port sections of the
|
||||
online documentation.
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART
|
||||
*/
|
||||
|
||||
/* Scheduler includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "queue.h"
|
||||
#include "task.h"
|
||||
|
||||
/* Demo application includes. */
|
||||
#include "serial.h"
|
||||
|
||||
/* Library includes. */
|
||||
#include "xparameters.h"
|
||||
#include "xuartlite.h"
|
||||
#include "xuartlite_l.h"
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Queues used to hold received characters, and characters waiting to be
|
||||
transmitted. */
|
||||
static xQueueHandle xRxedChars;
|
||||
static xQueueHandle xCharsForTx;
|
||||
|
||||
/* Structure that maintains information on the UART being used. */
|
||||
static XUartLite xUART;
|
||||
|
||||
/*
|
||||
* Sample UART interrupt handler. Note this is used to demonstrate the kernel
|
||||
* features and test the port - it is not intended to represent an efficient
|
||||
* implementation.
|
||||
*/
|
||||
static void vSerialISR( XUartLite *pxUART );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
|
||||
{
|
||||
/* NOTE: The baud rate used by this driver is determined by the hardware
|
||||
parameterization of the UART Lite peripheral, and the baud value passed to
|
||||
this function has no effect. */
|
||||
( void ) ulWantedBaud;
|
||||
|
||||
/* Create the queues used to hold Rx and Tx characters. */
|
||||
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
|
||||
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
|
||||
|
||||
/* Only initialise the UART if the queues were created correctly. */
|
||||
if( ( xRxedChars != NULL ) && ( xCharsForTx != NULL ) )
|
||||
{
|
||||
|
||||
XUartLite_Initialize( &xUART, XPAR_RS232_UART_DEVICE_ID );
|
||||
XUartLite_ResetFifos( &xUART );
|
||||
XUartLite_DisableInterrupt( &xUART );
|
||||
|
||||
if( xPortInstallInterruptHandler( XPAR_OPB_INTC_0_RS232_UART_INTERRUPT_INTR, ( XInterruptHandler )vSerialISR, (void *)&xUART ) == pdPASS )
|
||||
{
|
||||
/* xPortInstallInterruptHandler() could fail if
|
||||
vPortSetupInterruptController() has not been called prior to this
|
||||
function. */
|
||||
XUartLite_EnableInterrupt( &xUART );
|
||||
}
|
||||
}
|
||||
|
||||
/* There is only one port so the handle is not used. */
|
||||
return ( xComPortHandle ) 0;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
|
||||
{
|
||||
/* The port handle is not required as this driver only supports one UART. */
|
||||
( void ) pxPort;
|
||||
|
||||
/* Get the next character from the buffer. Return false if no characters
|
||||
are available, or arrive before xBlockTime expires. */
|
||||
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
|
||||
{
|
||||
return pdTRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
return pdFALSE;
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
|
||||
{
|
||||
portBASE_TYPE xReturn = pdTRUE;
|
||||
|
||||
portENTER_CRITICAL();
|
||||
{
|
||||
/* If the UART FIFO is full we can block posting the new data on the
|
||||
Tx queue. */
|
||||
if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) )
|
||||
{
|
||||
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
|
||||
{
|
||||
xReturn = pdFAIL;
|
||||
}
|
||||
}
|
||||
/* Otherwise, if there is data already in the queue we should add the
|
||||
new data to the back of the queue to ensure the sequencing is
|
||||
maintained. */
|
||||
else if( uxQueueMessagesWaiting( xCharsForTx ) )
|
||||
{
|
||||
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
|
||||
{
|
||||
xReturn = pdFAIL;
|
||||
}
|
||||
}
|
||||
/* If the UART FIFO is not full and there is no data already in the
|
||||
queue we can write directly to the FIFO without disrupting the
|
||||
sequence. */
|
||||
else
|
||||
{
|
||||
XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar );
|
||||
}
|
||||
}
|
||||
portEXIT_CRITICAL();
|
||||
|
||||
return xReturn;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vSerialClose( xComPortHandle xPort )
|
||||
{
|
||||
/* Not supported as not required by the demo application. */
|
||||
( void ) xPort;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void vSerialISR( XUartLite *pxUART )
|
||||
{
|
||||
unsigned portLONG ulISRStatus;
|
||||
portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE, lDidSomething;
|
||||
portCHAR cChar;
|
||||
|
||||
do
|
||||
{
|
||||
lDidSomething = pdFALSE;
|
||||
|
||||
ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );
|
||||
|
||||
if( ( ulISRStatus & XUL_SR_RX_FIFO_VALID_DATA ) != 0 )
|
||||
{
|
||||
/* A character is available - place it in the queue of received
|
||||
characters. This might wake a task that was blocked waiting for
|
||||
data. */
|
||||
cChar = ( portCHAR ) XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET );
|
||||
xTaskWokenByRx = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByRx );
|
||||
lDidSomething = pdTRUE;
|
||||
}
|
||||
|
||||
if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 )
|
||||
{
|
||||
/* There is space in the FIFO - if there are any characters queue for
|
||||
transmission they can be sent to the UART now. This might unblock a
|
||||
task that was waiting for space to become available on the Tx queue. */
|
||||
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )
|
||||
{
|
||||
XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar );
|
||||
lDidSomething = pdTRUE;
|
||||
}
|
||||
}
|
||||
} while( lDidSomething == pdTRUE );
|
||||
|
||||
/* If we woke any tasks we may require a context switch. */
|
||||
if( xTaskWokenByTx || xTaskWokenByRx )
|
||||
{
|
||||
portYIELD_FROM_ISR();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -1 +0,0 @@
|
||||
|
||||
@ -1 +0,0 @@
|
||||
-p virtex4
|
||||
@ -1,2 +0,0 @@
|
||||
-p virtex4 -lang vhdl
|
||||
|
||||
@ -1,18 +0,0 @@
|
||||
ppc405_0
|
||||
RTOSDEMO_SOURCES = RTOSDemo/main.c RTOSDemo/serial/serial.c RTOSDemo/partest/partest.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c RTOSDemo/../../../Source/tasks.c RTOSDemo/../../../Source/list.c RTOSDemo/../../../Source/queue.c RTOSDemo/../../../Source/portable/MemMang/heap_2.c RTOSDemo/../../Common/Minimal/flash.c RTOSDemo/../../Common/Minimal/blocktim.c RTOSDemo/../../Common/Minimal/dynamic.c RTOSDemo/../../Common/Minimal/flop.c RTOSDemo/../../Common/Minimal/GenQTest.c RTOSDemo/../../Common/Minimal/integer.c RTOSDemo/../../Common/Minimal/QPeek.c RTOSDemo/../../Common/Minimal/semtest.c RTOSDemo/../../Common/Minimal/BlockQ.c RTOSDemo/../../Common/Minimal/death.c RTOSDemo/../../Common/Minimal/comtest.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S
|
||||
RTOSDEMO_HEADERS = RTOSDemo/FreeRTOSConfig.h
|
||||
RTOSDEMO_CC = powerpc-eabi-gcc
|
||||
RTOSDEMO_CC_SIZE = powerpc-eabi-size
|
||||
RTOSDEMO_CC_OPT = -Os
|
||||
RTOSDEMO_CFLAGS = -D GCC_PPC405 -mregnames -Xlinker -Map=rtosdemo.map -Wall
|
||||
RTOSDEMO_CC_SEARCH = # -B
|
||||
RTOSDEMO_LIBPATH = -L./ppc405_0/lib/ # -L
|
||||
RTOSDEMO_INCLUDES = -I./ppc405_0/include/ -IRTOSDemo/ -I. -I./RTOSDemo/ -I../Common/include/ -I../../Source/include/ -I./ppc405_0/include/ -I./ppc405_0/include
|
||||
RTOSDEMO_LFLAGS = # -l
|
||||
RTOSDEMO_LINKER_SCRIPT = RTOSDemo/RTOSDemo.ld
|
||||
RTOSDEMO_CC_DEBUG_FLAG = -g
|
||||
RTOSDEMO_CC_PROFILE_FLAG = # -pg
|
||||
RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi
|
||||
RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR=
|
||||
RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE=
|
||||
RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE=
|
||||
@ -1 +0,0 @@
|
||||
-p virtex4 -lang vhdl -s mti
|
||||
@ -1 +0,0 @@
|
||||
guiSettings=FILTER=0;BUS_FLAT_VIEW=false;BUS_TREE_VIEW_HEADER=Name,Net,Direction,Range,Class,Sensitivity,Description,Frequency,Reset Polarity,IP Type,IP Version,IP Classification,Bus Connection,Mastership,Bus Standard,Address,Base Address,High Address,Size,Lock,ICache,DCache;BUS_TREE_VIEW_HEADER_MAP=0,15,16,17,18,19,20,21,12,13,14,1,2,4,5,3,7,8,9,10,11,6;BUS_TREE_VIEW_HIDDEN_SECTION=15,16,17,18,19,20,21,13,14,1,2,4,5,3,7,8,11,6;BUS_EXPANDED_NODE=RS232_Uart;BUS_TREE_VERTICAL_SCROLL=0;BUS_TREE_HORIZONTAL_SCROLL=0;
|
||||
@ -1 +0,0 @@
|
||||
-p xc4vfx12ff668-10
|
||||
@ -1 +0,0 @@
|
||||
-device xc4vfx12ff668-10data/system.ucf7 0
|
||||
@ -1 +0,0 @@
|
||||
-device xc4vfx12ff668-10data/system.ucf 0
|
||||
@ -1,339 +0,0 @@
|
||||
############################################################################
|
||||
## This system.ucf file is generated by Base System Builder based on the
|
||||
## settings in the selected Xilinx Board Definition file. Please add other
|
||||
## user constraints to this file based on customer design specifications.
|
||||
############################################################################
|
||||
|
||||
Net sys_clk_pin LOC=AE14;
|
||||
Net sys_clk_pin IOSTANDARD = LVCMOS33;
|
||||
Net sys_rst_pin LOC=D6;
|
||||
Net sys_rst_pin PULLUP;
|
||||
## System level constraints
|
||||
Net sys_clk_pin TNM_NET = sys_clk_pin;
|
||||
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
|
||||
Net sys_rst_pin TIG;
|
||||
NET "C405RSTCORERESETREQ" TPTHRU = "RST_GRP";
|
||||
NET "C405RSTCHIPRESETREQ" TPTHRU = "RST_GRP";
|
||||
NET "C405RSTSYSRESETREQ" TPTHRU = "RST_GRP";
|
||||
TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG;
|
||||
Net fpga_0_SRAM_CLOCK LOC=AF7;
|
||||
Net fpga_0_SRAM_CLOCK SLEW = FAST;
|
||||
Net fpga_0_SRAM_CLOCK IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_CLOCK DRIVE = 16;
|
||||
|
||||
## IO Devices constraints
|
||||
|
||||
#### Module RS232_Uart constraints
|
||||
|
||||
Net fpga_0_RS232_Uart_RX_pin LOC=W2;
|
||||
Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_RS232_Uart_TX_pin LOC=W1;
|
||||
Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33;
|
||||
|
||||
#### Module LEDs_4Bit constraints
|
||||
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2;
|
||||
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG;
|
||||
|
||||
#### Module LEDs_Positions constraints
|
||||
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2;
|
||||
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG;
|
||||
|
||||
#### Module SRAM_256Kx32 constraints
|
||||
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<29> LOC=Y1;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<29> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<29> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<29> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<28> LOC=Y2;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<28> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<28> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<28> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<27> LOC=AA1;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<27> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<27> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<27> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<26> LOC=AB1;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<26> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<26> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<26> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<25> LOC=AB2;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<25> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<25> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<25> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<24> LOC=AC1;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<24> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<24> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<24> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<23> LOC=AC2;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<23> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<23> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<23> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<22> LOC=AD1;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<22> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<22> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<22> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<21> LOC=AD2;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<21> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<21> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<21> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<20> LOC=AE3;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<20> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<20> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<20> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<19> LOC=AF3;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<19> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<19> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<19> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<18> LOC=W3;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<18> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<18> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<18> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<17> LOC=W6;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<17> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<17> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<17> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<16> LOC=W5;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<16> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<16> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<16> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<15> LOC=AA3;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<15> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<15> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<15> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<14> LOC=AA4;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<14> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<14> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<14> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<13> LOC=AB3;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<13> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<13> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<13> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<12> LOC=AB4;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<12> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<12> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<12> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<11> LOC=AC4;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<11> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<11> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<11> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<10> LOC=AB5;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<10> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<10> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<10> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<9> LOC=AC5;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<9> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<9> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_A_pin<9> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<3> LOC=Y6;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<3> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<3> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<3> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<2> LOC=Y5;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<2> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<2> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<2> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<1> LOC=Y4;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<1> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<1> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<1> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<0> LOC=Y3;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<0> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<0> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<0> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_WEN_pin LOC=AB6;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_WEN_pin IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_WEN_pin SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_WEN_pin DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<31> LOC=AD13;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<31> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<31> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<31> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<30> LOC=AC13;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<30> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<30> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<30> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<29> LOC=AC15;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<29> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<29> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<29> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<28> LOC=AC16;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<28> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<28> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<28> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<27> LOC=AA11;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<27> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<27> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<27> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<26> LOC=AA12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<26> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<26> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<26> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<25> LOC=AD14;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<25> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<25> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<25> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<24> LOC=AC14;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<24> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<24> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<24> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<23> LOC=AA13;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<23> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<23> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<23> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<22> LOC=AB13;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<22> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<22> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<22> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<21> LOC=AA15;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<21> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<21> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<21> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<20> LOC=AA16;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<20> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<20> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<20> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<19> LOC=AC11;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<19> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<19> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<19> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<18> LOC=AC12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<18> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<18> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<18> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<17> LOC=AB14;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<17> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<17> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<17> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<16> LOC=AA14;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<16> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<16> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<16> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<15> LOC=D12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<15> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<15> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<14> LOC=E13;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<14> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<14> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<13> LOC=C16;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<13> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<13> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<12> LOC=D16;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<12> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<12> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<11> LOC=D11;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<11> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<11> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<10> LOC=C11;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<10> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<10> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<9> LOC=E14;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<9> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<9> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<8> LOC=D15;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<8> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<8> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<7> LOC=D13;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<7> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<7> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<6> LOC=D14;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<6> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<6> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<5> LOC=F15;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<5> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<5> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<4> LOC=F16;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<4> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<4> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<3> LOC=F11;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<3> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<3> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<2> LOC=F12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<2> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<2> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<1> LOC=F13;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<1> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<1> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<0> LOC=F14;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<0> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<0> DRIVE = 12;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_OEN_pin<0> LOC=AC6;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_OEN_pin<0> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_OEN_pin<0> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_OEN_pin<0> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_CEN_pin<0> LOC=V7;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_CEN_pin<0> SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_CEN_pin<0> DRIVE = 8;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin LOC=W4;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin IOSTANDARD = LVCMOS33;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin SLEW = FAST;
|
||||
Net fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin DRIVE = 8;
|
||||
|
||||
@ -1,20 +0,0 @@
|
||||
-g CclkPin:PULLUP
|
||||
-g TdoPin:PULLNONE
|
||||
-g M1Pin:PULLDOWN
|
||||
-g DonePin:PULLUP
|
||||
-g DriveDone:No
|
||||
-g StartUpClk:JTAGCLK
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g M0Pin:PULLUP
|
||||
-g M2Pin:PULLUP
|
||||
-g ProgPin:PULLUP
|
||||
-g TckPin:PULLUP
|
||||
-g TdiPin:PULLUP
|
||||
-g TmsPin:PULLUP
|
||||
-g DonePipe:No
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Security:NONE
|
||||
#-m
|
||||
-g Persist:No
|
||||
@ -1,6 +0,0 @@
|
||||
setMode -bscan
|
||||
setCable -p auto
|
||||
identify
|
||||
assignfile -p 3 -file implementation/download.bit
|
||||
program -p 3
|
||||
quit
|
||||
@ -1,80 +0,0 @@
|
||||
FLOWTYPE = FPGA;
|
||||
###############################################################
|
||||
## Filename: fast_runtime.opt
|
||||
##
|
||||
## Option File For Xilinx FPGA Implementation Flow for Fast
|
||||
## Runtime.
|
||||
##
|
||||
## Version: 4.1.1
|
||||
###############################################################
|
||||
#
|
||||
# Options for Translator
|
||||
#
|
||||
# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
|
||||
#
|
||||
Program ngdbuild
|
||||
-p <partname>; # Partname to use - picked from xflow commandline
|
||||
-nt timestamp; # NGO File generation. Regenerate only when
|
||||
# source netlist is newer than existing
|
||||
# NGO file (default)
|
||||
-bm <design>.bmm # Block RAM memory map file
|
||||
<userdesign>; # User design - pick from xflow command line
|
||||
-uc <design>.ucf; # ucf constraints
|
||||
<design>.ngd; # Name of NGD file. Filebase same as design filebase
|
||||
End Program ngdbuild
|
||||
|
||||
#
|
||||
# Options for Mapper
|
||||
#
|
||||
# Type "map -h <arch>" for a detailed list of map command line options
|
||||
#
|
||||
Program map
|
||||
-o <design>_map.ncd; # Output Mapped ncd file
|
||||
-pr b; # Pack internal FF/latches into IOBs
|
||||
#-fp <design>.mfp; # Floorplan file
|
||||
<inputdir><design>.ngd; # Input NGD file
|
||||
<inputdir><design>.pcf; # Physical constraints file
|
||||
END Program map
|
||||
|
||||
#
|
||||
# Options for Post Map Trace
|
||||
#
|
||||
# Type "trce -h" for a detailed list of trce command line options
|
||||
#
|
||||
Program post_map_trce
|
||||
-e 3; # Produce error report limited to 3 items per constraint
|
||||
#-o <design>_map.twr; # Output trace report file
|
||||
-xml <design>_map.twx; # Output XML version of the timing report
|
||||
#-tsi <design>_map.tsi; # Produce Timing Specification Interaction report
|
||||
<inputdir><design>_map.ncd; # Input mapped ncd
|
||||
<inputdir><design>.pcf; # Physical constraints file
|
||||
END Program post_map_trce
|
||||
|
||||
#
|
||||
# Options for Place and Route
|
||||
#
|
||||
# Type "par -h" for a detailed list of par command line options
|
||||
#
|
||||
Program par
|
||||
-w; # Overwrite existing placed and routed ncd
|
||||
-ol high; # Overall effort level
|
||||
<inputdir><design>_map.ncd; # Input mapped NCD file
|
||||
<design>.ncd; # Output placed and routed NCD
|
||||
<inputdir><design>.pcf; # Input physical constraints file
|
||||
END Program par
|
||||
|
||||
#
|
||||
# Options for Post Par Trace
|
||||
#
|
||||
# Type "trce -h" for a detailed list of trce command line options
|
||||
#
|
||||
Program post_par_trce
|
||||
-e 3; # Produce error report limited to 3 items per constraint
|
||||
#-o <design>.twr; # Output trace report file
|
||||
-xml <design>.twx; # Output XML version of the timing report
|
||||
#-tsi <design>.tsi; # Produce Timing Specification Interaction report
|
||||
<inputdir><design>.ncd; # Input placed and routed ncd
|
||||
<inputdir><design>.pcf; # Physical constraints file
|
||||
END Program post_par_trce
|
||||
|
||||
|
||||
@ -1,255 +0,0 @@
|
||||
#################################################################
|
||||
# Makefile generated by Xilinx Platform Studio
|
||||
# Project:C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_Xilinx_Virtex4_GCC\system.xmp
|
||||
#################################################################
|
||||
|
||||
# Name of the Microprocessor system
|
||||
# The hardware specification of the system is in file :
|
||||
# C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_Xilinx_Virtex4_GCC\system.mhs
|
||||
# The software specification of the system is in file :
|
||||
# C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_Xilinx_Virtex4_GCC\system.mss
|
||||
|
||||
include system_incl.make
|
||||
|
||||
|
||||
#################################################################
|
||||
# EXTERNAL TARGETS
|
||||
#################################################################
|
||||
all:
|
||||
@echo "Makefile to build a Microprocessor system :"
|
||||
@echo "Run make with any of the following targets"
|
||||
@echo " "
|
||||
@echo " netlist : Generates the netlist for the given MHS "
|
||||
@echo " bits : Runs Implementation tools to generate the bitstream"
|
||||
@echo " exporttopn:Export to ProjNav"
|
||||
@echo " "
|
||||
@echo " libs : Configures the sw libraries for this system"
|
||||
@echo " program : Compiles the program sources for all the processor instances"
|
||||
@echo " "
|
||||
@echo " init_bram: Initializes bitstream with BRAM data"
|
||||
@echo " ace : Generate ace file from bitstream and elf"
|
||||
@echo " download : Downloads the bitstream onto the board"
|
||||
@echo " "
|
||||
@echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode"
|
||||
@echo " simmodel : Generates HDL simulation models for chosen simulation mode"
|
||||
@echo " behavioral:Generates behavioral HDL models with BRAM initialization"
|
||||
@echo " structural:Generates structural simulation HDL models with BRAM initialization"
|
||||
@echo " timing : Generates timing simulation HDL models with BRAM initialization"
|
||||
@echo " vp : Generates virtual platform model"
|
||||
@echo " "
|
||||
@echo " netlistclean: Deletes netlist"
|
||||
@echo " bitsclean: Deletes bit, ncd, bmm files"
|
||||
@echo " hwclean : Deletes implementation dir"
|
||||
@echo " libsclean: Deletes sw libraries"
|
||||
@echo " programclean: Deletes compiled ELF files"
|
||||
@echo " swclean : Deletes sw libraries and ELF files"
|
||||
@echo " simclean : Deletes simulation dir"
|
||||
@echo " vpclean : Deletes virtualplatform dir"
|
||||
@echo " clean : Deletes all generated files/directories"
|
||||
@echo " "
|
||||
@echo " make <target> : (Default)"
|
||||
@echo " Creates a Microprocessor system using default initializations"
|
||||
@echo " specified for each processor in MSS file"
|
||||
|
||||
|
||||
bits: $(SYSTEM_BIT)
|
||||
|
||||
ace: $(SYSTEM_ACE)
|
||||
|
||||
netlist: $(POSTSYN_NETLIST)
|
||||
|
||||
libs: $(LIBRARIES)
|
||||
|
||||
program: $(ALL_USER_ELF_FILES)
|
||||
|
||||
download: $(DOWNLOAD_BIT) dummy
|
||||
@echo "*********************************************"
|
||||
@echo "Downloading Bitstream onto the target board"
|
||||
@echo "*********************************************"
|
||||
impact -batch etc/download.cmd
|
||||
|
||||
init_bram: $(DOWNLOAD_BIT)
|
||||
|
||||
sim: $(DEFAULT_SIM_SCRIPT)
|
||||
cd simulation/behavioral; \
|
||||
$(SIM_CMD) &
|
||||
|
||||
simmodel: $(DEFAULT_SIM_SCRIPT)
|
||||
|
||||
behavioral_model: $(BEHAVIORAL_SIM_SCRIPT)
|
||||
|
||||
structural_model: $(STRUCTURAL_SIM_SCRIPT)
|
||||
|
||||
vp: $(VPEXEC)
|
||||
|
||||
clean: hwclean libsclean programclean simclean vpclean
|
||||
rm -f _impact.cmd
|
||||
|
||||
hwclean: netlistclean bitsclean
|
||||
rm -rf implementation synthesis xst hdl
|
||||
rm -rf xst.srp $(SYSTEM).srp
|
||||
|
||||
netlistclean:
|
||||
rm -f $(POSTSYN_NETLIST)
|
||||
rm -f $(BMM_FILE)
|
||||
|
||||
bitsclean:
|
||||
rm -f $(SYSTEM_BIT)
|
||||
rm -f implementation/$(SYSTEM).ncd
|
||||
rm -f implementation/$(SYSTEM)_bd.bmm
|
||||
|
||||
bitsclean:
|
||||
|
||||
simclean:
|
||||
rm -rf simulation/behavioral
|
||||
|
||||
swclean: libsclean programclean
|
||||
@echo ""
|
||||
|
||||
libsclean: $(LIBSCLEAN_TARGETS)
|
||||
|
||||
programclean: $(PROGRAMCLEAN_TARGETS)
|
||||
|
||||
vpclean:
|
||||
rm -rf virtualplatform
|
||||
|
||||
#################################################################
|
||||
# SOFTWARE PLATFORM FLOW
|
||||
#################################################################
|
||||
|
||||
|
||||
$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt
|
||||
@echo "*********************************************"
|
||||
@echo "Creating software libraries..."
|
||||
@echo "*********************************************"
|
||||
libgen $(LIBGEN_OPTIONS) $(MSSFILE)
|
||||
|
||||
|
||||
ppc405_0_libsclean:
|
||||
rm -rf ppc405_0/lib/
|
||||
|
||||
#################################################################
|
||||
# SOFTWARE APPLICATION RTOSDEMO
|
||||
#################################################################
|
||||
|
||||
RTOSDemo_program: $(RTOSDEMO_OUTPUT)
|
||||
|
||||
$(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \
|
||||
$(LIBRARIES) __xps/rtosdemo_compiler.opt
|
||||
@mkdir -p $(RTOSDEMO_OUTPUT_DIR)
|
||||
$(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \
|
||||
$(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \
|
||||
$(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS)
|
||||
$(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT)
|
||||
@echo ""
|
||||
|
||||
RTOSDemo_programclean:
|
||||
rm -f $(RTOSDEMO_OUTPUT)
|
||||
|
||||
#################################################################
|
||||
# BOOTLOOP ELF FILES
|
||||
#################################################################
|
||||
|
||||
|
||||
|
||||
$(PPC405_0_BOOTLOOP): $(PPC405_BOOTLOOP)
|
||||
@mkdir -p $(BOOTLOOP_DIR)
|
||||
cp -f $(PPC405_BOOTLOOP) $(PPC405_0_BOOTLOOP)
|
||||
|
||||
#################################################################
|
||||
# HARDWARE IMPLEMENTATION FLOW
|
||||
#################################################################
|
||||
|
||||
|
||||
$(BMM_FILE) \
|
||||
$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \
|
||||
$(CORE_STATE_DEVELOPMENT_FILES)
|
||||
@echo "****************************************************"
|
||||
@echo "Creating system netlist for hardware specification.."
|
||||
@echo "****************************************************"
|
||||
platgen $(PLATGEN_OPTIONS) $(MHSFILE)
|
||||
|
||||
$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES)
|
||||
@echo "Running synthesis..."
|
||||
bash -c "cd synthesis; ./synthesis.sh"
|
||||
|
||||
$(SYSTEM_BIT): $(FPGA_IMP_DEPENDENCY)
|
||||
@echo "*********************************************"
|
||||
@echo "Running Xilinx Implementation tools.."
|
||||
@echo "*********************************************"
|
||||
@cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf
|
||||
@cp -f $(XFLOW_OPT_FILE) implementation/xflow.opt
|
||||
xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc
|
||||
@echo "*********************************************"
|
||||
@echo "Running Bitgen.."
|
||||
@echo "*********************************************"
|
||||
@cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut
|
||||
cd implementation; bitgen -w -f bitgen.ut $(SYSTEM)
|
||||
|
||||
exporttopn:
|
||||
@echo "You have chosen XPS for implementation tool flow."
|
||||
@echo "Please select ProjNav as your implementation flow in Project Options."
|
||||
@echo "In batch mode, use commad xset pnproj <nplfile>."
|
||||
|
||||
$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt
|
||||
@cp -f implementation/$(SYSTEM)_bd.bmm .
|
||||
@echo "*********************************************"
|
||||
@echo "Initializing BRAM contents of the bitstream"
|
||||
@echo "*********************************************"
|
||||
bitinit $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \
|
||||
-bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT)
|
||||
@rm -f $(SYSTEM)_bd.bmm
|
||||
|
||||
$(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT)
|
||||
@echo "*********************************************"
|
||||
@echo "Creating system ace file"
|
||||
@echo "*********************************************"
|
||||
xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT) -target ppc_hw -ace $(SYSTEM_ACE)
|
||||
|
||||
#################################################################
|
||||
# SIMULATION FLOW
|
||||
#################################################################
|
||||
|
||||
|
||||
################## BEHAVIORAL SIMULATION ##################
|
||||
|
||||
$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \
|
||||
$(BRAMINIT_ELF_FILES)
|
||||
@echo "*********************************************"
|
||||
@echo "Creating behavioral simulation models..."
|
||||
@echo "*********************************************"
|
||||
simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE)
|
||||
|
||||
################## STRUCTURAL SIMULATION ##################
|
||||
|
||||
$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \
|
||||
$(BRAMINIT_ELF_FILES)
|
||||
@echo "*********************************************"
|
||||
@echo "Creating structural simulation models..."
|
||||
@echo "*********************************************"
|
||||
simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE)
|
||||
|
||||
|
||||
################## TIMING SIMULATION ##################
|
||||
|
||||
$(TIMING_SIM_SCRIPT): $(SYSTEM_BIT) __xps/simgen.opt \
|
||||
$(BRAMINIT_ELF_FILES)
|
||||
@echo "*********************************************"
|
||||
@echo "Creating timing simulation models..."
|
||||
@echo "*********************************************"
|
||||
simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE)
|
||||
|
||||
#################################################################
|
||||
# VIRTUAL PLATFORM FLOW
|
||||
#################################################################
|
||||
|
||||
|
||||
$(VPEXEC): $(MHSFILE) __xps/vpgen.opt
|
||||
@echo "****************************************************"
|
||||
@echo "Creating virtual platform for hardware specification.."
|
||||
@echo "****************************************************"
|
||||
vpgen $(VPGEN_OPTIONS) $(MHSFILE)
|
||||
|
||||
dummy:
|
||||
@echo ""
|
||||
|
||||
@ -1,235 +0,0 @@
|
||||
#
|
||||
# ##############################################################################
|
||||
#
|
||||
# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
|
||||
#
|
||||
# Tue Mar 04 08:41:46 2008
|
||||
#
|
||||
# Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1
|
||||
# Family: virtex4
|
||||
# Device: xc4vfx12
|
||||
# Package: ff668
|
||||
# Speed Grade: -10
|
||||
#
|
||||
# Processor: PPC 405
|
||||
# Processor clock frequency: 100.000000 MHz
|
||||
# Bus clock frequency: 100.000000 MHz
|
||||
# Debug interface: FPGA JTAG
|
||||
# Data Cache: 16 KB
|
||||
# Instruction Cache: 16 KB
|
||||
# On Chip Memory : 4 KB
|
||||
# Total Off Chip Memory : 1 MB
|
||||
# - SRAM_256Kx32 = 1 MB
|
||||
#
|
||||
# ##############################################################################
|
||||
|
||||
|
||||
PARAMETER VERSION = 2.1.0
|
||||
|
||||
|
||||
PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = I
|
||||
PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = O
|
||||
PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
|
||||
PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4]
|
||||
PORT fpga_0_SRAM_256Kx32_Mem_A_pin = fpga_0_SRAM_256Kx32_Mem_A, DIR = O, VEC = [9:29]
|
||||
PORT fpga_0_SRAM_256Kx32_Mem_BEN_pin = fpga_0_SRAM_256Kx32_Mem_BEN, DIR = O, VEC = [0:3]
|
||||
PORT fpga_0_SRAM_256Kx32_Mem_WEN_pin = fpga_0_SRAM_256Kx32_Mem_WEN, DIR = O
|
||||
PORT fpga_0_SRAM_256Kx32_Mem_DQ_pin = fpga_0_SRAM_256Kx32_Mem_DQ, DIR = IO, VEC = [0:31]
|
||||
PORT fpga_0_SRAM_256Kx32_Mem_OEN_pin = fpga_0_SRAM_256Kx32_Mem_OEN, DIR = O, VEC = [0:0]
|
||||
PORT fpga_0_SRAM_256Kx32_Mem_CEN_pin = fpga_0_SRAM_256Kx32_Mem_CEN, DIR = O, VEC = [0:0]
|
||||
PORT fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin = fpga_0_SRAM_256Kx32_Mem_ADV_LDN, DIR = O
|
||||
PORT fpga_0_SRAM_CLOCK = sys_clk_s, DIR = O
|
||||
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
|
||||
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
|
||||
|
||||
|
||||
BEGIN ppc405_virtex4
|
||||
PARAMETER INSTANCE = ppc405_0
|
||||
PARAMETER HW_VER = 1.01.a
|
||||
BUS_INTERFACE JTAGPPC = jtagppc_0_0
|
||||
BUS_INTERFACE IPLB = plb
|
||||
BUS_INTERFACE DPLB = plb
|
||||
PORT PLBCLK = sys_clk_s
|
||||
PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
|
||||
PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
|
||||
PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
|
||||
PORT RSTC405RESETCHIP = RSTC405RESETCHIP
|
||||
PORT RSTC405RESETCORE = RSTC405RESETCORE
|
||||
PORT RSTC405RESETSYS = RSTC405RESETSYS
|
||||
PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
|
||||
PORT CPMC405CLOCK = sys_clk_s
|
||||
END
|
||||
|
||||
BEGIN jtagppc_cntlr
|
||||
PARAMETER INSTANCE = jtagppc_0
|
||||
PARAMETER HW_VER = 2.00.a
|
||||
BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
|
||||
END
|
||||
|
||||
BEGIN proc_sys_reset
|
||||
PARAMETER INSTANCE = reset_block
|
||||
PARAMETER HW_VER = 1.00.a
|
||||
PARAMETER C_EXT_RESET_HIGH = 0
|
||||
PORT Ext_Reset_In = sys_rst_s
|
||||
PORT Slowest_sync_clk = sys_clk_s
|
||||
PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
|
||||
PORT Core_Reset_Req = C405RSTCORERESETREQ
|
||||
PORT System_Reset_Req = C405RSTSYSRESETREQ
|
||||
PORT Rstc405resetchip = RSTC405RESETCHIP
|
||||
PORT Rstc405resetcore = RSTC405RESETCORE
|
||||
PORT Rstc405resetsys = RSTC405RESETSYS
|
||||
PORT Bus_Struct_Reset = sys_bus_reset
|
||||
PORT Dcm_locked = dcm_0_lock
|
||||
END
|
||||
|
||||
BEGIN plb_v34
|
||||
PARAMETER INSTANCE = plb
|
||||
PARAMETER HW_VER = 1.02.a
|
||||
PARAMETER C_DCR_INTFCE = 0
|
||||
PARAMETER C_EXT_RESET_HIGH = 1
|
||||
PORT SYS_Rst = sys_bus_reset
|
||||
PORT PLB_Clk = sys_clk_s
|
||||
END
|
||||
|
||||
BEGIN opb_v20
|
||||
PARAMETER INSTANCE = opb
|
||||
PARAMETER HW_VER = 1.10.c
|
||||
PARAMETER C_EXT_RESET_HIGH = 1
|
||||
PORT SYS_Rst = sys_bus_reset
|
||||
PORT OPB_Clk = sys_clk_s
|
||||
END
|
||||
|
||||
BEGIN plb2opb_bridge
|
||||
PARAMETER INSTANCE = plb2opb
|
||||
PARAMETER HW_VER = 1.01.a
|
||||
PARAMETER C_DCR_INTFCE = 0
|
||||
PARAMETER C_NUM_ADDR_RNG = 1
|
||||
PARAMETER C_RNG0_BASEADDR = 0x40000000
|
||||
PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
|
||||
BUS_INTERFACE SPLB = plb
|
||||
BUS_INTERFACE MOPB = opb
|
||||
END
|
||||
|
||||
BEGIN opb_uartlite
|
||||
PARAMETER INSTANCE = RS232_Uart
|
||||
PARAMETER HW_VER = 1.00.b
|
||||
PARAMETER C_BAUDRATE = 115200
|
||||
PARAMETER C_DATA_BITS = 8
|
||||
PARAMETER C_ODD_PARITY = 0
|
||||
PARAMETER C_USE_PARITY = 0
|
||||
PARAMETER C_CLK_FREQ = 100000000
|
||||
PARAMETER C_BASEADDR = 0x40600000
|
||||
PARAMETER C_HIGHADDR = 0x4060ffff
|
||||
BUS_INTERFACE SOPB = opb
|
||||
PORT Interrupt = RS232_Uart_Interrupt
|
||||
PORT RX = fpga_0_RS232_Uart_RX
|
||||
PORT TX = fpga_0_RS232_Uart_TX
|
||||
END
|
||||
|
||||
BEGIN opb_gpio
|
||||
PARAMETER INSTANCE = LEDs_4Bit
|
||||
PARAMETER HW_VER = 3.01.b
|
||||
PARAMETER C_GPIO_WIDTH = 4
|
||||
PARAMETER C_IS_DUAL = 0
|
||||
PARAMETER C_IS_BIDIR = 1
|
||||
PARAMETER C_ALL_INPUTS = 0
|
||||
PARAMETER C_BASEADDR = 0x40000000
|
||||
PARAMETER C_HIGHADDR = 0x4000ffff
|
||||
BUS_INTERFACE SOPB = opb
|
||||
PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
|
||||
END
|
||||
|
||||
BEGIN opb_gpio
|
||||
PARAMETER INSTANCE = LEDs_Positions
|
||||
PARAMETER HW_VER = 3.01.b
|
||||
PARAMETER C_GPIO_WIDTH = 5
|
||||
PARAMETER C_IS_DUAL = 0
|
||||
PARAMETER C_IS_BIDIR = 1
|
||||
PARAMETER C_ALL_INPUTS = 0
|
||||
PARAMETER C_BASEADDR = 0x40020000
|
||||
PARAMETER C_HIGHADDR = 0x4002ffff
|
||||
BUS_INTERFACE SOPB = opb
|
||||
PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO
|
||||
END
|
||||
|
||||
BEGIN plb_emc
|
||||
PARAMETER INSTANCE = SRAM_256Kx32
|
||||
PARAMETER HW_VER = 2.00.a
|
||||
PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1
|
||||
PARAMETER C_PLB_CLK_PERIOD_PS = 10000
|
||||
PARAMETER C_NUM_BANKS_MEM = 1
|
||||
PARAMETER C_MAX_MEM_WIDTH = 32
|
||||
PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1
|
||||
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
|
||||
PARAMETER C_MEM0_WIDTH = 32
|
||||
PARAMETER C_SYNCH_MEM_0 = 1
|
||||
PARAMETER C_TCEDV_PS_MEM_0 = 0
|
||||
PARAMETER C_TWC_PS_MEM_0 = 0
|
||||
PARAMETER C_TAVDV_PS_MEM_0 = 0
|
||||
PARAMETER C_TWP_PS_MEM_0 = 0
|
||||
PARAMETER C_THZCE_PS_MEM_0 = 0
|
||||
PARAMETER C_TLZWE_PS_MEM_0 = 0
|
||||
PARAMETER C_MEM0_BASEADDR = 0x00000000
|
||||
PARAMETER C_MEM0_HIGHADDR = 0x000fffff
|
||||
BUS_INTERFACE SPLB = plb
|
||||
PORT Mem_A = fpga_0_SRAM_256Kx32_Mem_A_split
|
||||
PORT Mem_BEN = fpga_0_SRAM_256Kx32_Mem_BEN
|
||||
PORT Mem_WEN = fpga_0_SRAM_256Kx32_Mem_WEN
|
||||
PORT Mem_DQ = fpga_0_SRAM_256Kx32_Mem_DQ
|
||||
PORT Mem_OEN = fpga_0_SRAM_256Kx32_Mem_OEN
|
||||
PORT Mem_CEN = fpga_0_SRAM_256Kx32_Mem_CEN
|
||||
PORT Mem_ADV_LDN = fpga_0_SRAM_256Kx32_Mem_ADV_LDN
|
||||
END
|
||||
|
||||
BEGIN plb_bram_if_cntlr
|
||||
PARAMETER INSTANCE = plb_bram_if_cntlr_1
|
||||
PARAMETER HW_VER = 1.00.b
|
||||
PARAMETER c_include_burst_cacheln_support = 0
|
||||
PARAMETER c_plb_clk_period_ps = 10000
|
||||
PARAMETER c_baseaddr = 0xfffff000
|
||||
PARAMETER c_highaddr = 0xffffffff
|
||||
BUS_INTERFACE SPLB = plb
|
||||
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
|
||||
END
|
||||
|
||||
BEGIN bram_block
|
||||
PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
|
||||
PARAMETER HW_VER = 1.00.a
|
||||
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
|
||||
END
|
||||
|
||||
BEGIN opb_intc
|
||||
PARAMETER INSTANCE = opb_intc_0
|
||||
PARAMETER HW_VER = 1.00.c
|
||||
PARAMETER C_BASEADDR = 0x41200000
|
||||
PARAMETER C_HIGHADDR = 0x4120ffff
|
||||
BUS_INTERFACE SOPB = opb
|
||||
PORT Irq = EICC405EXTINPUTIRQ
|
||||
PORT Intr = RS232_Uart_Interrupt
|
||||
END
|
||||
|
||||
BEGIN util_bus_split
|
||||
PARAMETER INSTANCE = SRAM_256Kx32_util_bus_split_0
|
||||
PARAMETER HW_VER = 1.00.a
|
||||
PARAMETER C_SIZE_IN = 32
|
||||
PARAMETER C_LEFT_POS = 9
|
||||
PARAMETER C_SPLIT = 30
|
||||
PORT Sig = fpga_0_SRAM_256Kx32_Mem_A_split
|
||||
PORT Out1 = fpga_0_SRAM_256Kx32_Mem_A
|
||||
END
|
||||
|
||||
BEGIN dcm_module
|
||||
PARAMETER INSTANCE = dcm_0
|
||||
PARAMETER HW_VER = 1.00.a
|
||||
PARAMETER C_CLK0_BUF = TRUE
|
||||
PARAMETER C_CLKIN_PERIOD = 10.000000
|
||||
PARAMETER C_CLK_FEEDBACK = 1X
|
||||
PARAMETER C_DLL_FREQUENCY_MODE = LOW
|
||||
PARAMETER C_EXT_RESET_HIGH = 1
|
||||
PORT CLKIN = dcm_clk_s
|
||||
PORT CLK0 = sys_clk_s
|
||||
PORT CLKFB = sys_clk_s
|
||||
PORT RST = net_gnd
|
||||
PORT LOCKED = dcm_0_lock
|
||||
END
|
||||
|
||||
@ -1,82 +0,0 @@
|
||||
|
||||
PARAMETER VERSION = 2.2.0
|
||||
|
||||
|
||||
BEGIN OS
|
||||
PARAMETER OS_NAME = standalone
|
||||
PARAMETER OS_VER = 1.00.a
|
||||
PARAMETER PROC_INSTANCE = ppc405_0
|
||||
END
|
||||
|
||||
|
||||
BEGIN PROCESSOR
|
||||
PARAMETER DRIVER_NAME = cpu_ppc405
|
||||
PARAMETER DRIVER_VER = 1.00.a
|
||||
PARAMETER HW_INSTANCE = ppc405_0
|
||||
PARAMETER COMPILER = powerpc-eabi-gcc
|
||||
PARAMETER ARCHIVER = powerpc-eabi-ar
|
||||
PARAMETER CORE_CLOCK_FREQ_HZ = 100000000
|
||||
END
|
||||
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = generic
|
||||
PARAMETER DRIVER_VER = 1.00.a
|
||||
PARAMETER HW_INSTANCE = jtagppc_0
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = plbarb
|
||||
PARAMETER DRIVER_VER = 1.01.a
|
||||
PARAMETER HW_INSTANCE = plb
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = opbarb
|
||||
PARAMETER DRIVER_VER = 1.02.a
|
||||
PARAMETER HW_INSTANCE = opb
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = plb2opb
|
||||
PARAMETER DRIVER_VER = 1.00.a
|
||||
PARAMETER HW_INSTANCE = plb2opb
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = uartlite
|
||||
PARAMETER DRIVER_VER = 1.01.a
|
||||
PARAMETER HW_INSTANCE = RS232_Uart
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = gpio
|
||||
PARAMETER DRIVER_VER = 2.01.a
|
||||
PARAMETER HW_INSTANCE = LEDs_4Bit
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = gpio
|
||||
PARAMETER DRIVER_VER = 2.01.a
|
||||
PARAMETER HW_INSTANCE = LEDs_Positions
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = emc
|
||||
PARAMETER DRIVER_VER = 2.00.a
|
||||
PARAMETER HW_INSTANCE = SRAM_256Kx32
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = bram
|
||||
PARAMETER DRIVER_VER = 1.00.a
|
||||
PARAMETER HW_INSTANCE = plb_bram_if_cntlr_1
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = intc
|
||||
PARAMETER DRIVER_VER = 1.00.c
|
||||
PARAMETER HW_INSTANCE = opb_intc_0
|
||||
END
|
||||
|
||||
|
||||
@ -1,75 +0,0 @@
|
||||
#Please do not modify this file by hand
|
||||
XmpVersion: 8.2.02
|
||||
IntStyle: default
|
||||
MHS File: system.mhs
|
||||
MSS File: system.mss
|
||||
NPL File: projnav/system.ise
|
||||
Architecture: virtex4
|
||||
Device: xc4vfx12
|
||||
Package: ff668
|
||||
SpeedGrade: -10
|
||||
UseProjNav: 0
|
||||
PNImportBitFile:
|
||||
PNImportBmmFile:
|
||||
UserCmd1:
|
||||
UserCmd1Type: 0
|
||||
UserCmd2:
|
||||
UserCmd2Type: 0
|
||||
TopInst: system_i
|
||||
ReloadPbde: 0
|
||||
MainMhsEditor: 0
|
||||
InsertNoPads: 0
|
||||
WarnForEAArch: 1
|
||||
HdlLang: VHDL
|
||||
Simulator: mti
|
||||
SimModel: BEHAVIORAL
|
||||
SimXLib:
|
||||
SimEdkLib:
|
||||
MixLangSim: 1
|
||||
UcfFile: data/system.ucf
|
||||
FpgaImpMode: 0
|
||||
ShowLicenseDialog: 1
|
||||
ICacheAddr: SRAM_256Kx32,C_MEM0_BASEADDR
|
||||
DCacheAddr: SRAM_256Kx32,C_MEM0_BASEADDR
|
||||
Processor: ppc405_0
|
||||
BootLoop: 0
|
||||
XmdStub: 0
|
||||
SwProj: RTOSDemo
|
||||
Processor: ppc405_0
|
||||
Executable: RTOSDemo/executable.elf
|
||||
Source: RTOSDemo/main.c
|
||||
Source: RTOSDemo/serial/serial.c
|
||||
Source: RTOSDemo/partest/partest.c
|
||||
Source: RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c
|
||||
Source: RTOSDemo/../../../Source/tasks.c
|
||||
Source: RTOSDemo/../../../Source/list.c
|
||||
Source: RTOSDemo/../../../Source/queue.c
|
||||
Source: RTOSDemo/../../../Source/portable/MemMang/heap_2.c
|
||||
Source: RTOSDemo/../../Common/Minimal/flash.c
|
||||
Source: RTOSDemo/../../Common/Minimal/blocktim.c
|
||||
Source: RTOSDemo/../../Common/Minimal/dynamic.c
|
||||
Source: RTOSDemo/../../Common/Minimal/flop.c
|
||||
Source: RTOSDemo/../../Common/Minimal/GenQTest.c
|
||||
Source: RTOSDemo/../../Common/Minimal/integer.c
|
||||
Source: RTOSDemo/../../Common/Minimal/QPeek.c
|
||||
Source: RTOSDemo/../../Common/Minimal/semtest.c
|
||||
Source: RTOSDemo/../../Common/Minimal/BlockQ.c
|
||||
Source: RTOSDemo/../../Common/Minimal/death.c
|
||||
Source: RTOSDemo/../../Common/Minimal/comtest.c
|
||||
Source: RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S
|
||||
Header: RTOSDemo/FreeRTOSConfig.h
|
||||
DefaultInit: EXECUTABLE
|
||||
InitBram: 0
|
||||
Active: 1
|
||||
CompilerOptLevel: 4
|
||||
GlobPtrOpt: 0
|
||||
DebugSym: 1
|
||||
ProfileFlag: 0
|
||||
SearchIncl: . ./RTOSDemo/ ../Common/include/ ../../Source/include/ ./ppc405_0/include/ ./ppc405_0/include
|
||||
ProgStart:
|
||||
StackSize:
|
||||
HeapSize:
|
||||
LinkerScript: RTOSDemo/RTOSDemo.ld
|
||||
ProgCCFlags: -D GCC_PPC405 -mregnames -Xlinker -Map=rtosdemo.map -Wall
|
||||
CompileInXps: 1
|
||||
NonXpsApp: 0
|
||||
@ -1,134 +0,0 @@
|
||||
#################################################################
|
||||
# Makefile generated by Xilinx Platform Studio
|
||||
# Project:C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_Xilinx_Virtex4_GCC\system.xmp
|
||||
#################################################################
|
||||
|
||||
XILINX_EDK_DIR = C:/devtools/XilinxEDK
|
||||
|
||||
SYSTEM = system
|
||||
|
||||
MHSFILE = system.mhs
|
||||
|
||||
MSSFILE = system.mss
|
||||
|
||||
FPGA_ARCH = virtex4
|
||||
|
||||
DEVICE = xc4vfx12ff668-10
|
||||
|
||||
LANGUAGE = vhdl
|
||||
|
||||
SEARCHPATHOPT =
|
||||
|
||||
SUBMODULE_OPT =
|
||||
|
||||
PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT)
|
||||
|
||||
LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT)
|
||||
|
||||
VPGEN_OPTIONS = -p $(DEVICE) $(SEARCHPATHOPT)
|
||||
|
||||
RTOSDEMO_OUTPUT_DIR = RTOSDemo
|
||||
RTOSDEMO_OUTPUT = $(RTOSDEMO_OUTPUT_DIR)/executable.elf
|
||||
|
||||
MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf
|
||||
PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf
|
||||
PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf
|
||||
BOOTLOOP_DIR = bootloops
|
||||
|
||||
PPC405_0_BOOTLOOP = $(BOOTLOOP_DIR)/ppc405_0.elf
|
||||
|
||||
BRAMINIT_ELF_FILES =
|
||||
BRAMINIT_ELF_FILE_ARGS =
|
||||
|
||||
ALL_USER_ELF_FILES = $(RTOSDEMO_OUTPUT)
|
||||
|
||||
SIM_CMD = vsim
|
||||
|
||||
BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM).do
|
||||
|
||||
STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM).do
|
||||
|
||||
TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM).do
|
||||
|
||||
DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)
|
||||
|
||||
MIX_LANG_SIM_OPT = -mixed yes
|
||||
|
||||
SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -s mti
|
||||
|
||||
|
||||
LIBRARIES = \
|
||||
ppc405_0/lib/libxil.a
|
||||
VPEXEC = virtualplatform/vpexec.exe
|
||||
|
||||
LIBSCLEAN_TARGETS = ppc405_0_libsclean
|
||||
|
||||
PROGRAMCLEAN_TARGETS = RTOSDemo_programclean
|
||||
|
||||
CORE_STATE_DEVELOPMENT_FILES =
|
||||
|
||||
WRAPPER_NGC_FILES = implementation/ppc405_0_wrapper.ngc \
|
||||
implementation/jtagppc_0_wrapper.ngc \
|
||||
implementation/reset_block_wrapper.ngc \
|
||||
implementation/plb_wrapper.ngc \
|
||||
implementation/opb_wrapper.ngc \
|
||||
implementation/plb2opb_wrapper.ngc \
|
||||
implementation/rs232_uart_wrapper.ngc \
|
||||
implementation/leds_4bit_wrapper.ngc \
|
||||
implementation/leds_positions_wrapper.ngc \
|
||||
implementation/sram_256kx32_wrapper.ngc \
|
||||
implementation/plb_bram_if_cntlr_1_wrapper.ngc \
|
||||
implementation/plb_bram_if_cntlr_1_bram_wrapper.ngc \
|
||||
implementation/opb_intc_0_wrapper.ngc \
|
||||
implementation/sram_256kx32_util_bus_split_0_wrapper.ngc \
|
||||
implementation/dcm_0_wrapper.ngc
|
||||
|
||||
POSTSYN_NETLIST = implementation/$(SYSTEM).ngc
|
||||
|
||||
SYSTEM_BIT = implementation/$(SYSTEM).bit
|
||||
|
||||
DOWNLOAD_BIT = implementation/download.bit
|
||||
|
||||
SYSTEM_ACE = implementation/$(SYSTEM).ace
|
||||
|
||||
UCF_FILE = data/system.ucf
|
||||
|
||||
BMM_FILE = implementation/$(SYSTEM).bmm
|
||||
|
||||
BITGEN_UT_FILE = etc/bitgen.ut
|
||||
|
||||
XFLOW_OPT_FILE = etc/fast_runtime.opt
|
||||
XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE)
|
||||
|
||||
XPLORER_DEPENDENCY = __xps/xplorer.opt
|
||||
XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7
|
||||
|
||||
FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(BITGEN_UT_FILE) $(XFLOW_DEPENDENCY)
|
||||
|
||||
#################################################################
|
||||
# SOFTWARE APPLICATION RTOSDEMO
|
||||
#################################################################
|
||||
|
||||
RTOSDEMO_SOURCES = RTOSDemo/main.c RTOSDemo/serial/serial.c RTOSDemo/partest/partest.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c RTOSDemo/../../../Source/tasks.c RTOSDemo/../../../Source/list.c RTOSDemo/../../../Source/queue.c RTOSDemo/../../../Source/portable/MemMang/heap_2.c RTOSDemo/../../Common/Minimal/flash.c RTOSDemo/../../Common/Minimal/blocktim.c RTOSDemo/../../Common/Minimal/dynamic.c RTOSDemo/../../Common/Minimal/flop.c RTOSDemo/../../Common/Minimal/GenQTest.c RTOSDemo/../../Common/Minimal/integer.c RTOSDemo/../../Common/Minimal/QPeek.c RTOSDemo/../../Common/Minimal/semtest.c RTOSDemo/../../Common/Minimal/BlockQ.c RTOSDemo/../../Common/Minimal/death.c RTOSDemo/../../Common/Minimal/comtest.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S
|
||||
|
||||
RTOSDEMO_HEADERS = RTOSDemo/FreeRTOSConfig.h
|
||||
|
||||
RTOSDEMO_CC = powerpc-eabi-gcc
|
||||
RTOSDEMO_CC_SIZE = powerpc-eabi-size
|
||||
RTOSDEMO_CC_OPT = -Os
|
||||
RTOSDEMO_CFLAGS = -D GCC_PPC405 -mregnames -Xlinker -Map=rtosdemo.map -Wall
|
||||
RTOSDEMO_CC_SEARCH = # -B
|
||||
RTOSDEMO_LIBPATH = -L./ppc405_0/lib/ # -L
|
||||
RTOSDEMO_INCLUDES = -I./ppc405_0/include/ -IRTOSDemo/ -I. -I./RTOSDemo/ -I../Common/include/ -I../../Source/include/ -I./ppc405_0/include/ -I./ppc405_0/include
|
||||
RTOSDEMO_LFLAGS = # -l
|
||||
RTOSDEMO_LINKER_SCRIPT = RTOSDemo/RTOSDemo.ld
|
||||
RTOSDEMO_LINKER_SCRIPT_FLAG = -Wl,-T -Wl,$(RTOSDEMO_LINKER_SCRIPT)
|
||||
RTOSDEMO_CC_DEBUG_FLAG = -g
|
||||
RTOSDEMO_CC_PROFILE_FLAG = # -pg
|
||||
RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi
|
||||
RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR=
|
||||
RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE=
|
||||
RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE=
|
||||
RTOSDEMO_OTHER_CC_FLAGS= $(RTOSDEMO_CC_GLOBPTR_FLAG) \
|
||||
$(RTOSDEMO_CC_START_ADDR_FLAG) $(RTOSDEMO_CC_STACK_SIZE_FLAG) $(RTOSDEMO_CC_HEAP_SIZE_FLAG) \
|
||||
$(RTOSDEMO_LINKER_SCRIPT_FLAG) $(RTOSDEMO_CC_DEBUG_FLAG) $(RTOSDEMO_CC_PROFILE_FLAG)
|
||||
Loading…
Reference in New Issue