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Add GCC project for Infineon XMC4500 Hexagon kit CPU board.

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Richard Barry 13 years ago
parent c86abdb67c
commit b22ee3c997
20 changed files with 34402 additions and 0 deletions
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115
Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/.cproject
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70
Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/.project
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12
Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/.settings/com.atollic.truestudio.debug.hardware_device.prefs
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#Mon Mar 05 15:53:25 GMT 2012
BOARD=IFX_XMC4500
CODE_LOCATION=FLASH
ENDIAN=Little-endian
MCU=XMC4500-E144x1024
MCU_VENDOR=Infineon
MODEL=Pro
PROBE=IAR J-LINK
PROJECT_FORMAT_VERSION=2
TARGET=ARM\u00AE
VERSION=3.0.0
eclipse.preferences.version=1

12
Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/.settings/org.eclipse.cdt.managedbuilder.core.prefs
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#Mon Mar 05 15:57:25 GMT 2012
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Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/CMSIS/Include/arm_common_tables.h
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/* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved.
*
* $Date: 11. November 2010
* $Revision: V1.0.2
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Version 1.0.2 2010/11/11
* Documentation updated.
*
* Version 1.0.1 2010/10/05
* Production release and review comments incorporated.
*
* Version 1.0.0 2010/09/20
* Production release and review comments incorporated.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern uint16_t armBitRevTable[256];
extern q15_t armRecipTableQ15[64];
extern q31_t armRecipTableQ31[64];
extern const q31_t realCoefAQ31[1024];
extern const q31_t realCoefBQ31[1024];
#endif /* ARM_COMMON_TABLES_H */

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Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/CMSIS/Include/core_cm4.h
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Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/CMSIS/Include/core_cm4_simd.h
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/**************************************************************************//**
* @file core_cm4_simd.h
* @brief CMSIS Cortex-M4 SIMD Header File
* @version V2.10
* @date 19. July 2011
*
* @note
* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM4_SIMD_H
#define __CORE_CM4_SIMD_H
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
/* intrinsic __SADD8 see intrinsics.h */
/* intrinsic __QADD8 see intrinsics.h */
/* intrinsic __SHADD8 see intrinsics.h */
/* intrinsic __UADD8 see intrinsics.h */
/* intrinsic __UQADD8 see intrinsics.h */
/* intrinsic __UHADD8 see intrinsics.h */
/* intrinsic __SSUB8 see intrinsics.h */
/* intrinsic __QSUB8 see intrinsics.h */
/* intrinsic __SHSUB8 see intrinsics.h */
/* intrinsic __USUB8 see intrinsics.h */
/* intrinsic __UQSUB8 see intrinsics.h */
/* intrinsic __UHSUB8 see intrinsics.h */
/* intrinsic __SADD16 see intrinsics.h */
/* intrinsic __QADD16 see intrinsics.h */
/* intrinsic __SHADD16 see intrinsics.h */
/* intrinsic __UADD16 see intrinsics.h */
/* intrinsic __UQADD16 see intrinsics.h */
/* intrinsic __UHADD16 see intrinsics.h */
/* intrinsic __SSUB16 see intrinsics.h */
/* intrinsic __QSUB16 see intrinsics.h */
/* intrinsic __SHSUB16 see intrinsics.h */
/* intrinsic __USUB16 see intrinsics.h */
/* intrinsic __UQSUB16 see intrinsics.h */
/* intrinsic __UHSUB16 see intrinsics.h */
/* intrinsic __SASX see intrinsics.h */
/* intrinsic __QASX see intrinsics.h */
/* intrinsic __SHASX see intrinsics.h */
/* intrinsic __UASX see intrinsics.h */
/* intrinsic __UQASX see intrinsics.h */
/* intrinsic __UHASX see intrinsics.h */
/* intrinsic __SSAX see intrinsics.h */
/* intrinsic __QSAX see intrinsics.h */
/* intrinsic __SHSAX see intrinsics.h */
/* intrinsic __USAX see intrinsics.h */
/* intrinsic __UQSAX see intrinsics.h */
/* intrinsic __UHSAX see intrinsics.h */
/* intrinsic __USAD8 see intrinsics.h */
/* intrinsic __USADA8 see intrinsics.h */
/* intrinsic __SSAT16 see intrinsics.h */
/* intrinsic __USAT16 see intrinsics.h */
/* intrinsic __UXTB16 see intrinsics.h */
/* intrinsic __SXTB16 see intrinsics.h */
/* intrinsic __UXTAB16 see intrinsics.h */
/* intrinsic __SXTAB16 see intrinsics.h */
/* intrinsic __SMUAD see intrinsics.h */
/* intrinsic __SMUADX see intrinsics.h */
/* intrinsic __SMLAD see intrinsics.h */
/* intrinsic __SMLADX see intrinsics.h */
/* intrinsic __SMLALD see intrinsics.h */
/* intrinsic __SMLALDX see intrinsics.h */
/* intrinsic __SMUSD see intrinsics.h */
/* intrinsic __SMUSDX see intrinsics.h */
/* intrinsic __SMLSD see intrinsics.h */
/* intrinsic __SMLSDX see intrinsics.h */
/* intrinsic __SMLSLD see intrinsics.h */
/* intrinsic __SMLSLDX see intrinsics.h */
/* intrinsic __SEL see intrinsics.h */
/* intrinsic __QADD see intrinsics.h */
/* intrinsic __QSUB see intrinsics.h */
/* intrinsic __PKHBT see intrinsics.h */
/* intrinsic __PKHTB see intrinsics.h */
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SSAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SMLALD(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
#define __SMLALDX(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SMLSLD(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
#define __SMLSLDX(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#define __PKHBT(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
/* not yet supported */
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CORE_CM4_SIMD_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V2.10
* @date 26. July 2011
*
* @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
static __INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
static __INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
static __INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
static __INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
static __INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
static __INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
static __INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
static __INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
static __INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
static __INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
static __INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
static __INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V2.10
* @date 19. July 2011
*
* @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
static __INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
static __INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/CMSIS/Infineon/XMC4500_series/Include/XMC4500.h
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Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/CMSIS/Infineon/XMC4500_series/Include/gpio.h
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//*****************************************************************************
// To configure the same pin 1 of port 0, write
// Control_P0_1(mode, drivestrength); where the mode is INPUT, INPUT_PD ...
// OUTPUT_PP_GP ... OUTPUT_ODAF4. (see definitions below)
// and drivestrength is WEAK, MEDIUM, STRONG or VERYSTRONG
//
// To toggle reset or set a pin you need to call the macro and put in brackets
// the name of the port pin.
// Example: you want to toggle, reset and set pin 1 of port:
// Toggle(P0_1);
// Reset(P0_1);
// Set(P0_1);
//*****************************************************************************
#ifndef __GPIO_H__
#define __GPIO_H__
#include <XMC4500.h>
#define INPUT 0x00
#define INPUT_PD 0x01
#define INPUT_PU 0x02
#define INPUT_PPS 0x03
#define INPUT_INV 0x04
#define INPUT_INV_PD 0x05
#define INPUT_INV_PU 0x06
#define INPUT_INV_PPS 0x07
#define OUTPUT_PP_GP 0x10
#define OUTPUT_PP_AF1 0x11
#define OUTPUT_PP_AF2 0x12
#define OUTPUT_PP_AF3 0x13
#define OUTPUT_PP_AF4 0x14
#define OUTPUT_OD_GP 0x18
#define OUTPUT_OD_AF1 0x19
#define OUTPUT_OD_AF2 0x1A
#define OUTPUT_OD_AF3 0x1B
#define OUTPUT_OD_AF4 0X1C
#define WEAK 0x7
#define MEDIUM 0x4
#define STRONG 0x2
#define VERYSTRONG 0x0
#define Set(PinName) SET_##PinName
#define Reset(PinName) RESET_##PinName
#define Toggle(PinName) TOGGLE_##PinName
#define SET_P0_0 PORT0->OMR = 0x00000001
#define SET_P0_1 PORT0->OMR = 0x00000002
#define SET_P0_2 PORT0->OMR = 0x00000004
#define SET_P0_3 PORT0->OMR = 0x00000008
#define SET_P0_4 PORT0->OMR = 0x00000010
#define SET_P0_5 PORT0->OMR = 0x00000020
#define SET_P0_6 PORT0->OMR = 0x00000040
#define SET_P0_7 PORT0->OMR = 0x00000080
#define SET_P0_8 PORT0->OMR = 0x00000100
#define SET_P0_9 PORT0->OMR = 0x00000200
#define SET_P0_10 PORT0->OMR = 0x00000400
#define SET_P0_11 PORT0->OMR = 0x00000800
#define SET_P0_12 PORT0->OMR = 0x00001000
#define SET_P0_13 PORT0->OMR = 0x00002000
#define SET_P0_14 PORT0->OMR = 0x00004000
#define SET_P0_15 PORT0->OMR = 0x00008000
#define RESET_P0_0 PORT0->OMR = 0x00010000
#define RESET_P0_1 PORT0->OMR = 0x00020000
#define RESET_P0_2 PORT0->OMR = 0x00040000
#define RESET_P0_3 PORT0->OMR = 0x00080000
#define RESET_P0_4 PORT0->OMR = 0x00100000
#define RESET_P0_5 PORT0->OMR = 0x00200000
#define RESET_P0_6 PORT0->OMR = 0x00400000
#define RESET_P0_7 PORT0->OMR = 0x00800000
#define RESET_P0_8 PORT0->OMR = 0x01000000
#define RESET_P0_9 PORT0->OMR = 0x02000000
#define RESET_P0_10 PORT0->OMR = 0x04000000
#define RESET_P0_11 PORT0->OMR= 0x08000000
#define RESET_P0_12 PORT0->OMR = 0x10000000
#define RESET_P0_13 PORT0->OMR = 0x20000000
#define RESET_P0_14 PORT0->OMR = 0x40000000
#define RESET_P0_15 PORT0->OMR = 0x80000000
#define TOGGLE_P0_0 PORT0->OMR = 0x00010001
#define TOGGLE_P0_1 PORT0->OMR = 0x00020002
#define TOGGLE_P0_2 PORT0->OMR = 0x00040004
#define TOGGLE_P0_3 PORT0->OMR = 0x00080008
#define TOGGLE_P0_4 PORT0->OMR = 0x00100010
#define TOGGLE_P0_5 PORT0->OMR = 0x00200020
#define TOGGLE_P0_6 PORT0->OMR = 0x00400040
#define TOGGLE_P0_7 PORT0->OMR = 0x00800080
#define TOGGLE_P0_8 PORT0->OMR = 0x01000100
#define TOGGLE_P0_9 PORT0->OMR = 0x02000200
#define TOGGLE_P0_10 PORT0->OMR = 0x04000400
#define TOGGLE_P0_11 PORT0->OMR = 0x08000800
#define TOGGLE_P0_12 PORT0->OMR = 0x10001000
#define TOGGLE_P0_13 PORT0->OMR = 0x20002000
#define TOGGLE_P0_14 PORT0->OMR = 0x40004000
#define TOGGLE_P0_15 PORT0->OMR = 0x80008000
#define Control_P0_0(Mode, DriveStrength) PORT0->IOCR0 = (PORT0->IOCR0 & ~0x000000F8) | (Mode << 3); PORT0->PDR0 = (PORT0->PDR0 & ~0x00000007) | (DriveStrength)
#define Control_P0_1(Mode, DriveStrength) PORT0->IOCR0 = (PORT0->IOCR0 & ~0x0000F800) | (Mode << 11); PORT0->PDR0 = (PORT0->PDR0 & ~0x00000070) | (DriveStrength << 4)
#define Control_P0_2(Mode, DriveStrength) PORT0->IOCR0 = (PORT0->IOCR0 & ~0x00F80000) | (Mode << 19); PORT0->PDR0 = (PORT0->PDR0 & ~0x00000700) | (DriveStrength << 8)
#define Control_P0_3(Mode, DriveStrength) PORT0->IOCR0 = (PORT0->IOCR0 & ~0xF8000000) | (Mode << 27); PORT0->PDR0 = (PORT0->PDR0 & ~0x00007000) | (DriveStrength << 12)
#define Control_P0_4(Mode, DriveStrength) PORT0->IOCR4 = (PORT0->IOCR4 & ~0x000000F8) | (Mode << 3); PORT0->PDR0 = (PORT0->PDR0 & ~0x00070000) | (DriveStrength << 16)
#define Control_P0_5(Mode, DriveStrength) PORT0->IOCR4 = (PORT0->IOCR4 & ~0x0000F800) | (Mode << 11); PORT0->PDR0 = (PORT0->PDR0 & ~0x00700000) | (DriveStrength << 20)
#define Control_P0_6(Mode, DriveStrength) PORT0->IOCR4 = (PORT0->IOCR4 & ~0x00F80000) | (Mode << 19); PORT0->PDR0 = (PORT0->PDR0 & ~0x07000000) | (DriveStrength << 24)
#define Control_P0_7(Mode, DriveStrength) PORT0->IOCR4 = (PORT0->IOCR4 & ~0xF8000000) | (Mode << 27); PORT0->PDR0 = (PORT0->PDR0 & ~0x70000000) | (DriveStrength << 28)
#define Control_P0_8(Mode, DriveStrength) PORT0->IOCR8 = (PORT0->IOCR8 & ~0x000000F8) | (Mode << 3); PORT0->PDR1 = (PORT0->PDR1 & ~0x00000007) | (DriveStrength)
#define Control_P0_9(Mode, DriveStrength) PORT0->IOCR8 = (PORT0->IOCR8 & ~0x0000F800) | (Mode << 11); PORT0->PDR1 = (PORT0->PDR1 & ~0x00000070) | (DriveStrength << 4)
#define Control_P0_10(Mode, DriveStrength) PORT0->IOCR8 = (PORT0->IOCR8 & ~0x00F80000) | (Mode << 19); PORT0->PDR1 = (PORT0->PDR1 & ~0x00000700) | (DriveStrength << 8)
#define Control_P0_11(Mode, DriveStrength) PORT0->IOCR8 = (PORT0->IOCR8 & ~0xF8000000) | (Mode << 27); PORT0->PDR1 = (PORT0->PDR1 & ~0x00007000) | (DriveStrength << 12)
#define Control_P0_12(Mode, DriveStrength) PORT0->IOCR12 = (PORT0->IOCR12 & ~0x000000F8) | (Mode << 3); PORT0->PDR1 = (PORT0->PDR1 & ~0x00070000) | (DriveStrength << 16)
#define Control_P0_13(Mode, DriveStrength) PORT0->IOCR12 = (PORT0->IOCR12 & ~0x0000F800) | (Mode << 11); PORT0->PDR1 = (PORT0->PDR1 & ~0x00700000) | (DriveStrength << 20)
#define Control_P0_14(Mode, DriveStrength) PORT0->IOCR12 = (PORT0->IOCR12 & ~0x00F80000) | (Mode << 19); PORT0->PDR1 = (PORT0->PDR1 & ~0x07000000) | (DriveStrength << 24)
#define Control_P0_15(Mode, DriveStrength) PORT0->IOCR12 = (PORT0->IOCR12 & ~0xF8000000) | (Mode << 27); PORT0->PDR1 = (PORT0->PDR1 & ~0x70000000) | (DriveStrength << 28)
//********************************************
#define SET_P1_0 PORT1->OMR = 0x00000001
#define SET_P1_1 PORT1->OMR = 0x00000002
#define SET_P1_2 PORT1->OMR = 0x00000004
#define SET_P1_3 PORT1->OMR = 0x00000008
#define SET_P1_4 PORT1->OMR = 0x00000010
#define SET_P1_5 PORT1->OMR = 0x00000020
#define SET_P1_6 PORT1->OMR = 0x00000040
#define SET_P1_7 PORT1->OMR = 0x00000080
#define SET_P1_8 PORT1->OMR = 0x00000100
#define SET_P1_9 PORT1->OMR = 0x00000200
#define SET_P1_10 PORT1->OMR = 0x00000400
#define SET_P1_11 PORT1->OMR = 0x00000800
#define SET_P1_12 PORT1->OMR = 0x00001000
#define SET_P1_13 PORT1->OMR = 0x00002000
#define SET_P1_14 PORT1->OMR = 0x00004000
#define SET_P1_15 PORT1->OMR = 0x00008000
#define RESET_P1_0 PORT1->OMR = 0x00010000
#define RESET_P1_1 PORT1->OMR = 0x00020000
#define RESET_P1_2 PORT1->OMR = 0x00040000
#define RESET_P1_3 PORT1->OMR = 0x00080000
#define RESET_P1_4 PORT1->OMR = 0x00100000
#define RESET_P1_5 PORT1->OMR = 0x00200000
#define RESET_P1_6 PORT1->OMR = 0x00400000
#define RESET_P1_7 PORT1->OMR = 0x00800000
#define RESET_P1_8 PORT1->OMR = 0x01000000
#define RESET_P1_9 PORT1->OMR = 0x02000000
#define RESET_P1_10 PORT1->OMR = 0x04000000
#define RESET_P1_11 PORT1->OMR= 0x08000000
#define RESET_P1_12 PORT1->OMR = 0x10000000
#define RESET_P1_13 PORT1->OMR = 0x20000000
#define RESET_P1_14 PORT1->OMR = 0x40000000
#define RESET_P1_15 PORT1->OMR = 0x80000000
#define TOGGLE_P1_0 PORT1->OMR = 0x00010001
#define TOGGLE_P1_1 PORT1->OMR = 0x00020002
#define TOGGLE_P1_2 PORT1->OMR = 0x00040004
#define TOGGLE_P1_3 PORT1->OMR = 0x00080008
#define TOGGLE_P1_4 PORT1->OMR = 0x00100010
#define TOGGLE_P1_5 PORT1->OMR = 0x00200020
#define TOGGLE_P1_6 PORT1->OMR = 0x00400040
#define TOGGLE_P1_7 PORT1->OMR = 0x00800080
#define TOGGLE_P1_8 PORT1->OMR = 0x01000100
#define TOGGLE_P1_9 PORT1->OMR = 0x02000200
#define TOGGLE_P1_10 PORT1->OMR = 0x04000400
#define TOGGLE_P1_11 PORT1->OMR = 0x08000800
#define TOGGLE_P1_12 PORT1->OMR = 0x10001000
#define TOGGLE_P1_13 PORT1->OMR = 0x20002000
#define TOGGLE_P1_14 PORT1->OMR = 0x40004000
#define TOGGLE_P1_15 PORT1->OMR = 0x80008000
#define Control_P1_0(Mode, DriveStrength) PORT1->IOCR0 = (PORT1->IOCR0 & ~0x000000F8) | (Mode << 3); PORT1->PDR0 = (PORT1->PDR0 & ~0x00000007) | (DriveStrength)
#define Control_P1_1(Mode, DriveStrength) PORT1->IOCR0 = (PORT1->IOCR0 & ~0x0000F800) | (Mode << 11); PORT1->PDR0 = (PORT1->PDR0 & ~0x00000070) | (DriveStrength << 4)
#define Control_P1_2(Mode, DriveStrength) PORT1->IOCR0 = (PORT1->IOCR0 & ~0x00F80000) | (Mode << 19); PORT1->PDR0 = (PORT1->PDR0 & ~0x00000700) | (DriveStrength << 8)
#define Control_P1_3(Mode, DriveStrength) PORT1->IOCR0 = (PORT1->IOCR0 & ~0xF8000000) | (Mode << 27); PORT1->PDR0 = (PORT1->PDR0 & ~0x00007000) | (DriveStrength << 12)
#define Control_P1_4(Mode, DriveStrength) PORT1->IOCR4 = (PORT1->IOCR4 & ~0x000000F8) | (Mode << 3); PORT1->PDR0 = (PORT1->PDR0 & ~0x00070000) | (DriveStrength << 16)
#define Control_P1_5(Mode, DriveStrength) PORT1->IOCR4 = (PORT1->IOCR4 & ~0x0000F800) | (Mode << 11); PORT1->PDR0 = (PORT1->PDR0 & ~0x00700000) | (DriveStrength << 20)
#define Control_P1_6(Mode, DriveStrength) PORT1->IOCR4 = (PORT1->IOCR4 & ~0x00F80000) | (Mode << 19); PORT1->PDR0 = (PORT1->PDR0 & ~0x07000000) | (DriveStrength << 24)
#define Control_P1_7(Mode, DriveStrength) PORT1->IOCR4 = (PORT1->IOCR4 & ~0xF8000000) | (Mode << 27); PORT1->PDR0 = (PORT1->PDR0 & ~0x70000000) | (DriveStrength << 28)
#define Control_P1_8(Mode, DriveStrength) PORT1->IOCR8 = (PORT1->IOCR8 & ~0x000000F8) | (Mode << 3); PORT1->PDR1 = (PORT1->PDR1 & ~0x00000007) | (DriveStrength)
#define Control_P1_9(Mode, DriveStrength) PORT1->IOCR8 = (PORT1->IOCR8 & ~0x0000F800) | (Mode << 11); PORT1->PDR1 = (PORT1->PDR1 & ~0x00000070) | (DriveStrength << 4)
#define Control_P1_10(Mode, DriveStrength) PORT1->IOCR8 = (PORT1->IOCR8 & ~0x00F80000) | (Mode << 19); PORT1->PDR1 = (PORT1->PDR1 & ~0x00000700) | (DriveStrength << 8)
#define Control_P1_11(Mode, DriveStrength) PORT1->IOCR8 = (PORT1->IOCR8 & ~0xF8000000) | (Mode << 27); PORT1->PDR1 = (PORT1->PDR1 & ~0x00007000) | (DriveStrength << 12)
#define Control_P1_12(Mode, DriveStrength) PORT1->IOCR12 = (PORT1->IOCR12 & ~0x000000F8) | (Mode << 3); PORT1->PDR1 = (PORT1->PDR1 & ~0x00070000) | (DriveStrength << 16)
#define Control_P1_13(Mode, DriveStrength) PORT1->IOCR12 = (PORT1->IOCR12 & ~0x0000F800) | (Mode << 11); PORT1->PDR1 = (PORT1->PDR1 & ~0x00700000) | (DriveStrength << 20)
#define Control_P1_14(Mode, DriveStrength) PORT1->IOCR12 = (PORT1->IOCR12 & ~0x00F80000) | (Mode << 19); PORT1->PDR1 = (PORT1->PDR1 & ~0x07000000) | (DriveStrength << 24)
#define Control_P1_15(Mode, DriveStrength) PORT1->IOCR12 = (PORT1->IOCR12 & ~0xF8000000) | (Mode << 27); PORT1->PDR1 = (PORT1->PDR1 & ~0x70000000) | (DriveStrength << 28)
//********************************************
#define SET_P2_0 PORT2->OMR = 0x00000001
#define SET_P2_1 PORT2->OMR = 0x00000002
#define SET_P2_2 PORT2->OMR = 0x00000004
#define SET_P2_3 PORT2->OMR = 0x00000008
#define SET_P2_4 PORT2->OMR = 0x00000010
#define SET_P2_5 PORT2->OMR = 0x00000020
#define SET_P2_6 PORT2->OMR = 0x00000040
#define SET_P2_7 PORT2->OMR = 0x00000080
#define SET_P2_8 PORT2->OMR = 0x00000100
#define SET_P2_9 PORT2->OMR = 0x00000200
#define SET_P2_10 PORT2->OMR = 0x00000400
#define SET_P2_11 PORT2->OMR = 0x00000800
#define SET_P2_12 PORT2->OMR = 0x00001000
#define SET_P2_13 PORT2->OMR = 0x00002000
#define SET_P2_14 PORT2->OMR = 0x00004000
#define SET_P2_15 PORT2->OMR = 0x00008000
#define RESET_P2_0 PORT2->OMR = 0x00010000
#define RESET_P2_1 PORT2->OMR = 0x00020000
#define RESET_P2_2 PORT2->OMR = 0x00040000
#define RESET_P2_3 PORT2->OMR = 0x00080000
#define RESET_P2_4 PORT2->OMR = 0x00100000
#define RESET_P2_5 PORT2->OMR = 0x00200000
#define RESET_P2_6 PORT2->OMR = 0x00400000
#define RESET_P2_7 PORT2->OMR = 0x00800000
#define RESET_P2_8 PORT2->OMR = 0x01000000
#define RESET_P2_9 PORT2->OMR = 0x02000000
#define RESET_P2_10 PORT2->OMR = 0x04000000
#define RESET_P2_11 PORT2->OMR= 0x08000000
#define RESET_P2_12 PORT2->OMR = 0x10000000
#define RESET_P2_13 PORT2->OMR = 0x20000000
#define RESET_P2_14 PORT2->OMR = 0x40000000
#define RESET_P2_15 PORT2->OMR = 0x80000000
#define TOGGLE_P2_0 PORT2->OMR = 0x00010001
#define TOGGLE_P2_1 PORT2->OMR = 0x00020002
#define TOGGLE_P2_2 PORT2->OMR = 0x00040004
#define TOGGLE_P2_3 PORT2->OMR = 0x00080008
#define TOGGLE_P2_4 PORT2->OMR = 0x00100010
#define TOGGLE_P2_5 PORT2->OMR = 0x00200020
#define TOGGLE_P2_6 PORT2->OMR = 0x00400040
#define TOGGLE_P2_7 PORT2->OMR = 0x00800080
#define TOGGLE_P2_8 PORT2->OMR = 0x01000100
#define TOGGLE_P2_9 PORT2->OMR = 0x02000200
#define TOGGLE_P2_10 PORT2->OMR = 0x04000400
#define TOGGLE_P2_11 PORT2->OMR = 0x08000800
#define TOGGLE_P2_12 PORT2->OMR = 0x10001000
#define TOGGLE_P2_13 PORT2->OMR = 0x20002000
#define TOGGLE_P2_14 PORT2->OMR = 0x40004000
#define TOGGLE_P2_15 PORT2->OMR = 0x80008000
#define Control_P2_0(Mode, DriveStrength) PORT2->IOCR0 = (PORT2->IOCR0 & ~0x000000F8) | (Mode << 3); PORT2->PDR0 = (PORT2->PDR0 & ~0x00000007) | (DriveStrength)
#define Control_P2_1(Mode, DriveStrength) PORT2->IOCR0 = (PORT2->IOCR0 & ~0x0000F800) | (Mode << 11); PORT2->PDR0 = (PORT2->PDR0 & ~0x00000070) | (DriveStrength << 4)
#define Control_P2_2(Mode, DriveStrength) PORT2->IOCR0 = (PORT2->IOCR0 & ~0x00F80000) | (Mode << 19); PORT2->PDR0 = (PORT2->PDR0 & ~0x00000700) | (DriveStrength << 8)
#define Control_P2_3(Mode, DriveStrength) PORT2->IOCR0 = (PORT2->IOCR0 & ~0xF8000000) | (Mode << 27); PORT2->PDR0 = (PORT2->PDR0 & ~0x00007000) | (DriveStrength << 12)
#define Control_P2_4(Mode, DriveStrength) PORT2->IOCR4 = (PORT2->IOCR4 & ~0x000000F8) | (Mode << 3); PORT2->PDR0 = (PORT2->PDR0 & ~0x00070000) | (DriveStrength << 16)
#define Control_P2_5(Mode, DriveStrength) PORT2->IOCR4 = (PORT2->IOCR4 & ~0x0000F800) | (Mode << 11); PORT2->PDR0 = (PORT2->PDR0 & ~0x00700000) | (DriveStrength << 20)
#define Control_P2_6(Mode, DriveStrength) PORT2->IOCR4 = (PORT2->IOCR4 & ~0x00F80000) | (Mode << 19); PORT2->PDR0 = (PORT2->PDR0 & ~0x07000000) | (DriveStrength << 24)
#define Control_P2_7(Mode, DriveStrength) PORT2->IOCR4 = (PORT2->IOCR4 & ~0xF8000000) | (Mode << 27); PORT2->PDR0 = (PORT2->PDR0 & ~0x70000000) | (DriveStrength << 28)
#define Control_P2_8(Mode, DriveStrength) PORT2->IOCR8 = (PORT2->IOCR8 & ~0x000000F8) | (Mode << 3); PORT2->PDR1 = (PORT2->PDR1 & ~0x00000007) | (DriveStrength)
#define Control_P2_9(Mode, DriveStrength) PORT2->IOCR8 = (PORT2->IOCR8 & ~0x0000F800) | (Mode << 11); PORT2->PDR1 = (PORT2->PDR1 & ~0x00000070) | (DriveStrength << 4)
#define Control_P2_10(Mode, DriveStrength) PORT2->IOCR8 = (PORT2->IOCR8 & ~0x00F80000) | (Mode << 19); PORT2->PDR1 = (PORT2->PDR1 & ~0x00000700) | (DriveStrength << 8)
#define Control_P2_11(Mode, DriveStrength) PORT2->IOCR8 = (PORT2->IOCR8 & ~0xF8000000) | (Mode << 27); PORT2->PDR1 = (PORT2->PDR1 & ~0x00007000) | (DriveStrength << 12)
#define Control_P2_12(Mode, DriveStrength) PORT2->IOCR12 = (PORT2->IOCR12 & ~0x000000F8) | (Mode << 3); PORT2->PDR1 = (PORT2->PDR1 & ~0x00070000) | (DriveStrength << 16)
#define Control_P2_13(Mode, DriveStrength) PORT2->IOCR12 = (PORT2->IOCR12 & ~0x0000F800) | (Mode << 11); PORT2->PDR1 = (PORT2->PDR1 & ~0x00700000) | (DriveStrength << 20)
#define Control_P2_14(Mode, DriveStrength) PORT2->IOCR12 = (PORT2->IOCR12 & ~0x00F80000) | (Mode << 19); PORT2->PDR1 = (PORT2->PDR1 & ~0x07000000) | (DriveStrength << 24)
#define Control_P2_15(Mode, DriveStrength) PORT2->IOCR12 = (PORT2->IOCR12 & ~0xF8000000) | (Mode << 27); PORT2->PDR1 = (PORT2->PDR1 & ~0x70000000) | (DriveStrength << 28)
//********************************************
#define SET_P3_0 PORT3->OMR = 0x00000001
#define SET_P3_1 PORT3->OMR = 0x00000002
#define SET_P3_2 PORT3->OMR = 0x00000004
#define SET_P3_3 PORT3->OMR = 0x00000008
#define SET_P3_4 PORT3->OMR = 0x00000010
#define SET_P3_5 PORT3->OMR = 0x00000020
#define SET_P3_6 PORT3->OMR = 0x00000040
#define SET_P3_7 PORT3->OMR = 0x00000080
#define SET_P3_8 PORT3->OMR = 0x00000100
#define SET_P3_9 PORT3->OMR = 0x00000200
#define SET_P3_10 PORT3->OMR = 0x00000400
#define SET_P3_11 PORT3->OMR = 0x00000800
#define SET_P3_12 PORT3->OMR = 0x00001000
#define SET_P3_13 PORT3->OMR = 0x00002000
#define SET_P3_14 PORT3->OMR = 0x00004000
#define SET_P3_15 PORT3->OMR = 0x00008000
#define RESET_P3_0 PORT3->OMR = 0x00010000
#define RESET_P3_1 PORT3->OMR = 0x00020000
#define RESET_P3_2 PORT3->OMR = 0x00040000
#define RESET_P3_3 PORT3->OMR = 0x00080000
#define RESET_P3_4 PORT3->OMR = 0x00100000
#define RESET_P3_5 PORT3->OMR = 0x00200000
#define RESET_P3_6 PORT3->OMR = 0x00400000
#define RESET_P3_7 PORT3->OMR = 0x00800000
#define RESET_P3_8 PORT3->OMR = 0x01000000
#define RESET_P3_9 PORT3->OMR = 0x02000000
#define RESET_P3_10 PORT3->OMR = 0x04000000
#define RESET_P3_11 PORT3->OMR= 0x08000000
#define RESET_P3_12 PORT3->OMR = 0x10000000
#define RESET_P3_13 PORT3->OMR = 0x20000000
#define RESET_P3_14 PORT3->OMR = 0x40000000
#define RESET_P3_15 PORT3->OMR = 0x80000000
#define TOGGLE_P3_0 PORT3->OMR = 0x00010001
#define TOGGLE_P3_1 PORT3->OMR = 0x00020002
#define TOGGLE_P3_2 PORT3->OMR = 0x00040004
#define TOGGLE_P3_3 PORT3->OMR = 0x00080008
#define TOGGLE_P3_4 PORT3->OMR = 0x00100010
#define TOGGLE_P3_5 PORT3->OMR = 0x00200020
#define TOGGLE_P3_6 PORT3->OMR = 0x00400040
#define TOGGLE_P3_7 PORT3->OMR = 0x00800080
#define TOGGLE_P3_8 PORT3->OMR = 0x01000100
#define TOGGLE_P3_9 PORT3->OMR = 0x02000200
#define TOGGLE_P3_10 PORT3->OMR = 0x04000400
#define TOGGLE_P3_11 PORT3->OMR = 0x08000800
#define TOGGLE_P3_12 PORT3->OMR = 0x10001000
#define TOGGLE_P3_13 PORT3->OMR = 0x20002000
#define TOGGLE_P3_14 PORT3->OMR = 0x40004000
#define TOGGLE_P3_15 PORT3->OMR = 0x80008000
#define Control_P3_0(Mode, DriveStrength) PORT3->IOCR0 = (PORT3->IOCR0 & ~0x000000F8) | (Mode << 3); PORT3->PDR0 = (PORT3->PDR0 & ~0x00000007) | (DriveStrength)
#define Control_P3_1(Mode, DriveStrength) PORT3->IOCR0 = (PORT3->IOCR0 & ~0x0000F800) | (Mode << 11); PORT3->PDR0 = (PORT3->PDR0 & ~0x00000070) | (DriveStrength << 4)
#define Control_P3_2(Mode, DriveStrength) PORT3->IOCR0 = (PORT3->IOCR0 & ~0x00F80000) | (Mode << 19); PORT3->PDR0 = (PORT3->PDR0 & ~0x00000700) | (DriveStrength << 8)
#define Control_P3_3(Mode, DriveStrength) PORT3->IOCR0 = (PORT3->IOCR0 & ~0xF8000000) | (Mode << 27); PORT3->PDR0 = (PORT3->PDR0 & ~0x00007000) | (DriveStrength << 12)
#define Control_P3_4(Mode, DriveStrength) PORT3->IOCR4 = (PORT3->IOCR4 & ~0x000000F8) | (Mode << 3); PORT3->PDR0 = (PORT3->PDR0 & ~0x00070000) | (DriveStrength << 16)
#define Control_P3_5(Mode, DriveStrength) PORT3->IOCR4 = (PORT3->IOCR4 & ~0x0000F800) | (Mode << 11); PORT3->PDR0 = (PORT3->PDR0 & ~0x00700000) | (DriveStrength << 20)
#define Control_P3_6(Mode, DriveStrength) PORT3->IOCR4 = (PORT3->IOCR4 & ~0x00F80000) | (Mode << 19); PORT3->PDR0 = (PORT3->PDR0 & ~0x07000000) | (DriveStrength << 24)
#define Control_P3_7(Mode, DriveStrength) PORT3->IOCR4 = (PORT3->IOCR4 & ~0xF8000000) | (Mode << 27); PORT3->PDR0 = (PORT3->PDR0 & ~0x70000000) | (DriveStrength << 28)
#define Control_P3_8(Mode, DriveStrength) PORT3->IOCR8 = (PORT3->IOCR8 & ~0x000000F8) | (Mode << 3); PORT3->PDR1 = (PORT3->PDR1 & ~0x00000007) | (DriveStrength)
#define Control_P3_9(Mode, DriveStrength) PORT3->IOCR8 = (PORT3->IOCR8 & ~0x0000F800) | (Mode << 11); PORT3->PDR1 = (PORT3->PDR1 & ~0x00000070) | (DriveStrength << 4)
#define Control_P3_10(Mode, DriveStrength) PORT3->IOCR8 = (PORT3->IOCR8 & ~0x00F80000) | (Mode << 19); PORT3->PDR1 = (PORT3->PDR1 & ~0x00000700) | (DriveStrength << 8)
#define Control_P3_11(Mode, DriveStrength) PORT3->IOCR8 = (PORT3->IOCR8 & ~0xF8000000) | (Mode << 27); PORT3->PDR1 = (PORT3->PDR1 & ~0x00007000) | (DriveStrength << 12)
#define Control_P3_12(Mode, DriveStrength) PORT3->IOCR12 = (PORT3->IOCR12 & ~0x000000F8) | (Mode << 3); PORT3->PDR1 = (PORT3->PDR1 & ~0x00070000) | (DriveStrength << 16)
#define Control_P3_13(Mode, DriveStrength) PORT3->IOCR12 = (PORT3->IOCR12 & ~0x0000F800) | (Mode << 11); PORT3->PDR1 = (PORT3->PDR1 & ~0x00700000) | (DriveStrength << 20)
#define Control_P3_14(Mode, DriveStrength) PORT3->IOCR12 = (PORT3->IOCR12 & ~0x00F80000) | (Mode << 19); PORT3->PDR1 = (PORT3->PDR1 & ~0x07000000) | (DriveStrength << 24)
#define Control_P3_15(Mode, DriveStrength) PORT3->IOCR12 = (PORT3->IOCR12 & ~0xF8000000) | (Mode << 27); PORT3->PDR1 = (PORT3->PDR1 & ~0x70000000) | (DriveStrength << 28)
//********************************************
#define SET_P4_0 PORT4->OMR = 0x00000001
#define SET_P4_1 PORT4->OMR = 0x00000002
#define SET_P4_2 PORT4->OMR = 0x00000004
#define SET_P4_3 PORT4->OMR = 0x00000008
#define SET_P4_4 PORT4->OMR = 0x00000010
#define SET_P4_5 PORT4->OMR = 0x00000020
#define SET_P4_6 PORT4->OMR = 0x00000040
#define SET_P4_7 PORT4->OMR = 0x00000080
#define RESET_P4_0 PORT4->OMR = 0x00010000
#define RESET_P4_1 PORT4->OMR = 0x00020000
#define RESET_P4_2 PORT4->OMR = 0x00040000
#define RESET_P4_3 PORT4->OMR = 0x00080000
#define RESET_P4_4 PORT4->OMR = 0x00100000
#define RESET_P4_5 PORT4->OMR = 0x00200000
#define RESET_P4_6 PORT4->OMR = 0x00400000
#define RESET_P4_7 PORT4->OMR = 0x00800000
#define TOGGLE_P4_0 PORT4->OMR = 0x00010001
#define TOGGLE_P4_1 PORT4->OMR = 0x00020002
#define TOGGLE_P4_2 PORT4->OMR = 0x00040004
#define TOGGLE_P4_3 PORT4->OMR = 0x00080008
#define TOGGLE_P4_4 PORT4->OMR = 0x00100010
#define TOGGLE_P4_5 PORT4->OMR = 0x00200020
#define TOGGLE_P4_6 PORT4->OMR = 0x00400040
#define TOGGLE_P4_7 PORT4->OMR = 0x00800080
#define Control_P4_0(Mode, DriveStrength) PORT4->IOCR0 = (PORT4->IOCR0 & ~0x000000F8) | (Mode << 3); PORT4->PDR0 = (PORT4->PDR0 & ~0x00000007) | (DriveStrength)
#define Control_P4_1(Mode, DriveStrength) PORT4->IOCR0 = (PORT4->IOCR0 & ~0x0000F800) | (Mode << 11); PORT4->PDR0 = (PORT4->PDR0 & ~0x00000070) | (DriveStrength << 4)
#define Control_P4_2(Mode, DriveStrength) PORT4->IOCR0 = (PORT4->IOCR0 & ~0x00F80000) | (Mode << 19); PORT4->PDR0 = (PORT4->PDR0 & ~0x00000700) | (DriveStrength << 8)
#define Control_P4_3(Mode, DriveStrength) PORT4->IOCR0 = (PORT4->IOCR0 & ~0xF8000000) | (Mode << 27); PORT4->PDR0 = (PORT4->PDR0 & ~0x00007000) | (DriveStrength << 12)
#define Control_P4_4(Mode, DriveStrength) PORT4->IOCR4 = (PORT4->IOCR4 & ~0x000000F8) | (Mode << 3); PORT4->PDR0 = (PORT4->PDR0 & ~0x00070000) | (DriveStrength << 16)
#define Control_P4_5(Mode, DriveStrength) PORT4->IOCR4 = (PORT4->IOCR4 & ~0x0000F800) | (Mode << 11); PORT4->PDR0 = (PORT4->PDR0 & ~0x00700000) | (DriveStrength << 20)
#define Control_P4_6(Mode, DriveStrength) PORT4->IOCR4 = (PORT4->IOCR4 & ~0x00F80000) | (Mode << 19); PORT4->PDR0 = (PORT4->PDR0 & ~0x07000000) | (DriveStrength << 24)
#define Control_P4_7(Mode, DriveStrength) PORT4->IOCR4 = (PORT4->IOCR4 & ~0xF8000000) | (Mode << 27); PORT4->PDR0 = (PORT4->PDR0 & ~0x70000000) | (DriveStrength << 28)
//********************************************
#define SET_P5_0 PORT5->OMR = 0x00000001
#define SET_P5_1 PORT5->OMR = 0x00000002
#define SET_P5_2 PORT5->OMR = 0x00000004
#define SET_P5_3 PORT5->OMR = 0x00000008
#define SET_P5_4 PORT5->OMR = 0x00000010
#define SET_P5_5 PORT5->OMR = 0x00000020
#define SET_P5_6 PORT5->OMR = 0x00000040
#define SET_P5_7 PORT5->OMR = 0x00000080
#define SET_P5_8 PORT5->OMR = 0x00000100
#define SET_P5_9 PORT5->OMR = 0x00000200
#define SET_P5_10 PORT5->OMR = 0x00000400
#define SET_P5_11 PORT5->OMR = 0x00000800
#define SET_P5_12 PORT5->OMR = 0x00001000
#define SET_P5_13 PORT5->OMR = 0x00002000
#define SET_P5_14 PORT5->OMR = 0x00004000
#define SET_P5_15 PORT5->OMR = 0x00008000
#define RESET_P5_0 PORT5->OMR = 0x00010000
#define RESET_P5_1 PORT5->OMR = 0x00020000
#define RESET_P5_2 PORT5->OMR = 0x00040000
#define RESET_P5_3 PORT5->OMR = 0x00080000
#define RESET_P5_4 PORT5->OMR = 0x00100000
#define RESET_P5_5 PORT5->OMR = 0x00200000
#define RESET_P5_6 PORT5->OMR = 0x00400000
#define RESET_P5_7 PORT5->OMR = 0x00800000
#define RESET_P5_8 PORT5->OMR = 0x01000000
#define RESET_P5_9 PORT5->OMR = 0x02000000
#define RESET_P5_10 PORT5->OMR = 0x04000000
#define RESET_P5_11 PORT5->OMR= 0x08000000
#define RESET_P5_12 PORT5->OMR = 0x10000000
#define RESET_P5_13 PORT5->OMR = 0x20000000
#define RESET_P5_14 PORT5->OMR = 0x40000000
#define RESET_P5_15 PORT5->OMR = 0x80000000
#define TOGGLE_P5_0 PORT5->OMR = 0x00010001
#define TOGGLE_P5_1 PORT5->OMR = 0x00020002
#define TOGGLE_P5_2 PORT5->OMR = 0x00040004
#define TOGGLE_P5_3 PORT5->OMR = 0x00080008
#define TOGGLE_P5_4 PORT5->OMR = 0x00100010
#define TOGGLE_P5_5 PORT5->OMR = 0x00200020
#define TOGGLE_P5_6 PORT5->OMR = 0x00400040
#define TOGGLE_P5_7 PORT5->OMR = 0x00800080
#define TOGGLE_P5_8 PORT5->OMR = 0x01000100
#define TOGGLE_P5_9 PORT5->OMR = 0x02000200
#define TOGGLE_P5_10 PORT5->OMR = 0x04000400
#define TOGGLE_P5_11 PORT5->OMR = 0x08000800
#define TOGGLE_P5_12 PORT5->OMR = 0x10001000
#define TOGGLE_P5_13 PORT5->OMR = 0x20002000
#define TOGGLE_P5_14 PORT5->OMR = 0x40004000
#define TOGGLE_P5_15 PORT5->OMR = 0x80008000
#define Control_P5_0(Mode, DriveStrength) PORT5->IOCR0 = (PORT5->IOCR0 & ~0x000000F8) | (Mode << 3); PORT5->PDR0 = (PORT5->PDR0 & ~0x00000007) | (DriveStrength)
#define Control_P5_1(Mode, DriveStrength) PORT5->IOCR0 = (PORT5->IOCR0 & ~0x0000F800) | (Mode << 11); PORT5->PDR0 = (PORT5->PDR0 & ~0x00000070) | (DriveStrength << 4)
#define Control_P5_2(Mode, DriveStrength) PORT5->IOCR0 = (PORT5->IOCR0 & ~0x00F80000) | (Mode << 19); PORT5->PDR0 = (PORT5->PDR0 & ~0x00000700) | (DriveStrength << 8)
#define Control_P5_3(Mode, DriveStrength) PORT5->IOCR0 = (PORT5->IOCR0 & ~0xF8000000) | (Mode << 27); PORT5->PDR0 = (PORT5->PDR0 & ~0x00007000) | (DriveStrength << 12)
#define Control_P5_4(Mode, DriveStrength) PORT5->IOCR4 = (PORT5->IOCR4 & ~0x000000F8) | (Mode << 3); PORT5->PDR0 = (PORT5->PDR0 & ~0x00070000) | (DriveStrength << 16)
#define Control_P5_5(Mode, DriveStrength) PORT5->IOCR4 = (PORT5->IOCR4 & ~0x0000F800) | (Mode << 11); PORT5->PDR0 = (PORT5->PDR0 & ~0x00700000) | (DriveStrength << 20)
#define Control_P5_6(Mode, DriveStrength) PORT5->IOCR4 = (PORT5->IOCR4 & ~0x00F80000) | (Mode << 19); PORT5->PDR0 = (PORT5->PDR0 & ~0x07000000) | (DriveStrength << 24)
#define Control_P5_7(Mode, DriveStrength) PORT5->IOCR4 = (PORT5->IOCR4 & ~0xF8000000) | (Mode << 27); PORT5->PDR0 = (PORT5->PDR0 & ~0x70000000) | (DriveStrength << 28)
#define Control_P5_8(Mode, DriveStrength) PORT5->IOCR8 = (PORT5->IOCR8 & ~0x000000F8) | (Mode << 3); PORT5->PDR1 = (PORT5->PDR1 & ~0x00000007) | (DriveStrength)
#define Control_P5_9(Mode, DriveStrength) PORT5->IOCR8 = (PORT5->IOCR8 & ~0x0000F800) | (Mode << 11); PORT5->PDR1 = (PORT5->PDR1 & ~0x00000070) | (DriveStrength << 4)
#define Control_P5_10(Mode, DriveStrength) PORT5->IOCR8 = (PORT5->IOCR8 & ~0x00F80000) | (Mode << 19); PORT5->PDR1 = (PORT5->PDR1 & ~0x00000700) | (DriveStrength << 8)
#define Control_P5_11(Mode, DriveStrength) PORT5->IOCR8 = (PORT5->IOCR8 & ~0xF8000000) | (Mode << 27); PORT5->PDR1 = (PORT5->PDR1 & ~0x00007000) | (DriveStrength << 12)
#define Control_P5_12(Mode, DriveStrength) PORT5->IOCR12 = (PORT5->IOCR12 & ~0x000000F8) | (Mode << 3); PORT5->PDR1 = (PORT5->PDR1 & ~0x00070000) | (DriveStrength << 16)
#define Control_P5_13(Mode, DriveStrength) PORT5->IOCR12 = (PORT5->IOCR12 & ~0x0000F800) | (Mode << 11); PORT5->PDR1 = (PORT5->PDR1 & ~0x00700000) | (DriveStrength << 20)
#define Control_P5_14(Mode, DriveStrength) PORT5->IOCR12 = (PORT5->IOCR12 & ~0x00F80000) | (Mode << 19); PORT5->PDR1 = (PORT5->PDR1 & ~0x07000000) | (DriveStrength << 24)
#define Control_P5_15(Mode, DriveStrength) PORT5->IOCR12 = (PORT5->IOCR12 & ~0xF8000000) | (Mode << 27); PORT5->PDR1 = (PORT5->PDR1 & ~0x70000000) | (DriveStrength << 28)
//********************************************
#define SET_P6_0 PORT6->OMR = 0x00000001
#define SET_P6_1 PORT6->OMR = 0x00000002
#define SET_P6_2 PORT6->OMR = 0x00000004
#define SET_P6_3 PORT6->OMR = 0x00000008
#define SET_P6_4 PORT6->OMR = 0x00000010
#define SET_P6_5 PORT6->OMR = 0x00000020
#define SET_P6_6 PORT6->OMR = 0x00000040
#define SET_P6_7 PORT6->OMR = 0x00000080
#define SET_P6_8 PORT6->OMR = 0x00000100
#define SET_P6_9 PORT6->OMR = 0x00000200
#define SET_P6_10 PORT6->OMR = 0x00000400
#define SET_P6_11 PORT6->OMR = 0x00000800
#define SET_P6_12 PORT6->OMR = 0x00001000
#define SET_P6_13 PORT6->OMR = 0x00002000
#define SET_P6_14 PORT6->OMR = 0x00004000
#define SET_P6_15 PORT6->OMR = 0x00008000
#define RESET_P6_0 PORT6->OMR = 0x00010000
#define RESET_P6_1 PORT6->OMR = 0x00020000
#define RESET_P6_2 PORT6->OMR = 0x00040000
#define RESET_P6_3 PORT6->OMR = 0x00080000
#define RESET_P6_4 PORT6->OMR = 0x00100000
#define RESET_P6_5 PORT6->OMR = 0x00200000
#define RESET_P6_6 PORT6->OMR = 0x00400000
#define TOGGLE_P6_0 PORT6->OMR = 0x00010001
#define TOGGLE_P6_1 PORT6->OMR = 0x00020002
#define TOGGLE_P6_2 PORT6->OMR = 0x00040004
#define TOGGLE_P6_3 PORT6->OMR = 0x00080008
#define TOGGLE_P6_4 PORT6->OMR = 0x00100010
#define TOGGLE_P6_5 PORT6->OMR = 0x00200020
#define TOGGLE_P6_6 PORT6->OMR = 0x00400040
#define Control_P6_0(Mode, DriveStrength) PORT6->IOCR0 = (PORT6->IOCR0 & ~0x000000F8) | (Mode << 3); PORT6->PDR0 = (PORT6->PDR0 & ~0x00000007) | (DriveStrength)
#define Control_P6_1(Mode, DriveStrength) PORT6->IOCR0 = (PORT6->IOCR0 & ~0x0000F800) | (Mode << 11); PORT6->PDR0 = (PORT6->PDR0 & ~0x00000070) | (DriveStrength << 4)
#define Control_P6_2(Mode, DriveStrength) PORT6->IOCR0 = (PORT6->IOCR0 & ~0x00F80000) | (Mode << 19); PORT6->PDR0 = (PORT6->PDR0 & ~0x00000700) | (DriveStrength << 8)
#define Control_P6_3(Mode, DriveStrength) PORT6->IOCR0 = (PORT6->IOCR0 & ~0xF8000000) | (Mode << 27); PORT6->PDR0 = (PORT6->PDR0 & ~0x00007000) | (DriveStrength << 12)
#define Control_P6_4(Mode, DriveStrength) PORT6->IOCR4 = (PORT6->IOCR4 & ~0x000000F8) | (Mode << 3); PORT6->PDR0 = (PORT6->PDR0 & ~0x00070000) | (DriveStrength << 16)
#define Control_P6_5(Mode, DriveStrength) PORT6->IOCR4 = (PORT6->IOCR4 & ~0x0000F800) | (Mode << 11); PORT6->PDR0 = (PORT6->PDR0 & ~0x00700000) | (DriveStrength << 20)
#define Control_P6_6(Mode, DriveStrength) PORT6->IOCR4 = (PORT6->IOCR4 & ~0x00F80000) | (Mode << 19); PORT6->PDR0 = (PORT6->PDR0 & ~0x07000000) | (DriveStrength << 24)
//********************************************
#endif

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Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/CMSIS/Infineon/XMC4500_series/Include/system_XMC4500.h
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/**************************************************************************//**
* @file system_XMC4500.h
* @brief Header file for the XMC4500-Series systeminit
*
* @version V1.4
* @date 31. Januar 2012
*
* @note
* Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
* This file can be freely distributed within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
*
******************************************************************************/
#ifndef __SYSTEM_XMC4500_H
#define __SYSTEM_XMC4500_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/* clock definitions, do not modify! */
#define SCU_CLOCK_CRYSTAL 1
/*
* mandatory clock parameters **************************************************
*/
/* source for clock generation
* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
*
**************************************************************************************/
#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
#define CLOCK_OSC_HP 24000000
#define CLOCK_CRYSTAL_FREQUENCY 12000000
#define SYSTEM_FREQUENCY 120000000
/* OSC_HP setup parameters */
#define OSC_HP_MODE 0
#define OSCHPWDGDIV 2
/* MAIN PLL setup parameters */
#define PLL_K1DIV 1
#define PLL_K2DIV 3
#define PLL_PDIV 1
#define PLL_NDIV 79
#define PLL_K2DIV_STEP_1 19 //PLL output is 24Mhz
#define PLL_K2DIV_STEP_2 7 //PLL output to 60Mhz
#define PLL_K2DIV_STEP_3 4 //PLL output to 96Mhz
#define USBPLL_PDIV 1
#define USBPLL_NDIV 15
#ifdef __cplusplus
}
#endif
#endif

149
Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/FreeRTOSConfig.h
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/*
FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#include <stdint.h>
extern uint32_t SystemCoreClock;
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( SystemCoreClock )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40960 ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 1
#define configGENERATE_RUN_TIME_STATS 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 2 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 6 /* 63 priority levels */
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x3f
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names. */
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
#define xPortSysTickHandler SysTick_Handler
#endif /* FREERTOS_CONFIG_H */

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/*
FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/******************************************************************************
* This project provides two demo applications. A simple blinky style project,
* and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
* select between the two. The simply blinky demo is implemented and described
* in main_blinky.c. The more comprehensive test and demo application is
* implemented and described in main_full.c.
*
* This file implements the code that is not demo specific, including the
* hardware setup and FreeRTOS hook functions.
*
*
* Additional code:
*
* This demo does not contain a non-kernel interrupt service routine that
* can be used as an example for application writers to use as a reference.
* Therefore, the framework of a dummy (not installed) handler is provided
* in this file. The dummy function is called Dummy_IRQHandler(). Please
* ensure to read the comments in the function itself, but more importantly,
* the notes on the function contained on the documentation page for this demo
* that is found on the FreeRTOS.org web site.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Hardware includes. */
#include "XMC4500.h"
#include "System_XMC4500.h"
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
or 0 to run the more comprehensive test and demo application. */
#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
/*-----------------------------------------------------------*/
/*
* Set up the hardware ready to run this demo.
*/
static void prvSetupHardware( void );
/*
* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
* main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
*/
extern void main_blinky( void );
extern void main_full( void );
/*-----------------------------------------------------------*/
int main( void )
{
/* Prepare the hardware to run this demo. */
prvSetupHardware();
/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
of this file. */
#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
{
main_blinky();
}
#else
{
main_full();
}
#endif
return 0;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
extern void SystemCoreClockUpdate( void );
/* Ensure SystemCoreClock variable is set. */
SystemCoreClockUpdate();
/* Configure pin P3.9 for the LED. */
PORT3->IOCR8 = 0x00008000;
/* Ensure all priority bits are assigned as preemption priority bits. */
NVIC_SetPriorityGrouping( 0 );
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* vApplicationMallocFailedHook() will only be called if
configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
function that will get called if a call to pvPortMalloc() fails.
pvPortMalloc() is called internally by the kernel whenever a task, queue,
timer or semaphore is created. It is also called by various parts of the
demo application. If heap_1.c or heap_2.c are used, then the size of the
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
to query the size of free heap space that remains (although it does not
provide information on how the remaining heap might be fragmented). */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
task. It is essential that code added to this hook function never attempts
to block in any way (for example, call xQueueReceive() with a block time
specified, or call vTaskDelay()). If the application makes use of the
vTaskDelete() API function (as this demo application does) then it is also
important that vApplicationIdleHook() is permitted to return to its calling
function, because it is the responsibility of the idle task to clean up
memory allocated by the kernel to any task that has since been deleted. */
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
function is called if a stack overflow is detected. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationTickHook( void )
{
/* This function will be called by each tick interrupt if
configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
added here, but the tick hook is called from an interrupt context, so
code must not attempt to block, and only the interrupt safe FreeRTOS API
functions can be used (those that end in FromISR()). */
}
/*-----------------------------------------------------------*/
#ifdef JUST_AN_EXAMPLE_ISR
void Dummy_IRQHandler(void)
{
long lHigherPriorityTaskWoken = pdFALSE;
/* Clear the interrupt if necessary. */
Dummy_ClearITPendingBit();
/* This interrupt does nothing more than demonstrate how to synchronise a
task with an interrupt. A semaphore is used for this purpose. Note
lHigherPriorityTaskWoken is initialised to zero. */
xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );
/* If there was a task that was blocked on the semaphore, and giving the
semaphore caused the task to unblock, and the unblocked task has a priority
higher than the current Running state task (the task that this interrupt
interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE
internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the
portEND_SWITCHING_ISR() macro will result in a context switch being pended to
ensure this interrupt returns directly to the unblocked, higher priority,
task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */
portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
}
#endif /* JUST_AN_EXAMPLE_ISR */

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/*
FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky style
* project, and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
* in main.c. This file implements the simply blinky style version.
*
* NOTE 2: This file only contains the source code that is specific to the
* basic demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware, are defined in main.c.
******************************************************************************
*
* main_blinky() creates one queue, and two tasks. It then starts the
* scheduler.
*
* The Queue Send Task:
* The queue send task is implemented by the prvQueueSendTask() function in
* this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
* block for 200 milliseconds, before sending the value 100 to the queue that
* was created within main_blinky(). Once the value is sent, the task loops
* back around to block for another 200 milliseconds.
*
* The Queue Receive Task:
* The queue receive task is implemented by the prvQueueReceiveTask() function
* in this file. prvQueueReceiveTask() sits in a loop where it repeatedly
* blocks on attempts to read data from the queue that was created within
* main_blinky(). When data is received, the task checks the value of the
* data, and if the value equals the expected 100, toggles the LED. The 'block
* time' parameter passed to the queue receive function specifies that the
* task should be held in the Blocked state indefinitely to wait for data to
* be available on the queue. The queue receive task will only leave the
* Blocked state when the queue send task writes to the queue. As the queue
* send task writes to the queue every 200 milliseconds, the queue receive
* task leaves the Blocked state every 200 milliseconds, and therefore toggles
* the LED every 200 milliseconds.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Hardware includes. */
#include "XMC4500.h"
#include "System_XMC4500.h"
/* Priorities at which the tasks are created. */
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The rate at which data is sent to the queue. The 200ms value is converted
to ticks using the portTICK_RATE_MS constant. */
#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )
/* The number of items the queue can hold. This is 1 as the receive task
will remove items as they are added, meaning the send task should always find
the queue empty. */
#define mainQUEUE_LENGTH ( 1 )
/* Values passed to the two tasks just to check the task parameter
functionality. */
#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )
#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )
/* To toggle the single LED */
#define mainTOGGLE_LED() ( PORT3->OMR = 0x02000200 )
/*-----------------------------------------------------------*/
/*
* The tasks as described in the comments at the top of this file.
*/
static void prvQueueReceiveTask( void *pvParameters );
static void prvQueueSendTask( void *pvParameters );
/*
* Called by main() to create the simply blinky style application if
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
*/
void main_blinky( void );
/*
* The hardware only has a single LED. Simply toggle it.
*/
extern void vMainToggleLED( void );
/*-----------------------------------------------------------*/
/* The queue used by both tasks. */
static xQueueHandle xQueue = NULL;
/*-----------------------------------------------------------*/
void main_blinky( void )
{
/* Create the queue. */
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
if( xQueue != NULL )
{
/* Start the two tasks as described in the comments at the top of this
file. */
xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */
mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
NULL ); /* The task handle is not required, so NULL is passed. */
xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );
/* Start the tasks and timer running. */
vTaskStartScheduler();
}
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was insufficient FreeRTOS heap memory available for the idle and/or
timer tasks to be created. See the memory management section on the
FreeRTOS web site for more details. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvQueueSendTask( void *pvParameters )
{
portTickType xNextWakeTime;
const unsigned long ulValueToSend = 100UL;
/* Check the task parameter is as expected. */
configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again.
The block time is specified in ticks, the constant used converts ticks
to ms. While in the Blocked state this task will not consume any CPU
time. */
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
/* Send to the queue - causing the queue receive task to unblock and
toggle the LED. 0 is used as the block time so the sending operation
will not block - it shouldn't need to block as the queue should always
be empty at this point in the code. */
xQueueSend( xQueue, &ulValueToSend, 0U );
}
}
/*-----------------------------------------------------------*/
static void prvQueueReceiveTask( void *pvParameters )
{
unsigned long ulReceivedValue;
/* Check the task parameter is as expected. */
configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );
for( ;; )
{
/* Wait until something arrives in the queue - this task will block
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
FreeRTOSConfig.h. */
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
/* To get here something must have been received from the queue, but
is it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == 100UL )
{
mainTOGGLE_LED();
ulReceivedValue = 0U;
}
}
}
/*-----------------------------------------------------------*/

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/*
FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky style
* project, and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
* in main.c. This file implements the comprehensive test and demo version.
*
* NOTE 2: This file only contains the source code that is specific to the
* full demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware, are defined in main.c.
******************************************************************************
*
* main_full() creates all the demo application tasks and a software timer, then
* starts the scheduler. The web documentation provides more details of the
* standard demo application tasks, which provide no particular functionality,
* but do provide a good example of how to use the FreeRTOS API.
*
* In addition to the standard demo tasks, the following tasks and tests are
* defined and/or created within this file:
*
* "Reg test" tasks - These fill both the core and floating point registers with
* known values, then check that each register maintains its expected value for
* the lifetime of the task. Each task uses a different set of values. The reg
* test tasks execute with a very low priority, so get preempted very
* frequently. A register containing an unexpected value is indicative of an
* error in the context switching mechanism.
*
* "Check" timer - The check software timer period is initially set to three
* seconds. The callback function associated with the check software timer
* checks that all the standard demo tasks, and the register check tasks, are
* not only still executing, but are executing without reporting any errors. If
* the check software timer discovers that a task has either stalled, or
* reported an error, then it changes its own execution period from the initial
* three seconds, to just 200ms. The check software timer callback function
* also toggles the single LED each time it is called. This provides a visual
* indication of the system status: If the LED toggles every three seconds,
* then no issues have been discovered. If the LED toggles every 200ms, then
* an issue has been discovered with at least one task.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "timers.h"
#include "semphr.h"
/* Standard demo application includes. */
#include "flop.h"
#include "integer.h"
#include "PollQ.h"
#include "semtest.h"
#include "dynamic.h"
#include "BlockQ.h"
#include "blocktim.h"
#include "countsem.h"
#include "GenQTest.h"
#include "recmutex.h"
#include "death.h"
/* Hardware includes. */
#include "XMC4500.h"
#include "System_XMC4500.h"
/* Priorities for the demo application tasks. */
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
/* To toggle the single LED */
#define mainTOGGLE_LED() ( PORT3->OMR = 0x02000200 )
/* A block time of zero simply means "don't block". */
#define mainDONT_BLOCK ( 0UL )
/* The period after which the check timer will expire, in ms, provided no errors
have been reported by any of the standard demo tasks. ms are converted to the
equivalent in ticks using the portTICK_RATE_MS constant. */
#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )
/* The period at which the check timer will expire, in ms, if an error has been
reported in one of the standard demo tasks. ms are converted to the equivalent
in ticks using the portTICK_RATE_MS constant. */
#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )
/*-----------------------------------------------------------*/
/*
* The check timer callback function, as described at the top of this file.
*/
static void prvCheckTimerCallback( xTimerHandle xTimer );
/*
* Register check tasks, and the tasks used to write over and check the contents
* of the FPU registers, as described at the top of this file. The nature of
* these files necessitates that they are written in an assembly file.
*/
static void vRegTest1Task( void *pvParameters ) __attribute__((naked));
static void vRegTest2Task( void *pvParameters ) __attribute__((naked));
/*-----------------------------------------------------------*/
/* The following two variables are used to communicate the status of the
register check tasks to the check software timer. If the variables keep
incrementing, then the register check tasks has not discovered any errors. If
a variable stops incrementing, then an error has been found. */
volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
/*-----------------------------------------------------------*/
void main_full( void )
{
xTimerHandle xCheckTimer = NULL;
/* Start all the other standard demo/test tasks. The have not particular
functionality, but do demonstrate how to use the FreeRTOS API and test the
kernel port. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vStartDynamicPriorityTasks();
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vCreateBlockTimeTasks();
vStartCountingSemaphoreTasks();
vStartGenericQueueTasks( tskIDLE_PRIORITY );
vStartRecursiveMutexTasks();
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartMathTasks( mainFLOP_TASK_PRIORITY );
/* Create the register check tasks, as described at the top of this
file */
xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
/* Create the software timer that performs the 'check' functionality,
as described at the top of this file. */
xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */
( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */
pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
( void * ) 0, /* The ID is not used, so can be set to anything. */
prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */
);
if( xCheckTimer != NULL )
{
xTimerStart( xCheckTimer, mainDONT_BLOCK );
}
/* The set of tasks created by the following function call have to be
created last as they keep account of the number of tasks they expect to see
running. */
vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
/* Start the scheduler. */
vTaskStartScheduler();
/* If all is well, the scheduler will now be running, and the following line
will never be reached. If the following line does execute, then there was
insufficient FreeRTOS heap memory available for the idle and/or timer tasks
to be created. See the memory management section on the FreeRTOS web site
for more details. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvCheckTimerCallback( xTimerHandle xTimer )
{
static long lChangedTimerPeriodAlready = pdFALSE;
static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
unsigned long ulErrorFound = pdFALSE;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none have detected an error. */
if( xAreMathsTaskStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if( xIsCreateTaskStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
/* Check that the register test 1 task is still running. */
if( ulLastRegTest1Value == ulRegTest1LoopCounter )
{
ulErrorFound = pdTRUE;
}
ulLastRegTest1Value = ulRegTest1LoopCounter;
/* Check that the register test 2 task is still running. */
if( ulLastRegTest2Value == ulRegTest2LoopCounter )
{
ulErrorFound = pdTRUE;
}
ulLastRegTest2Value = ulRegTest2LoopCounter;
/* Toggle the check LED to give an indication of the system status. If
the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then
everything is ok. A faster toggle indicates an error. */
mainTOGGLE_LED();
/* Have any errors been latch in ulErrorFound? If so, shorten the
period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.
This will result in an increase in the rate at which mainCHECK_LED
toggles. */
if( ulErrorFound != pdFALSE )
{
if( lChangedTimerPeriodAlready == pdFALSE )
{
lChangedTimerPeriodAlready = pdTRUE;
/* This call to xTimerChangePeriod() uses a zero block time.
Functions called from inside of a timer callback function must
*never* attempt to block. */
xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );
}
}
}
/*-----------------------------------------------------------*/
/* This is a naked function. */
static void vRegTest1Task( void *pvParameters )
{
__asm volatile
(
" /* Fill the core registers with known values. */ \n"
" mov r0, #100 \n"
" mov r1, #101 \n"
" mov r2, #102 \n"
" mov r3, #103 \n"
" mov r4, #104 \n"
" mov r5, #105 \n"
" mov r6, #106 \n"
" mov r7, #107 \n"
" mov r8, #108 \n"
" mov r9, #109 \n"
" mov r10, #110 \n"
" mov r11, #111 \n"
" mov r12, #112 \n"
" \n"
" /* Fill the VFP registers with known values. */ \n"
" vmov d0, r0, r1 \n"
" vmov d1, r2, r3 \n"
" vmov d2, r4, r5 \n"
" vmov d3, r6, r7 \n"
" vmov d4, r8, r9 \n"
" vmov d5, r10, r11 \n"
" vmov d6, r0, r1 \n"
" vmov d7, r2, r3 \n"
" vmov d8, r4, r5 \n"
" vmov d9, r6, r7 \n"
" vmov d10, r8, r9 \n"
" vmov d11, r10, r11 \n"
" vmov d12, r0, r1 \n"
" vmov d13, r2, r3 \n"
" vmov d14, r4, r5 \n"
" vmov d15, r6, r7 \n"
" \n"
"reg1_loop: \n"
" /* Check all the VFP registers still contain the values set above.\n"
" First save registers that are clobbered by the test. */ \n"
" push { r0-r1 } \n"
" \n"
" vmov r0, r1, d0 \n"
" cmp r0, #100 \n"
" bne reg1_error_loopf \n"
" cmp r1, #101 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d1 \n"
" cmp r0, #102 \n"
" bne reg1_error_loopf \n"
" cmp r1, #103 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d2 \n"
" cmp r0, #104 \n"
" bne reg1_error_loopf \n"
" cmp r1, #105 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d3 \n"
" cmp r0, #106 \n"
" bne reg1_error_loopf \n"
" cmp r1, #107 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d4 \n"
" cmp r0, #108 \n"
" bne reg1_error_loopf \n"
" cmp r1, #109 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d5 \n"
" cmp r0, #110 \n"
" bne reg1_error_loopf \n"
" cmp r1, #111 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d6 \n"
" cmp r0, #100 \n"
" bne reg1_error_loopf \n"
" cmp r1, #101 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d7 \n"
" cmp r0, #102 \n"
" bne reg1_error_loopf \n"
" cmp r1, #103 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d8 \n"
" cmp r0, #104 \n"
" bne reg1_error_loopf \n"
" cmp r1, #105 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d9 \n"
" cmp r0, #106 \n"
" bne reg1_error_loopf \n"
" cmp r1, #107 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d10 \n"
" cmp r0, #108 \n"
" bne reg1_error_loopf \n"
" cmp r1, #109 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d11 \n"
" cmp r0, #110 \n"
" bne reg1_error_loopf \n"
" cmp r1, #111 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d12 \n"
" cmp r0, #100 \n"
" bne reg1_error_loopf \n"
" cmp r1, #101 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d13 \n"
" cmp r0, #102 \n"
" bne reg1_error_loopf \n"
" cmp r1, #103 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d14 \n"
" cmp r0, #104 \n"
" bne reg1_error_loopf \n"
" cmp r1, #105 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d15 \n"
" cmp r0, #106 \n"
" bne reg1_error_loopf \n"
" cmp r1, #107 \n"
" bne reg1_error_loopf \n"
" \n"
" /* Restore the registers that were clobbered by the test. */\n"
" pop {r0-r1} \n"
" \n"
" /* VFP register test passed. Jump to the core register test. */\n"
" b reg1_loopf_pass \n"
" \n"
"reg1_error_loopf: \n"
" /* If this line is hit then a VFP register value was found to be\n"
" incorrect. */ \n"
" b reg1_error_loopf \n"
" \n"
"reg1_loopf_pass: \n"
" \n"
" cmp r0, #100 \n"
" bne reg1_error_loop \n"
" cmp r1, #101 \n"
" bne reg1_error_loop \n"
" cmp r2, #102 \n"
" bne reg1_error_loop \n"
" cmp r3, #103 \n"
" bne reg1_error_loop \n"
" cmp r4, #104 \n"
" bne reg1_error_loop \n"
" cmp r5, #105 \n"
" bne reg1_error_loop \n"
" cmp r6, #106 \n"
" bne reg1_error_loop \n"
" cmp r7, #107 \n"
" bne reg1_error_loop \n"
" cmp r8, #108 \n"
" bne reg1_error_loop \n"
" cmp r9, #109 \n"
" bne reg1_error_loop \n"
" cmp r10, #110 \n"
" bne reg1_error_loop \n"
" cmp r11, #111 \n"
" bne reg1_error_loop \n"
" cmp r12, #112 \n"
" bne reg1_error_loop \n"
" \n"
" /* Everything passed, increment the loop counter. */ \n"
" push { r0-r1 } \n"
" ldr r0, =ulRegTest1LoopCounter \n"
" ldr r1, [r0] \n"
" adds r1, r1, #1 \n"
" str r1, [r0] \n"
" pop { r0-r1 } \n"
" \n"
" /* Start again. */ \n"
" b reg1_loop \n"
" \n"
"reg1_error_loop: \n"
" /* If this line is hit then there was an error in a core register value.\n"
" The loop ensures the loop counter stops incrementing. */\n"
" b reg1_error_loop \n"
" nop "
);
}
/*-----------------------------------------------------------*/
/* This is a naked function. */
static void vRegTest2Task( void *pvParameters )
{
__asm volatile
(
" /* Set all the core registers to known values. */ \n"
" mov r0, #-1 \n"
" mov r1, #1 \n"
" mov r2, #2 \n"
" mov r3, #3 \n"
" mov r4, #4 \n"
" mov r5, #5 \n"
" mov r6, #6 \n"
" mov r7, #7 \n"
" mov r8, #8 \n"
" mov r9, #9 \n"
" mov r10, #10 \n"
" mov r11, #11 \n"
" mov r12, #12 \n"
" \n"
" /* Set all the VFP to known values. */ \n"
" vmov d0, r0, r1 \n"
" vmov d1, r2, r3 \n"
" vmov d2, r4, r5 \n"
" vmov d3, r6, r7 \n"
" vmov d4, r8, r9 \n"
" vmov d5, r10, r11 \n"
" vmov d6, r0, r1 \n"
" vmov d7, r2, r3 \n"
" vmov d8, r4, r5 \n"
" vmov d9, r6, r7 \n"
" vmov d10, r8, r9 \n"
" vmov d11, r10, r11 \n"
" vmov d12, r0, r1 \n"
" vmov d13, r2, r3 \n"
" vmov d14, r4, r5 \n"
" vmov d15, r6, r7 \n"
" \n"
"reg2_loop: \n"
" \n"
" /* Check all the VFP registers still contain the values set above.\n"
" First save registers that are clobbered by the test. */ \n"
" push { r0-r1 } \n"
" \n"
" vmov r0, r1, d0 \n"
" cmp r0, #-1 \n"
" bne reg2_error_loopf \n"
" cmp r1, #1 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d1 \n"
" cmp r0, #2 \n"
" bne reg2_error_loopf \n"
" cmp r1, #3 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d2 \n"
" cmp r0, #4 \n"
" bne reg2_error_loopf \n"
" cmp r1, #5 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d3 \n"
" cmp r0, #6 \n"
" bne reg2_error_loopf \n"
" cmp r1, #7 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d4 \n"
" cmp r0, #8 \n"
" bne reg2_error_loopf \n"
" cmp r1, #9 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d5 \n"
" cmp r0, #10 \n"
" bne reg2_error_loopf \n"
" cmp r1, #11 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d6 \n"
" cmp r0, #-1 \n"
" bne reg2_error_loopf \n"
" cmp r1, #1 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d7 \n"
" cmp r0, #2 \n"
" bne reg2_error_loopf \n"
" cmp r1, #3 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d8 \n"
" cmp r0, #4 \n"
" bne reg2_error_loopf \n"
" cmp r1, #5 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d9 \n"
" cmp r0, #6 \n"
" bne reg2_error_loopf \n"
" cmp r1, #7 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d10 \n"
" cmp r0, #8 \n"
" bne reg2_error_loopf \n"
" cmp r1, #9 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d11 \n"
" cmp r0, #10 \n"
" bne reg2_error_loopf \n"
" cmp r1, #11 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d12 \n"
" cmp r0, #-1 \n"
" bne reg2_error_loopf \n"
" cmp r1, #1 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d13 \n"
" cmp r0, #2 \n"
" bne reg2_error_loopf \n"
" cmp r1, #3 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d14 \n"
" cmp r0, #4 \n"
" bne reg2_error_loopf \n"
" cmp r1, #5 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d15 \n"
" cmp r0, #6 \n"
" bne reg2_error_loopf \n"
" cmp r1, #7 \n"
" bne reg2_error_loopf \n"
" \n"
" /* Restore the registers that were clobbered by the test. */\n"
" pop {r0-r1} \n"
" \n"
" /* VFP register test passed. Jump to the core register test. */\n"
" b reg2_loopf_pass \n"
" \n"
"reg2_error_loopf: \n"
" /* If this line is hit then a VFP register value was found to be\n"
" incorrect. */ \n"
" b reg2_error_loopf \n"
" \n"
"reg2_loopf_pass: \n"
" \n"
" cmp r0, #-1 \n"
" bne reg2_error_loop \n"
" cmp r1, #1 \n"
" bne reg2_error_loop \n"
" cmp r2, #2 \n"
" bne reg2_error_loop \n"
" cmp r3, #3 \n"
" bne reg2_error_loop \n"
" cmp r4, #4 \n"
" bne reg2_error_loop \n"
" cmp r5, #5 \n"
" bne reg2_error_loop \n"
" cmp r6, #6 \n"
" bne reg2_error_loop \n"
" cmp r7, #7 \n"
" bne reg2_error_loop \n"
" cmp r8, #8 \n"
" bne reg2_error_loop \n"
" cmp r9, #9 \n"
" bne reg2_error_loop \n"
" cmp r10, #10 \n"
" bne reg2_error_loop \n"
" cmp r11, #11 \n"
" bne reg2_error_loop \n"
" cmp r12, #12 \n"
" bne reg2_error_loop \n"
" \n"
" /* Increment the loop counter to indicate this test is still functioning\n"
" correctly. */ \n"
" push { r0-r1 } \n"
" ldr r0, =ulRegTest2LoopCounter \n"
" ldr r1, [r0] \n"
" adds r1, r1, #1 \n"
" str r1, [r0] \n"
" pop { r0-r1 } \n"
" \n"
" /* Start again. */ \n"
" b reg2_loop \n"
" \n"
"reg2_error_loop: \n"
" /* If this line is hit then there was an error in a core register value.\n"
" This loop ensures the loop counter variable stops incrementing. */\n"
" b reg2_error_loop \n"
" nop \n"
);
}

652
Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/startup_XMC4500.s
Unescape Escape View File

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/**
*****************************************************************************
**
** File : startup_XMC4500.s
**
** Abstract : This assembler file contains interrupt vector and
** startup code for Infineon XMC4500.
**
** Functions : Reset_Handler
** Default_Handler
**
** Target : ARM Cortex-M4
**
** Environment : Atollic TrueSTUDIO(R)
**
** Distribution: The file is distributed “as is,” without any warranty
** of any kind.
**
** (c)Copyright Atollic AB.
** You may use this file as-is or modify it according to the needs of your
** project. Distribution of this file (unmodified or modified) is not
** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
** rights to distribute the assembled, compiled & linked contents of this
** file as part of an application binary file, provided that it is built
** using the Atollic TrueSTUDIO(R) toolchain.
**
*****************************************************************************
*/
/**
**===========================================================================
** Revisions
**===========================================================================
** Date Modification
** 2011-12-30 First issue.
**===========================================================================
*/
/**
**===========================================================================
** Definitions
**===========================================================================
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* Linker script definitions */
/* start address for the initialization values of the .data section */
.word _sidata
/* start address for the .data section */
.word _sdata
/* end address for the .data section */
.word _edata
/* start address for the .bss section */
.word _sbss
/* end address for the .bss section */
.word _ebss
.equ PREF_PCON, 0x58004000
.equ SCU_GCU_PEEN, 0x5000413C
.equ SCU_GCU_PEFLAG, 0x50004150
/**
**===========================================================================
** Program - Reset_Handler
** Abstract: This code gets called after a reset event.
** 1. Copy .data section from ROM to RAM
** 2. Clear .bss section (Zero init)
** 3. Call system initialzation routine
** 4. Run static constructors
** 5. Enter main
** 6. Loop forever if returning from main
**===========================================================================
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Remap vector table - added by RB. */
ldr r0, =g_pfnVectors
ldr r1, =0xE000ED08 /* VTOR register */
str r0,[r1]
/* Disable Branch prediction */
ldr r0,=PREF_PCON
ldr r1,[r0]
orr r1,r1,#0x00010000
str r1,[r0]
/* Clear existing parity errors if any */
ldr r0,=SCU_GCU_PEFLAG
ldr r1,=0xFFFFFFFF
str r1,[r0]
/* Disable parity */
ldr r0,=SCU_GCU_PEEN
mov r1,#0
str r1,[R0]
/* Enable un-aligned memory access - added by RB. */
ldr r1, =0xE000ED14
ldr.w r0,[R1,#0x0]
bic r0,r0,#0x8
str.w r0,[r1,#0x0]
ldr sp, =_estack /* set stack pointer */
/* 1. copy .data section (Copy from ROM to RAM) */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* 2. Clear .bss section (Zero init) */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* 3. Call system initialzation routine */
bl SystemInit
/* 4. Run static constructors */
bl __libc_init_array
/* 5. Enter main */
bl main
/* 6. Loop forever if returning from main */
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
**===========================================================================
** Program - Default_Handler
** Abstract: This code gets called when the processor receives an
** unexpected interrupt.
**===========================================================================
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
InfiniteLoop:
b InfiniteLoop
.size Default_Handler, .-Default_Handler
/**
**===========================================================================
** Reset, Exception, and Interrupt vectors
**===========================================================================
*/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
/* Processor exception vectors */
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* Interrupt Handlers for XMC4500 Peripherals */
.word SCU_0_IRQHandler /* Handler name for SR SCU_0 */
.word ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */
.word ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */
.word ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */
.word ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */
.word ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */
.word ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */
.word ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */
.word ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */
.word 0 /* Not Available */
.word 0 /* Not Available */
.word 0 /* Not Available */
.word PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */
.word 0 /* Not Available */
.word VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */
.word VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */
.word VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */
.word VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */
.word VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */
.word VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */
.word VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */
.word VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */
.word VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */
.word VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */
.word VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */
.word VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */
.word VADC0_G2_0_IRQHandler /* Handler name for SR VADC0_G2_0 */
.word VADC0_G2_1_IRQHandler /* Handler name for SR VADC0_G2_1 */
.word VADC0_G2_2_IRQHandler /* Handler name for SR VADC0_G2_2 */
.word VADC0_G2_3_IRQHandler /* Handler name for SR VADC0_G2_3 */
.word VADC0_G3_0_IRQHandler /* Handler name for SR VADC0_G3_0 */
.word VADC0_G3_1_IRQHandler /* Handler name for SR VADC0_G3_1 */
.word VADC0_G3_2_IRQHandler /* Handler name for SR VADC0_G3_2 */
.word VADC0_G3_3_IRQHandler /* Handler name for SR VADC0_G3_3 */
.word DSD0_0_IRQHandler /* Handler name for SR DSD0_0 */
.word DSD0_1_IRQHandler /* Handler name for SR DSD0_1 */
.word DSD0_2_IRQHandler /* Handler name for SR DSD0_2 */
.word DSD0_3_IRQHandler /* Handler name for SR DSD0_3 */
.word DSD0_4_IRQHandler /* Handler name for SR DSD0_4 */
.word DSD0_5_IRQHandler /* Handler name for SR DSD0_5 */
.word DSD0_6_IRQHandler /* Handler name for SR DSD0_6 */
.word DSD0_7_IRQHandler /* Handler name for SR DSD0_7 */
.word DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */
.word DAC0_1_IRQHandler /* Handler name for SR DAC0_0 */
.word CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */
.word CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */
.word CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */
.word CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */
.word CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */
.word CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */
.word CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */
.word CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */
.word CCU42_0_IRQHandler /* Handler name for SR CCU42_0 */
.word CCU42_1_IRQHandler /* Handler name for SR CCU42_1 */
.word CCU42_2_IRQHandler /* Handler name for SR CCU42_2 */
.word CCU42_3_IRQHandler /* Handler name for SR CCU42_3 */
.word CCU43_0_IRQHandler /* Handler name for SR CCU43_0 */
.word CCU43_1_IRQHandler /* Handler name for SR CCU43_1 */
.word CCU43_2_IRQHandler /* Handler name for SR CCU43_2 */
.word CCU43_3_IRQHandler /* Handler name for SR CCU43_3 */
.word CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */
.word CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */
.word CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */
.word CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */
.word CCU81_0_IRQHandler /* Handler name for SR CCU81_0 */
.word CCU81_1_IRQHandler /* Handler name for SR CCU81_1 */
.word CCU81_2_IRQHandler /* Handler name for SR CCU81_2 */
.word CCU81_3_IRQHandler /* Handler name for SR CCU81_3 */
.word POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */
.word POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */
.word POSIF1_0_IRQHandler /* Handler name for SR POSIF1_0 */
.word POSIF1_1_IRQHandler /* Handler name for SR POSIF1_1 */
.word 0 /* Not Available */
.word 0 /* Not Available */
.word 0 /* Not Available */
.word 0 /* Not Available */
.word CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */
.word CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */
.word CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */
.word CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */
.word CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */
.word CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */
.word CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */
.word CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */
.word USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */
.word USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */
.word USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */
.word USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */
.word USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */
.word USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */
.word USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */
.word USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */
.word USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */
.word USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */
.word USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */
.word USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */
.word USIC2_0_IRQHandler /* Handler name for SR USIC2_0 */
.word USIC2_1_IRQHandler /* Handler name for SR USIC2_1 */
.word USIC2_2_IRQHandler /* Handler name for SR USIC2_2 */
.word USIC2_3_IRQHandler /* Handler name for SR USIC2_3 */
.word USIC2_4_IRQHandler /* Handler name for SR USIC2_4 */
.word USIC2_5_IRQHandler /* Handler name for SR USIC2_5 */
.word LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */
.word 0 /* Not Available */
.word FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */
.word GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */
.word SDMMC0_0_IRQHandler /* Handler name for SR SDMMC0_0 */
.word USB0_0_IRQHandler /* Handler name for SR USB0_0 */
.word ETH0_0_IRQHandler /* Handler name for SR ETH0_0 */
.word 0 /* Not Available */
.word GPDMA1_0_IRQHandler /* Handler name for SR GPDMA1_0 */
.word 0 /* Not Available */
/**
**===========================================================================
** Provide weak aliases for each Exception handler to the Default_Handler.
**===========================================================================
*/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak SCU_0_IRQHandler
.thumb_set SCU_0_IRQHandler,Default_Handler
.weak ERU0_0_IRQHandler
.thumb_set ERU0_0_IRQHandler,Default_Handler
.weak ERU0_1_IRQHandler
.thumb_set ERU0_1_IRQHandler,Default_Handler
.weak ERU0_2_IRQHandler
.thumb_set ERU0_2_IRQHandler,Default_Handler
.weak ERU0_3_IRQHandler
.thumb_set ERU0_3_IRQHandler,Default_Handler
.weak ERU1_0_IRQHandler
.thumb_set ERU1_0_IRQHandler,Default_Handler
.weak ERU1_1_IRQHandler
.thumb_set ERU1_1_IRQHandler,Default_Handler
.weak ERU1_2_IRQHandler
.thumb_set ERU1_2_IRQHandler,Default_Handler
.weak ERU1_3_IRQHandler
.thumb_set ERU1_3_IRQHandler,Default_Handler
.weak PMU0_0_IRQHandler
.thumb_set PMU0_0_IRQHandler,Default_Handler
.weak VADC0_C0_0_IRQHandler
.thumb_set VADC0_C0_0_IRQHandler,Default_Handler
.weak VADC0_C0_1_IRQHandler
.thumb_set VADC0_C0_1_IRQHandler,Default_Handler
.weak VADC0_C0_2_IRQHandler
.thumb_set VADC0_C0_2_IRQHandler,Default_Handler
.weak VADC0_C0_3_IRQHandler
.thumb_set VADC0_C0_3_IRQHandler,Default_Handler
.weak VADC0_G0_0_IRQHandler
.thumb_set VADC0_G0_0_IRQHandler,Default_Handler
.weak VADC0_G0_1_IRQHandler
.thumb_set VADC0_G0_1_IRQHandler,Default_Handler
.weak VADC0_G0_2_IRQHandler
.thumb_set VADC0_G0_2_IRQHandler,Default_Handler
.weak VADC0_G0_3_IRQHandler
.thumb_set VADC0_G0_3_IRQHandler,Default_Handler
.weak VADC0_G1_0_IRQHandler
.thumb_set VADC0_G1_0_IRQHandler,Default_Handler
.weak VADC0_G1_1_IRQHandler
.thumb_set VADC0_G1_1_IRQHandler,Default_Handler
.weak VADC0_G1_2_IRQHandler
.thumb_set VADC0_G1_2_IRQHandler,Default_Handler
.weak VADC0_G1_3_IRQHandler
.thumb_set VADC0_G1_3_IRQHandler,Default_Handler
.weak VADC0_G2_0_IRQHandler
.thumb_set VADC0_G2_0_IRQHandler,Default_Handler
.weak VADC0_G2_1_IRQHandler
.thumb_set VADC0_G2_1_IRQHandler,Default_Handler
.weak VADC0_G2_2_IRQHandler
.thumb_set VADC0_G2_2_IRQHandler,Default_Handler
.weak VADC0_G2_3_IRQHandler
.thumb_set VADC0_G2_3_IRQHandler,Default_Handler
.weak VADC0_G3_0_IRQHandler
.thumb_set VADC0_G3_0_IRQHandler,Default_Handler
.weak VADC0_G3_1_IRQHandler
.thumb_set VADC0_G3_1_IRQHandler,Default_Handler
.weak VADC0_G3_2_IRQHandler
.thumb_set VADC0_G3_2_IRQHandler,Default_Handler
.weak VADC0_G3_3_IRQHandler
.thumb_set VADC0_G3_3_IRQHandler,Default_Handler
.weak DSD0_0_IRQHandler
.thumb_set DSD0_0_IRQHandler,Default_Handler
.weak DSD0_1_IRQHandler
.thumb_set DSD0_1_IRQHandler,Default_Handler
.weak DSD0_2_IRQHandler
.thumb_set DSD0_2_IRQHandler,Default_Handler
.weak DSD0_3_IRQHandler
.thumb_set DSD0_3_IRQHandler,Default_Handler
.weak DSD0_4_IRQHandler
.thumb_set DSD0_4_IRQHandler,Default_Handler
.weak DSD0_5_IRQHandler
.thumb_set DSD0_5_IRQHandler,Default_Handler
.weak DSD0_6_IRQHandler
.thumb_set DSD0_6_IRQHandler,Default_Handler
.weak DSD0_7_IRQHandler
.thumb_set DSD0_7_IRQHandler,Default_Handler
.weak DAC0_0_IRQHandler
.thumb_set DAC0_0_IRQHandler,Default_Handler
.weak DAC0_1_IRQHandler
.thumb_set DAC0_1_IRQHandler,Default_Handler
.weak CCU40_0_IRQHandler
.thumb_set CCU40_0_IRQHandler,Default_Handler
.weak CCU40_1_IRQHandler
.thumb_set CCU40_1_IRQHandler,Default_Handler
.weak CCU40_2_IRQHandler
.thumb_set CCU40_2_IRQHandler,Default_Handler
.weak CCU40_3_IRQHandler
.thumb_set CCU40_3_IRQHandler,Default_Handler
.weak CCU41_0_IRQHandler
.thumb_set CCU41_0_IRQHandler,Default_Handler
.weak CCU41_1_IRQHandler
.thumb_set CCU41_1_IRQHandler,Default_Handler
.weak CCU41_2_IRQHandler
.thumb_set CCU41_2_IRQHandler,Default_Handler
.weak CCU41_3_IRQHandler
.thumb_set CCU41_3_IRQHandler,Default_Handler
.weak CCU42_0_IRQHandler
.thumb_set CCU42_0_IRQHandler,Default_Handler
.weak CCU42_1_IRQHandler
.thumb_set CCU42_1_IRQHandler,Default_Handler
.weak CCU42_2_IRQHandler
.thumb_set CCU42_2_IRQHandler,Default_Handler
.weak CCU42_3_IRQHandler
.thumb_set CCU42_3_IRQHandler,Default_Handler
.weak CCU43_0_IRQHandler
.thumb_set CCU43_0_IRQHandler,Default_Handler
.weak CCU43_1_IRQHandler
.thumb_set CCU43_1_IRQHandler,Default_Handler
.weak CCU43_2_IRQHandler
.thumb_set CCU43_2_IRQHandler,Default_Handler
.weak CCU43_3_IRQHandler
.thumb_set CCU43_3_IRQHandler,Default_Handler
.weak CCU80_0_IRQHandler
.thumb_set CCU80_0_IRQHandler,Default_Handler
.weak CCU80_1_IRQHandler
.thumb_set CCU80_1_IRQHandler,Default_Handler
.weak CCU80_2_IRQHandler
.thumb_set CCU80_2_IRQHandler,Default_Handler
.weak CCU80_3_IRQHandler
.thumb_set CCU80_3_IRQHandler,Default_Handler
.weak CCU81_0_IRQHandler
.thumb_set CCU81_0_IRQHandler,Default_Handler
.weak CCU81_1_IRQHandler
.thumb_set CCU81_1_IRQHandler,Default_Handler
.weak CCU81_2_IRQHandler
.thumb_set CCU81_2_IRQHandler,Default_Handler
.weak CCU81_3_IRQHandler
.thumb_set CCU81_3_IRQHandler,Default_Handler
.weak POSIF0_0_IRQHandler
.thumb_set POSIF0_0_IRQHandler,Default_Handler
.weak POSIF0_1_IRQHandler
.thumb_set POSIF0_1_IRQHandler,Default_Handler
.weak POSIF1_0_IRQHandler
.thumb_set POSIF1_0_IRQHandler,Default_Handler
.weak POSIF1_1_IRQHandler
.thumb_set POSIF1_1_IRQHandler,Default_Handler
.weak CAN0_0_IRQHandler
.thumb_set CAN0_0_IRQHandler,Default_Handler
.weak CAN0_1_IRQHandler
.thumb_set CAN0_1_IRQHandler,Default_Handler
.weak CAN0_2_IRQHandler
.thumb_set CAN0_2_IRQHandler,Default_Handler
.weak CAN0_3_IRQHandler
.thumb_set CAN0_3_IRQHandler,Default_Handler
.weak CAN0_4_IRQHandler
.thumb_set CAN0_4_IRQHandler,Default_Handler
.weak CAN0_5_IRQHandler
.thumb_set CAN0_5_IRQHandler,Default_Handler
.weak CAN0_6_IRQHandler
.thumb_set CAN0_6_IRQHandler,Default_Handler
.weak CAN0_7_IRQHandler
.thumb_set CAN0_7_IRQHandler,Default_Handler
.weak USIC0_0_IRQHandler
.thumb_set USIC0_0_IRQHandler,Default_Handler
.weak USIC0_1_IRQHandler
.thumb_set USIC0_1_IRQHandler,Default_Handler
.weak USIC0_2_IRQHandler
.thumb_set USIC0_2_IRQHandler,Default_Handler
.weak USIC0_3_IRQHandler
.thumb_set USIC0_3_IRQHandler,Default_Handler
.weak USIC0_4_IRQHandler
.thumb_set USIC0_4_IRQHandler,Default_Handler
.weak USIC0_5_IRQHandler
.thumb_set USIC0_5_IRQHandler,Default_Handler
.weak USIC1_0_IRQHandler
.thumb_set USIC1_0_IRQHandler,Default_Handler
.weak USIC1_1_IRQHandler
.thumb_set USIC1_1_IRQHandler,Default_Handler
.weak USIC1_2_IRQHandler
.thumb_set USIC1_2_IRQHandler,Default_Handler
.weak USIC1_3_IRQHandler
.thumb_set USIC1_3_IRQHandler,Default_Handler
.weak USIC1_4_IRQHandler
.thumb_set USIC1_4_IRQHandler,Default_Handler
.weak USIC1_5_IRQHandler
.thumb_set USIC1_5_IRQHandler,Default_Handler
.weak USIC2_0_IRQHandler
.thumb_set USIC2_0_IRQHandler,Default_Handler
.weak USIC2_1_IRQHandler
.thumb_set USIC2_1_IRQHandler,Default_Handler
.weak USIC2_2_IRQHandler
.thumb_set USIC2_2_IRQHandler,Default_Handler
.weak USIC2_3_IRQHandler
.thumb_set USIC2_3_IRQHandler,Default_Handler
.weak USIC2_4_IRQHandler
.thumb_set USIC2_4_IRQHandler,Default_Handler
.weak USIC2_5_IRQHandler
.thumb_set USIC2_5_IRQHandler,Default_Handler
.weak LEDTS0_0_IRQHandler
.thumb_set LEDTS0_0_IRQHandler,Default_Handler
.weak FCE0_0_IRQHandler
.thumb_set FCE0_0_IRQHandler,Default_Handler
.weak GPDMA0_0_IRQHandler
.thumb_set GPDMA0_0_IRQHandler,Default_Handler
.weak SDMMC0_0_IRQHandler
.thumb_set SDMMC0_0_IRQHandler,Default_Handler
.weak USB0_0_IRQHandler
.thumb_set USB0_0_IRQHandler,Default_Handler
.weak ETH0_0_IRQHandler
.thumb_set ETH0_0_IRQHandler,Default_Handler
.weak GPDMA1_0_IRQHandler
.thumb_set GPDMA1_0_IRQHandler,Default_Handler
.end

419
Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/system_XMC4500.c
Unescape Escape View File

@ -0,0 +1,419 @@
/******************************************************************************
* @file system_XMC4500.c
* @brief Device specific initialization for the XMC4500-Series according to CMSIS
* @version V2.2
* @date 20. January 2012
*
* @note
* Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
* This file can be freely distributed within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
*
******************************************************************************/
#include "System_XMC4500.h"
#include <XMC4500.h>
/*----------------------------------------------------------------------------
Define clocks is located in System_XMC4500.h
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/*!< System Clock Frequency (Core Clock)*/
uint32_t SystemCoreClock = CLOCK_OSC_HP;
/*----------------------------------------------------------------------------
Keil pragma to prevent warnings
*----------------------------------------------------------------------------*/
#if defined(__ARMCC_VERSION)
#pragma diag_suppress 177
#endif
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Watchdog Configuration -------------------------------
//
// <e> Watchdog Configuration
// <o1.0> Disable Watchdog
//
// </e>
*/
#define WDT_SETUP 1
#define WDTENB_nVal 0x00000001
/*--------------------- CLOCK Configuration -------------------------------
//
// <e> Main Clock Configuration
// <o1.0..1> CPU clock divider
// <0=> fCPU = fSYS
// <1=> fCPU = fSYS / 2
// <o2.0..1> Peripheral Bus clock divider
// <0=> fPB = fCPU
// <1=> fPB = fCPU / 2
// <o3.0..1> CCU Bus clock divider
// <0=> fCCU = fCPU
// <1=> fCCU = fCPU / 2
//
// </e>
//
*/
#define SCU_CLOCK_SETUP 1
#define SCU_CPUCLKCR_DIV 0x00000000
#define SCU_PBCLKCR_DIV 0x00000000
#define SCU_CCUCLKCR_DIV 0x00000000
/*--------------------- USB CLOCK Configuration ---------------------------
//
// <e> USB Clock Configuration
//
// </e>
//
*/
#define SCU_USB_CLOCK_SETUP 0
/*--------------------- CLOCKOUT Configuration -------------------------------
//
// <e> Clock OUT Configuration
// <o1.0..1> Clockout Source Selection
// <0=> System Clock
// <2=> USB Clock
// <3=> Divided value of PLL Clock
// <o2.0..1> Clockout Pin Selection
// <0=> P1.15
// <1=> P0.8
//
//
// </e>
//
*/
#define SCU_CLOCKOUT_SETUP 0 // recommended to keep disabled
#define SCU_CLOCKOUT_SOURCE 0x00000000
#define SCU_CLOCKOUT_PIN 0x00000000
/*----------------------------------------------------------------------------
static functions declarations
*----------------------------------------------------------------------------*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void);
#endif
#if (SCU_USB_CLOCK_SETUP == 1)
static void USBClockSetup(void);
#endif
/**
* @brief Setup the microcontroller system.
* Initialize the PLL and update the
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Setup the WDT */
#if (WDT_SETUP == 1)
WDT->CTR &= ~WDTENB_nVal;
#endif
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
/* Disable branch prediction - PCON.PBS = 1 */
PREF->PCON |= (PREF_PCON_PBS_Msk);
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
/* Setup the clockout */
/* README README README README README README README README README README */
/*
* Please use the CLOCKOUT feature with diligence. Use this only if you know
* what you are doing.
*
* You must be aware that the settings below can potentially be in conflict
* with DAVE code generation engine preferences.
*
* Even worse, the setting below configures the ports as output ports while in
* reality, the board on which this chip is mounted may have a source driving
* the ports.
*
* So use this feature only when you are absolutely sure that the port must
* indeed be configured as an output AND you are NOT linking this startup code
* with code that was generated by DAVE code engine.
*/
#if (SCU_CLOCKOUT_SETUP == 1)
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;
if (SCU_CLOCKOUT_PIN) {
PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */
PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
}
else PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
#endif
/* Setup the System clock */
#if (SCU_CLOCK_SETUP == 1)
SystemClockSetup();
#endif
/* Setup the USB PL */
#if (SCU_USB_CLOCK_SETUP == 1)
USBClockSetup();
#endif
}
/**
* @brief Update SystemCoreClock according to Clock Register Values
* @note -
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
SystemCoreClock = SYSTEM_FREQUENCY;/*!< System Clock Frequency (Core Clock)*/
}
/**
* @brief -
* @note -
* @param None
* @retval None
*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void)
{
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk |
SCU_PLL_PLLCON0_PLLPWD_Msk);
/* Enable OSC_HP */
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
{
/* Enable the OSC_HP*/
SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4);
/* Setup OSC WDG devider */
SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16);
/* Select external OSC as PLL input */
SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
/* Restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
do
{
; /* here a timeout need to be added */
}while(!( (SCU_PLL->PLLSTAT) &
(SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |
SCU_PLL_PLLSTAT_PLLSP_Msk)
)
);
}
/* Setup Main PLL */
/* Select FOFI as system clock */
if(SCU_CLK->SYSCLKCR != 0X000000)
SCU_CLK->SYSCLKCR = 0x00000000; /*Select FOFI*/
/* Go to bypass the Main PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
/* disconnect OSC_HP to PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) |
(PLL_K2DIV_STEP_1<<16) | (PLL_PDIV<<24));
/* we may have to set OSCDISCDIS */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/* connect OSC_HP to PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
/* wait for PLL Lock */
while (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk));
/* Go back to the Main PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
/*********************************************************
here we need to setup the system clock divider
*********************************************************/
SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
/* Switch system clock to PLL */
SCU_CLK->SYSCLKCR |= 0x00010000;
/*********************************************************
here the ramp up of the system clock starts
*********************************************************/
/* Delay for next K2 step ~50µs */
/********************************/
/* Set reload register */
SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;
/* Load the SysTick Counter Value */
SysTick->VAL = 0;
/* Enable SysTick IRQ and SysTick Timer */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk;
/* wait for ~50µs */
while (SysTick->VAL >= 100);
/* Stop SysTick Timer */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
/********************************/
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) |
(PLL_K2DIV_STEP_2<<16) | (PLL_PDIV<<24));
/* Delay for next K2 step ~50µs */
/********************************/
SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
/* Load the SysTick Counter Value */
SysTick->VAL = 0;
/* Enable SysTick IRQ and SysTick Timer */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
/* Wait for ~50µs */
while (SysTick->VAL >= 100);
/* Stop SysTick Timer */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
/********************************/
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) |
(PLL_K2DIV_STEP_3<<16) | (PLL_PDIV<<24));
/* Delay for next K2 step ~50µs */
/********************************/
SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
/* Load the SysTick Counter Value */
SysTick->VAL = 0;
/* Enable SysTick IRQ and SysTick Timer */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
/* Wait for ~50µs */
while (SysTick->VAL >= 100);
/* Stop SysTick Timer */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
/********************************/
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV<<16) |
(PLL_PDIV<<24));
/* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk |
SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;
return(1);
}
#endif
/**
* @brief -
* @note -
* @param None
* @retval None
*/
#if(SCU_USB_CLOCK_SETUP == 1)
static void USBClockSetup(void)
{
/* enable PLL first */
SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk |
SCU_PLL_USBPLLCON_PLLPWD_Msk);
/* check and if not already running enable OSC_HP */
if(!((SCU_PLL->PLLSTAT) &
(SCU_PLL_PLLSTAT_PLLHV_Msk |
SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)))
{
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
{
SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4); /*enable the OSC_HP*/
/* setup OSC WDG devider */
SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16);
/* select external OSC as PLL input */
SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
do
{
; /* here a timeout need to be added */
}while(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk |
SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)));
}
}
/* Setup USB PLL */
/* Go to bypass the Main PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
/* disconnect OSC_FI to PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
/* Setup devider settings for main PLL */
SCU_PLL->USBPLLCON = ((USBPLL_NDIV<<8) | (USBPLL_PDIV<<24));
/* we may have to set OSCDISCDIS */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
/* connect OSC_FI to PLL */
SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
/* wait for PLL Lock */
while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
}
#endif

174
Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/xmc4500_flash.ld
Unescape Escape View File

@ -0,0 +1,174 @@
/*
*****************************************************************************
**
** File : xmc4500_flash.ld
**
** Abstract : Linker script for XMC4500-E144x1024 Device with
** 1024KByte FLASH, 64KByte RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : Infineon XMC4500
**
** Environment : Atollic TrueSTUDIO(R)
**
** Distribution: The file is distributed “as is,” without any warranty
** of any kind.
**
** (c)Copyright Atollic AB.
** You may use this file as-is or modify it according to the needs of your
** project. Distribution of this file (unmodified or modified) is not
** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
** rights to distribute the assembled, compiled & linked contents of this
** file as part of an application binary file, provided that it is built
** using the Atollic TrueSTUDIO(R) toolchain.
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x10010000; /* end of 64K RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0; /* required amount of heap */
_Min_Stack_Size = 0x200; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
FLASH1_cached (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
FLASH1_uncached (rx) : ORIGIN = 0x0C000000, LENGTH = 1024K
PSRAM1 (xrw) : ORIGIN = 0x10000000, LENGTH = 64K
DSRAM1_system (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
DSRAM2_comm (xrw) : ORIGIN = 0x30000000, LENGTH = 32K
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
_isr_vector = .; /* define isr_vector start address */
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH1_uncached
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH1_uncached
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH1_uncached
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH1_uncached
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH1_uncached
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH1_uncached
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH1_uncached
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >DSRAM1_system AT> FLASH1_uncached
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >DSRAM1_system
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(4);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(4);
} >DSRAM1_system
/* MEMORY_bank1 section, code must be located here explicitly */
/* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
.memory_b1_text :
{
*(.mb1text) /* .mb1text sections (code) */
*(.mb1text*) /* .mb1text* sections (code) */
*(.mb1rodata) /* read-only data (constants) */
*(.mb1rodata*)
} >MEMORY_B1
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}
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