Add Vectored Interrupt Support To SiFive RISC-V Demo (#871)
Update SiFive IAR demo to support vectored interrupts. This is a near copy of https://github.com/FreeRTOS/FreeRTOS/pull/797. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>pull/864/head^2
Kody Stribrny
2 years ago
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GitHub
parent
1fc8a8ee42
commit
54d4eeaa26
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# RISC-V SiFive HiFive1 Rev B Demo
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View https://www.freertos.org/RTOS-RISC-V-FreedomStudio-IAR-HiFive-RevB.html for more information on how to run this demo
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/*
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* FreeRTOS V202112.00
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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EXTERN freertos_risc_v_exception_handler
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EXTERN freertos_risc_v_interrupt_handler
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EXTERN freertos_risc_v_mtimer_interrupt_handler
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SECTION `.text`:CODE:ROOT(7)
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CODE
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.option norvc
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PUBLIC freertos_vector_table
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freertos_vector_table:
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IRQ_0:
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j freertos_risc_v_exception_handler
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IRQ_1:
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j freertos_risc_v_interrupt_handler
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IRQ_2:
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j freertos_risc_v_interrupt_handler
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IRQ_3:
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j freertos_risc_v_interrupt_handler
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IRQ_4:
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j freertos_risc_v_interrupt_handler
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IRQ_5:
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j freertos_risc_v_interrupt_handler
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IRQ_6:
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j freertos_risc_v_interrupt_handler
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IRQ_7:
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j freertos_risc_v_mtimer_interrupt_handler
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IRQ_8:
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j freertos_risc_v_interrupt_handler
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IRQ_9:
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j freertos_risc_v_interrupt_handler
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IRQ_10:
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j freertos_risc_v_interrupt_handler
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IRQ_11:
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j freertos_risc_v_interrupt_handler
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IRQ_12:
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j freertos_risc_v_interrupt_handler
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IRQ_13:
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j freertos_risc_v_interrupt_handler
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IRQ_14:
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j freertos_risc_v_interrupt_handler
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IRQ_15:
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j freertos_risc_v_interrupt_handler
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IRQ_LC0:
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j freertos_risc_v_interrupt_handler
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IRQ_LC1:
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j freertos_risc_v_interrupt_handler
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IRQ_LC2:
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j freertos_risc_v_interrupt_handler
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IRQ_LC3:
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j freertos_risc_v_interrupt_handler
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IRQ_LC4:
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j freertos_risc_v_interrupt_handler
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IRQ_LC5:
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j freertos_risc_v_interrupt_handler
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IRQ_LC6:
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j freertos_risc_v_interrupt_handler
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IRQ_LC7:
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j freertos_risc_v_interrupt_handler
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IRQ_LC8:
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j freertos_risc_v_interrupt_handler
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IRQ_LC9:
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j freertos_risc_v_interrupt_handler
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IRQ_LC10:
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j freertos_risc_v_interrupt_handler
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IRQ_LC11:
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j freertos_risc_v_interrupt_handler
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IRQ_LC12:
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j freertos_risc_v_interrupt_handler
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IRQ_LC13:
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j freertos_risc_v_interrupt_handler
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IRQ_LC14:
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j freertos_risc_v_interrupt_handler
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IRQ_LC15:
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j freertos_risc_v_interrupt_handler
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/*-----------------------------------------------------------*/
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@ -1 +1 @@
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Subproject commit b0a8bd8f28d0138b5eb70e8b53da3e9d17ce8d40
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Subproject commit f789a0e7907feca1a9019637219f0fd113a6c380
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