Fix: Demo/RX200_RX231-RSK_GCC_e2studio_IAR RTOS demo project IAR build error (#239)
Co-authored-by: Ming Yue <mingyue86010@gmail.com>pull/282/head^2
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fb7881cfeb
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@ -1,116 +0,0 @@
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/*---------------------------------------------------------------------------*/
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/* - defaults.s - */
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/* */
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/* This module contains default values for the following symbols */
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/* */
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/* For RxV1 core: */
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/* __MDES @ 0xFFFFFF80 to 0xFFFFFF83 */
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/* __OFS1 @ 0xFFFFFF88 to 0xFFFFFF8B */
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/* __OFS0 @ 0xFFFFFF8C to 0xFFFFFF8F */
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/* __ROM_CODE @ 0xFFFFFF9C */
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/* __ID_BYTES_1_4 @ 0xFFFFFFA0 to 0xFFFFFFA3 */
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/* __ID_BYTES_5_8 @ 0xFFFFFFA4 to 0xFFFFFFA7 */
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/* __ID_BYTES_9_12 @ 0xFFFFFFA8 to 0xFFFFFFAB */
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/* __ID_BYTES_13_16 @ 0xFFFFFFAC to 0xFFFFFFAF */
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/* */
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/* For RxV1 core: */
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/* __MDES @ 0xFFFFFF80 to 0xFFFFFF83 */
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/* __OFS1 @ 0xFFFFFF88 to 0xFFFFFF8B */
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/* __OFS0 @ 0xFFFFFF8C to 0xFFFFFF8F */
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/* __ROM_CODE @ 0xFFFFFF9C to 0xFFFFFF9F */
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/* __OSIS_1 @ 0xFFFFFFA0 to 0xFFFFFFA3 */
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/* __OSIS_2 @ 0xFFFFFFA4 to 0xFFFFFFA7 */
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/* __OSIS_3 @ 0xFFFFFFA8 to 0xFFFFFFAB */
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/* __OSIS_4 @ 0xFFFFFFAC to 0xFFFFFFAF */
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/* */
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/* For RxV2 core (RX64M): */
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/* __SPCC @ 0x00120040 to 0x00120043 */
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/* __TMEF @ 0x00120048 to 0x0012004B */
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/* __OSIS_1 @ 0x00120050 to 0x00120053 */
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/* __OSIS_2 @ 0x00120054 to 0x00120057 */
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/* __OSIS_3 @ 0x00120058 to 0x0012005D */
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/* __OSIS_4 @ 0x0012005C to 0x0012005F */
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/* __TMINF @ 0x00120060 to 0x00120063 */
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/* __MDE @ 0x00120064 to 0x00120067 */
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/* __OFS0 @ 0x00120068 to 0x0012006B */
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/* __OFS1 @ 0x0012006C to 0x0012006F */
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/* */
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/* To override default values in library add this file to your */
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/* project and change the values. */
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/* */
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/* Copyright 2014 IAR Systems AB. */
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/* */
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/* $Revision: 6046 $ */
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/* */
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/*---------------------------------------------------------------------------*/
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MODULE DEFAULTS
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SECTION .text:CONST:NOROOT
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#if __CORE__ == __CORE_V1__
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PUBWEAK __MDES
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PUBWEAK __OFS1
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PUBWEAK __OFS0
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PUBWEAK __ROM_CODE
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PUBWEAK __ID_BYTES_1_4
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PUBWEAK __ID_BYTES_5_8
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PUBWEAK __ID_BYTES_9_12
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PUBWEAK __ID_BYTES_13_16
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#if __LITTLE_ENDIAN__
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__MDES equ 0xffffffff
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#else
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__MDES equ 0xfffffff8
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#endif
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__OFS0 equ 0xffffffff
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__OFS1 equ 0xffffffff
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__ROM_CODE equ 0xffffffff
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__ID_BYTES_1_4 equ 0xffffffff
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__ID_BYTES_5_8 equ 0xffffffff
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__ID_BYTES_9_12 equ 0xffffffff
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__ID_BYTES_13_16 equ 0xffffffff
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#else /* __CORE__ == __CORE_V2__ */
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PUBWEAK __ROM_CODE
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PUBWEAK __MDE
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PUBWEAK __OFS1
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PUBWEAK __OFS0
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PUBWEAK __OSIS_1
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PUBWEAK __OSIS_2
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PUBWEAK __OSIS_3
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PUBWEAK __OSIS_4
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PUBWEAK __SPCC
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PUBWEAK __TMEF
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PUBWEAK __TMINF
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__ROM_CODE equ 0xffffffff
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// 0x00120040 SPCC register
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__SPCC equ 0xffffffff
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// 0x00120048 TMEF register
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__TMEF equ 0xffffffff
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// 0x00120050 OSIC register (ID codes)
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__OSIS_1 equ 0xffffffff
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__OSIS_2 equ 0xffffffff
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__OSIS_3 equ 0xffffffff
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__OSIS_4 equ 0xffffffff
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// 0x00120060 TMINF register
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__TMINF equ 0xffffffff
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// 0x00120064 MDE register (Single Chip Mode)
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#if __LITTLE_ENDIAN__
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__MDE equ 0xffffffff // little
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#else
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__MDE equ 0xfffffff8 // big
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#endif
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// 0x00120068 OFS0 register
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__OFS0 equ 0xffffffff
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// 0x0012006c OFS1 register
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__OFS1 equ 0xffffffff
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#endif
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END
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@ -1,56 +0,0 @@
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;-----------------------------------------------------------------------------
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; Exception vector table. We install all fixed interrupts in
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; a section called EXCEPTVECT. All fixed interrupts have a
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; hard coded name that is default handled in this file.
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; See fixedint.c for information how to replace them with handlers written in C.
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;
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; $Revision: 6884 $
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;
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// This segment part is marked as ROOT, since it must
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// be preserved by the linker.
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MODULE EXCEPTVECT
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SECTION .exceptvect:CONST:ROOT
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#if __CORE__ == __CORE_V2__
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EXTERN ___excep_access_inst
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EXTERN ___privileged_handler
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EXTERN ___undefined_handler
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EXTERN ___undefined_interrupt_source_handler
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EXTERN ___NMI_handler
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EXTERN __float_placeholder
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EXTERN __MDE
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EXTERN __OFS1
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EXTERN __OFS0
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EXTERN __ROM_CODE
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EXTERN __OSIS_1
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EXTERN __OSIS_2
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EXTERN __OSIS_3
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EXTERN __OSIS_4
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PUBLIC __exceptvect
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DATA
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__exceptvect:
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DC32 __MDE // 0xFFFFFF80 MDE register (Single Chip Mode)
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DS32 1
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DC32 __OFS1 // 0xFFFFFF88 OFS1 register
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DC32 __OFS0 // 0xFFFFFF8C OFS0 register
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DS32 3
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DC32 __ROM_CODE // 0xFFFFFF8C ROM code protection
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DC32 __OSIS_1 // 0xFFFFFFA0 OSIC register (ID codes)
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DC32 __OSIS_2 // 0xFFFFFFA4 OSIC register (ID codes)
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DC32 __OSIS_3 // 0xFFFFFFA8 OSIC register (ID codes)
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DC32 __OSIS_4 // 0xFFFFFFAC OSIC register (ID codes)
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DS32 8
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DC32 ___privileged_handler // Exception(Supervisor Instruction)
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DC32 ___excep_access_inst // Exception(Access Instruction)
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DC32 ___undefined_interrupt_source_handler
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DC32 ___undefined_handler // Exception(Undefined Instruction)
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DC32 ___undefined_interrupt_source_handler
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DC32 __float_placeholder // Exception(Floating Point)
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DC32 ___undefined_interrupt_source_handler
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DC32 ___undefined_interrupt_source_handler
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DC32 ___undefined_interrupt_source_handler
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DC32 ___undefined_interrupt_source_handler
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DC32 ___NMI_handler // NMI
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#endif
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END
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@ -1,47 +0,0 @@
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//-----------------------------------------------------------------------------
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// ILINK command file template for the Renesas RX microcontroller R5F52318
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//-----------------------------------------------------------------------------
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define memory mem with size = 4G;
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define region ROM_region16 = mem:[from 0xFFFF8000 to 0xFFFFFFFF];
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define region RAM_region16 = mem:[from 0x00000004 to 0x00007FFF];
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define region ROM_region24 = mem:[from 0xFFF80000 to 0xFFFFFFFF];
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define region RAM_region24 = mem:[from 0x00000004 to 0x0000FFFF];
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define region ROM_region32 = mem:[from 0xFFF80000 to 0xFFFFFFFF];
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define region RAM_region32 = mem:[from 0x00000004 to 0x0000FFFF];
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define region DATA_FLASH_region = mem:[from 0x00100000 to 0x00101FFF];
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initialize by copy { rw, ro section D, ro section D_1, ro section D_2 };
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initialize by copy with packing = none { section __DLIB_PERTHREAD };
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do not initialize { section .*.noinit };
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define block HEAP with alignment = 4, size = _HEAP_SIZE { };
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define block USTACK with alignment = 4, size = _USTACK_SIZE { };
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define block ISTACK with alignment = 4, size = _ISTACK_SIZE { };
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define block STACKS with fixed order { block ISTACK,
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block USTACK };
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place at address mem:0x00120040 { ro section .option_rom };
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place at address mem:0xFFFFFF80 { ro section .exceptvect };
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place at address mem:0xFFFFFFFC { ro section .resetvect };
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"ROM16":place in ROM_region16 { ro section .code16*,
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ro section .data16* };
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"RAM16":place in RAM_region16 { rw section .data16*,
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rw section __DLIB_PERTHREAD };
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"ROM24":place in ROM_region24 { ro section .code24*,
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ro section .data24* };
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"RAM24":place in RAM_region24 { rw section .data24* };
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"ROM32":place in ROM_region32 { ro };
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"RAM32":place in RAM_region32 { rw,
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ro section D,
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ro section D_1,
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ro section D_2,
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block HEAP,
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block STACKS };
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"DATAFLASH":place in DATA_FLASH_region
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{ ro section .dataflash* };
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@ -1,40 +0,0 @@
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// This segment part is marked as ROOT, since it must
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// be preserved by the linker.
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MODULE OPTION_ROM
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SECTION .option_rom:CONST:ROOT
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#if __CORE__ == __CORE_V2__
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EXTERN __MDE
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EXTERN __OFS1
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EXTERN __OFS0
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EXTERN __SPCC
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EXTERN __TMEF
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EXTERN __TMINF
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EXTERN __OSIS_1
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EXTERN __OSIS_2
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EXTERN __OSIS_3
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EXTERN __OSIS_4
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PUBLIC __option_rom
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// Special configuration registers for 64M
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DATA
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__option_rom:
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#if 0
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DC32 __SPCC // 0x00120040 SPCC register
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DS32 1 // 0x00120044 reserved
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DC32 __TMEF // 0x00120048 TMEF register
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DS32 1 // 0x0012004C reserved
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; DC32 __OSIS_1 // 0x00120050 OSIC register (ID codes)
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; DC32 __OSIS_2 // 0x00120054 OSIC register (ID codes)
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; DC32 __OSIS_3 // 0x00120058 OSIC register (ID codes)
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; DC32 __OSIS_4 // 0x0012005C OSIC register (ID codes)
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DC32 __TMINF // 0x00120060 TMINF register
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; DC32 __MDE // 0x00120064 MDE register (Single Chip Mode)
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; DC32 __OFS0 // 0x00120068 OFS0 register
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; DC32 __OFS1 // 0x0012006C OFS1 register
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#endif
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#endif
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END
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