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Common scheduler code:

Browse Source 
- Back out changes that allow mutexes to be given from a semaphore after tests showed issues that would not be fast to fix.

Demo projects:

- Update the Microblaze Kintex 7 project and BSP to use version 2015.2 of the Xilinx SDK.
pull/1/head
Richard Barry 10 years ago
parent 95eed0c8f3
commit 4c847711bd
155 changed files with 28884 additions and 78 deletions
Show Stats Download Patch File Download Diff File

56
FreeRTOS/Demo/Common/Minimal/IntSemTest.c
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@ -163,7 +163,7 @@ static SemaphoreHandle_t xMasterSlaveMutex = NULL;
/* Flag that allows the master task to control when the interrupt gives or does
not give the mutex. There is no mutual exclusion on this variable, but this is
only test code and it should be fine in the 32=bit test environment. */
static BaseType_t xOkToGiveMutex = pdFALSE, xOkToGiveCountingSemaphore = pdFALSE, xOkToGiveMasterSlaveMutex = pdFALSE;
static BaseType_t xOkToGiveMutex = pdFALSE, xOkToGiveCountingSemaphore = pdFALSE;
/* Used to coordinate timing between tasks and the interrupt. */
const TickType_t xInterruptGivePeriod = pdMS_TO_TICKS( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS );
@ -217,8 +217,6 @@ static void vInterruptMutexMasterTask( void *pvParameters )
static void prvTakeAndGiveInTheSameOrder( void )
{
static BaseType_t xGiveFromTask = pdTRUE;
/* Ensure the slave is suspended, and that this task is running at the
lower priority as expected as the start conditions. */
#if( INCLUDE_eTaskGetState == 1 )
@ -295,27 +293,10 @@ static BaseType_t xGiveFromTask = pdTRUE;
/* Finally give back the shared mutex. This time the higher priority
task should run before this task runs again - so this task should have
disinherited the priority and the higher priority task should be in the
suspended state again. Alternatve beetween giving the mutex from this task,
and giving it from the interrupt. */
if( xGiveFromTask == pdTRUE )
{
if( xSemaphoreGive( xMasterSlaveMutex ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
/* Give the mutex from the interrupt on the next go around. */
xGiveFromTask = pdFALSE;
}
else
suspended state again. */
if( xSemaphoreGive( xMasterSlaveMutex ) != pdPASS )
{
/* Wait for the mutex to be given from the interrupt. */
xOkToGiveMasterSlaveMutex = pdTRUE;
vTaskDelay( xInterruptGivePeriod + ( xInterruptGivePeriod >> 1 ) );
xOkToGiveMasterSlaveMutex = pdFALSE;
/* Give the mutex from the task on the next go around. */
xGiveFromTask = pdTRUE;
xErrorDetected = pdTRUE;
}
if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY )
@ -533,36 +514,15 @@ TickType_t xTimeNow;
xTimeNow = xTaskGetTickCountFromISR();
if( ( ( TickType_t ) ( xTimeNow - xLastGiveTime ) ) >= pdMS_TO_TICKS( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ) )
{
configASSERT( xISRMutex );
if( xOkToGiveMutex != pdFALSE )
{
configASSERT( xISRMutex );
/* Null is used as the second parameter in this give, and non-NULL
in the other gives, for code coverage reasons. NOTE: This is a
Mutex, so xQueueGiveFromISR() should be used in place of
xSemaphoreGiveFromISR() in case there is a mutex holder that has
inherited a priority (although, in the case of xISRMutex, there
isn't). The "item to queue" parameter is set to NULL as no data is
copied into a mutex.*/
xQueueSendFromISR( ( QueueHandle_t ) xISRMutex, NULL, NULL );
/* Second give attempt should fail. */
configASSERT( xQueueSendFromISR( xISRMutex, NULL, &xHigherPriorityTaskWoken ) == pdFAIL );
}
if( xOkToGiveMasterSlaveMutex != pdFALSE )
{
configASSERT( xOkToGiveMasterSlaveMutex );
/* NOTE: This is a Mutex, so xQueueGiveFromISR() should be used in
place of xSemaphoreGiveFromISR() in case there is a mutex holder
that has inherited a priority (as indeed there is in this case).
The "item to queue" parameter is set to NULL as no data is copied
into a mutex. */
xQueueSendFromISR( ( QueueHandle_t ) xMasterSlaveMutex, NULL, NULL );
in the other gives for code coverage reasons. */
xSemaphoreGiveFromISR( xISRMutex, NULL );
/* Second give attempt should fail. */
configASSERT( xQueueSendFromISR( xMasterSlaveMutex, NULL, &xHigherPriorityTaskWoken ) == pdFAIL );
configASSERT( xSemaphoreGiveFromISR( xISRMutex, &xHigherPriorityTaskWoken ) == pdFAIL );
}
if( xOkToGiveCountingSemaphore != pdFALSE )

5
FreeRTOS/Demo/Common/Minimal/flop.c
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@ -90,7 +90,10 @@
/* Demo program include files. */
#include "flop.h"
#define mathSTACK_SIZE configMINIMAL_STACK_SIZE
#ifndef mathSTACK_SIZE
#define mathSTACK_SIZE configMINIMAL_STACK_SIZE
#endif
#define mathNUMBER_OF_TASKS ( 4 )
/* Four tasks, each of which performs a different floating point calculation.

668
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/include/xparameters.h
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@ -0,0 +1,668 @@
#ifndef XPARAMETERS_H /* prevent circular inclusions */
#define XPARAMETERS_H /* by using protection macros */
/* Definitions for bus frequencies */
#define XPAR_CPU_M_AXI_DP_FREQ_HZ 100000000
/******************************************************************/
/* Canonical definitions for bus frequencies */
/******************************************************************/
#define XPAR_CPU_CORE_CLOCK_FREQ_HZ 100000000
#define XPAR_MICROBLAZE_CORE_CLOCK_FREQ_HZ 100000000
/******************************************************************/
/* Definitions for peripheral MICROBLAZE_0 */
#define XPAR_MICROBLAZE_0_ADDR_TAG_BITS 15
#define XPAR_MICROBLAZE_0_ALLOW_DCACHE_WR 1
#define XPAR_MICROBLAZE_0_ALLOW_ICACHE_WR 1
#define XPAR_MICROBLAZE_0_AREA_OPTIMIZED 0
#define XPAR_MICROBLAZE_0_ASYNC_INTERRUPT 1
#define XPAR_MICROBLAZE_0_AVOID_PRIMITIVES 0
#define XPAR_MICROBLAZE_0_BASE_VECTORS 0x00000000
#define XPAR_MICROBLAZE_0_BRANCH_TARGET_CACHE_SIZE 0
#define XPAR_MICROBLAZE_0_CACHE_BYTE_SIZE 32768
#define XPAR_MICROBLAZE_0_DATA_SIZE 32
#define XPAR_MICROBLAZE_0_DCACHE_ADDR_TAG 15
#define XPAR_MICROBLAZE_0_DCACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_0_DCACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_0_DCACHE_BYTE_SIZE 32768
#define XPAR_MICROBLAZE_0_DCACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_0_DCACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_0_DCACHE_HIGHADDR 0xBFFFFFFF
#define XPAR_MICROBLAZE_0_DCACHE_LINE_LEN 8
#define XPAR_MICROBLAZE_0_DCACHE_USE_WRITEBACK 1
#define XPAR_MICROBLAZE_0_DCACHE_VICTIMS 8
#define XPAR_MICROBLAZE_0_DEBUG_COUNTER_WIDTH 32
#define XPAR_MICROBLAZE_0_DEBUG_ENABLED 1
#define XPAR_MICROBLAZE_0_DEBUG_EVENT_COUNTERS 5
#define XPAR_MICROBLAZE_0_DEBUG_EXTERNAL_TRACE 0
#define XPAR_MICROBLAZE_0_DEBUG_LATENCY_COUNTERS 1
#define XPAR_MICROBLAZE_0_DEBUG_PROFILE_SIZE 0
#define XPAR_MICROBLAZE_0_DEBUG_TRACE_SIZE 8192
#define XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION 1
#define XPAR_MICROBLAZE_0_DYNAMIC_BUS_SIZING 0
#define XPAR_MICROBLAZE_0_D_AXI 1
#define XPAR_MICROBLAZE_0_D_LMB 1
#define XPAR_MICROBLAZE_0_ECC_USE_CE_EXCEPTION 0
#define XPAR_MICROBLAZE_0_EDGE_IS_POSITIVE 1
#define XPAR_MICROBLAZE_0_ENABLE_DISCRETE_PORTS 0
#define XPAR_MICROBLAZE_0_ENDIANNESS 1
#define XPAR_MICROBLAZE_0_FAULT_TOLERANT 0
#define XPAR_MICROBLAZE_0_FPU_EXCEPTION 1
#define XPAR_MICROBLAZE_0_FREQ 100000000
#define XPAR_MICROBLAZE_0_FSL_EXCEPTION 0
#define XPAR_MICROBLAZE_0_FSL_LINKS 0
#define XPAR_MICROBLAZE_0_ICACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_0_ICACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_0_ICACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_0_ICACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_0_ICACHE_HIGHADDR 0xBFFFFFFF
#define XPAR_MICROBLAZE_0_ICACHE_LINE_LEN 8
#define XPAR_MICROBLAZE_0_ICACHE_STREAMS 1
#define XPAR_MICROBLAZE_0_ICACHE_VICTIMS 8
#define XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION 1
#define XPAR_MICROBLAZE_0_INTERCONNECT 2
#define XPAR_MICROBLAZE_0_INTERRUPT_IS_EDGE 0
#define XPAR_MICROBLAZE_0_I_AXI 0
#define XPAR_MICROBLAZE_0_I_LMB 1
#define XPAR_MICROBLAZE_0_LOCKSTEP_SELECT 0
#define XPAR_MICROBLAZE_0_LOCKSTEP_SLAVE 0
#define XPAR_MICROBLAZE_0_M0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_MMU_DTLB_SIZE 4
#define XPAR_MICROBLAZE_0_MMU_ITLB_SIZE 2
#define XPAR_MICROBLAZE_0_MMU_PRIVILEGED_INSTR 0
#define XPAR_MICROBLAZE_0_MMU_TLB_ACCESS 3
#define XPAR_MICROBLAZE_0_MMU_ZONES 2
#define XPAR_MICROBLAZE_0_M_AXI_DC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_DC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_0_M_AXI_DC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_0_M_AXI_DC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_DC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_DC_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_0_M_AXI_DC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_DC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_DC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_0_M_AXI_DC_USER_VALUE 31
#define XPAR_MICROBLAZE_0_M_AXI_DC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_DP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_DP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_DP_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_0_M_AXI_DP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_0_M_AXI_IC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_IC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_0_M_AXI_IC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_0_M_AXI_IC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_IC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_IC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_IC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_IC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_0_M_AXI_IC_USER_VALUE 31
#define XPAR_MICROBLAZE_0_M_AXI_IC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_IP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_IP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_IP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_0_NUMBER_OF_PC_BRK 8
#define XPAR_MICROBLAZE_0_NUMBER_OF_RD_ADDR_BRK 2
#define XPAR_MICROBLAZE_0_NUMBER_OF_WR_ADDR_BRK 2
#define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK 2
#define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK_DEBUG 2
#define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK_IRQ 1
#define XPAR_MICROBLAZE_0_NUM_SYNC_FF_DBG_CLK 1
#define XPAR_MICROBLAZE_0_OPCODE_0X0_ILLEGAL 1
#define XPAR_MICROBLAZE_0_OPTIMIZATION 0
#define XPAR_MICROBLAZE_0_PC_WIDTH 32
#define XPAR_MICROBLAZE_0_PVR 0
#define XPAR_MICROBLAZE_0_PVR_USER1 0x00
#define XPAR_MICROBLAZE_0_PVR_USER2 0x00000000
#define XPAR_MICROBLAZE_0_RESET_MSR 0x00000000
#define XPAR_MICROBLAZE_0_S0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_SCO 0
#define XPAR_MICROBLAZE_0_TRACE 1
#define XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS 1
#define XPAR_MICROBLAZE_0_USE_BARREL 1
#define XPAR_MICROBLAZE_0_USE_BRANCH_TARGET_CACHE 1
#define XPAR_MICROBLAZE_0_USE_CONFIG_RESET 0
#define XPAR_MICROBLAZE_0_USE_DCACHE 1
#define XPAR_MICROBLAZE_0_USE_DIV 1
#define XPAR_MICROBLAZE_0_USE_EXTENDED_FSL_INSTR 0
#define XPAR_MICROBLAZE_0_USE_EXT_BRK 0
#define XPAR_MICROBLAZE_0_USE_EXT_NM_BRK 0
#define XPAR_MICROBLAZE_0_USE_FPU 2
#define XPAR_MICROBLAZE_0_USE_HW_MUL 2
#define XPAR_MICROBLAZE_0_USE_ICACHE 1
#define XPAR_MICROBLAZE_0_USE_INTERRUPT 1
#define XPAR_MICROBLAZE_0_USE_MMU 0
#define XPAR_MICROBLAZE_0_USE_MSR_INSTR 1
#define XPAR_MICROBLAZE_0_USE_PCMP_INSTR 1
#define XPAR_MICROBLAZE_0_USE_REORDER_INSTR 1
#define XPAR_MICROBLAZE_0_USE_STACK_PROTECTION 1
#define XPAR_MICROBLAZE_0_COMPONENT_NAME base_microblaze_design_microblaze_0_0
#define XPAR_MICROBLAZE_0_EDK_IPTYPE PROCESSOR
#define XPAR_MICROBLAZE_0_EDK_SPECIAL microblaze
#define XPAR_MICROBLAZE_0_G_TEMPLATE_LIST 2
#define XPAR_MICROBLAZE_0_G_USE_EXCEPTIONS 1
/******************************************************************/
#define XPAR_CPU_ID 0
#define XPAR_MICROBLAZE_ID 0
#define XPAR_MICROBLAZE_ADDR_TAG_BITS 15
#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
#define XPAR_MICROBLAZE_ALLOW_ICACHE_WR 1
#define XPAR_MICROBLAZE_AREA_OPTIMIZED 0
#define XPAR_MICROBLAZE_ASYNC_INTERRUPT 1
#define XPAR_MICROBLAZE_AVOID_PRIMITIVES 0
#define XPAR_MICROBLAZE_BASE_VECTORS 0x00000000
#define XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE 0
#define XPAR_MICROBLAZE_CACHE_BYTE_SIZE 32768
#define XPAR_MICROBLAZE_DATA_SIZE 32
#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 15
#define XPAR_MICROBLAZE_DCACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_DCACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_DCACHE_BYTE_SIZE 32768
#define XPAR_MICROBLAZE_DCACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_DCACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0xBFFFFFFF
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 8
#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 1
#define XPAR_MICROBLAZE_DCACHE_VICTIMS 8
#define XPAR_MICROBLAZE_DEBUG_COUNTER_WIDTH 32
#define XPAR_MICROBLAZE_DEBUG_ENABLED 1
#define XPAR_MICROBLAZE_DEBUG_EVENT_COUNTERS 5
#define XPAR_MICROBLAZE_DEBUG_EXTERNAL_TRACE 0
#define XPAR_MICROBLAZE_DEBUG_LATENCY_COUNTERS 1
#define XPAR_MICROBLAZE_DEBUG_PROFILE_SIZE 0
#define XPAR_MICROBLAZE_DEBUG_TRACE_SIZE 8192
#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 1
#define XPAR_MICROBLAZE_DYNAMIC_BUS_SIZING 0
#define XPAR_MICROBLAZE_D_AXI 1
#define XPAR_MICROBLAZE_D_LMB 1
#define XPAR_MICROBLAZE_ECC_USE_CE_EXCEPTION 0
#define XPAR_MICROBLAZE_EDGE_IS_POSITIVE 1
#define XPAR_MICROBLAZE_ENABLE_DISCRETE_PORTS 0
#define XPAR_MICROBLAZE_ENDIANNESS 1
#define XPAR_MICROBLAZE_FAULT_TOLERANT 0
#define XPAR_MICROBLAZE_FPU_EXCEPTION 1
#define XPAR_MICROBLAZE_FREQ 100000000
#define XPAR_MICROBLAZE_FSL_EXCEPTION 0
#define XPAR_MICROBLAZE_FSL_LINKS 0
#define XPAR_MICROBLAZE_ICACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_ICACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_ICACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_ICACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0xBFFFFFFF
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 8
#define XPAR_MICROBLAZE_ICACHE_STREAMS 1
#define XPAR_MICROBLAZE_ICACHE_VICTIMS 8
#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 1
#define XPAR_MICROBLAZE_INTERCONNECT 2
#define XPAR_MICROBLAZE_INTERRUPT_IS_EDGE 0
#define XPAR_MICROBLAZE_I_AXI 0
#define XPAR_MICROBLAZE_I_LMB 1
#define XPAR_MICROBLAZE_LOCKSTEP_SELECT 0
#define XPAR_MICROBLAZE_LOCKSTEP_SLAVE 0
#define XPAR_MICROBLAZE_M0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MMU_DTLB_SIZE 4
#define XPAR_MICROBLAZE_MMU_ITLB_SIZE 2
#define XPAR_MICROBLAZE_MMU_PRIVILEGED_INSTR 0
#define XPAR_MICROBLAZE_MMU_TLB_ACCESS 3
#define XPAR_MICROBLAZE_MMU_ZONES 2
#define XPAR_MICROBLAZE_M_AXI_DC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_DC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_DC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DC_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_M_AXI_DC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_M_AXI_DC_USER_VALUE 31
#define XPAR_MICROBLAZE_M_AXI_DC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DP_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_M_AXI_DP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_M_AXI_IC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_IC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_IC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_M_AXI_IC_USER_VALUE 31
#define XPAR_MICROBLAZE_M_AXI_IC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_NUMBER_OF_PC_BRK 8
#define XPAR_MICROBLAZE_NUMBER_OF_RD_ADDR_BRK 2
#define XPAR_MICROBLAZE_NUMBER_OF_WR_ADDR_BRK 2
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK 2
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_DEBUG 2
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_IRQ 1
#define XPAR_MICROBLAZE_NUM_SYNC_FF_DBG_CLK 1
#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 1
#define XPAR_MICROBLAZE_OPTIMIZATION 0
#define XPAR_MICROBLAZE_PC_WIDTH 32
#define XPAR_MICROBLAZE_PVR 0
#define XPAR_MICROBLAZE_PVR_USER1 0x00
#define XPAR_MICROBLAZE_PVR_USER2 0x00000000
#define XPAR_MICROBLAZE_RESET_MSR 0x00000000
#define XPAR_MICROBLAZE_S0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_SCO 0
#define XPAR_MICROBLAZE_TRACE 1
#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 1
#define XPAR_MICROBLAZE_USE_BARREL 1
#define XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE 1
#define XPAR_MICROBLAZE_USE_CONFIG_RESET 0
#define XPAR_MICROBLAZE_USE_DCACHE 1
#define XPAR_MICROBLAZE_USE_DIV 1
#define XPAR_MICROBLAZE_USE_EXTENDED_FSL_INSTR 0
#define XPAR_MICROBLAZE_USE_EXT_BRK 0
#define XPAR_MICROBLAZE_USE_EXT_NM_BRK 0
#define XPAR_MICROBLAZE_USE_FPU 2
#define XPAR_MICROBLAZE_USE_HW_MUL 2
#define XPAR_MICROBLAZE_USE_ICACHE 1
#define XPAR_MICROBLAZE_USE_INTERRUPT 1
#define XPAR_MICROBLAZE_USE_MMU 0
#define XPAR_MICROBLAZE_USE_MSR_INSTR 1
#define XPAR_MICROBLAZE_USE_PCMP_INSTR 1
#define XPAR_MICROBLAZE_USE_REORDER_INSTR 1
#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 1
#define XPAR_MICROBLAZE_COMPONENT_NAME base_microblaze_design_microblaze_0_0
#define XPAR_MICROBLAZE_EDK_IPTYPE PROCESSOR
#define XPAR_MICROBLAZE_EDK_SPECIAL microblaze
#define XPAR_MICROBLAZE_G_TEMPLATE_LIST 2
#define XPAR_MICROBLAZE_G_USE_EXCEPTIONS 1
/******************************************************************/
/******************************************************************/
/* Definitions for driver BRAM */
#define XPAR_XBRAM_NUM_INSTANCES 2
/* Definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR */
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID 0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC 0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_FAULT_INJECT 0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS 0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS 0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS 0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH 0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER 0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_WRITE_ACCESS 2
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_BASEADDR 0x00000000
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR 0x0003FFFF
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF
/* Definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR */
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID 1
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC 0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_FAULT_INJECT 0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS 0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS 0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS 0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH 0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER 0
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_WRITE_ACCESS 2
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_BASEADDR 0x00000000
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR 0x0003FFFF
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF
/******************************************************************/
/* Canonical definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR */
#define XPAR_BRAM_0_DEVICE_ID XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID
#define XPAR_BRAM_0_DATA_WIDTH 32
#define XPAR_BRAM_0_ECC 0
#define XPAR_BRAM_0_FAULT_INJECT 0
#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0
#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0
#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 1
#define XPAR_BRAM_0_WRITE_ACCESS 2
#define XPAR_BRAM_0_BASEADDR 0x00000000
#define XPAR_BRAM_0_HIGHADDR 0x0003FFFF
/* Canonical definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR */
#define XPAR_BRAM_1_DEVICE_ID XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID
#define XPAR_BRAM_1_DATA_WIDTH 32
#define XPAR_BRAM_1_ECC 0
#define XPAR_BRAM_1_FAULT_INJECT 0
#define XPAR_BRAM_1_CE_FAILING_REGISTERS 0
#define XPAR_BRAM_1_UE_FAILING_REGISTERS 0
#define XPAR_BRAM_1_ECC_STATUS_REGISTERS 0
#define XPAR_BRAM_1_CE_COUNTER_WIDTH 0
#define XPAR_BRAM_1_ECC_ONOFF_REGISTER 0
#define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 1
#define XPAR_BRAM_1_WRITE_ACCESS 2
#define XPAR_BRAM_1_BASEADDR 0x00000000
#define XPAR_BRAM_1_HIGHADDR 0x0003FFFF
/******************************************************************/
/* Definitions for driver EMACLITE */
#define XPAR_XEMACLITE_NUM_INSTANCES 1
/* Definitions for peripheral AXI_ETHERNETLITE_0 */
#define XPAR_AXI_ETHERNETLITE_0_DEVICE_ID 0
#define XPAR_AXI_ETHERNETLITE_0_BASEADDR 0x40E00000
#define XPAR_AXI_ETHERNETLITE_0_HIGHADDR 0x40E0FFFF
#define XPAR_AXI_ETHERNETLITE_0_TX_PING_PONG 1
#define XPAR_AXI_ETHERNETLITE_0_RX_PING_PONG 1
#define XPAR_AXI_ETHERNETLITE_0_INCLUDE_MDIO 1
#define XPAR_AXI_ETHERNETLITE_0_INCLUDE_INTERNAL_LOOPBACK 0
/******************************************************************/
/* Canonical definitions for peripheral AXI_ETHERNETLITE_0 */
#define XPAR_EMACLITE_0_DEVICE_ID XPAR_AXI_ETHERNETLITE_0_DEVICE_ID
#define XPAR_EMACLITE_0_BASEADDR 0x40E00000
#define XPAR_EMACLITE_0_HIGHADDR 0x40E0FFFF
#define XPAR_EMACLITE_0_TX_PING_PONG 1
#define XPAR_EMACLITE_0_RX_PING_PONG 1
#define XPAR_EMACLITE_0_INCLUDE_MDIO 1
#define XPAR_EMACLITE_0_INCLUDE_INTERNAL_LOOPBACK 0
/******************************************************************/
/* Definitions for driver GPIO */
#define XPAR_XGPIO_NUM_INSTANCES 1
/* Definitions for peripheral AXI_GPIO_0 */
#define XPAR_AXI_GPIO_0_BASEADDR 0x40000000
#define XPAR_AXI_GPIO_0_HIGHADDR 0x4000FFFF
#define XPAR_AXI_GPIO_0_DEVICE_ID 0
#define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0
#define XPAR_AXI_GPIO_0_IS_DUAL 0
/******************************************************************/
/* Canonical definitions for peripheral AXI_GPIO_0 */
#define XPAR_GPIO_0_BASEADDR 0x40000000
#define XPAR_GPIO_0_HIGHADDR 0x4000FFFF
#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
#define XPAR_GPIO_0_INTERRUPT_PRESENT 0
#define XPAR_GPIO_0_IS_DUAL 0
/******************************************************************/
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 3
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_HAS_SIE 1
#define XPAR_XINTC_HAS_CIE 1
#define XPAR_XINTC_HAS_IVR 1
/* Definitions for driver INTC */
#define XPAR_XINTC_NUM_INSTANCES 1
/* Definitions for peripheral AXI_INTC_0 */
#define XPAR_AXI_INTC_0_DEVICE_ID 0
#define XPAR_AXI_INTC_0_BASEADDR 0x41200000
#define XPAR_AXI_INTC_0_HIGHADDR 0x4120FFFF
#define XPAR_AXI_INTC_0_KIND_OF_INTR 0xFFFFFFFE
#define XPAR_AXI_INTC_0_HAS_FAST 0
#define XPAR_AXI_INTC_0_IVAR_RESET_VALUE 0x00000010
#define XPAR_AXI_INTC_0_NUM_INTR_INPUTS 3
/******************************************************************/
#define XPAR_INTC_SINGLE_BASEADDR 0x41200000
#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_AXI_INTC_0_DEVICE_ID
#define XPAR_AXI_INTC_0_TYPE 0
#define XPAR_AXI_TIMER_0_INTERRUPT_MASK 0X000001
#define XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR 0
#define XPAR_AXI_UARTLITE_0_INTERRUPT_MASK 0X000002
#define XPAR_AXI_INTC_0_AXI_UARTLITE_0_INTERRUPT_INTR 1
#define XPAR_AXI_ETHERNETLITE_0_IP2INTC_IRPT_MASK 0X000004
#define XPAR_AXI_INTC_0_AXI_ETHERNETLITE_0_IP2INTC_IRPT_INTR 2
/******************************************************************/
/* Canonical definitions for peripheral AXI_INTC_0 */
#define XPAR_INTC_0_DEVICE_ID XPAR_AXI_INTC_0_DEVICE_ID
#define XPAR_INTC_0_BASEADDR 0x41200000
#define XPAR_INTC_0_HIGHADDR 0x4120FFFF
#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFFE
#define XPAR_INTC_0_HAS_FAST 0
#define XPAR_INTC_0_IVAR_RESET_VALUE 0x00000010
#define XPAR_INTC_0_NUM_INTR_INPUTS 3
#define XPAR_INTC_0_INTC_TYPE 0
#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR
#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_AXI_INTC_0_AXI_UARTLITE_0_INTERRUPT_INTR
#define XPAR_INTC_0_EMACLITE_0_VEC_ID XPAR_AXI_INTC_0_AXI_ETHERNETLITE_0_IP2INTC_IRPT_INTR
/******************************************************************/
/* Definitions for driver MIG_7SERIES */
#define XPAR_XMIG7SERIES_NUM_INSTANCES 1
/* Definitions for peripheral MIG_7SERIES_0 */
#define XPAR_MIG_7SERIES_0_DEVICE_ID 0
#define XPAR_MIG_7SERIES_0_DDR3_ROW_WIDTH 14
#define XPAR_MIG_7SERIES_0_DDR3_COL_WIDTH 0
#define XPAR_MIG_7SERIES_0_DDR3_BANK_WIDTH 3
#define XPAR_MIG_7SERIES_0_DDR3_DQ_WIDTH 64
/******************************************************************/
/* Definitions for peripheral MIG_7SERIES_0 */
#define XPAR_MIG_7SERIES_0_BASEADDR 0x80000000
#define XPAR_MIG_7SERIES_0_HIGHADDR 0xBFFFFFFF
/******************************************************************/
/* Canonical definitions for peripheral MIG_7SERIES_0 */
#define XPAR_MIG7SERIES_0_DEVICE_ID XPAR_MIG_7SERIES_0_DEVICE_ID
#define XPAR_MIG7SERIES_0_DDR_ROW_WIDTH 14
#define XPAR_MIG7SERIES_0_DDR_COL_WIDTH 0
#define XPAR_MIG7SERIES_0_DDR_BANK_WIDTH 3
#define XPAR_MIG7SERIES_0_DDR_DQ_WIDTH 64
#define XPAR_MIG7SERIES_0_BASEADDR 0x80000000
#define XPAR_MIG7SERIES_0_HIGHADDR 0xBFFFFFFF
/******************************************************************/
/* Definitions for driver TMRCTR */
#define XPAR_XTMRCTR_NUM_INSTANCES 1
/* Definitions for peripheral AXI_TIMER_0 */
#define XPAR_AXI_TIMER_0_DEVICE_ID 0
#define XPAR_AXI_TIMER_0_BASEADDR 0x41C00000
#define XPAR_AXI_TIMER_0_HIGHADDR 0x41C0FFFF
#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 100000000
/******************************************************************/
/* Canonical definitions for peripheral AXI_TIMER_0 */
#define XPAR_TMRCTR_0_DEVICE_ID 0
#define XPAR_TMRCTR_0_BASEADDR 0x41C00000
#define XPAR_TMRCTR_0_HIGHADDR 0x41C0FFFF
#define XPAR_TMRCTR_0_CLOCK_FREQ_HZ XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ
/******************************************************************/
/* Definitions for driver UARTLITE */
#define XPAR_XUARTLITE_NUM_INSTANCES 1
/* Definitions for peripheral AXI_UARTLITE_0 */
#define XPAR_AXI_UARTLITE_0_BASEADDR 0x40600000
#define XPAR_AXI_UARTLITE_0_HIGHADDR 0x4060FFFF
#define XPAR_AXI_UARTLITE_0_DEVICE_ID 0
#define XPAR_AXI_UARTLITE_0_BAUDRATE 115200
#define XPAR_AXI_UARTLITE_0_USE_PARITY 0
#define XPAR_AXI_UARTLITE_0_ODD_PARITY 0
#define XPAR_AXI_UARTLITE_0_DATA_BITS 8
/******************************************************************/
/* Canonical definitions for peripheral AXI_UARTLITE_0 */
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_AXI_UARTLITE_0_DEVICE_ID
#define XPAR_UARTLITE_0_BASEADDR 0x40600000
#define XPAR_UARTLITE_0_HIGHADDR 0x4060FFFF
#define XPAR_UARTLITE_0_BAUDRATE 115200
#define XPAR_UARTLITE_0_USE_PARITY 0
#define XPAR_UARTLITE_0_ODD_PARITY 0
#define XPAR_UARTLITE_0_DATA_BITS 8
/******************************************************************/
#endif /* end of protection macro */

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FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/Makefile
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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling bram"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
make clean
include:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OUTS}

144
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram.c
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/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/**
* @file xbram.c
*
* The implementation of the XBram driver's basic functionality.
* See xbram.h for more information about the driver.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 05/11/10 First release
* 3.01a sa 13/01/12 Added CorrectableFailingDataRegs and
* UncorrectableFailingDataRegs in
* XBram_CfgInitialize API.
*</pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xbram.h"
#include "xstatus.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
* Initialize the XBram instance provided by the caller based on the given
* configuration data.
*
* Nothing is done except to initialize the InstancePtr.
*
* @param InstancePtr is a pointer to an XBram instance.
* The memory the pointer references must be pre-allocated by
* the caller. Further calls to manipulate the driver through
* the XBram API must be made with this pointer.
* @param Config is a reference to a structure containing information
* about a specific BRAM device. This function
* initializes an InstancePtr object for a specific device
* specified by the contents of Config. This function can
* initialize multiple instance objects with the use of multiple
* calls giving different Config information on each call.
* @param EffectiveAddr is the device base address in the virtual memory
* address space. The caller is responsible for keeping the
* address mapping from EffectiveAddr to the device physical base
* address unchanged once this function is invoked. Unexpected
* errors may occur if the address mapping changes after this
* function is called. If address translation is not used, use
* Config->BaseAddress for this parameters, passing the physical
* address instead.
*
* @return
* - XST_SUCCESS Initialization was successful.
*
* @note None.
*
*****************************************************************************/
int XBram_CfgInitialize(XBram *InstancePtr,
XBram_Config *Config,
u32 EffectiveAddr)
{
/*
* Assert arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
/*
* Set some default values.
*/
InstancePtr->Config.CtrlBaseAddress = EffectiveAddr;
InstancePtr->Config.MemBaseAddress = Config->MemBaseAddress;
InstancePtr->Config.MemHighAddress = Config->MemHighAddress;
InstancePtr->Config.DataWidth = Config->DataWidth;
InstancePtr->Config.EccPresent = Config->EccPresent;
InstancePtr->Config.FaultInjectionPresent =
Config->FaultInjectionPresent;
InstancePtr->Config.CorrectableFailingRegisters =
Config->CorrectableFailingRegisters;
InstancePtr->Config.CorrectableFailingDataRegs =
Config->CorrectableFailingDataRegs;
InstancePtr->Config.UncorrectableFailingRegisters =
Config->UncorrectableFailingRegisters;
InstancePtr->Config.UncorrectableFailingDataRegs =
Config->UncorrectableFailingDataRegs;
InstancePtr->Config.EccStatusInterruptPresent =
Config->EccStatusInterruptPresent;
InstancePtr->Config.CorrectableCounterBits =
Config->CorrectableCounterBits;
InstancePtr->Config.WriteAccess = Config->WriteAccess;
/*
* Indicate the instance is now ready to use, initialized without error
*/
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return (XST_SUCCESS);
}

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/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xbram.h
*
* If ECC is not enabled, this driver exists only to allow the tools to
* create a memory test application and to populate xparameters.h with memory
* range constants. In this case there is no source code.
*
* If ECC is enabled, this file contains the software API definition of the
* Xilinx BRAM Interface Controller (XBram) device driver.
*
* The Xilinx BRAM controller is a soft IP core designed for Xilinx
* FPGAs and contains the following general features:
* - LMB v2.0 bus interfaces with byte enable support
* - Used in conjunction with bram_block peripheral to provide fast BRAM
* memory solution for MicroBlaze ILMB and DLMB ports
* - Supports byte, half-word, and word transfers
* - Supports optional BRAM error correction and detection.
*
* The driver provides interrupt management functions. Implementation of
* interrupt handlers is left to the user. Refer to the provided interrupt
* example in the examples directory for details.
*
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, virtual
* memory, or cache control must be satisfied by the layer above this driver.
*
* <b>Initialization & Configuration</b>
*
* The XBram_Config structure is used by the driver to configure
* itself. This configuration structure is typically created by the tool-chain
* based on HW build properties.
*
* To support multiple runtime loading and initialization strategies employed
* by various operating systems, the driver instance can be initialized as
* follows:
*
* - XBram_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) -
* Uses a configuration structure provided by the caller. If running in a
* system with address translation, the provided virtual memory base address
* replaces the physical address present in the configuration structure.
*
* @note
*
* This API utilizes 32 bit I/O to the BRAM registers. With less
* than 32 bits, the unused bits from registers are read as zero and written as
* don't cares.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 3.00a sa 05/11/10 Added ECC support
* 3.01a sa 01/13/12 Changed Selftest API from
* XBram_SelfTest(XBram *InstancePtr) to
* XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
* fixed a problem with interrupt generation for CR 639274
* Modified Selftest example to return XST_SUCCESS when
* ECC is not enabled and return XST_FAILURE when ECC is
* enabled and Control Base Address is zero (CR 636581)
* Modified Selftest to use correct CorrectableCounterBits
* for CR 635655
* Updated to check CorrectableFailingDataRegs in the case
* of LMB BRAM.
* Added CorrectableFailingDataRegs and
* UncorrectableFailingDataRegs to the config structure to
* distinguish between AXI BRAM and LMB BRAM.
* These registers are not present in the current version of
* the AXI BRAM Controller.
* 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
* 3.02a sa 04/16/12 Modified driver tcl to sort the address parameters
* to support both xps and vivado designs.
* 3.02a adk 24/4/13 Modified the tcl file to avoid warnings
* when ecc is disabled cr:705002.
* 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in xbram_selftest.c to
* flush the Cache after writing to BRAM in InjectErrors
* API(CR #719011)
* 4.0 adk 19/12/13 Updated as per the New Tcl API's
* </pre>
*****************************************************************************/
#ifndef XBRAM_H /* prevent circular inclusions */
#define XBRAM_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xbram_hw.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 DataWidth; /**< BRAM data width */
int EccPresent; /**< Is ECC supported in H/W */
int FaultInjectionPresent; /**< Is Fault Injection
* supported in H/W */
int CorrectableFailingRegisters; /**< Is Correctable Failing Registers
* supported in H/W */
int CorrectableFailingDataRegs; /**< Is Correctable Failing Data
* Registers supported in H/W */
int UncorrectableFailingRegisters; /**< Is Un-correctable Failing
* Registers supported in H/W */
int UncorrectableFailingDataRegs; /**< Is Un-correctable Failing Data
* Registers supported in H/W */
int EccStatusInterruptPresent; /**< Are ECC status and interrupts
* supported in H/W */
int CorrectableCounterBits; /**< Number of bits in the
* Correctable Error Counter */
int EccOnOffRegister; /**< Is ECC on/off register supported
* in h/w */
int EccOnOffResetValue; /**< Reset value of the ECC on/off
* register in h/w */
int WriteAccess; /**< Is write access enabled in
* h/w */
u32 MemBaseAddress; /**< Device memory base address */
u32 MemHighAddress; /**< Device memory high address */
u32 CtrlBaseAddress; /**< Device register base address.*/
u32 CtrlHighAddress; /**< Device register base address.*/
} XBram_Config;
/**
* The XBram driver instance data. The user is required to
* allocate a variable of this type for every BRAM device in the
* system. A pointer to a variable of this type is then passed to the driver
* API functions.
*/
typedef struct {
XBram_Config Config; /* BRAM config structure */
u32 IsReady; /* Device is initialized and ready */
} XBram;
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Function Prototypes *****************************/
/*
* Functions in xbram_sinit.c
*/
XBram_Config *XBram_LookupConfig(u16 DeviceId);
/*
* Functions implemented in xbram.c
*/
int XBram_CfgInitialize(XBram *InstancePtr, XBram_Config *Config,
u32 EffectiveAddr);
/*
* Functions implemented in xbram_selftest.c
*/
int XBram_SelfTest(XBram *InstancePtr, u8 IntMask);
/*
* Functions implemented in xbram_intr.c
*/
void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask);
void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask);
void XBram_InterruptClear(XBram *InstancePtr, u32 Mask);
u32 XBram_InterruptGetEnabled(XBram *InstancePtr);
u32 XBram_InterruptGetStatus(XBram *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xbram.h"
/*
* The configuration table for devices
*/
XBram_Config XBram_ConfigTable[] =
{
{
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DATA_WIDTH,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_FAULT_INJECT,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_WRITE_ACCESS,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_BASEADDR,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR
},
{
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DATA_WIDTH,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_FAULT_INJECT,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_WRITE_ACCESS,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_BASEADDR,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR,
XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR
}
};

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/******************************************************************************
*
* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbram_hw.h
*
* This header file contains identifiers and driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 24/11/10 First release
* </pre>
*
******************************************************************************/
#ifndef XBRAM_HW_H /* prevent circular inclusions */
#define XBRAM_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Registers
*
* Register offsets for this device.
* @{
*/
#define XBRAM_ECC_STATUS_OFFSET 0x0 /**< ECC status Register */
#define XBRAM_ECC_EN_IRQ_OFFSET 0x4 /**< ECC interrupt enable Register */
#define XBRAM_ECC_ON_OFF_OFFSET 0x8 /**< ECC on/off register */
#define XBRAM_CE_CNT_OFFSET 0xC /**< Correctable error counter Register */
#define XBRAM_CE_FFD_0_OFFSET 0x100 /**< Correctable error first failing
* data Register, 31-0 */
#define XBRAM_CE_FFD_1_OFFSET 0x104 /**< Correctable error first failing
* data Register, 63-32 */
#define XBRAM_CE_FFD_2_OFFSET 0x108 /**< Correctable error first failing
* data Register, 95-64 */
#define XBRAM_CE_FFD_3_OFFSET 0x10C /**< Correctable error first failing
* data Register, 127-96 */
#define XBRAM_CE_FFD_4_OFFSET 0x110 /**< Correctable error first failing
* data Register, 159-128 */
#define XBRAM_CE_FFD_5_OFFSET 0x114 /**< Correctable error first failing
* data Register, 191-160 */
#define XBRAM_CE_FFD_6_OFFSET 0x118 /**< Correctable error first failing
* data Register, 223-192 */
#define XBRAM_CE_FFD_7_OFFSET 0x11C /**< Correctable error first failing
* data Register, 255-224 */
#define XBRAM_CE_FFD_8_OFFSET 0x120 /**< Correctable error first failing
* data Register, 287-256 */
#define XBRAM_CE_FFD_9_OFFSET 0x124 /**< Correctable error first failing
* data Register, 319-288 */
#define XBRAM_CE_FFD_10_OFFSET 0x128 /**< Correctable error first failing
* data Register, 351-320 */
#define XBRAM_CE_FFD_11_OFFSET 0x12C /**< Correctable error first failing
* data Register, 383-352 */
#define XBRAM_CE_FFD_12_OFFSET 0x130 /**< Correctable error first failing
* data Register, 415-384 */
#define XBRAM_CE_FFD_13_OFFSET 0x134 /**< Correctable error first failing
* data Register, 447-416 */
#define XBRAM_CE_FFD_14_OFFSET 0x138 /**< Correctable error first failing
* data Register, 479-448 */
#define XBRAM_CE_FFD_15_OFFSET 0x13C /**< Correctable error first failing
* data Register, 511-480 */
#define XBRAM_CE_FFD_16_OFFSET 0x140 /**< Correctable error first failing
* data Register, 543-512 */
#define XBRAM_CE_FFD_17_OFFSET 0x144 /**< Correctable error first failing
* data Register, 575-544 */
#define XBRAM_CE_FFD_18_OFFSET 0x148 /**< Correctable error first failing
* data Register, 607-576 */
#define XBRAM_CE_FFD_19_OFFSET 0x14C /**< Correctable error first failing
* data Register, 639-608 */
#define XBRAM_CE_FFD_20_OFFSET 0x150 /**< Correctable error first failing
* data Register, 671-640 */
#define XBRAM_CE_FFD_21_OFFSET 0x154 /**< Correctable error first failing
* data Register, 703-672 */
#define XBRAM_CE_FFD_22_OFFSET 0x158 /**< Correctable error first failing
* data Register, 735-704 */
#define XBRAM_CE_FFD_23_OFFSET 0x15C /**< Correctable error first failing
* data Register, 767-736 */
#define XBRAM_CE_FFD_24_OFFSET 0x160 /**< Correctable error first failing
* data Register, 799-768 */
#define XBRAM_CE_FFD_25_OFFSET 0x164 /**< Correctable error first failing
* data Register, 831-800 */
#define XBRAM_CE_FFD_26_OFFSET 0x168 /**< Correctable error first failing
* data Register, 863-832 */
#define XBRAM_CE_FFD_27_OFFSET 0x16C /**< Correctable error first failing
* data Register, 895-864 */
#define XBRAM_CE_FFD_28_OFFSET 0x170 /**< Correctable error first failing
* data Register, 927-896 */
#define XBRAM_CE_FFD_29_OFFSET 0x174 /**< Correctable error first failing
* data Register, 959-928 */
#define XBRAM_CE_FFD_30_OFFSET 0x178 /**< Correctable error first failing
* data Register, 991-960 */
#define XBRAM_CE_FFD_31_OFFSET 0x17C /**< Correctable error first failing
* data Register, 1023-992 */
#define XBRAM_CE_FFE_0_OFFSET 0x180 /**< Correctable error first failing
* ECC Register, 31-0 */
#define XBRAM_CE_FFE_1_OFFSET 0x184 /**< Correctable error first failing
* ECC Register, 63-32 */
#define XBRAM_CE_FFE_2_OFFSET 0x188 /**< Correctable error first failing
* ECC Register, 95-64 */
#define XBRAM_CE_FFE_3_OFFSET 0x18C /**< Correctable error first failing
* ECC Register, 127-96 */
#define XBRAM_CE_FFE_4_OFFSET 0x190 /**< Correctable error first failing
* ECC Register, 159-128 */
#define XBRAM_CE_FFE_5_OFFSET 0x194 /**< Correctable error first failing
* ECC Register, 191-160 */
#define XBRAM_CE_FFE_6_OFFSET 0x198 /**< Correctable error first failing
* ECC Register, 223-192 */
#define XBRAM_CE_FFE_7_OFFSET 0x19C /**< Correctable error first failing
* ECC Register, 255-224 */
#define XBRAM_CE_FFA_0_OFFSET 0x1C0 /**< Correctable error first failing
* address Register 31-0 */
#define XBRAM_CE_FFA_1_OFFSET 0x1C4 /**< Correctable error first failing
* address Register 63-32 */
#define XBRAM_UE_FFD_0_OFFSET 0x200 /**< Uncorrectable error first failing
* data Register, 31-0 */
#define XBRAM_UE_FFD_1_OFFSET 0x204 /**< Uncorrectable error first failing
* data Register, 63-32 */
#define XBRAM_UE_FFD_2_OFFSET 0x208 /**< Uncorrectable error first failing
* data Register, 95-64 */
#define XBRAM_UE_FFD_3_OFFSET 0x20C /**< Uncorrectable error first failing
* data Register, 127-96 */
#define XBRAM_UE_FFD_4_OFFSET 0x210 /**< Uncorrectable error first failing
* data Register, 159-128 */
#define XBRAM_UE_FFD_5_OFFSET 0x214 /**< Uncorrectable error first failing
* data Register, 191-160 */
#define XBRAM_UE_FFD_6_OFFSET 0x218 /**< Uncorrectable error first failing
* data Register, 223-192 */
#define XBRAM_UE_FFD_7_OFFSET 0x21C /**< Uncorrectable error first failing
* data Register, 255-224 */
#define XBRAM_UE_FFD_8_OFFSET 0x220 /**< Uncorrectable error first failing
* data Register, 287-256 */
#define XBRAM_UE_FFD_9_OFFSET 0x224 /**< Uncorrectable error first failing
* data Register, 319-288 */
#define XBRAM_UE_FFD_10_OFFSET 0x228 /**< Uncorrectable error first failing
* data Register, 351-320 */
#define XBRAM_UE_FFD_11_OFFSET 0x22C /**< Uncorrectable error first failing
* data Register, 383-352 */
#define XBRAM_UE_FFD_12_OFFSET 0x230 /**< Uncorrectable error first failing
* data Register, 415-384 */
#define XBRAM_UE_FFD_13_OFFSET 0x234 /**< Uncorrectable error first failing
* data Register, 447-416 */
#define XBRAM_UE_FFD_14_OFFSET 0x238 /**< Uncorrectable error first failing
* data Register, 479-448 */
#define XBRAM_UE_FFD_15_OFFSET 0x23C /**< Uncorrectable error first failing
* data Register, 511-480 */
#define XBRAM_UE_FFD_16_OFFSET 0x240 /**< Uncorrectable error first failing
* data Register, 543-512 */
#define XBRAM_UE_FFD_17_OFFSET 0x244 /**< Uncorrectable error first failing
* data Register, 575-544 */
#define XBRAM_UE_FFD_18_OFFSET 0x248 /**< Uncorrectable error first failing
* data Register, 607-576 */
#define XBRAM_UE_FFD_19_OFFSET 0x24C /**< Uncorrectable error first failing
* data Register, 639-608 */
#define XBRAM_UE_FFD_20_OFFSET 0x250 /**< Uncorrectable error first failing
* data Register, 671-640 */
#define XBRAM_UE_FFD_21_OFFSET 0x254 /**< Uncorrectable error first failing
* data Register, 703-672 */
#define XBRAM_UE_FFD_22_OFFSET 0x258 /**< Uncorrectable error first failing
* data Register, 735-704 */
#define XBRAM_UE_FFD_23_OFFSET 0x25C /**< Uncorrectable error first failing
* data Register, 767-736 */
#define XBRAM_UE_FFD_24_OFFSET 0x260 /**< Uncorrectable error first failing
* data Register, 799-768 */
#define XBRAM_UE_FFD_25_OFFSET 0x264 /**< Uncorrectable error first failing
* data Register, 831-800 */
#define XBRAM_UE_FFD_26_OFFSET 0x268 /**< Uncorrectable error first failing
* data Register, 863-832 */
#define XBRAM_UE_FFD_27_OFFSET 0x26C /**< Uncorrectable error first failing
* data Register, 895-864 */
#define XBRAM_UE_FFD_28_OFFSET 0x270 /**< Uncorrectable error first failing
* data Register, 927-896 */
#define XBRAM_UE_FFD_29_OFFSET 0x274 /**< Uncorrectable error first failing
* data Register, 959-928 */
#define XBRAM_UE_FFD_30_OFFSET 0x278 /**< Uncorrectable error first failing
* data Register, 991-960 */
#define XBRAM_UE_FFD_31_OFFSET 0x27C /**< Uncorrectable error first failing
* data Register, 1023-992 */
#define XBRAM_UE_FFE_0_OFFSET 0x280 /**< Uncorrectable error first failing
* ECC Register, 31-0 */
#define XBRAM_UE_FFE_1_OFFSET 0x284 /**< Uncorrectable error first failing
* ECC Register, 63-32 */
#define XBRAM_UE_FFE_2_OFFSET 0x288 /**< Uncorrectable error first failing
* ECC Register, 95-64 */
#define XBRAM_UE_FFE_3_OFFSET 0x28C /**< Uncorrectable error first failing
* ECC Register, 127-96 */
#define XBRAM_UE_FFE_4_OFFSET 0x290 /**< Uncorrectable error first failing
* ECC Register, 159-128 */
#define XBRAM_UE_FFE_5_OFFSET 0x294 /**< Uncorrectable error first failing
* ECC Register, 191-160 */
#define XBRAM_UE_FFE_6_OFFSET 0x298 /**< Uncorrectable error first failing
* ECC Register, 223-192 */
#define XBRAM_UE_FFE_7_OFFSET 0x29C /**< Uncorrectable error first failing
* ECC Register, 255-224 */
#define XBRAM_UE_FFA_0_OFFSET 0x2C0 /**< Uncorrectable error first failing
* address Register 31-0 */
#define XBRAM_UE_FFA_1_OFFSET 0x2C4 /**< Uncorrectable error first failing
* address Register 63-32 */
#define XBRAM_FI_D_0_OFFSET 0x300 /**< Fault injection Data Register,
* 31-0 */
#define XBRAM_FI_D_1_OFFSET 0x304 /**< Fault injection Data Register,
* 63-32 */
#define XBRAM_FI_D_2_OFFSET 0x308 /**< Fault injection Data Register,
* 95-64 */
#define XBRAM_FI_D_3_OFFSET 0x30C /**< Fault injection Data Register,
* 127-96 */
#define XBRAM_FI_D_4_OFFSET 0x310 /**< Fault injection Data Register,
* 159-128 */
#define XBRAM_FI_D_5_OFFSET 0x314 /**< Fault injection Data Register,
* 191-160 */
#define XBRAM_FI_D_6_OFFSET 0x318 /**< Fault injection Data Register,
* 223-192 */
#define XBRAM_FI_D_7_OFFSET 0x31C /**< Fault injection Data Register,
* 255-224 */
#define XBRAM_FI_D_8_OFFSET 0x320 /**< Fault injection Data Register,
* 287-256 */
#define XBRAM_FI_D_9_OFFSET 0x324 /**< Fault injection Data Register,
* 319-288 */
#define XBRAM_FI_D_10_OFFSET 0x328 /**< Fault injection Data Register,
* 351-320 */
#define XBRAM_FI_D_11_OFFSET 0x32C /**< Fault injection Data Register,
* 383-352 */
#define XBRAM_FI_D_12_OFFSET 0x330 /**< Fault injection Data Register,
* 415-384 */
#define XBRAM_FI_D_13_OFFSET 0x334 /**< Fault injection Data Register,
* 447-416 */
#define XBRAM_FI_D_14_OFFSET 0x338 /**< Fault injection Data Register,
* 479-448 */
#define XBRAM_FI_D_15_OFFSET 0x33C /**< Fault injection Data Register,
* 511-480 */
#define XBRAM_FI_D_16_OFFSET 0x340 /**< Fault injection Data Register,
* 543-512 */
#define XBRAM_FI_D_17_OFFSET 0x344 /**< Fault injection Data Register,
* 575-544 */
#define XBRAM_FI_D_18_OFFSET 0x348 /**< Fault injection Data Register,
* 607-576 */
#define XBRAM_FI_D_19_OFFSET 0x34C /**< Fault injection Data Register,
* 639-608 */
#define XBRAM_FI_D_20_OFFSET 0x350 /**< Fault injection Data Register,
* 671-640 */
#define XBRAM_FI_D_21_OFFSET 0x354 /**< Fault injection Data Register,
* 703-672 */
#define XBRAM_FI_D_22_OFFSET 0x358 /**< Fault injection Data Register,
* 735-704 */
#define XBRAM_FI_D_23_OFFSET 0x35C /**< Fault injection Data Register,
* 767-736 */
#define XBRAM_FI_D_24_OFFSET 0x360 /**< Fault injection Data Register,
* 799-768 */
#define XBRAM_FI_D_25_OFFSET 0x364 /**< Fault injection Data Register,
* 831-800 */
#define XBRAM_FI_D_26_OFFSET 0x368 /**< Fault injection Data Register,
* 863-832 */
#define XBRAM_FI_D_27_OFFSET 0x36C /**< Fault injection Data Register,
* 895-864 */
#define XBRAM_FI_D_28_OFFSET 0x370 /**< Fault injection Data Register,
* 927-896 */
#define XBRAM_FI_D_29_OFFSET 0x374 /**< Fault injection Data Register,
* 959-928 */
#define XBRAM_FI_D_30_OFFSET 0x378 /**< Fault injection Data Register,
* 991-960 */
#define XBRAM_FI_D_31_OFFSET 0x37C /**< Fault injection Data Register,
* 1023-992 */
#define XBRAM_FI_ECC_0_OFFSET 0x380 /**< Fault injection ECC Register,
* 31-0 */
#define XBRAM_FI_ECC_1_OFFSET 0x384 /**< Fault injection ECC Register,
* 63-32 */
#define XBRAM_FI_ECC_2_OFFSET 0x388 /**< Fault injection ECC Register,
* 95-64 */
#define XBRAM_FI_ECC_3_OFFSET 0x38C /**< Fault injection ECC Register,
* 127-96 */
#define XBRAM_FI_ECC_4_OFFSET 0x390 /**< Fault injection ECC Register,
* 159-128 */
#define XBRAM_FI_ECC_5_OFFSET 0x394 /**< Fault injection ECC Register,
* 191-160 */
#define XBRAM_FI_ECC_6_OFFSET 0x398 /**< Fault injection ECC Register,
* 223-192 */
#define XBRAM_FI_ECC_7_OFFSET 0x39C /**< Fault injection ECC Register,
* 255-224 */
/* @} */
/** @name Interrupt Status and Enable Register bitmaps and masks
*
* Bit definitions for the ECC status register and ECC interrupt enable register.
* @{
*/
#define XBRAM_IR_CE_MASK 0x2 /**< Mask for the correctable error */
#define XBRAM_IR_UE_MASK 0x1 /**< Mask for the uncorrectable error */
#define XBRAM_IR_ALL_MASK 0x3 /**< Mask of all bits */
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XBram_In32 Xil_In32
#define XBram_Out32 Xil_Out32
#define XBram_In16 Xil_In16
#define XBram_Out16 Xil_Out16
#define XBram_In8 Xil_In8
#define XBram_Out8 Xil_Out8
/****************************************************************************/
/**
*
* Write a value to a BRAM register. A 32 bit write is performed.
*
* @param BaseAddress is the base address of the BRAM device register.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note C-style signature:
* void XBram_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
****************************************************************************/
#define XBram_WriteReg(BaseAddress, RegOffset, Data) \
XBram_Out32((BaseAddress) + (RegOffset), (u32)(Data))
/****************************************************************************/
/**
*
* Read a value from a BRAM register. A 32 bit read is performed.
*
* @param BaseAddress is the base address of the BRAM device registers.
* @param RegOffset is the register offset from the base to read from.
*
* @return Data read from the register.
*
* @note C-style signature:
* u32 XBram_ReadReg(u32 BaseAddress, u32 RegOffset)
*
****************************************************************************/
#define XBram_ReadReg(BaseAddress, RegOffset) \
XBram_In32((BaseAddress) + (RegOffset))
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_intr.c
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/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xbram_intr.c
*
* Implements BRAM interrupt processing functions for the
* XBram driver. See xbram.h for more information
* about the driver.
*
* The functions in this file require the hardware device to be built with
* interrupt capabilities. The functions will assert if called using hardware
* that does not have interrupt capabilities.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 05/11/10 Initial release
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xbram.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
* Enable interrupts. This function will assert if the hardware device has not
* been built with interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
* @param Mask is the mask to enable. Bit positions of 1 are enabled.
* This mask is formed by OR'ing bits from XBRAM_IR*
* bits which are contained in xbram_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
/*
* Read the interrupt enable register and only enable the specified
* interrupts without disabling or enabling any others.
*/
Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET);
XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET,
Register | Mask);
}
/****************************************************************************/
/**
* Disable interrupts. This function allows each specific interrupt to be
* disabled. This function will assert if the hardware device has not been
* built with interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
* @param Mask is the mask to disable. Bits set to 1 are disabled. This
* mask is formed by OR'ing bits from XBRAM_IR* bits
* which are contained in xbram_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
/*
* Read the interrupt enable register and only disable the specified
* interrupts without enabling or disabling any others.
*/
Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET);
XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET,
Register & (~Mask));
}
/****************************************************************************/
/**
* Clear pending interrupts with the provided mask. This function should be
* called after the software has serviced the interrupts that are pending.
* This function will assert if the hardware device has not been built with
* interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
* @param Mask is the mask to clear pending interrupts for. Bit positions
* of 1 are cleared. This mask is formed by OR'ing bits from
* XBRAM_IR* bits which are contained in
* xbram_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XBram_InterruptClear(XBram *InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
/*
* Read the interrupt status register and only clear the interrupts
* that are specified without affecting any others. Since the register
* is a toggle on write, make sure any bits to be written are already
* set.
*/
Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_STATUS_OFFSET);
XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_STATUS_OFFSET,
Register & Mask);
}
/****************************************************************************/
/**
* Returns the interrupt enable mask. This function will assert if the
* hardware device has not been built with interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
*
* @return A mask of bits made from XBRAM_IR* bits which
* are contained in xbram_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
u32 XBram_InterruptGetEnabled(XBram * InstancePtr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->Config.CtrlBaseAddress != 0);
return XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET);
}
/****************************************************************************/
/**
* Returns the status of interrupt signals. Any bit in the mask set to 1
* indicates that the channel associated with the bit has asserted an interrupt
* condition. This function will assert if the hardware device has not been
* built with interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
*
* @return A pointer to a mask of bits made from XBRAM_IR*
* bits which are contained in xbram_hw.h.
*
* @note
*
* The interrupt status indicates the status of the device irregardless if
* the interrupts from the devices have been enabled or not through
* XBram_InterruptEnable().
*
*****************************************************************************/
u32 XBram_InterruptGetStatus(XBram * InstancePtr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->Config.CtrlBaseAddress != 0);
return XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET);
}

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/******************************************************************************
*
* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xbram_selftest.c
*
* The implementation of the XBram driver's self test function. This SelfTest
* is only applicable if ECC is enabled.
* If ECC is not enabled then this function will return XST_SUCCESS.
* See xbram.h for more information about the driver.
* Temp change
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 11/24/10 First release
* 3.01a sa 01/13/12 Changed Selftest API from
* XBram_SelfTest(XBram *InstancePtr) to
* XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
* fixed a problem with interrupt generation for CR 639274
* Modified Selftest example to return XST_SUCCESS when
* ECC is not enabled and return XST_FAILURE when ECC is
* enabled and Control Base Address is zero (CR 636581)
* Modified Selftest to use correct CorrectableCounterBits
* for CR 635655
* Updated to check CorrectableFailingDataRegs in the case
* of LMB BRAM.
* 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
* 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in InjectErrors API to
* flush the Cache after writing to BRAM (CR #719011)
* </pre>
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xbram.h"
#include "xil_cache.h"
/************************** Constant Definitions ****************************/
#define TOTAL_BITS 39
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
#define RD(reg) XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress, \
XBRAM_ ## reg)
#define WR(reg, data) XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress, \
XBRAM_ ## reg, data)
#define CHECK(reg, data, result) if (result!=XST_SUCCESS || RD(reg)!=data) \
result = XST_FAILURE;
/************************** Variable Definitions ****************************/
static u32 PrngResult;
/************************** Function Prototypes *****************************/
static inline u32 PrngData(u32 *PrngResult);
static inline u32 CalculateEcc(u32 Data);
static void InjectErrors(XBram * InstancePtr, u32 Addr,
int Index1, int Index2, int Width,
u32 *ActualData, u32 *ActualEcc);
/*****************************************************************************/
/**
* Generate a pseudo random number.
*
* @param The PrngResult is the previous random number in the pseudo
* random sequence, also knwon as the seed. It is modified to
* the calculated pseudo random number by the function.
*
* @return The generated pseudo random number
*
* @note None.
*
******************************************************************************/
static inline u32 PrngData(u32 *PrngResult)
{
*PrngResult = *PrngResult * 0x77D15E25 + 0x3617C161;
return *PrngResult;
}
/*****************************************************************************/
/**
* Calculate ECC from Data.
*
* @param The Data Value
*
* @return The calculated ECC
*
* @note None.
*
******************************************************************************/
static inline u32 CalculateEcc(u32 Data)
{
unsigned char c[7], d[32];
u32 Result = 0;
int Index;
for (Index = 0; Index < 32; Index++) {
d[31 - Index] = Data & 1;
Data = Data >> 1;
}
c[0] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[8] ^ d[10] ^ d[11] ^
d[13] ^ d[15] ^ d[17] ^ d[19] ^ d[21] ^ d[23] ^ d[25] ^ d[26] ^
d[28] ^ d[30];
c[1] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[9] ^ d[10] ^ d[12] ^
d[13] ^ d[16] ^ d[17] ^ d[20] ^ d[21] ^ d[24] ^ d[25] ^ d[27] ^
d[28] ^ d[31];
c[2] = d[1] ^ d[2] ^ d[3] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[14] ^
d[15] ^ d[16] ^ d[17] ^ d[22] ^ d[23] ^ d[24] ^ d[25] ^ d[29] ^
d[30] ^ d[31];
c[3] = d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[18] ^
d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[25];
c[4] = d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^
d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[25];
c[5] = d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];
c[6] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^
d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^
d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^
d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31] ^
c[5] ^ c[4] ^ c[3] ^ c[2] ^ c[1] ^ c[0];
for (Index = 0; Index < 7; Index++) {
Result = Result << 1;
Result |= c[Index] & 1;
}
return Result;
}
/*****************************************************************************/
/**
* Get the expected actual data read in case of uncorrectable errors.
*
* @param The injected data value including errors (if any)
* @param The syndrome (calculated ecc ^ actual ecc read)
*
* @return The actual data value read
*
* @note None.
*
******************************************************************************/
static inline u32 UncorrectableData(u32 Data, u8 Syndrome)
{
switch (Syndrome) {
case 0x03: return Data ^ 0x00000034;
case 0x05: return Data ^ 0x001a2000;
case 0x09: return Data ^ 0x0d000000;
case 0x0d: return Data ^ 0x00001a00;
case 0x11: return Data ^ 0x60000000;
case 0x13: return Data ^ 0x00000003;
case 0x15: return Data ^ 0x00018000;
case 0x19: return Data ^ 0x00c00000;
case 0x1d: return Data ^ 0x00000180;
case 0x21: return Data ^ 0x80000000;
case 0x23: return Data ^ 0x00000008;
case 0x25: return Data ^ 0x00040000;
case 0x29: return Data ^ 0x02000000;
case 0x2d: return Data ^ 0x00000400;
case 0x31: return Data ^ 0x10000000;
case 0x35: return Data ^ 0x00004000;
case 0x39: return Data ^ 0x00200000;
case 0x3d: return Data ^ 0x00000040;
}
return Data;
}
/*****************************************************************************/
/**
* Inject errors using the hardware fault injection functionality, and write
* random data and read it back using the indicated location.
*
* @param InstancePtr is a pointer to the XBram instance to
* be worked on.
* @param The Addr is the indicated memory location to use
* @param The Index1 is the bit location of the first injected error
* @param The Index2 is the bit location of the second injected error
* @param The Width is the data byte width
* @param The ActualData is filled in with expected data for checking
* @param The ActualEcc is filled in with expected ECC for checking
*
* @return None
*
* @note None.
*
******************************************************************************/
static void InjectErrors(XBram * InstancePtr, u32 Addr,
int Index1, int Index2, int Width,
u32 *ActualData, u32 *ActualEcc)
{
u32 InjectedData = 0;
u32 InjectedEcc = 0;
u32 RandomData = PrngData(&PrngResult);
if (Index1 < 32) {
InjectedData = 1 << Index1;
} else {
InjectedEcc = 1 << (Index1 - 32);
}
if (Index2 < 32) {
InjectedData |= (1 << Index2);
} else {
InjectedEcc |= 1 << (Index2 - 32);
}
WR(FI_D_0_OFFSET, InjectedData);
WR(FI_ECC_0_OFFSET, InjectedEcc);
XBram_Out32(Addr, RandomData);
Xil_DCacheFlushRange(Addr, 4);
switch (Width) {
case 1: /* Byte - Write to do Read-Modify-Write */
XBram_Out8(Addr, PrngData(&PrngResult) & 0xFF);
break;
case 2: /* Halfword - Write to do Read-Modify-Write */
XBram_Out16(Addr, PrngData(&PrngResult) & 0xFFFF);
break;
case 4: /* Word - Read */
(void) XBram_In32(Addr);
break;
}
*ActualData = InjectedData ^ RandomData;
*ActualEcc = InjectedEcc ^ CalculateEcc(RandomData);
}
/*****************************************************************************/
/**
* Run a self-test on the driver/device. Unless fault injection is implemented
* in hardware, this function only does a minimal test in which available
* registers (if any) are written and read.
*
* With fault injection, all possible single-bit and double-bit errors are
* injected, and checked to the extent possible, given the implemented hardware.
*
* @param InstancePtr is a pointer to the XBram instance.
* @param IntMask is the interrupt mask to use. When testing
* with interrupts, this should be set to allow interrupt
* generation, otherwise it should be 0.
*
* @return
* - XST_SUCCESS if fault injection/detection is working properly OR
* if ECC is Not Enabled in the HW.
* - XST_FAILURE if the injected fault is not correctly detected or
* the Control Base Address is Zero when ECC is enabled.
* .
*
* If the BRAM device is not present in the
* hardware a bus error could be generated. Other indicators of a
* bus error, such as registers in bridges or buses, may be
* necessary to determine if this function caused a bus error.
*
* @note None.
*
******************************************************************************/
int XBram_SelfTest(XBram *InstancePtr, u8 IntMask)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
if (InstancePtr->Config.EccPresent == 0) {
return (XST_SUCCESS);
}
if (InstancePtr->Config.CtrlBaseAddress == 0) {
return (XST_SUCCESS);
}
/*
* Only 32-bit data width is supported as of yet. 64-bit and 128-bit
* widths will be supported in future.
*/
if (InstancePtr->Config.DataWidth != 32)
return (XST_SUCCESS);
/*
* Read from the implemented readable registers in the hardware device.
*/
if (InstancePtr->Config.CorrectableFailingRegisters) {
(void) RD(CE_FFA_0_OFFSET);
}
if (InstancePtr->Config.CorrectableFailingDataRegs) {
(void) RD(CE_FFD_0_OFFSET);
(void) RD(CE_FFE_0_OFFSET);
}
if (InstancePtr->Config.UncorrectableFailingRegisters) {
(void) RD(UE_FFA_0_OFFSET);
}
if (InstancePtr->Config.UncorrectableFailingDataRegs) {
(void) RD(UE_FFD_0_OFFSET);
(void) RD(UE_FFE_0_OFFSET);
}
/*
* Write and read the implemented read/write registers in the hardware
* device.
*/
if (InstancePtr->Config.EccStatusInterruptPresent) {
WR(ECC_EN_IRQ_OFFSET, 0);
if (RD(ECC_EN_IRQ_OFFSET) != 0) {
return (XST_FAILURE);
}
}
if (InstancePtr->Config.CorrectableCounterBits > 0) {
u32 Value;
/* Calculate counter max value */
if (InstancePtr->Config.CorrectableCounterBits == 32) {
Value = 0xFFFFFFFF;
} else {
Value = (1 <<
InstancePtr->Config.CorrectableCounterBits) - 1;
}
WR(CE_CNT_OFFSET, Value);
if (RD(CE_CNT_OFFSET) != Value) {
return (XST_FAILURE);
}
WR(CE_CNT_OFFSET, 0);
if (RD(CE_CNT_OFFSET) != 0) {
return (XST_FAILURE);
}
}
/*
* If fault injection is implemented, inject all possible single-bit
* and double-bit errors, and check all observable effects.
*/
if (InstancePtr->Config.FaultInjectionPresent &&
InstancePtr->Config.WriteAccess != 0) {
const u32 Addr[2] = {InstancePtr->Config.MemBaseAddress &
0xfffffffc,
InstancePtr->Config.MemHighAddress &
0xfffffffc};
u32 SavedWords[2];
u32 ActualData;
u32 ActualEcc;
u32 CounterValue = 0;
u32 CounterMax;
int WordIndex = 0;
int Result = XST_SUCCESS;
int Index1;
int Index2;
int Width;
PrngResult = 42; /* Random seed */
/* Save two words in BRAM used for test */
SavedWords[0] = XBram_In32(Addr[0]);
SavedWords[1] = XBram_In32(Addr[1]);
for (Width = 1; Width <= 4; Width <<= 1) {
/* Calculate counter max value */
if (InstancePtr->Config.CorrectableCounterBits == 32) {
CounterMax = 0xFFFFFFFF;
} else {
CounterMax =(1 <<
InstancePtr->Config.CorrectableCounterBits) - 1;
}
/* Inject and check all single bit errors */
for (Index1 = 0; Index1 < TOTAL_BITS; Index1++) {
/* Save counter value */
if (InstancePtr->Config.CorrectableCounterBits > 0) {
CounterValue = RD(CE_CNT_OFFSET);
}
/* Inject single bit error */
InjectErrors(InstancePtr, Addr[WordIndex], Index1,
Index1, Width, &ActualData, &ActualEcc);
/* Check that CE is set */
if (InstancePtr->Config.EccStatusInterruptPresent) {
CHECK(ECC_STATUS_OFFSET,
XBRAM_IR_CE_MASK, Result);
}
/* Check that address, data, ECC are correct */
if (InstancePtr->Config.CorrectableFailingRegisters) {
CHECK(CE_FFA_0_OFFSET, Addr[WordIndex], Result);
}
/* Checks are only for LMB BRAM */
if (InstancePtr->Config.CorrectableFailingDataRegs) {
CHECK(CE_FFD_0_OFFSET, ActualData, Result);
CHECK(CE_FFE_0_OFFSET, ActualEcc, Result);
}
/* Check that counter has incremented */
if (InstancePtr->Config.CorrectableCounterBits > 0 &&
CounterValue < CounterMax) {
CHECK(CE_CNT_OFFSET,
CounterValue + 1, Result);
}
/* Restore correct data in the used word */
XBram_Out32(Addr[WordIndex], SavedWords[WordIndex]);
/* Allow interrupts to occur */
/* Clear status register */
if (InstancePtr->Config.EccStatusInterruptPresent) {
WR(ECC_EN_IRQ_OFFSET, IntMask);
WR(ECC_STATUS_OFFSET, XBRAM_IR_ALL_MASK);
WR(ECC_EN_IRQ_OFFSET, 0);
}
/* Switch to the other word */
WordIndex = WordIndex ^ 1;
if (Result != XST_SUCCESS) break;
}
if (Result != XST_SUCCESS) {
return XST_FAILURE;
}
for (Index1 = 0; Index1 < TOTAL_BITS; Index1++) {
for (Index2 = 0; Index2 < TOTAL_BITS; Index2++) {
if (Index1 != Index2) {
/* Inject double bit error */
InjectErrors(InstancePtr,
Addr[WordIndex],
Index1, Index2, Width,
&ActualData,
&ActualEcc);
/* Check that UE is set */
if (InstancePtr->Config.
EccStatusInterruptPresent) {
CHECK(ECC_STATUS_OFFSET,
XBRAM_IR_UE_MASK,
Result);
}
/* Check that address, data, ECC are correct */
if (InstancePtr->Config.
UncorrectableFailingRegisters) {
CHECK(UE_FFA_0_OFFSET, Addr[WordIndex],
Result);
CHECK(UE_FFD_0_OFFSET,
ActualData, Result);
CHECK(UE_FFE_0_OFFSET, ActualEcc,
Result);
}
/* Restore correct data in the used word */
XBram_Out32(Addr[WordIndex],
SavedWords[WordIndex]);
/* Allow interrupts to occur */
/* Clear status register */
if (InstancePtr->Config.
EccStatusInterruptPresent) {
WR(ECC_EN_IRQ_OFFSET, IntMask);
WR(ECC_STATUS_OFFSET,
XBRAM_IR_ALL_MASK);
WR(ECC_EN_IRQ_OFFSET, 0);
}
/* Switch to the other word */
WordIndex = WordIndex ^ 1;
}
if (Result != XST_SUCCESS) break;
}
if (Result != XST_SUCCESS) break;
}
/* Check saturation of correctable error counter */
if (InstancePtr->Config.CorrectableCounterBits > 0 &&
Result == XST_SUCCESS) {
WR(CE_CNT_OFFSET, CounterMax);
InjectErrors(InstancePtr, Addr[WordIndex], 0, 0,
4, &ActualData, &ActualEcc);
CHECK(CE_CNT_OFFSET, CounterMax, Result);
}
/* Restore the two words used for test */
XBram_Out32(Addr[0], SavedWords[0]);
XBram_Out32(Addr[1], SavedWords[1]);
/* Clear the Status Register. */
if (InstancePtr->Config.EccStatusInterruptPresent) {
WR(ECC_STATUS_OFFSET, XBRAM_IR_ALL_MASK);
}
/* Set Correctable Counter to zero */
if (InstancePtr->Config.CorrectableCounterBits > 0) {
WR(CE_CNT_OFFSET, 0);
}
if (Result != XST_SUCCESS) break;
} /* Width loop */
return (Result);
}
return (XST_SUCCESS);
}

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/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xbram_sinit.c
*
* The implementation of the XBram driver's static initialzation
* functionality.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 2.01a jvb 10/13/05 First release
* 2.11a mta 03/21/07 Updated to new coding style
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xstatus.h"
#include "xparameters.h"
#include "xbram.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
extern XBram_Config XBram_ConfigTable[];
/************************** Function Prototypes *****************************/
/*****************************************************************************/
/**
* Lookup the device configuration based on the unique device ID. The table
* ConfigTable contains the configuration info for each device in the system.
*
* @param DeviceId is the device identifier to lookup.
*
* @return
* - A pointer of data type XBram_Config which
* points to the device configuration if DeviceID is found.
* - NULL if DeviceID is not found.
*
* @note None.
*
******************************************************************************/
XBram_Config *XBram_LookupConfig(u16 DeviceId)
{
XBram_Config *CfgPtr = NULL;
int Index;
for (Index = 0; Index < XPAR_XBRAM_NUM_INSTANCES; Index++) {
if (XBram_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XBram_ConfigTable[Index];
break;
}
}
return CfgPtr;
}

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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I${INCLUDEDIR}
OUTS = *.o
LIBSOURCES=*.c
INCLUDEFILES=xio.h
libs:
echo "Compiling cpu"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OUTS}

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/******************************************************************************
*
* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file fsl.h
*
* This file contains macros for interfacing to the Fast Simplex Link (FSL)
* interface..
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a ecm 06/20/07 Initial version, moved over from bsp area
* 1.11c ecm 08/26/08 Fixed the missing 'FSL_DEFAULT' define that was causing
* assembly errors.
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef _FSL_H
#define _FSL_H
/***************************** Include Files *********************************/
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/* if these have not been defined already, define here */
#ifndef stringify
/* necessary for pre-processor */
#define stringify(s) tostring(s)
#define tostring(s) #s
#endif /* stringify */
/* Extended FSL macros. These now replace all of the previous FSL macros */
#define FSL_DEFAULT
#define FSL_NONBLOCKING n
#define FSL_EXCEPTION e
#define FSL_CONTROL c
#define FSL_ATOMIC a
#define FSL_NONBLOCKING_EXCEPTION ne
#define FSL_NONBLOCKING_CONTROL nc
#define FSL_NONBLOCKING_ATOMIC na
#define FSL_EXCEPTION_CONTROL ec
#define FSL_EXCEPTION_ATOMIC ea
#define FSL_CONTROL_ATOMIC ca
#define FSL_NONBLOCKING_EXCEPTION_CONTROL nec
#define FSL_NONBLOCKING_EXCEPTION_ATOMIC nea
#define FSL_NONBLOCKING_CONTROL_ATOMIC nca
#define FSL_EXCEPTION_CONTROL_ATOMIC eca
#define FSL_NONBLOCKING_EXCEPTION_CONTROL_ATOMIC neca
#define getfslx(val, id, flags) asm volatile (stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
#define putfslx(val, id, flags) asm volatile (stringify(flags) "put\t%0,rfsl" stringify(id) :: "d" (val))
#define tgetfslx(val, id, flags) asm volatile ("t" stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
#define tputfslx(id, flags) asm volatile ("t" stringify(flags) "put\trfsl" stringify(id))
#define getdfslx(val, var, flags) asm volatile (stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
#define putdfslx(val, var, flags) asm volatile (stringify(flags) "putd\t%0,%1" :: "d" (val), "d" (var))
#define tgetdfslx(val, var, flags) asm volatile ("t" stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
#define tputdfslx(var, flags) asm volatile ("t" stringify(flags) "putd\t%0" :: "d" (var))
/* if the mb_interface.h file has been included already, the following are not needed and will not be defined */
/* Legacy FSL Access Macros */
#ifndef getfsl
/* Blocking Data Read and Write to FSL no. id */
#define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
#define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Data Read and Write to FSL no. id */
#define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
#define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
/* Blocking Control Read and Write to FSL no. id */
#define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
#define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Control Read and Write to FSL no. id */
#define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
#define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
/* Polling versions of FSL access macros. This makes the FSL access interruptible */
#define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
#define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
/* FSL valid and error check macros. */
#define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result))
#define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \
"andi\t%0,%0,0x10" : "=d" (error))
#endif /* legacy FSL defines */
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* _FSL_H */

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/******************************************************************************
*
* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xio.c
*
* Contains I/O functions for memory-mapped or non-memory-mapped I/O
* architectures. These functions encapsulate generic CPU I/O requirements.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a rpm 11/07/03 Added InSwap/OutSwap routines for endian conversion
* 1.01a ecm 02/24/06 CR225908 corrected the extra curly braces in macros
* and bumped version to 1.01.a.
* 2.11a mta 03/21/07 Updated to new coding style.
*
* </pre>
*
* @note
*
* This file may contain architecture-dependent code.
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xio.h"
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* Performs a 16-bit endian converion.
*
* @param Source contains the value to be converted.
* @param DestPtr contains a pointer to the location to put the
* converted value.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIo_EndianSwap16(u16 Source, u16 *DestPtr)
{
*DestPtr = (u16) (((Source & 0xFF00) >> 8) | ((Source & 0x00FF) << 8));
}
/*****************************************************************************/
/**
*
* Performs a 32-bit endian converion.
*
* @param Source contains the value to be converted.
* @param DestPtr contains a pointer to the location to put the
* converted value.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIo_EndianSwap32(u32 Source, u32 *DestPtr)
{
/* get each of the half words from the 32 bit word */
u16 LoWord = (u16) (Source & 0x0000FFFF);
u16 HiWord = (u16) ((Source & 0xFFFF0000) >> 16);
/* byte swap each of the 16 bit half words */
LoWord = (((LoWord & 0xFF00) >> 8) | ((LoWord & 0x00FF) << 8));
HiWord = (((HiWord & 0xFF00) >> 8) | ((HiWord & 0x00FF) << 8));
/* swap the half words before returning the value */
*DestPtr = (u32) ((LoWord << 16) | HiWord);
}
/*****************************************************************************/
/**
*
* Performs an input operation for a 16-bit memory location by reading from the
* specified address and returning the byte-swapped value read from that
* address.
*
* @param InAddress contains the address to perform the input
* operation at.
*
* @return The byte-swapped value read from the specified input address.
*
* @note None.
*
******************************************************************************/
u16 XIo_InSwap16(XIo_Address InAddress)
{
u16 InData;
/* get the data then swap it */
InData = XIo_In16(InAddress);
return (u16) (((InData & 0xFF00) >> 8) | ((InData & 0x00FF) << 8));
}
/*****************************************************************************/
/**
*
* Performs an input operation for a 32-bit memory location by reading from the
* specified address and returning the byte-swapped value read from that
* address.
*
* @param InAddress contains the address to perform the input
* operation at.
*
* @return The byte-swapped value read from the specified input address.
*
* @note None.
*
******************************************************************************/
u32 XIo_InSwap32(XIo_Address InAddress)
{
u32 InData;
u32 SwapData;
/* get the data then swap it */
InData = XIo_In32(InAddress);
XIo_EndianSwap32(InData, &SwapData);
return SwapData;
}
/*****************************************************************************/
/**
*
* Performs an output operation for a 16-bit memory location by writing the
* specified value to the the specified address. The value is byte-swapped
* before being written.
*
* @param OutAddress contains the address to perform the output
* operation at.
* @param Value contains the value to be output at the specified address.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIo_OutSwap16(XIo_Address OutAddress, u16 Value)
{
u16 OutData;
/* swap the data then output it */
OutData = (u16) (((Value & 0xFF00) >> 8) | ((Value & 0x00FF) << 8));
XIo_Out16(OutAddress, OutData);
}
/*****************************************************************************/
/**
*
* Performs an output operation for a 32-bit memory location by writing the
* specified value to the the specified address. The value is byte-swapped
* before being written.
*
* @param OutAddress contains the address at which the
* output operation has to be done.
* @param Value contains the value to be output at the specified address.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIo_OutSwap32(XIo_Address OutAddress, u32 Value)
{
u32 OutData;
/* swap the data then output it */
XIo_EndianSwap32(Value, &OutData);
XIo_Out32(OutAddress, OutData);
}

263
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/xio.h
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/******************************************************************************
*
* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xio.h
*
* This file contains the interface for the XIo component, which encapsulates
* the Input/Output functions for processors that do not require any special
* I/O handling.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a rpm 11/07/03 Added InSwap/OutSwap routines for endian conversion
* 1.00a xd 11/04/04 Improved support for doxygen
* 1.01a ecm 02/24/06 CR225908 corrected the extra curly braces in macros
* and bumped version to 1.01.a.
* 1.11a mta 03/21/07 Updated to new coding style.
* 1.11b va 04/17/08 Updated Tcl for better CORE_CLOCK_FREQ_HZ definition
* 1.11a sdm 03/12/09 Updated Tcl to define correct value for CORE_CLOCK_FREQ_HZ
* (CR #502010)
* 1.13a sdm 03/12/09 Updated the Tcl to pull appropriate libraries for Little
* Endian Microblaze
* 2.0 adk 19/12/13 Updated as per the New Tcl API's
* 2.1 bss 04/14/14 Updated tcl to copy libgloss.a and libgcc.a libraries
* 2.1 bss 04/29/14 Updated to copy libgloss.a if exists otherwise libxil.a
* CR#794205
* 2.2 bss 08/04/14 Updated driver tcl to add protection macros for
* xparameters.h (CR#802257).
*
* </pre>
*
* @note
*
* This file may contain architecture-dependent items (memory-mapped or
* non-memory-mapped I/O).
*
******************************************************************************/
#ifndef XIO_H /* prevent circular inclusions */
#define XIO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/**
* Typedef for an I/O address. Typically correlates to the width of the
* address bus.
*/
typedef u32 XIo_Address;
/***************** Macros (Inline Functions) Definitions *********************/
/*
* The following macros allow optimized I/O operations for memory mapped I/O.
* It should be noted that macros cannot be used if synchronization of the I/O
* operation is needed as it will likely break some code.
*/
/*****************************************************************************/
/**
*
* Performs an input operation for an 8-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define XIo_In8(InputPtr) (*(volatile u8 *)(InputPtr))
/*****************************************************************************/
/**
*
* Performs an input operation for a 16-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define XIo_In16(InputPtr) (*(volatile u16 *)(InputPtr))
/*****************************************************************************/
/**
*
* Performs an input operation for a 32-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define XIo_In32(InputPtr) (*(volatile u32 *)(InputPtr))
/*****************************************************************************/
/**
*
* Performs an output operation for an 8-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation
* at.
* @param Value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define XIo_Out8(OutputPtr, Value) \
(*(volatile u8 *)((OutputPtr)) = (Value))
/*****************************************************************************/
/**
*
* Performs an output operation for a 16-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation
* at.
* @param Value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define XIo_Out16(OutputPtr, Value) \
(*(volatile u16 *)((OutputPtr)) = (Value))
/*****************************************************************************/
/**
*
* Performs an output operation for a 32-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation
* at.
* @param Value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define XIo_Out32(OutputPtr, Value) \
(*(volatile u32 *)((OutputPtr)) = (Value))
/* The following macros allow the software to be transportable across
* processors which use big or little endian memory models.
*
* Defined first is a no-op endian conversion macro. This macro is not to
* be used directly by software. Instead, the XIo_To/FromLittleEndianXX and
* XIo_To/FromBigEndianXX macros below are to be used to allow the endian
* conversion to only be performed when necessary
*/
#define XIo_EndianNoop(Source, DestPtr) (*DestPtr = Source)
#ifdef XLITTLE_ENDIAN
#define XIo_ToLittleEndian16 XIo_EndianNoop
#define XIo_ToLittleEndian32 XIo_EndianNoop
#define XIo_FromLittleEndian16 XIo_EndianNoop
#define XIo_FromLittleEndian32 XIo_EndianNoop
#define XIo_ToBigEndian16(Source, DestPtr) XIo_EndianSwap16(Source, DestPtr)
#define XIo_ToBigEndian32(Source, DestPtr) XIo_EndianSwap32(Source, DestPtr)
#define XIo_FromBigEndian16 XIo_ToBigEndian16
#define XIo_FromBigEndian32 XIo_ToBigEndian32
#else
#define XIo_ToLittleEndian16(Source, DestPtr) XIo_EndianSwap16(Source, DestPtr)
#define XIo_ToLittleEndian32(Source, DestPtr) XIo_EndianSwap32(Source, DestPtr)
#define XIo_FromLittleEndian16 XIo_ToLittleEndian16
#define XIo_FromLittleEndian32 XIo_ToLittleEndian32
#define XIo_ToBigEndian16 XIo_EndianNoop
#define XIo_ToBigEndian32 XIo_EndianNoop
#define XIo_FromBigEndian16 XIo_EndianNoop
#define XIo_FromBigEndian32 XIo_EndianNoop
#endif
/************************** Function Prototypes ******************************/
/* The following functions allow the software to be transportable across
* processors which use big or little endian memory models. These functions
* should not be directly called, but the macros XIo_To/FromLittleEndianXX and
* XIo_To/FromBigEndianXX should be used to allow the endian conversion to only
* be performed when necessary.
*/
void XIo_EndianSwap16(u16 Source, u16 *DestPtr);
void XIo_EndianSwap32(u32 Source, u32 *DestPtr);
/* The following functions handle IO addresses where data must be swapped
* They cannot be implemented as macros
*/
u16 XIo_InSwap16(XIo_Address InAddress);
u32 XIo_InSwap32(XIo_Address InAddress);
void XIo_OutSwap16(XIo_Address OutAddress, u16 Value);
void XIo_OutSwap32(XIo_Address OutAddress, u32 Value);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/Makefile
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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling emaclite"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OUTS}

967
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite.c
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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemaclite.c
*
* Functions in this file are the minimum required functions for the EmacLite
* driver. See xemaclite.h for a detailed description of the driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- --------------------------------------------------------
* 1.01a ecm 01/31/04 First release
* 1.11a mta 03/21/07 Updated to new coding style
* 1.11a ecm 05/18/07 Updated the TxBufferAvailable routine to look at both
* the active and busy bits
* 1.13a sv 02/1/08 Updated the TxBufferAvailable routine to return
* busy status properly
* 2.00a ktn 02/16/09 Added support for MDIO
* 2.01a ktn 07/20/09 Modified XEmacLite_Send function to use Ping buffers
* Interrupt enable bit since this alone is used to enable
* the interrupts for both Ping and Pong Buffers.
* 3.00a ktn 10/22/09 Updated driver to use the HAL APIs/macros.
* The macros have been renamed to remove _m from the name.
* 3.01a ktn 07/08/10 The macro XEmacLite_GetReceiveDataLength is changed to
* a static function.
* Updated the XEmacLite_GetReceiveDataLength and
* XEmacLite_Recv functions to support little endian
* MicroBlaze.
* 3.02a sdm 07/22/11 Removed redundant code in XEmacLite_Recv functions for
* CR617290
* 3.04a srt 04/13/13 Removed warnings (CR 705000).
*
* </pre>
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_io.h"
#include "xenv.h"
#include "xemaclite.h"
#include "xemaclite_i.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static u16 XEmacLite_GetReceiveDataLength(u32 BaseAddress);
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Initialize a specific XEmacLite instance/driver. The initialization entails:
* - Initialize fields of the XEmacLite instance structure.
*
* The driver defaults to polled mode operation.
*
* @param InstancePtr is a pointer to the XEmacLite instance.
* @param EmacLiteConfigPtr points to the XEmacLite device configuration
* structure.
* @param EffectiveAddr is the device base address in the virtual memory
* address space. If the address translation is not used then the
* physical address is passed.
* Unexpected errors may occur if the address mapping is changed
* after this function is invoked.
*
* @return
* - XST_SUCCESS if initialization was successful.
*
* @note The initialization of the PHY device is not done in this
* function. The user needs to use XEmacLite_PhyRead and
* XEmacLite_PhyWrite functions to access the PHY device.
*
******************************************************************************/
int XEmacLite_CfgInitialize(XEmacLite *InstancePtr,
XEmacLite_Config *EmacLiteConfigPtr,
u32 EffectiveAddr)
{
/*
* Verify that each of the inputs are valid.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(EmacLiteConfigPtr != NULL);
/*
* Zero the provided instance memory.
*/
memset(InstancePtr, 0, sizeof(XEmacLite));
/*
* Set some default values for instance data, don't indicate the device
* is ready to use until everything has been initialized successfully.
*/
InstancePtr->EmacLiteConfig.BaseAddress = EffectiveAddr;
InstancePtr->EmacLiteConfig.DeviceId = EmacLiteConfigPtr->DeviceId;
InstancePtr->EmacLiteConfig.TxPingPong = EmacLiteConfigPtr->TxPingPong;
InstancePtr->EmacLiteConfig.RxPingPong = EmacLiteConfigPtr->RxPingPong;
InstancePtr->EmacLiteConfig.MdioInclude = EmacLiteConfigPtr->MdioInclude;
InstancePtr->EmacLiteConfig.Loopback = EmacLiteConfigPtr->Loopback;
InstancePtr->NextTxBufferToUse = 0x0;
InstancePtr->NextRxBufferToUse = 0x0;
InstancePtr->RecvHandler = (XEmacLite_Handler) StubHandler;
InstancePtr->SendHandler = (XEmacLite_Handler) StubHandler;
/*
* Clear the TX CSR's in case this is a restart.
*/
XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_TSR_OFFSET, 0);
XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_BUFFER_OFFSET + XEL_TSR_OFFSET, 0);
/*
* Since there were no failures, indicate the device is ready to use.
*/
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* Send an Ethernet frame. The ByteCount is the total frame size, including
* header.
*
* @param InstancePtr is a pointer to the XEmacLite instance.
* @param FramePtr is a pointer to frame. For optimal performance, a
* 32-bit aligned buffer should be used but it is not required, the
* function will align the data if necessary.
* @param ByteCount is the size, in bytes, of the frame
*
* @return
* - XST_SUCCESS if data was transmitted.
* - XST_FAILURE if buffer(s) was (were) full and no valid data was
* transmitted.
*
* @note
*
* This function call is not blocking in nature, i.e. it will not wait until the
* frame is transmitted.
*
******************************************************************************/
int XEmacLite_Send(XEmacLite *InstancePtr, u8 *FramePtr, unsigned ByteCount)
{
u32 Register;
u32 BaseAddress;
u32 EmacBaseAddress;
u32 IntrEnableStatus;
/*
* Verify that each of the inputs are valid.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
/*
* Determine the expected TX buffer address.
*/
BaseAddress = XEmacLite_NextTransmitAddr(InstancePtr);
EmacBaseAddress = InstancePtr->EmacLiteConfig.BaseAddress;
/*
* Check the Length if it is too large, truncate it.
* The maximum Tx packet size is
* Ethernet header (14 Bytes) + Maximum MTU (1500 bytes).
*/
if (ByteCount > XEL_MAX_TX_FRAME_SIZE) {
ByteCount = XEL_MAX_TX_FRAME_SIZE;
}
/*
* Determine if the expected buffer address is empty.
*/
Register = XEmacLite_GetTxStatus(BaseAddress);
/*
* If the expected buffer is available, fill it with the provided data
* Align if necessary.
*/
if ((Register & (XEL_TSR_XMIT_BUSY_MASK |
XEL_TSR_XMIT_ACTIVE_MASK)) == 0) {
/*
* Switch to next buffer if configured.
*/
if (InstancePtr->EmacLiteConfig.TxPingPong != 0) {
InstancePtr->NextTxBufferToUse ^= XEL_BUFFER_OFFSET;
}
/*
* Write the frame to the buffer.
*/
XEmacLite_AlignedWrite(FramePtr, (u32 *) BaseAddress,
ByteCount);
/*
* The frame is in the buffer, now send it.
*/
XEmacLite_WriteReg(BaseAddress, XEL_TPLR_OFFSET,
(ByteCount & (XEL_TPLR_LENGTH_MASK_HI |
XEL_TPLR_LENGTH_MASK_LO)));
/*
* Update the Tx Status Register to indicate that there is a
* frame to send.
* If the interrupt enable bit of Ping buffer(since this
* controls both the buffers) is enabled then set the
* XEL_TSR_XMIT_ACTIVE_MASK flag which is used by the interrupt
* handler to call the callback function provided by the user
* to indicate that the frame has been transmitted.
*/
Register = XEmacLite_GetTxStatus(BaseAddress);
Register |= XEL_TSR_XMIT_BUSY_MASK;
IntrEnableStatus = XEmacLite_GetTxStatus(EmacBaseAddress);
if ((IntrEnableStatus & XEL_TSR_XMIT_IE_MASK) != 0) {
Register |= XEL_TSR_XMIT_ACTIVE_MASK;
}
XEmacLite_SetTxStatus(BaseAddress, Register);
return XST_SUCCESS;
}
/*
* If the expected buffer was full, try the other buffer if configured.
*/
if (InstancePtr->EmacLiteConfig.TxPingPong != 0) {
BaseAddress ^= XEL_BUFFER_OFFSET;
/*
* Determine if the expected buffer address is empty.
*/
Register = XEmacLite_GetTxStatus(BaseAddress);
/*
* If the next buffer is available, fill it with the provided
* data.
*/
if ((Register & (XEL_TSR_XMIT_BUSY_MASK |
XEL_TSR_XMIT_ACTIVE_MASK)) == 0) {
/*
* Write the frame to the buffer.
*/
XEmacLite_AlignedWrite(FramePtr, (u32 *) BaseAddress,
ByteCount);
/*
* The frame is in the buffer, now send it.
*/
XEmacLite_WriteReg(BaseAddress, XEL_TPLR_OFFSET,
(ByteCount & (XEL_TPLR_LENGTH_MASK_HI |
XEL_TPLR_LENGTH_MASK_LO)));
/*
* Update the Tx Status Register to indicate that there
* is a frame to send.
* If the interrupt enable bit of Ping buffer(since this
* controls both the buffers) is enabled then set the
* XEL_TSR_XMIT_ACTIVE_MASK flag which is used by the
* interrupt handler to call the callback function
* provided by the user to indicate that the frame has
* been transmitted.
*/
Register = XEmacLite_GetTxStatus(BaseAddress);
Register |= XEL_TSR_XMIT_BUSY_MASK;
IntrEnableStatus =
XEmacLite_GetTxStatus(EmacBaseAddress);
if ((IntrEnableStatus & XEL_TSR_XMIT_IE_MASK) != 0) {
Register |= XEL_TSR_XMIT_ACTIVE_MASK;
}
XEmacLite_SetTxStatus(BaseAddress, Register);
/*
* Do not switch to next buffer, there is a sync problem
* and the expected buffer should not change.
*/
return XST_SUCCESS;
}
}
/*
* Buffer(s) was(were) full, return failure to allow for polling usage.
*/
return XST_FAILURE;
}
/*****************************************************************************/
/**
*
* Receive a frame. Intended to be called from the interrupt context or
* with a wrapper which waits for the receive frame to be available.
*
* @param InstancePtr is a pointer to the XEmacLite instance.
* @param FramePtr is a pointer to a buffer where the frame will
* be stored. The buffer must be at least XEL_MAX_FRAME_SIZE bytes.
* For optimal performance, a 32-bit aligned buffer should be used
* but it is not required, the function will align the data if
* necessary.
*
* @return
*
* The type/length field of the frame received. When the type/length field
* contains the type, XEL_MAX_FRAME_SIZE bytes will be copied out of the
* buffer and it is up to the higher layers to sort out the frame.
* Function returns 0 if there is no data waiting in the receive buffer or
* the pong buffer if configured.
*
* @note
*
* This function call is not blocking in nature, i.e. it will not wait until
* a frame arrives.
*
******************************************************************************/
u16 XEmacLite_Recv(XEmacLite *InstancePtr, u8 *FramePtr)
{
u16 LengthType;
u16 Length;
u32 Register;
u32 BaseAddress;
/*
* Verify that each of the inputs are valid.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
/*
* Determine the expected buffer address.
*/
BaseAddress = XEmacLite_NextReceiveAddr(InstancePtr);
/*
* Verify which buffer has valid data.
*/
Register = XEmacLite_GetRxStatus(BaseAddress);
if ((Register & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
/*
* The driver is in sync, update the next expected buffer if
* configured.
*/
if (InstancePtr->EmacLiteConfig.RxPingPong != 0) {
InstancePtr->NextRxBufferToUse ^= XEL_BUFFER_OFFSET;
}
}
else {
/*
* The instance is out of sync, try other buffer if other
* buffer is configured, return 0 otherwise. If the instance is
* out of sync, do not update the 'NextRxBufferToUse' since it
* will correct on subsequent calls.
*/
if (InstancePtr->EmacLiteConfig.RxPingPong != 0) {
BaseAddress ^= XEL_BUFFER_OFFSET;
}
else {
return 0; /* No data was available */
}
/*
* Verify that buffer has valid data.
*/
Register = XEmacLite_GetRxStatus(BaseAddress);
if ((Register & XEL_RSR_RECV_DONE_MASK) !=
XEL_RSR_RECV_DONE_MASK) {
return 0; /* No data was available */
}
}
/*
* Get the length of the frame that arrived.
*/
LengthType = XEmacLite_GetReceiveDataLength(BaseAddress);
/*
* Check if length is valid.
*/
if (LengthType > XEL_MAX_FRAME_SIZE) {
if (LengthType == XEL_ETHER_PROTO_TYPE_IP) {
/*
* The packet is a an IP Packet.
*/
#ifdef __LITTLE_ENDIAN__
Length = (XEmacLite_ReadReg((BaseAddress),
XEL_HEADER_IP_LENGTH_OFFSET +
XEL_RXBUFF_OFFSET) &
(XEL_RPLR_LENGTH_MASK_HI |
XEL_RPLR_LENGTH_MASK_LO));
Length = (u16) (((Length & 0xFF00) >> 8) | ((Length & 0x00FF) << 8));
#else
Length = ((XEmacLite_ReadReg((BaseAddress),
XEL_HEADER_IP_LENGTH_OFFSET +
XEL_RXBUFF_OFFSET) >>
XEL_HEADER_SHIFT) &
(XEL_RPLR_LENGTH_MASK_HI |
XEL_RPLR_LENGTH_MASK_LO));
#endif
Length += XEL_HEADER_SIZE + XEL_FCS_SIZE;
} else if (LengthType == XEL_ETHER_PROTO_TYPE_ARP) {
/*
* The packet is an ARP Packet.
*/
Length = XEL_ARP_PACKET_SIZE + XEL_HEADER_SIZE +
XEL_FCS_SIZE;
} else {
/*
* Field contains type other than IP or ARP, use max
* frame size and let user parse it.
*/
Length = XEL_MAX_FRAME_SIZE;
}
} else {
/*
* Use the length in the frame, plus the header and trailer.
*/
Length = LengthType + XEL_HEADER_SIZE + XEL_FCS_SIZE;
}
/*
* Read from the EmacLite.
*/
XEmacLite_AlignedRead(((u32 *) (BaseAddress + XEL_RXBUFF_OFFSET)),
FramePtr, Length);
/*
* Acknowledge the frame.
*/
Register = XEmacLite_GetRxStatus(BaseAddress);
Register &= ~XEL_RSR_RECV_DONE_MASK;
XEmacLite_SetRxStatus(BaseAddress, Register);
return Length;
}
/*****************************************************************************/
/**
*
* Set the MAC address for this device. The address is a 48-bit value.
*
* @param InstancePtr is a pointer to the XEmacLite instance.
* @param AddressPtr is a pointer to a 6-byte MAC address.
* the format of the MAC address is major octet to minor octet
*
* @return None.
*
* @note
*
* - TX must be idle and RX should be idle for deterministic results.
* It is recommended that this function should be called after the
* initialization and before transmission of any packets from the device.
* - Function will not return if hardware is absent or not functioning
* properly.
* - The MAC address can be programmed using any of the two transmit
* buffers (if configured).
*
******************************************************************************/
void XEmacLite_SetMacAddress(XEmacLite *InstancePtr, u8 *AddressPtr)
{
u32 BaseAddress;
/*
* Verify that each of the inputs are valid.
*/
Xil_AssertVoid(InstancePtr != NULL);
/*
* Determine the expected TX buffer address.
*/
BaseAddress = XEmacLite_NextTransmitAddr(InstancePtr);
/*
* Copy the MAC address to the Transmit buffer.
*/
XEmacLite_AlignedWrite(AddressPtr,
(u32 *) BaseAddress,
XEL_MAC_ADDR_SIZE);
/*
* Set the length.
*/
XEmacLite_WriteReg(BaseAddress,
XEL_TPLR_OFFSET,
XEL_MAC_ADDR_SIZE);
/*
* Update the MAC address in the EmacLite.
*/
XEmacLite_SetTxStatus(BaseAddress, XEL_TSR_PROG_MAC_ADDR);
/*
* Wait for EmacLite to finish with the MAC address update.
*/
while ((XEmacLite_GetTxStatus(BaseAddress) &
XEL_TSR_PROG_MAC_ADDR) != 0);
}
/******************************************************************************/
/**
*
* This is a stub for the send and receive callbacks. The stub
* is here in case the upper layers forget to set the handlers.
*
* @param CallBackRef is a pointer to the upper layer callback reference.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void StubHandler(void *CallBackRef)
{
(void)(CallBackRef);
Xil_AssertVoidAlways();
}
/****************************************************************************/
/**
*
* Determine if there is a transmit buffer available.
*
* @param InstancePtr is the pointer to the instance of the driver to
* be worked on.
*
* @return
* - TRUE if there is a TX buffer available for data to be written
* - FALSE if Tx Buffer is not available.
*
* @note None.
*
*****************************************************************************/
int XEmacLite_TxBufferAvailable(XEmacLite *InstancePtr)
{
u32 Register;
int TxPingBusy;
int TxPongBusy;
/*
* Verify that each of the inputs are valid.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
/*
* Read the Tx Status and determine if the buffer is available.
*/
Register = XEmacLite_GetTxStatus(InstancePtr->EmacLiteConfig.
BaseAddress);
TxPingBusy = (Register & (XEL_TSR_XMIT_BUSY_MASK |
XEL_TSR_XMIT_ACTIVE_MASK));
/*
* Read the Tx Status of the second buffer register and determine if the
* buffer is available.
*/
if (InstancePtr->EmacLiteConfig.TxPingPong != 0) {
Register = XEmacLite_GetTxStatus(InstancePtr->EmacLiteConfig.
BaseAddress +
XEL_BUFFER_OFFSET);
TxPongBusy = (Register & (XEL_TSR_XMIT_BUSY_MASK |
XEL_TSR_XMIT_ACTIVE_MASK));
return (!(TxPingBusy && TxPongBusy));
}
return (!TxPingBusy);
}
/****************************************************************************/
/**
*
* Flush the Receive buffers. All data will be lost.
*
* @param InstancePtr is the pointer to the instance of the driver to
* be worked on.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XEmacLite_FlushReceive(XEmacLite *InstancePtr)
{
u32 Register;
/*
* Verify that each of the inputs are valid.
*/
Xil_AssertVoid(InstancePtr != NULL);
/*
* Read the current buffer register and determine if the buffer is
* available.
*/
Register = XEmacLite_GetRxStatus(InstancePtr->EmacLiteConfig.
BaseAddress);
/*
* Preserve the IE bit.
*/
Register &= XEL_RSR_RECV_IE_MASK;
/*
* Write out the value to flush the RX buffer.
*/
XEmacLite_SetRxStatus(InstancePtr->EmacLiteConfig.BaseAddress,
Register);
/*
* If the pong buffer is available, flush it also.
*/
if (InstancePtr->EmacLiteConfig.RxPingPong != 0) {
/*
* Read the current buffer register and determine if the buffer
* is available.
*/
Register = XEmacLite_GetRxStatus(InstancePtr->EmacLiteConfig.
BaseAddress +
XEL_BUFFER_OFFSET);
/*
* Preserve the IE bit.
*/
Register &= XEL_RSR_RECV_IE_MASK;
/*
* Write out the value to flush the RX buffer.
*/
XEmacLite_SetRxStatus(InstancePtr->EmacLiteConfig.BaseAddress +
XEL_BUFFER_OFFSET, Register);
}
}
/******************************************************************************/
/**
*
* Read the specified PHY register.
*
* @param InstancePtr is the pointer to the instance of the driver.
* @param PhyAddress is the address of the PHY device. The valid range is
* is from 0 to 31.
* @param RegNum is the register number in the PHY device which
* is to be read. The valid range is is from 0 to 31.
* @param PhyDataPtr is a pointer to the data in which the data read
* from the PHY device is returned.
*
* @return
* - XST_SUCCESS if the data is read from the PHY.
* - XST_DEVICE_BUSY if MDIO is busy.
*
* @note This function waits for the completion of MDIO data transfer.
*
*****************************************************************************/
int XEmacLite_PhyRead(XEmacLite *InstancePtr, u32 PhyAddress, u32 RegNum,
u16 *PhyDataPtr)
{
u32 PhyAddrReg;
u32 MdioCtrlReg;
/*
* Verify that each of the inputs are valid.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->EmacLiteConfig.MdioInclude == TRUE);
Xil_AssertNonvoid(PhyAddress <= 31);
Xil_AssertNonvoid(RegNum <= 31);
Xil_AssertNonvoid(PhyDataPtr != NULL);
/*
* Verify MDIO master status.
*/
if (XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_MDIOCNTR_OFFSET) &
XEL_MDIOCNTR_STATUS_MASK) {
return XST_DEVICE_BUSY;
}
PhyAddrReg = ((((PhyAddress << XEL_MDIO_ADDRESS_SHIFT) &
XEL_MDIO_ADDRESS_MASK) | RegNum) | XEL_MDIO_OP_MASK);
XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_MDIOADDR_OFFSET, PhyAddrReg);
/*
* Enable MDIO and start the transfer.
*/
MdioCtrlReg =
XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_MDIOCNTR_OFFSET);
XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_MDIOCNTR_OFFSET,
MdioCtrlReg |
XEL_MDIOCNTR_STATUS_MASK |
XEL_MDIOCNTR_ENABLE_MASK);
/*
* Wait till the completion of transfer.
*/
while ((XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_MDIOCNTR_OFFSET) &
XEL_MDIOCNTR_STATUS_MASK));
/*
* Read data from MDIO read data register.
*/
*PhyDataPtr = (u16)XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_MDIORD_OFFSET);
/*
* Disable the MDIO.
*/
MdioCtrlReg =
XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_MDIOCNTR_OFFSET);
XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_MDIOCNTR_OFFSET,
MdioCtrlReg & ~XEL_MDIOCNTR_ENABLE_MASK);
return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* Write the given data to the specified register in the PHY device.
*
* @param InstancePtr is the pointer to the instance of the driver.
* @param PhyAddress is the address of the PHY device. The valid range is
* is from 0 to 31.
* @param RegNum is the register number in the PHY device which
* is to be written. The valid range is is from 0 to 31.
* @param PhyData is the data to be written to the specified register in
* the PHY device.
*
* @return
* - XST_SUCCESS if the data is written to the PHY.
* - XST_DEVICE_BUSY if MDIO is busy.
*
* @note This function waits for the completion of MDIO data transfer.
*
*******************************************************************************/
int XEmacLite_PhyWrite(XEmacLite *InstancePtr, u32 PhyAddress, u32 RegNum,
u16 PhyData)
{
u32 PhyAddrReg;
u32 MdioCtrlReg;
/*
* Verify that each of the inputs are valid.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->EmacLiteConfig.MdioInclude == TRUE);
Xil_AssertNonvoid(PhyAddress <= 31);
Xil_AssertNonvoid(RegNum <= 31);
/*
* Verify MDIO master status.
*/
if (XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_MDIOCNTR_OFFSET) &
XEL_MDIOCNTR_STATUS_MASK) {
return XST_DEVICE_BUSY;
}
PhyAddrReg = ((((PhyAddress << XEL_MDIO_ADDRESS_SHIFT) &
XEL_MDIO_ADDRESS_MASK) | RegNum) & ~XEL_MDIO_OP_MASK);
XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_MDIOADDR_OFFSET, PhyAddrReg);
/*
* Write data to MDIO write data register.
*/
XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_MDIOWR_OFFSET, (u32)PhyData);
/*
* Enable MDIO and start the transfer.
*/
MdioCtrlReg =
XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_MDIOCNTR_OFFSET);
XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_MDIOCNTR_OFFSET,
MdioCtrlReg | XEL_MDIOCNTR_STATUS_MASK |
XEL_MDIOCNTR_ENABLE_MASK);
/*
* Wait till the completion of transfer.
*/
while ((XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_MDIOCNTR_OFFSET) & XEL_MDIOCNTR_STATUS_MASK));
/*
* Disable the MDIO.
*/
MdioCtrlReg =
XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_MDIOCNTR_OFFSET);
XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_MDIOCNTR_OFFSET,
MdioCtrlReg & ~XEL_MDIOCNTR_ENABLE_MASK);
return XST_SUCCESS;
}
/****************************************************************************/
/**
*
* Enable Internal loop back functionality.
*
* @param InstancePtr is the pointer to the instance of the driver.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XEmacLite_EnableLoopBack(XEmacLite *InstancePtr)
{
u32 TsrReg;
/*
* Verify that each of the inputs are valid.
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->EmacLiteConfig.Loopback == TRUE);
TsrReg = XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_TSR_OFFSET);
XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_TSR_OFFSET, TsrReg | XEL_TSR_LOOPBACK_MASK);
}
/****************************************************************************/
/**
*
* Disable Internal loop back functionality.
*
* @param InstancePtr is the pointer to the instance of the driver.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XEmacLite_DisableLoopBack(XEmacLite *InstancePtr)
{
u32 TsrReg;
/*
* Verify that each of the inputs are valid.
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->EmacLiteConfig.Loopback == TRUE);
TsrReg = XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_TSR_OFFSET);
XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
XEL_TSR_OFFSET, TsrReg & (~XEL_TSR_LOOPBACK_MASK));
}
/*****************************************************************************/
/**
*
* Return the length of the data in the Receive Buffer.
*
* @param BaseAddress contains the base address of the device.
*
* @return The type/length field of the frame received.
*
* @note None.
*
******************************************************************************/
static u16 XEmacLite_GetReceiveDataLength(u32 BaseAddress)
{
u16 Length;
#ifdef __LITTLE_ENDIAN__
Length = (XEmacLite_ReadReg((BaseAddress),
XEL_HEADER_OFFSET + XEL_RXBUFF_OFFSET) &
(XEL_RPLR_LENGTH_MASK_HI | XEL_RPLR_LENGTH_MASK_LO));
Length = (u16) (((Length & 0xFF00) >> 8) | ((Length & 0x00FF) << 8));
#else
Length = ((XEmacLite_ReadReg((BaseAddress),
XEL_HEADER_OFFSET + XEL_RXBUFF_OFFSET) >>
XEL_HEADER_SHIFT) &
(XEL_RPLR_LENGTH_MASK_HI | XEL_RPLR_LENGTH_MASK_LO));
#endif
return Length;
}

404
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite.h
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@ -0,0 +1,404 @@
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemaclite.h
*
* The Xilinx Ethernet Lite (EmacLite) driver. This driver supports the Xilinx
* Ethernet Lite 10/100 MAC (EmacLite).
*
* The Xilinx Ethernet Lite 10/100 MAC supports the following features:
* - Media Independent Interface (MII) for connection to external
* 10/100 Mbps PHY transceivers
* - Independent internal transmit and receive buffers
* - CSMA/CD compliant operations for half-duplex modes
* - Unicast and broadcast
* - Automatic FCS insertion
* - Automatic pad insertion on transmit
* - Configurable ping/pong buffers for either/both transmit and receive
* buffer areas
* - Interrupt driven mode
* - Internal loop back
* - MDIO Support to access PHY Registers
*
* The Xilinx Ethernet Lite 10/100 MAC does not support the following features:
* - multi-frame buffering
* only 1 transmit frame is allowed into each transmit buffer,
* only 1 receive frame is allowed into each receive buffer.
* the hardware blocks reception until buffer is emptied
* - Pause frame (flow control) detection in full-duplex mode
* - Programmable inter frame gap
* - Multicast and promiscuous address filtering
* - Automatic source address insertion or overwrite
*
* <b>Driver Description</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the EmacLite. The driver handles transmission and reception
* of Ethernet frames, as well as configuration of the controller. It does not
* handle protocol stack functionality such as Link Layer Control (LLC) or the
* Address Resolution Protocol (ARP). The protocol stack that makes use of the
* driver handles this functionality. This implies that the driver is simply a
* pass-through mechanism between a protocol stack and the EmacLite.
*
* Since the driver is a simple pass-through mechanism between a protocol stack
* and the EmacLite, no assembly or disassembly of Ethernet frames is done at
* the driver-level. This assumes that the protocol stack passes a correctly
* formatted Ethernet frame to the driver for transmission, and that the driver
* does not validate the contents of an incoming frame. A single device driver
* can support multiple EmacLite devices.
*
* The driver supports interrupt driven mode and the default mode of operation
* is polled mode. If interrupts are desired, XEmacLite_InterruptEnable() must
* be called.
*
* <b>Device Configuration</b>
*
* The device can be configured in various ways during the FPGA implementation
* process. Configuration parameters are stored in the xemaclite_g.c file.
* A table is defined where each entry contains configuration information for an
* EmacLite device. This information includes such things as the base address
* of the memory-mapped device and the number of buffers.
*
* <b>Interrupt Processing</b>
*
* After _Initialize is called, _InterruptEnable can be called to enable the
* interrupt driven functionality. If polled operation is desired, just call
* _Send and check the return code. If XST_FAILURE is returned, call _Send with
* the same data until XST_SUCCESS is returned. The same idea applies to _Recv.
* Call _Recv until the returned length is non-zero at which point the received
* data is in the buffer provided in the function call.
*
* The Transmit and Receive interrupts are enabled within the _InterruptEnable
* function and disabled in the _InterruptDisable function. The _Send and _Recv
* functions acknowledge the EmacLite generated interrupts associated with each
* function.
* It is the application's responsibility to acknowledge any associated Interrupt
* Controller interrupts if it is used in the system.
*
* <b>Memory Buffer Alignment</b>
*
* The alignment of the input/output buffers for the _Send and _Recv routine is
* not required to be 32 bits. If the buffer is not aligned on a 32-bit boundary
* there will be a performance impact while the driver aligns the data for
* transmission or upon reception.
*
* For optimum performance, the user should provide a 32-bit aligned buffer
* to the _Send and _Recv routines.
*
* <b>Asserts</b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that application developers leave asserts on during
* development.
*
* @note
*
* This driver requires EmacLite hardware version 1.01a and higher. It is not
* compatible with earlier versions of the EmacLite hardware. Use version 1.00a
* software driver for hardware version 1.00a/b.
*
* The RX hardware is enabled from powerup and there is no disable. It is
* possible that frames have been received prior to the initialization
* of the driver. If this situation is possible, call XEmacLite_FlushReceive()
* to empty the receive buffers after initialization.
*
* This driver is intended to be RTOS and processor independent. It works
* with physical addresses only. Any needs for dynamic memory management,
* threads or thread mutual exclusion, virtual memory, or cache control must
* be satisfied by the layer above this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.01a ecm 01/30/04 First release
* 1.11a mta 03/21/07 Updated to new coding style
* 1.12a mta 11/28/07 Added the function XEmacLite_CfgInitialize,
* moved the functions XEmacLite_LookupConfig and
* XEmacLite_Initialize to xemaclite_sinit.c for removing
* the dependency on the static config table and
* xparameters.h from the driver initialization
* 1.13a sv 02/1/08 Updated the TxBufferAvailable routine to return
* busy status properly and added macros for Tx/Rx status
* 1.14a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
* file
* 2.00a ktn 02/16/09 Added support for MDIO and internal loop back
* 2.01a ktn 07/20/09 Updated the XEmacLite_AlignedWrite and
* XEmacLite_AlignedRead functions to use volatile
* variables so that they are not optimized.
* Modified the XEmacLite_EnableInterrupts and
* XEmacLite_DisableInterrupts functions to enable/disable
* the interrupt in the Ping buffer as this is used to enable
* the interrupts for both Ping and Pong Buffers.
* The interrupt enable bit in the Pong buffer is not used by
* the HW.
* Modified XEmacLite_Send function to use Ping buffers
* Interrupt enable bit since this alone is used to enable
* the interrupts for both Ping and Pong Buffers.
* 3.00a ktn 10/22/09 Updated driver to use the HAL Processor APIs/macros.
* The macros have been renamed to remove _m from the name in
* all the driver files.
* The macros changed in this file are
* XEmacLite_mNextTransmitAddr is XEmacLite_NextTransmitAddr,
* XEmacLite_mNextReceiveAddr is XEmacLite_NextReceiveAddr,
* XEmacLite_mIsMdioConfigured is XEmacLite_IsMdioConfigured,
* XEmacLite_mIsLoopbackConfigured is
* XEmacLite_IsLoopbackConfigured.
* See xemaclite_i.h for the macros which have changed.
* 3.01a ktn 07/08/10 The macro XEmacLite_GetReceiveDataLength in the
* xemaclite.c file is changed to a static function.
* XEmacLite_GetReceiveDataLength and XEmacLite_Recv
* functions are updated to support little endian
* MicroBlaze.
* 3.02a sdm 07/22/11 Removed redundant code in XEmacLite_Recv functions for
* CR617290
* 3.03a asa 04/05/12 Defined the flag __LITTLE_ENDIAN__ for cases where the
* driver is compiled with ARM toolchain.
* 3.04a srt 04/13/13 Removed warnings (CR 705000).
* 4.0 adk 19/12/13 Updated as per the New Tcl API's
*
* </pre>
*
*
******************************************************************************/
#ifndef XEMACLITE_H /* prevent circular inclusions */
#define XEMACLITE_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xenv.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xemaclite_l.h"
#ifdef __ARMEL__
#ifndef __LITTLE_ENDIAN__
#define __LITTLE_ENDIAN__
#endif
#endif
/************************** Constant Definitions *****************************/
/*
* Device information
*/
#define XEL_DEVICE_NAME "xemaclite"
#define XEL_DEVICE_DESC "Xilinx Ethernet Lite 10/100 MAC"
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for a device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Device base address */
u8 TxPingPong; /**< 1 if TX Pong buffer configured, 0 otherwise */
u8 RxPingPong; /**< 1 if RX Pong buffer configured, 0 otherwise */
u8 MdioInclude; /**< 1 if MDIO is enabled, 0 otherwise */
u8 Loopback; /**< 1 if internal loopback is enabled, 0 otherwise */
} XEmacLite_Config;
/*
* Callback when data is sent or received .
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions, and passed back to the
* upper layer when the callback is invoked.
*/
typedef void (*XEmacLite_Handler) (void *CallBackRef);
/**
* The XEmacLite driver instance data. The user is required to allocate a
* variable of this type for every EmacLite device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XEmacLite_Config EmacLiteConfig; /* Device configuration */
u32 IsReady; /* Device is initialized and ready */
u32 NextTxBufferToUse; /* Next TX buffer to write to */
u32 NextRxBufferToUse; /* Next RX buffer to read from */
/*
* Callbacks
*/
XEmacLite_Handler RecvHandler;
void *RecvRef;
XEmacLite_Handler SendHandler;
void *SendRef;
} XEmacLite;
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* Return the next expected Transmit Buffer's address.
*
* @param InstancePtr is the pointer to the instance of the driver to
* be worked on
*
* @note C-Style signature:
* u32 XEmacLite_NextTransmitAddr(XEmacLite *InstancePtr);
*
* This macro returns the address of the next transmit buffer to put data into.
* This is used to determine the destination of the next transmit data frame.
*
*****************************************************************************/
#define XEmacLite_NextTransmitAddr(InstancePtr) \
((InstancePtr)->EmacLiteConfig.BaseAddress + \
(InstancePtr)->NextTxBufferToUse) + XEL_TXBUFF_OFFSET
/****************************************************************************/
/**
*
* Return the next expected Receive Buffer's address.
*
* @param InstancePtr is the pointer to the instance of the driver to
* be worked on
*
* @note C-Style signature:
* u32 XEmacLite_NextReceiveAddr(XEmacLite *InstancePtr);
*
* This macro returns the address of the next receive buffer to read data from.
* This is the expected receive buffer address if the driver is in sync.
*
*****************************************************************************/
#define XEmacLite_NextReceiveAddr(InstancePtr) \
((InstancePtr)->EmacLiteConfig.BaseAddress + \
(InstancePtr)->NextRxBufferToUse)
/*****************************************************************************/
/**
*
* This macro determines if the device is currently configured for MDIO.
*
* @param InstancePtr is the pointer to the instance of the
* EmacLite driver.
*
* @return
* - TRUE if the device is configured for MDIO.
* - FALSE if the device is NOT configured for MDIO.
*
* @note C-Style signature:
* int XEmacLite_IsMdioConfigured(XEmacLite *InstancePtr)
*
******************************************************************************/
#define XEmacLite_IsMdioConfigured(InstancePtr) \
((InstancePtr)->EmacLiteConfig.MdioInclude == 1)
/*****************************************************************************/
/**
*
* This macro determines if the device is currently configured for internal
* loopback.
*
* @param InstancePtr is the pointer to the instance of the
* EmacLite driver.
*
* @return
* - TRUE if the device is configured for internal loopback.
* - FALSE if the device is NOT configured for internal loopback.
*
* @note C-Style signature:
* int XEmacLite_IsLoopbackConfigured(XEmacLite *InstancePtr)
*
******************************************************************************/
#define XEmacLite_IsLoopbackConfigured(InstancePtr) \
((InstancePtr)->EmacLiteConfig.Loopback == 1)
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/*
* Functions in xemaclite.c
*/
int XEmacLite_CfgInitialize(XEmacLite *InstancePtr,
XEmacLite_Config *EmacLiteConfigPtr,
u32 EffectiveAddr);
void XEmacLite_SetMacAddress(XEmacLite *InstancePtr, u8 *AddressPtr);
int XEmacLite_TxBufferAvailable(XEmacLite *InstancePtr);
void XEmacLite_FlushReceive(XEmacLite *InstancePtr);
int XEmacLite_Send(XEmacLite *InstancePtr, u8 *FramePtr, unsigned ByteCount);
u16 XEmacLite_Recv(XEmacLite *InstancePtr, u8 *FramePtr);
int XEmacLite_PhyRead(XEmacLite *InstancePtr, u32 PhyAddress, u32 RegNum,
u16 *PhyDataPtr);
int XEmacLite_PhyWrite(XEmacLite *InstancePtr, u32 PhyAddress, u32 RegNum,
u16 PhyData);
void XEmacLite_EnableLoopBack(XEmacLite *InstancePtr);
void XEmacLite_DisableLoopBack(XEmacLite *InstancePtr);
/*
* Initialization functions in xemaclite_sinit.c
*/
XEmacLite_Config *XEmacLite_LookupConfig(u16 DeviceId);
int XEmacLite_Initialize(XEmacLite *InstancePtr, u16 DeviceId);
/*
* Interrupt driven functions in xemaclite_intr.c
*/
int XEmacLite_EnableInterrupts(XEmacLite *InstancePtr);
void XEmacLite_DisableInterrupts(XEmacLite *InstancePtr);
void XEmacLite_InterruptHandler(void *InstancePtr);
void XEmacLite_SetRecvHandler(XEmacLite *InstancePtr, void *CallBackRef,
XEmacLite_Handler FuncPtr);
void XEmacLite_SetSendHandler(XEmacLite *InstancePtr, void *CallBackRef,
XEmacLite_Handler FuncPtr);
/*
* Selftest function in xemaclite_selftest.c
*/
int XEmacLite_SelfTest(XEmacLite *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

59
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_g.c
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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xemaclite.h"
/*
* The configuration table for devices
*/
XEmacLite_Config XEmacLite_ConfigTable[] =
{
{
XPAR_AXI_ETHERNETLITE_0_DEVICE_ID,
XPAR_AXI_ETHERNETLITE_0_BASEADDR,
XPAR_AXI_ETHERNETLITE_0_TX_PING_PONG,
XPAR_AXI_ETHERNETLITE_0_RX_PING_PONG,
XPAR_AXI_ETHERNETLITE_0_INCLUDE_MDIO,
XPAR_AXI_ETHERNETLITE_0_INCLUDE_INTERNAL_LOOPBACK
}
};

136
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_i.h
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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************/
/**
* @file xemaclite_i.h
*
* This header file contains internal identifiers, which are those shared
* between the files of the driver. It is intended for internal use only.
*
* NOTES:
*
* None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.01a ecm 05/21/04 First release
* 1.11a mta 03/21/07 Updated to new coding style
* 1.13a sv 02/1/08 Added macros to Get/Set Tx/Rx status
* 3.00a ktn 10/22/09 The macros have been renamed to remove _m from the name.
* The macros changed in this file are
* XEmacLite_mGetTxActive changed to XEmacLite_GetTxActive,
* XEmacLite_mSetTxActive changed to XEmacLite_SetTxActive.
*
* </pre>
******************************************************************************/
#ifndef XEMACLITE_I_H /* prevent circular inclusions */
#define XEMACLITE_I_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xemaclite.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* Get the TX active location to check status. This is used to check if
* the TX buffer is currently active. There isn't any way in the hardware
* to implement this but the register is fully populated so the driver can
* set the bit in the send routine and the ISR can clear the bit when
* the handler is complete. This mimics the correct operation of the hardware
* if it was possible to do this in hardware.
*
* @param BaseAddress is the base address of the device
*
* @return Contents of active bit in register.
*
* @note C-Style signature:
* u32 XEmacLite_GetTxActive(u32 BaseAddress)
*
*****************************************************************************/
#define XEmacLite_GetTxActive(BaseAddress) \
(XEmacLite_ReadReg((BaseAddress), XEL_TSR_OFFSET))
/****************************************************************************/
/**
*
* Set the TX active location to update status. This is used to set the bit
* indicating which TX buffer is currently active. There isn't any way in the
* hardware to implement this but the register is fully populated so the driver
* can set the bit in the send routine and the ISR can clear the bit when
* the handler is complete. This mimics the correct operation of the hardware
* if it was possible to do this in hardware.
*
* @param BaseAddress is the base address of the device
* @param Mask is the data to be written
*
* @return None
*
* @note C-Style signature:
* void XEmacLite_SetTxActive(u32 BaseAddress, u32 Mask)
*
*****************************************************************************/
#define XEmacLite_SetTxActive(BaseAddress, Mask) \
(XEmacLite_WriteReg((BaseAddress), XEL_TSR_OFFSET, (Mask)))
/************************** Variable Definitions ****************************/
extern XEmacLite_Config XEmacLite_ConfigTable[];
/************************** Function Prototypes ******************************/
void XEmacLite_AlignedWrite(void *SrcPtr, u32 *DestPtr, unsigned ByteCount);
void XEmacLite_AlignedRead(u32 *SrcPtr, void *DestPtr, unsigned ByteCount);
void StubHandler(void *CallBackRef);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_intr.c
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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemaclite_intr.c
*
* Functions in this file are for the interrupt driven processing functionality.
* See xemaclite.h for a detailed description of the driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- --------------------------------------------------------
* 1.01a ecm 03/31/04 First release
* 1.11a mta 03/21/07 Updated to new coding style
* 2.01a ktn 07/20/09 Modified the XEmacLite_EnableInterrupts and
* XEmacLite_DisableInterrupts functions to enable/disable
* the interrupt in the Ping buffer as this is used to enable
* the interrupts for both Ping and Pong Buffers.
* The interrupt enable bit in the Pong buffer is not used by
* the HW.
* 3.00a ktn 10/22/09 Updated file to use the HAL Processor APIs/macros.
* The macros have been renamed to remove _m from the name.
*
* </pre>
******************************************************************************/
/***************************** Include Files *********************************/
#include "xemaclite_i.h"
#include "xil_io.h"
#include "xemaclite.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Enable the EmacLite Interrupts.
*
* This function must be called before other functions to send or receive data
* in interrupt driven mode. The user should have connected the
* interrupt handler of the driver to an interrupt source such as an interrupt
* controller or the processor interrupt prior to this function being called.
*
* @param InstancePtr is a pointer to the XEmacLite instance.
*
* @return
* - XST_SUCCESS if the device interrupts were enabled
* successfully.
* - XST_NO_CALLBACK if the callbacks were not set.
*
* @note None.
*
******************************************************************************/
int XEmacLite_EnableInterrupts(XEmacLite *InstancePtr)
{
u32 Register;
u32 BaseAddress;
/*
* Verify that each of the inputs are valid.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
BaseAddress = InstancePtr->EmacLiteConfig.BaseAddress;
/*
* Verify that the handlers are in place.
*/
if ((InstancePtr->RecvHandler == (XEmacLite_Handler) StubHandler) ||
(InstancePtr->SendHandler == (XEmacLite_Handler) StubHandler)) {
return XST_NO_CALLBACK;
}
/*
* Enable the TX interrupts for both the buffers, the Interrupt Enable
* is common for the both the buffers and is defined in the
* Ping buffer.
*/
Register = XEmacLite_GetTxStatus(BaseAddress);
Register |= XEL_TSR_XMIT_IE_MASK;
XEmacLite_SetTxStatus(BaseAddress, Register);
/*
* Enable the RX interrupts for both the buffers, the Interrupt Enable
* is common for the both the buffers and is defined in the
* Ping buffer.
*/
Register = XEmacLite_GetRxStatus(BaseAddress);
Register |= XEL_RSR_RECV_IE_MASK;
XEmacLite_SetRxStatus(BaseAddress, Register);
/*
* Enable the global interrupt output.
*/
XEmacLite_WriteReg(BaseAddress, XEL_GIER_OFFSET, XEL_GIER_GIE_MASK);
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* Disables the interrupts from the device (the higher layer software is
* responsible for disabling interrupts at the interrupt controller).
*
* To start using the device again, _EnableInterrupts must be called.
*
* @param InstancePtr is a pointer to the XEmacLite instance .
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XEmacLite_DisableInterrupts(XEmacLite *InstancePtr)
{
u32 Register;
u32 BaseAddress;
/*
* Verify that each of the inputs are valid.
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
BaseAddress = InstancePtr->EmacLiteConfig.BaseAddress;
/*
* Disable the global interrupt output.
*/
XEmacLite_WriteReg(BaseAddress, XEL_GIER_OFFSET, 0);
/*
* Disable the TX interrupts for both the buffers, the Interrupt Enable
* is common for the both the buffers and is defined in the
* Ping buffer.
*/
Register = XEmacLite_GetTxStatus(BaseAddress);
Register &= ~XEL_TSR_XMIT_IE_MASK;
XEmacLite_SetTxStatus(BaseAddress, Register);
/*
* Disable the RX interrupts for both the buffers, the Interrupt Enable
* is common for the both the buffers and is defined in the
* Ping buffer.
*/
Register = XEmacLite_GetRxStatus(BaseAddress);
Register &= ~XEL_RSR_RECV_IE_MASK;
XEmacLite_SetRxStatus(BaseAddress, Register);
}
/*****************************************************************************/
/**
*
* Interrupt handler for the EmacLite driver. It performs the following
* processing:
*
* - Get the interrupt status from the registers to determine the source
* of the interrupt.
* - Call the appropriate handler based on the source of the interrupt.
*
* @param InstancePtr contains a pointer to the EmacLite device instance
* for the interrupt.
*
* @return None.
*
* @note None.
*
*
******************************************************************************/
void XEmacLite_InterruptHandler(void *InstancePtr)
{
XEmacLite *EmacLitePtr;
int TxCompleteIntr = FALSE;
u32 BaseAddress;
u32 TxStatus;
/*
* Verify that each of the inputs are valid.
*/
Xil_AssertVoid(InstancePtr != NULL);
/*
* Convert the non-typed pointer to an EmacLite instance pointer
* such that there is access to the device.
*/
EmacLitePtr = (XEmacLite *) InstancePtr;
BaseAddress = EmacLitePtr->EmacLiteConfig.BaseAddress;
if ((XEmacLite_IsRxEmpty(BaseAddress) != TRUE) ||
(XEmacLite_IsRxEmpty(BaseAddress +
XEL_BUFFER_OFFSET) != TRUE)) {
/*
* Call the RX callback.
*/
EmacLitePtr->RecvHandler(EmacLitePtr->RecvRef);
}
TxStatus = XEmacLite_GetTxStatus(BaseAddress);
if (((TxStatus & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
(TxStatus & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
/*
* Clear the Tx Active bit in the Tx Status Register.
*/
TxStatus &= ~XEL_TSR_XMIT_ACTIVE_MASK;
XEmacLite_SetTxStatus(BaseAddress, TxStatus);
/*
* Update the flag indicating that there was a Tx Interrupt.
*/
TxCompleteIntr = TRUE;
}
TxStatus = XEmacLite_GetTxStatus(BaseAddress + XEL_BUFFER_OFFSET);
if (((TxStatus & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
(TxStatus & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
/*
* Clear the Tx Active bit in the Tx Status Register.
*/
TxStatus &= ~XEL_TSR_XMIT_ACTIVE_MASK;
XEmacLite_SetTxStatus(BaseAddress + XEL_BUFFER_OFFSET,
TxStatus);
/*
* Update the flag indicating that there was a Tx Interrupt.
*/
TxCompleteIntr = TRUE;
}
/*
* If there was a TX interrupt, call the callback.
*/
if (TxCompleteIntr == TRUE) {
/*
* Call the TX callback.
*/
EmacLitePtr->SendHandler(EmacLitePtr->SendRef);
}
}
/*****************************************************************************/
/**
*
* Sets the callback function for handling received frames in interrupt mode.
* The upper layer software should call this function during initialization.
* The callback is called when a frame is received. The callback function
* should communicate the data to a thread such that the processing is not
* performed in an interrupt context.
*
* The callback is invoked by the driver within interrupt context, so it needs
* to do its job quickly. If there are other potentially slow operations
* within the callback, these should be done at task-level.
*
* @param InstancePtr is a pointer to the XEmacLite instance..
* @param CallBackRef is a reference pointer to be passed back to the
* application in the callback. This helps the application
* correlate the callback to a particular driver.
* @param FuncPtr is the pointer to the callback function.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XEmacLite_SetRecvHandler(XEmacLite *InstancePtr, void *CallBackRef,
XEmacLite_Handler FuncPtr)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(FuncPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
InstancePtr->RecvHandler = FuncPtr;
InstancePtr->RecvRef = CallBackRef;
}
/*****************************************************************************/
/**
*
* Sets the callback function for handling transmitted frames in interrupt mode.
* The upper layer software should call this function during initialization.
* The callback is called when a frame is transmitted. The callback function
* should communicate the data to a thread such that the processing is not
* performed in an interrupt context.
*
* The callback is invoked by the driver within interrupt context, so it needs
* to do its job quickly. If there are other potentially slow operations
* within the callback, these should be done at task-level.
*
* @param InstancePtr is a pointer to the XEmacLite instance.
* @param CallBackRef is a reference pointer to be passed back to the
* application in the callback. This helps the application
* correlate the callback to a particular driver.
* @param FuncPtr is the pointer to the callback function.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XEmacLite_SetSendHandler(XEmacLite *InstancePtr, void *CallBackRef,
XEmacLite_Handler FuncPtr)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(FuncPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
InstancePtr->SendHandler = FuncPtr;
InstancePtr->SendRef = CallBackRef;
}

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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemaclite_l.c
*
* This file contains the minimal, polled functions to send and receive Ethernet
* frames.
*
* Refer to xemaclite.h for more details.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 06/01/02 First release
* 1.01a ecm 03/31/04 Additional functionality and the _AlignedRead and
* _AlignedWrite functions.
* 1.11a mta 03/21/07 Updated to new coding style
* 2.01a ktn 07/20/09 Updated the XEmacLite_AlignedWrite and
* XEmacLite_AlignedRead functions to use volatile
* variables so that they are not optimized.
* 3.00a ktn 10/22/09 The macros have been renamed to remove _m from the name.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xemaclite_l.h"
#include "xemaclite_i.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
void XEmacLite_AlignedWrite(void *SrcPtr, u32 *DestPtr, unsigned ByteCount);
void XEmacLite_AlignedRead(u32 *SrcPtr, void *DestPtr, unsigned ByteCount);
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Send an Ethernet frame. The size is the total frame size, including header.
* This function blocks waiting for the frame to be transmitted.
*
* @param BaseAddress is the base address of the device
* @param FramePtr is a pointer to frame
* @param ByteCount is the size, in bytes, of the frame
*
* @return None.
*
* @note
*
* This function call is blocking in nature, i.e. it will wait until the
* frame is transmitted. This function can hang and not exit if the
* hardware is not configured properly.
*
* If the ping buffer is the destination of the data, the argument should be
* DeviceAddress + XEL_TXBUFF_OFFSET.
* If the pong buffer is the destination of the data, the argument should be
* DeviceAddress + XEL_TXBUFF_OFFSET + XEL_BUFFER_OFFSET.
* The function does not take the different buffers into consideration.
*
******************************************************************************/
void XEmacLite_SendFrame(u32 BaseAddress, u8 *FramePtr, unsigned ByteCount)
{
u32 Register;
/*
* Write data to the EmacLite
*/
XEmacLite_AlignedWrite(FramePtr, (u32 *) (BaseAddress), ByteCount);
/*
* The frame is in the buffer, now send it
*/
XEmacLite_WriteReg(BaseAddress, XEL_TPLR_OFFSET,
(ByteCount & (XEL_TPLR_LENGTH_MASK_HI |
XEL_TPLR_LENGTH_MASK_LO)));
Register = XEmacLite_GetTxStatus(BaseAddress);
XEmacLite_SetTxStatus(BaseAddress, Register | XEL_TSR_XMIT_BUSY_MASK);
/*
* Loop on the status waiting for the transmit to be complete.
*/
while (!XEmacLite_IsTxDone(BaseAddress));
}
/*****************************************************************************/
/**
*
* Receive a frame. Wait for a frame to arrive.
*
* @param BaseAddress is the base address of the device
* @param FramePtr is a pointer to a buffer where the frame will
* be stored.
*
* @return
*
* The type/length field of the frame received. When the type/length field
* contains the type , XEL_MAX_FRAME_SIZE bytes will be copied out of the
* buffer and it is up to the higher layers to sort out the frame.
*
* @note
*
* This function call is blocking in nature, i.e. it will wait until a
* frame arrives.
*
* If the ping buffer is the source of the data, the argument should be
* DeviceAddress + XEL_RXBUFF_OFFSET.
* If the pong buffer is the source of the data, the argument should be
* DeviceAddress + XEL_RXBUFF_OFFSET + XEL_BUFFER_OFFSET.
* The function does not take the different buffers into consideration.
*
******************************************************************************/
u16 XEmacLite_RecvFrame(u32 BaseAddress, u8 *FramePtr)
{
u16 LengthType;
u16 Length;
u32 Register;
/*
* Wait for a frame to arrive - this is a blocking call
*/
while (XEmacLite_IsRxEmpty(BaseAddress));
/*
* Get the length of the frame that arrived, only 32-bit reads are
* allowed LengthType is in the upper half of the 32-bit word.
*/
Register = XEmacLite_ReadReg(BaseAddress, XEL_RPLR_OFFSET);
LengthType = (u16) ((Register >> 16) &
(XEL_RPLR_LENGTH_MASK_HI |
XEL_RPLR_LENGTH_MASK_LO));
/*
* Check if length is valid
*/
if (LengthType > XEL_MAX_FRAME_SIZE) {
/*
* Field contain type, use max frame size and
* let user parse it
*/
Length = XEL_MAX_FRAME_SIZE;
}
else {
/*
* Use the length in the frame, plus the header and trailer
*/
Length = LengthType + XEL_HEADER_SIZE + XEL_FCS_SIZE;
}
/*
* Read each byte from the EmacLite
*/
XEmacLite_AlignedRead((u32 *) (BaseAddress + XEL_RXBUFF_OFFSET),
FramePtr, Length);
/*
* Acknowledge the frame
*/
Register = XEmacLite_GetRxStatus(BaseAddress);
Register &= ~XEL_RSR_RECV_DONE_MASK;
XEmacLite_SetRxStatus(BaseAddress, Register);
return LengthType;
}
/******************************************************************************/
/**
*
* This function aligns the incoming data and writes it out to a 32-bit
* aligned destination address range.
*
* @param SrcPtr is a pointer to incoming data of any alignment.
* @param DestPtr is a pointer to outgoing data of 32-bit alignment.
* @param ByteCount is the number of bytes to write.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XEmacLite_AlignedWrite(void *SrcPtr, u32 *DestPtr, unsigned ByteCount)
{
unsigned Index;
unsigned Length = ByteCount;
volatile u32 AlignBuffer;
volatile u32 *To32Ptr;
u32 *From32Ptr;
volatile u16 *To16Ptr;
u16 *From16Ptr;
volatile u8 *To8Ptr;
u8 *From8Ptr;
To32Ptr = DestPtr;
if ((((u32) SrcPtr) & 0x00000003) == 0) {
/*
* Word aligned buffer, no correction needed.
*/
From32Ptr = (u32 *) SrcPtr;
while (Length > 3) {
/*
* Output each word destination.
*/
*To32Ptr++ = *From32Ptr++;
/*
* Adjust length accordingly
*/
Length -= 4;
}
/*
* Set up to output the remaining data, zero the temp buffer
first.
*/
AlignBuffer = 0;
To8Ptr = (u8 *) &AlignBuffer;
From8Ptr = (u8 *) From32Ptr;
}
else if ((((u32) SrcPtr) & 0x00000001) != 0) {
/*
* Byte aligned buffer, correct.
*/
AlignBuffer = 0;
To8Ptr = (u8 *) &AlignBuffer;
From8Ptr = (u8 *) SrcPtr;
while (Length > 3) {
/*
* Copy each byte into the temporary buffer.
*/
for (Index = 0; Index < 4; Index++) {
*To8Ptr++ = *From8Ptr++;
}
/*
* Output the buffer
*/
*To32Ptr++ = AlignBuffer;
/*.
* Reset the temporary buffer pointer and adjust length.
*/
To8Ptr = (u8 *) &AlignBuffer;
Length -= 4;
}
/*
* Set up to output the remaining data, zero the temp buffer
* first.
*/
AlignBuffer = 0;
To8Ptr = (u8 *) &AlignBuffer;
}
else {
/*
* Half-Word aligned buffer, correct.
*/
AlignBuffer = 0;
/*
* This is a funny looking cast. The new gcc, version 3.3.x has
* a strict cast check for 16 bit pointers, aka short pointers.
* The following warning is issued if the initial 'void *' cast
* is not used:
* 'dereferencing type-punned pointer will break strict-aliasing
* rules'
*/
To16Ptr = (u16 *) ((void *) &AlignBuffer);
From16Ptr = (u16 *) SrcPtr;
while (Length > 3) {
/*
* Copy each half word into the temporary buffer.
*/
for (Index = 0; Index < 2; Index++) {
*To16Ptr++ = *From16Ptr++;
}
/*
* Output the buffer.
*/
*To32Ptr++ = AlignBuffer;
/*
* Reset the temporary buffer pointer and adjust length.
*/
/*
* This is a funny looking cast. The new gcc, version
* 3.3.x has a strict cast check for 16 bit pointers,
* aka short pointers. The following warning is issued
* if the initial 'void *' cast is not used:
* 'dereferencing type-punned pointer will break
* strict-aliasing rules'
*/
To16Ptr = (u16 *) ((void *) &AlignBuffer);
Length -= 4;
}
/*
* Set up to output the remaining data, zero the temp buffer
* first.
*/
AlignBuffer = 0;
To8Ptr = (u8 *) &AlignBuffer;
From8Ptr = (u8 *) From16Ptr;
}
/*
* Output the remaining data, zero the temp buffer first.
*/
for (Index = 0; Index < Length; Index++) {
*To8Ptr++ = *From8Ptr++;
}
*To32Ptr++ = AlignBuffer;
}
/******************************************************************************/
/**
*
* This function reads from a 32-bit aligned source address range and aligns
* the writes to the provided destination pointer alignment.
*
* @param SrcPtr is a pointer to incoming data of 32-bit alignment.
* @param DestPtr is a pointer to outgoing data of any alignment.
* @param ByteCount is the number of bytes to read.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XEmacLite_AlignedRead(u32 *SrcPtr, void *DestPtr, unsigned ByteCount)
{
unsigned Index;
unsigned Length = ByteCount;
volatile u32 AlignBuffer;
u32 *To32Ptr;
volatile u32 *From32Ptr;
u16 *To16Ptr;
volatile u16 *From16Ptr;
u8 *To8Ptr;
volatile u8 *From8Ptr;
From32Ptr = (u32 *) SrcPtr;
if ((((u32) DestPtr) & 0x00000003) == 0) {
/*
* Word aligned buffer, no correction needed.
*/
To32Ptr = (u32 *) DestPtr;
while (Length > 3) {
/*
* Output each word.
*/
*To32Ptr++ = *From32Ptr++;
/*
* Adjust length accordingly.
*/
Length -= 4;
}
/*
* Set up to read the remaining data.
*/
To8Ptr = (u8 *) To32Ptr;
}
else if ((((u32) DestPtr) & 0x00000001) != 0) {
/*
* Byte aligned buffer, correct.
*/
To8Ptr = (u8 *) DestPtr;
while (Length > 3) {
/*
* Copy each word into the temporary buffer.
*/
AlignBuffer = *From32Ptr++;
From8Ptr = (u8 *) &AlignBuffer;
/*
* Write data to destination.
*/
for (Index = 0; Index < 4; Index++) {
*To8Ptr++ = *From8Ptr++;
}
/*
* Adjust length
*/
Length -= 4;
}
}
else {
/*
* Half-Word aligned buffer, correct.
*/
To16Ptr = (u16 *) DestPtr;
while (Length > 3) {
/*
* Copy each word into the temporary buffer.
*/
AlignBuffer = *From32Ptr++;
/*
* This is a funny looking cast. The new gcc, version
* 3.3.x has a strict cast check for 16 bit pointers,
* aka short pointers. The following warning is issued
* if the initial 'void *' cast is not used:
* 'dereferencing type-punned pointer will break
* strict-aliasing rules'
*/
From16Ptr = (u16 *) ((void *) &AlignBuffer);
/*
* Write data to destination.
*/
for (Index = 0; Index < 2; Index++) {
*To16Ptr++ = *From16Ptr++;
}
/*
* Adjust length.
*/
Length -= 4;
}
/*
* Set up to read the remaining data.
*/
To8Ptr = (u8 *) To16Ptr;
}
/*
* Read the remaining data.
*/
AlignBuffer = *From32Ptr++;
From8Ptr = (u8 *) &AlignBuffer;
for (Index = 0; Index < Length; Index++) {
*To8Ptr++ = *From8Ptr++;
}
}

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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemaclite_l.h
*
* This header file contains identifiers and basic driver functions and macros
* that can be used to access the Xilinx Ethernet Lite 10/100 MAC (EmacLite).
*
* Refer to xemaclite.h for more details.
*
* @note
*
* The functions and macros in this file assume that the proper device address is
* provided in the argument. If the ping buffer is the source or destination,
* the argument should be DeviceAddress + XEL_(T/R)XBUFF_OFFSET. If the pong
* buffer is the source or destination, the argument should be
* DeviceAddress + XEL_(T/R)XBUFF_OFFSET + XEL_BUFFER_OFFSET. The driver does
* not take the different buffers into consideration.
* For more details on the ping/pong buffer configuration please refer to the
* Ethernet Lite 10/100 Media Access Controller hardware specification.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 06/01/02 First release
* 1.01a ecm 03/31/04 Additional functionality and the _AlignedRead and
* AlignedWrite functions.
* Moved the bulk of description to xemaclite.h
* 1.11a mta 03/21/07 Updated to new coding style
* 2.00a ktn 02/16/09 Added support for MDIO and internal loop back
* 3.00a ktn 10/22/09 The macros have been renamed to remove _m from the name.
* The macros changed in this file are
* XEmacLite_mReadReg changed to XEmacLite_mReadReg,
* XEmacLite_mWriteReg changed to XEmacLite_mWriteReg,
* XEmacLite_mGetTxStatus changed to XEmacLite_GetTxStatus,
* XEmacLite_mSetTxStatus changed to XEmacLite_SetTxStatus,
* XEmacLite_mGetRxStatus changed to XEmacLite_GetRxStatus,
* XEmacLite_mSetRxStatus changed to XEmacLite_SetRxStatus,
* XEmacLite_mIsTxDone changed to XEmacLite_IsTxDone and
* XEmacLite_mIsRxEmpty changed to XEmacLite_IsRxEmpty.
* </pre>
*
******************************************************************************/
#ifndef XEMAC_LITE_L_H /* prevent circular inclusions */
#define XEMAC_LITE_L_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/**
* Register offsets for the Ethernet MAC.
*/
#define XEL_TXBUFF_OFFSET (0x00000000) /**< Transmit Buffer */
#define XEL_MDIOADDR_OFFSET (XEL_TXBUFF_OFFSET + 0x07E4)/**< MDIO Address offset
register */
#define XEL_MDIOWR_OFFSET (XEL_TXBUFF_OFFSET + 0x07E8) /**< MDIO write data
register offset */
#define XEL_MDIORD_OFFSET (XEL_TXBUFF_OFFSET + 0x07EC) /**< MDIO read data
register offset*/
#define XEL_MDIOCNTR_OFFSET (XEL_TXBUFF_OFFSET + 0x07F0)/**< MDIO Control
Register offset */
#define XEL_GIER_OFFSET (XEL_TXBUFF_OFFSET + 0x07F8) /**< Offset for the GIE
Register */
#define XEL_TSR_OFFSET (XEL_TXBUFF_OFFSET + 0x07FC) /**< Tx status */
#define XEL_TPLR_OFFSET (XEL_TXBUFF_OFFSET + 0x07F4) /**< Tx packet length */
#define XEL_RXBUFF_OFFSET (0x00001000) /**< Receive Buffer */
#define XEL_RSR_OFFSET (XEL_RXBUFF_OFFSET + 0x07FC) /**< Rx status */
#define XEL_RPLR_OFFSET (XEL_RXBUFF_OFFSET + 0x0C) /**< Rx packet length */
#define XEL_MAC_HI_OFFSET (XEL_TXBUFF_OFFSET + 0x14) /**< MAC address hi
offset */
#define XEL_MAC_LO_OFFSET (XEL_TXBUFF_OFFSET) /**< MAC address lo
offset */
#define XEL_BUFFER_OFFSET (0x00000800) /**< Next buffer's
offset same for
both TX and RX */
/**
* MDIO Address/Write Data/Read Data Register Bit Masks
*/
#define XEL_MDIO_ADDRESS_MASK 0x00003E0 /**< PHY Address mask */
#define XEL_MDIO_ADDRESS_SHIFT 0x5 /**< PHY Address shift*/
#define XEL_MDIO_OP_MASK 0x00000400 /**< PHY read access */
/**
* MDIO Control Register Bit Masks
*/
#define XEL_MDIOCNTR_STATUS_MASK 0x00000001 /**< MDIO transfer in
Progress */
#define XEL_MDIOCNTR_ENABLE_MASK 0x00000008 /**< MDIO Enable */
/**
* Global Interrupt Enable Register (GIER) Bit Masks
*/
#define XEL_GIER_GIE_MASK 0x80000000 /**< Global Enable */
/**
* Transmit Status Register (TSR) Bit Masks
*/
#define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /**< Xmit complete */
#define XEL_TSR_PROGRAM_MASK 0x00000002 /**< Program the MAC
address */
#define XEL_TSR_XMIT_IE_MASK 0x00000008 /**< Xmit interrupt
enable bit */
#define XEL_TSR_LOOPBACK_MASK 0x00000010 /**< Loop back enable
bit */
#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /**< Buffer is active,
SW bit only. This
is not documented
in the HW spec */
/**
* define for programming the MAC address into the EmacLite
*/
#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
/**
* Receive Status Register (RSR)
*/
#define XEL_RSR_RECV_DONE_MASK 0x00000001 /**< Recv complete */
#define XEL_RSR_RECV_IE_MASK 0x00000008 /**< Recv interrupt
enable bit */
/**
* Transmit Packet Length Register (TPLR)
*/
#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00 /**< Transmit packet length
upper byte */
#define XEL_TPLR_LENGTH_MASK_LO 0x000000FF /**< Transmit packet length
lower byte */
/**
* Receive Packet Length Register (RPLR)
*/
#define XEL_RPLR_LENGTH_MASK_HI 0x0000FF00 /**< Receive packet length
upper byte */
#define XEL_RPLR_LENGTH_MASK_LO 0x000000FF /**< Receive packet length
lower byte */
#define XEL_HEADER_SIZE 14 /**< Size of header in bytes */
#define XEL_MTU_SIZE 1500 /**< Max size of data in frame */
#define XEL_FCS_SIZE 4 /**< Size of CRC */
#define XEL_HEADER_OFFSET 12 /**< Offset to length field */
#define XEL_HEADER_SHIFT 16 /**< Right shift value to align
length */
#define XEL_MAX_FRAME_SIZE (XEL_HEADER_SIZE+XEL_MTU_SIZE+ XEL_FCS_SIZE) /**< Max
length of Rx frame used if
length/type field
contains the type (> 1500) */
#define XEL_MAX_TX_FRAME_SIZE (XEL_HEADER_SIZE + XEL_MTU_SIZE) /**< Max
length of Tx frame */
#define XEL_MAC_ADDR_SIZE 6 /**< length of MAC address */
/*
* General Ethernet Definitions
*/
#define XEL_ETHER_PROTO_TYPE_IP 0x0800 /**< IP Protocol */
#define XEL_ETHER_PROTO_TYPE_ARP 0x0806 /**< ARP Protocol */
#define XEL_ETHER_PROTO_TYPE_VLAN 0x8100 /**< VLAN Tagged */
#define XEL_ARP_PACKET_SIZE 28 /**< Max ARP packet size */
#define XEL_HEADER_IP_LENGTH_OFFSET 16 /**< IP Length Offset */
#define XEL_VLAN_TAG_SIZE 4 /**< VLAN Tag Size */
/***************** Macros (Inline Functions) Definitions *********************/
#define XEmacLite_In32 Xil_In32
#define XEmacLite_Out32 Xil_Out32
/****************************************************************************/
/**
*
* Read from the specified EmacLite device register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to select the specific register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XEmacLite_ReadReg(u32 BaseAddress, u32 RegOffset);
*
******************************************************************************/
#define XEmacLite_ReadReg(BaseAddress, RegOffset) \
XEmacLite_In32((BaseAddress) + (RegOffset))
/***************************************************************************/
/**
*
* Write to the specified EmacLite device register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to select the specific register.
* @param RegisterValue is the value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XEmacLite_WriteReg(u32 BaseAddress, u32 RegOffset,
* u32 RegisterValue);
******************************************************************************/
#define XEmacLite_WriteReg(BaseAddress, RegOffset, RegisterValue) \
XEmacLite_Out32((BaseAddress) + (RegOffset), (RegisterValue))
/****************************************************************************/
/**
*
* Get the Tx Status Register Contents.
*
* @param BaseAddress is the base address of the device
*
* @return The contents of the Tx Status Register.
*
* @note C-Style signature:
* u32 XEmacLite_GetTxStatus(u32 BaseAddress)
*
*****************************************************************************/
#define XEmacLite_GetTxStatus(BaseAddress) \
(XEmacLite_ReadReg((BaseAddress), XEL_TSR_OFFSET))
/****************************************************************************/
/**
*
* Set the Tx Status Register Contents.
*
* @param BaseAddress is the base address of the device
* @param Data is the value to be written to the Register.
*
* @return None.
*
* @note C-Style signature:
* u32 XEmacLite_SetTxStatus(u32 BaseAddress, u32 Data)
*
*****************************************************************************/
#define XEmacLite_SetTxStatus(BaseAddress, Data) \
(XEmacLite_WriteReg((BaseAddress), XEL_TSR_OFFSET, (Data)))
/****************************************************************************/
/**
*
* Get the Rx Status Register Contents.
*
* @param BaseAddress is the base address of the device
*
* @return The contents of the Rx Status Register.
*
* @note C-Style signature:
* u32 XEmacLite_GetRxStatus(u32 BaseAddress)
*
*****************************************************************************/
#define XEmacLite_GetRxStatus(BaseAddress) \
(XEmacLite_ReadReg((BaseAddress), XEL_RSR_OFFSET))
/****************************************************************************/
/**
*
* Set the Rx Status Register Contents.
*
* @param BaseAddress is the base address of the device
* @param Data is the value to be written to the Register.
*
* @return None.
*
* @note C-Style signature:
* u32 XEmacLite_SetRxStatus(u32 BaseAddress, u32 Data)
*
*****************************************************************************/
#define XEmacLite_SetRxStatus(BaseAddress, Data) \
(XEmacLite_WriteReg((BaseAddress), XEL_RSR_OFFSET, (Data)))
/****************************************************************************/
/**
*
* Check to see if the transmission is complete.
*
* @param BaseAddress is the base address of the device
*
* @return TRUE if it is done, or FALSE if it is not.
*
* @note C-Style signature:
* int XEmacLite_IsTxDone(u32 BaseAddress)
*
*****************************************************************************/
#define XEmacLite_IsTxDone(BaseAddress) \
((XEmacLite_ReadReg((BaseAddress), XEL_TSR_OFFSET) & \
XEL_TSR_XMIT_BUSY_MASK) != XEL_TSR_XMIT_BUSY_MASK)
/****************************************************************************/
/**
*
* Check to see if the receive is empty.
*
* @param BaseAddress is the base address of the device
*
* @return TRUE if it is empty, or FALSE if it is not.
*
* @note C-Style signature:
* int XEmacLite_IsRxEmpty(u32 BaseAddress)
*
*****************************************************************************/
#define XEmacLite_IsRxEmpty(BaseAddress) \
((XEmacLite_ReadReg((BaseAddress), XEL_RSR_OFFSET) & \
XEL_RSR_RECV_DONE_MASK) != XEL_RSR_RECV_DONE_MASK)
/************************** Function Prototypes ******************************/
void XEmacLite_SendFrame(u32 BaseAddress, u8 *FramePtr, unsigned ByteCount);
u16 XEmacLite_RecvFrame(u32 BaseAddress, u8 *FramePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemaclite_selftest.c
*
* Function(s) in this file are the required functions for the EMAC Lite
* driver sefftest for the hardware.
* See xemaclite.h for a detailed description of the driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- --------------------------------------------------------
* 1.01a ecm 01/31/04 First release
* 1.11a mta 03/21/07 Updated to new coding style
* 3.00a ktn 10/22/09 Updated driver to use the HAL Processor APIs/macros.
* </pre>
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_io.h"
#include "xemaclite.h"
#include "xemaclite_i.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Performs a SelfTest on the EmacLite device as follows:
* - Writes to the mandatory TX buffer and reads back to verify.
* - If configured, writes to the secondary TX buffer and reads back to verify.
* - Writes to the mandatory RX buffer and reads back to verify.
* - If configured, writes to the secondary RX buffer and reads back to verify.
*
*
* @param InstancePtr is a pointer to the XEmacLite instance .
*
* @return
* - XST_SUCCESS if the device Passed the Self Test.
* - XST_FAILURE if any of the data read backs fail.
*
* @note None.
*
******************************************************************************/
int XEmacLite_SelfTest(XEmacLite * InstancePtr)
{
u32 BaseAddress;
u8 Index;
u8 TestString[4] = { 0xDE, 0xAD, 0xBE, 0xEF };
u8 ReturnString[4] = { 0x0, 0x0, 0x0, 0x0 };
/*
* Verify that each of the inputs are valid.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
/*
* Determine the TX buffer address
*/
BaseAddress = InstancePtr->EmacLiteConfig.BaseAddress +
XEL_TXBUFF_OFFSET;
/*
* Write the TestString to the TX buffer in EMAC Lite then
* back from the EMAC Lite and verify
*/
XEmacLite_AlignedWrite(TestString, (u32 *) BaseAddress,
sizeof(TestString));
XEmacLite_AlignedRead((u32 *) BaseAddress, ReturnString,
sizeof(ReturnString));
for (Index = 0; Index < 4; Index++) {
if (ReturnString[Index] != TestString[Index]) {
return XST_FAILURE;
}
/*
* Zero the return string for the next test
*/
ReturnString[Index] = 0;
}
/*
* If the second buffer is configured, test it also
*/
if (InstancePtr->EmacLiteConfig.TxPingPong != 0) {
BaseAddress += XEL_BUFFER_OFFSET;
/*
* Write the TestString to the optional TX buffer in EMAC Lite
* then back from the EMAC Lite and verify
*/
XEmacLite_AlignedWrite(TestString, (u32 *) BaseAddress,
sizeof(TestString));
XEmacLite_AlignedRead((u32 *) BaseAddress, ReturnString,
sizeof(ReturnString));
for (Index = 0; Index < 4; Index++) {
if (ReturnString[Index] != TestString[Index]) {
return XST_FAILURE;
}
/*
* Zero the return string for the next test
*/
ReturnString[Index] = 0;
}
}
/*
* Determine the RX buffer address
*/
BaseAddress = InstancePtr->EmacLiteConfig.BaseAddress +
XEL_RXBUFF_OFFSET;
/*
* Write the TestString to the RX buffer in EMAC Lite then
* back from the EMAC Lite and verify
*/
XEmacLite_AlignedWrite(TestString, (u32 *) (BaseAddress),
sizeof(TestString));
XEmacLite_AlignedRead((u32 *) (BaseAddress), ReturnString,
sizeof(ReturnString));
for (Index = 0; Index < 4; Index++) {
if (ReturnString[Index] != TestString[Index]) {
return XST_FAILURE;
}
/*
* Zero the return string for the next test
*/
ReturnString[Index] = 0;
}
/*
* If the second buffer is configured, test it also
*/
if (InstancePtr->EmacLiteConfig.RxPingPong != 0) {
BaseAddress += XEL_BUFFER_OFFSET;
/*
* Write the TestString to the optional RX buffer in EMAC Lite
* then back from the EMAC Lite and verify
*/
XEmacLite_AlignedWrite(TestString, (u32 *) BaseAddress,
sizeof(TestString));
XEmacLite_AlignedRead((u32 *) BaseAddress, ReturnString,
sizeof(ReturnString));
for (Index = 0; Index < 4; Index++) {
if (ReturnString[Index] != TestString[Index]) {
return XST_FAILURE;
}
/*
* Zero the return string for the next test
*/
ReturnString[Index] = 0;
}
}
return XST_SUCCESS;
}

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FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_sinit.c
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/******************************************************************************
*
* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemaclite_sinit.c
*
* This file contains the implementation of the XEmacLite driver's static
* initialization functionality.
*
* @note None.
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.12a sv 11/28/07 First release
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xemaclite.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern XEmacLite_Config XEmacLite_ConfigTable[];
/*****************************************************************************/
/**
*
* Lookup the device configuration based on the unique device ID. The table
* XEmacLite_ConfigTable contains the configuration info for each device in the
* system.
*
* @param DeviceId is the unique device ID of the device being looked up.
*
* @return A pointer to the configuration table entry corresponding to the
* given device ID, or NULL if no match is found.
*
* @note None.
*
******************************************************************************/
XEmacLite_Config *XEmacLite_LookupConfig(u16 DeviceId)
{
XEmacLite_Config *CfgPtr = NULL;
u32 Index;
for (Index = 0; Index < XPAR_XEMACLITE_NUM_INSTANCES; Index++) {
if (XEmacLite_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XEmacLite_ConfigTable[Index];
break;
}
}
return CfgPtr;
}
/*****************************************************************************/
/**
*
* Initialize a specific XEmacLite instance/driver. The initialization entails:
* - Initialize fields of the XEmacLite instance structure.
*
* The driver defaults to polled mode operation.
*
* @param InstancePtr is a pointer to the XEmacLite instance.
* @param DeviceId is the unique id of the device controlled by this
* XEmacLite instance. Passing in a device id associates the
* generic XEmacLite instance to a specific device, as chosen by
* the caller or application developer.
*
* @return
* - XST_SUCCESS if initialization was successful.
* - XST_DEVICE_NOT_FOUND/XST_FAILURE if device configuration
* information was not found for a device with the supplied
* device ID.
*
* @note None
*
******************************************************************************/
int XEmacLite_Initialize(XEmacLite *InstancePtr, u16 DeviceId)
{
int Status;
XEmacLite_Config *EmacLiteConfigPtr;/* Pointer to Configuration data. */
/*
* Verify that each of the inputs are valid.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
/*
* Lookup the device configuration in the configuration table. Use this
* configuration info down below when initializing this driver.
*/
EmacLiteConfigPtr = XEmacLite_LookupConfig(DeviceId);
if (EmacLiteConfigPtr == NULL) {
return XST_DEVICE_NOT_FOUND;
}
Status = XEmacLite_CfgInitialize(InstancePtr,
EmacLiteConfigPtr,
EmacLiteConfigPtr->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
}

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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=xgpio_l.h xgpio.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling gpio"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
make clean
include:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OUTS}

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FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio.c
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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio.c
*
* The implementation of the XGpio driver's basic functionality. See xgpio.h
* for more information about the driver.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 02/04/02 First release
* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
* 2.01a jvb 12/13/05 Changed Initialize() into CfgInitialize(), and made
* CfgInitialize() take a pointer to a config structure
* instead of a device id. Moved Initialize() into
* xgpio_sinit.c, and had Initialize() call CfgInitialize()
* after it retrieved the config structure using the device
* id. Removed include of xparameters.h along with any
* dependencies on xparameters.h and the _g.c config table.
* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the
* macros to remove _m from the name.
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xgpio.h"
#include "xstatus.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
* Initialize the XGpio instance provided by the caller based on the
* given configuration data.
*
* Nothing is done except to initialize the InstancePtr.
*
* @param InstancePtr is a pointer to an XGpio instance. The memory the
* pointer references must be pre-allocated by the caller. Further
* calls to manipulate the driver through the XGpio API must be
* made with this pointer.
* @param Config is a reference to a structure containing information
* about a specific GPIO device. This function initializes an
* InstancePtr object for a specific device specified by the
* contents of Config. This function can initialize multiple
* instance objects with the use of multiple calls giving different
* Config information on each call.
* @param EffectiveAddr is the device base address in the virtual memory
* address space. The caller is responsible for keeping the address
* mapping from EffectiveAddr to the device physical base address
* unchanged once this function is invoked. Unexpected errors may
* occur if the address mapping changes after this function is
* called. If address translation is not used, use
* Config->BaseAddress for this parameters, passing the physical
* address instead.
*
* @return
* - XST_SUCCESS Initialization was successfull.
*
* @note None.
*
*****************************************************************************/
int XGpio_CfgInitialize(XGpio * InstancePtr, XGpio_Config * Config,
u32 EffectiveAddr)
{
/*
* Assert arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
/*
* Set some default values.
*/
#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0)
InstancePtr->BaseAddress = ((EffectiveAddr >> 2)) & 0xFFF;
#else
InstancePtr->BaseAddress = EffectiveAddr;
#endif
InstancePtr->InterruptPresent = Config->InterruptPresent;
InstancePtr->IsDual = Config->IsDual;
/*
* Indicate the instance is now ready to use, initialized without error
*/
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return (XST_SUCCESS);
}
/****************************************************************************/
/**
* Set the input/output direction of all discrete signals for the specified
* GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
* @param DirectionMask is a bitmask specifying which discretes are input
* and which are output. Bits set to 0 are output and bits set to 1
* are input.
*
* @return None.
*
* @note The hardware must be built for dual channels if this function
* is used with any channel other than 1. If it is not, this
* function will assert.
*
*****************************************************************************/
void XGpio_SetDataDirection(XGpio * InstancePtr, unsigned Channel,
u32 DirectionMask)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((Channel == 1) ||
((Channel == 2) && (InstancePtr->IsDual == TRUE)));
XGpio_WriteReg(InstancePtr->BaseAddress,
((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET,
DirectionMask);
}
/****************************************************************************/
/**
* Get the input/output direction of all discrete signals for the specified
* GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
*
* @return Bitmask specifying which discretes are input and
* which are output. Bits set to 0 are output and bits set to 1 are
* input.
*
* @note
*
* The hardware must be built for dual channels if this function is used
* with any channel other than 1. If it is not, this function will assert.
*
*****************************************************************************/
u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid((Channel == 1) ||
((Channel == 2) &&
(InstancePtr->IsDual == TRUE)));
return XGpio_ReadReg(InstancePtr->BaseAddress,
((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET);
}
/****************************************************************************/
/**
* Read state of discretes for the specified GPIO channnel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
*
* @return Current copy of the discretes register.
*
* @note The hardware must be built for dual channels if this function
* is used with any channel other than 1. If it is not, this
* function will assert.
*
*****************************************************************************/
u32 XGpio_DiscreteRead(XGpio * InstancePtr, unsigned Channel)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid((Channel == 1) ||
((Channel == 2) && (InstancePtr->IsDual == TRUE)));
return XGpio_ReadReg(InstancePtr->BaseAddress,
((Channel - 1) * XGPIO_CHAN_OFFSET) +
XGPIO_DATA_OFFSET);
}
/****************************************************************************/
/**
* Write to discretes register for the specified GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
* @param Data is the value to be written to the discretes register.
*
* @return None.
*
* @note The hardware must be built for dual channels if this function
* is used with any channel other than 1. If it is not, this
* function will assert. See also XGpio_DiscreteSet() and
* XGpio_DiscreteClear().
*
*****************************************************************************/
void XGpio_DiscreteWrite(XGpio * InstancePtr, unsigned Channel, u32 Data)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((Channel == 1) ||
((Channel == 2) && (InstancePtr->IsDual == TRUE)));
XGpio_WriteReg(InstancePtr->BaseAddress,
((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET,
Data);
}

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio.h
*
* This file contains the software API definition of the Xilinx General Purpose
* I/O (XGpio) device driver.
*
* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and
* contains the following general features:
* - Support for up to 32 I/O discretes for each channel (64 bits total).
* - Each of the discretes can be configured for input or output.
* - Configurable support for dual channels and interrupt generation.
*
* The driver provides interrupt management functions. Implementation of
* interrupt handlers is left to the user. Refer to the provided interrupt
* example in the examples directory for details.
*
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, virtual
* memory, or cache control must be satisfied by the layer above this driver.
*
* <b>Initialization & Configuration</b>
*
* The XGpio_Config structure is used by the driver to configure itself. This
* configuration structure is typically created by the tool-chain based on HW
* build properties.
*
* To support multiple runtime loading and initialization strategies employed
* by various operating systems, the driver instance can be initialized in one
* of the following ways:
*
* - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own
* configuration structure created by the tool-chain based on an ID provided
* by the tool-chain.
*
* - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
* configuration structure provided by the caller. If running in a system
* with address translation, the provided virtual memory base address
* replaces the physical address present in the configuration structure.
*
* @note
*
* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
* the unused bits from registers are read as zero and written as don't cares.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 03/13/02 First release
* 2.00a jhl 11/26/03 Added support for dual channels and interrupts
* 2.01a jvb 12/14/05 I separated dependency on the static config table and
* xparameters.h from the driver initialization by moving
* _Initialize and _LookupConfig to _sinit.c. I also added
* the new _CfgInitialize routine.
* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
* to properly update the Interrupt Enable register
* 2.13a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
* file
* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
* Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and
* XGpio_mReadReg to XGpio_ReadReg. Removed the macros
* XGpio_mSetDataDirection, XGpio_mGetDataReg and
* XGpio_mSetDataReg. Users should use XGpio_WriteReg and
* XGpio_ReadReg to achieve the same functionality.
* 3.01a bss 04/18/13 Updated driver tcl to generate Canonical params in
* xparameters.h. CR#698589
* 4.0 adk 19/12/13 Updated as per the New Tcl API's
* </pre>
*****************************************************************************/
#ifndef XGPIO_H /* prevent circular inclusions */
#define XGPIO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xgpio_l.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /* Unique ID of device */
u32 BaseAddress; /* Device base address */
int InterruptPresent; /* Are interrupts supported in h/w */
int IsDual; /* Are 2 channels supported in h/w */
} XGpio_Config;
/**
* The XGpio driver instance data. The user is required to allocate a
* variable of this type for every GPIO device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
u32 BaseAddress; /* Device base address */
u32 IsReady; /* Device is initialized and ready */
int InterruptPresent; /* Are interrupts supported in h/w */
int IsDual; /* Are 2 channels supported in h/w */
} XGpio;
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Function Prototypes *****************************/
/*
* Initialization functions in xgpio_sinit.c
*/
int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId);
XGpio_Config *XGpio_LookupConfig(u16 DeviceId);
/*
* API Basic functions implemented in xgpio.c
*/
int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config,
u32 EffectiveAddr);
void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
u32 DirectionMask);
u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel);
u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask);
/*
* API Functions implemented in xgpio_extra.c
*/
void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask);
void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask);
/*
* API Functions implemented in xgpio_selftest.c
*/
int XGpio_SelfTest(XGpio *InstancePtr);
/*
* API Functions implemented in xgpio_intr.c
*/
void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask);
void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask);
void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask);
u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
u32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio_extra.c
*
* The implementation of the XGpio driver's advanced discrete functions.
* See xgpio.h for more information about the driver.
*
* @note
*
* These APIs can only be used if the GPIO_IO ports in the IP are used for
* connecting to the external output ports.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 02/04/02 First release
* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
* 2.11a mta 03/21/07 Updated to new coding style
* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros
* XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
* to XGpio_ReadReg.
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xgpio.h"
#include "xgpio_i.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
* Set output discrete(s) to logic 1 for the specified GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
* @param Mask is the set of bits that will be set to 1 in the discrete
* data register. All other bits in the data register are
* unaffected.
*
* @return None.
*
* @note
*
* The hardware must be built for dual channels if this function is used
* with any channel other than 1. If it is not, this function will assert.
*
* This API can only be used if the GPIO_IO ports in the IP are used for
* connecting to the external output ports.
*
*****************************************************************************/
void XGpio_DiscreteSet(XGpio * InstancePtr, unsigned Channel, u32 Mask)
{
u32 Current;
unsigned DataOffset;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((Channel == 1) ||
((Channel == 2) && (InstancePtr->IsDual == TRUE)));
/*
* Calculate the offset to the data register of the GPIO once
*/
DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
/*
* Read the contents of the data register, merge in Mask and write
* back results
*/
Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset);
Current |= Mask;
XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
}
/****************************************************************************/
/**
* Set output discrete(s) to logic 0 for the specified GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
* @param Mask is the set of bits that will be set to 0 in the discrete
* data register. All other bits in the data register are
* unaffected.
*
* @return None.
*
* @note
*
* The hardware must be built for dual channels if this function is used
* with any channel other than 1. If it is not, this function will assert.
*
* This API can only be used if the GPIO_IO ports in the IP are used for
* connecting to the external output ports.
*
*****************************************************************************/
void XGpio_DiscreteClear(XGpio * InstancePtr, unsigned Channel, u32 Mask)
{
u32 Current;
unsigned DataOffset;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((Channel == 1) ||
((Channel == 2) && (InstancePtr->IsDual == TRUE)));
/*
* Calculate the offset to the data register of the GPIO once
*/
DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
/*
* Read the contents of the data register, merge in Mask and write
* back results
*/
Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset);
Current &= ~Mask;
XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
}

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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xgpio.h"
/*
* The configuration table for devices
*/
XGpio_Config XGpio_ConfigTable[] =
{
{
XPAR_AXI_GPIO_0_DEVICE_ID,
XPAR_AXI_GPIO_0_BASEADDR,
XPAR_AXI_GPIO_0_INTERRUPT_PRESENT,
XPAR_AXI_GPIO_0_IS_DUAL
}
};

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************/
/**
* @file xgpio_i.h
*
* This header file contains internal identifiers, which are those shared
* between the files of the driver. It is intended for internal use only.
*
* NOTES:
*
* None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 03/13/02 First release
* 2.11a mta 03/21/07 Updated to new coding style
* </pre>
******************************************************************************/
#ifndef XGPIO_I_H /* prevent circular inclusions */
#define XGPIO_I_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xgpio.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions ****************************/
extern XGpio_Config XGpio_ConfigTable[];
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio_intr.c
*
* Implements GPIO interrupt processing functions for the XGpio driver.
* See xgpio.h for more information about the driver.
*
* The functions in this file require the hardware device to be built with
* interrupt capabilities. The functions will assert if called using hardware
* that does not have interrupt capabilities.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 2.00a jhl 11/26/03 Initial release
* 2.11a mta 03/21/07 Updated to new coding style
* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
* to properly update the Interrupt Enable register
* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros
* XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
* to XGpio_ReadReg.
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xgpio.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
* Enable the interrupt output signal. Interrupts enabled through
* XGpio_InterruptEnable() will not be passed through until the global enable
* bit is set by this function. This function is designed to allow all
* interrupts (both channels) to be enabled easily for exiting a critical
* section. This function will assert if the hardware device has not been
* built with interrupt capabilities.
*
* @param InstancePtr is the GPIO instance to operate on.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpio_InterruptGlobalEnable(XGpio * InstancePtr)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET,
XGPIO_GIE_GINTR_ENABLE_MASK);
}
/****************************************************************************/
/**
* Disable the interrupt output signal. Interrupts enabled through
* XGpio_InterruptEnable() will no longer be passed through until the global
* enable bit is set by XGpio_InterruptGlobalEnable(). This function is
* designed to allow all interrupts (both channels) to be disabled easily for
* entering a critical section. This function will assert if the hardware
* device has not been built with interrupt capabilities.
*
* @param InstancePtr is the GPIO instance to operate on.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpio_InterruptGlobalDisable(XGpio * InstancePtr)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET, 0x0);
}
/****************************************************************************/
/**
* Enable interrupts. The global interrupt must also be enabled by calling
* XGpio_InterruptGlobalEnable() for interrupts to occur. This function will
* assert if the hardware device has not been built with interrupt capabilities.
*
* @param InstancePtr is the GPIO instance to operate on.
* @param Mask is the mask to enable. Bit positions of 1 are enabled.
* This mask is formed by OR'ing bits from XGPIO_IR* bits which
* are contained in xgpio_l.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpio_InterruptEnable(XGpio * InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
/*
* Read the interrupt enable register and only enable the specified
* interrupts without disabling or enabling any others.
*/
Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
Register | Mask);
}
/****************************************************************************/
/**
* Disable interrupts. This function allows specific interrupts for each
* channel to be disabled. This function will assert if the hardware device
* has not been built with interrupt capabilities.
*
* @param InstancePtr is the GPIO instance to operate on.
* @param Mask is the mask to disable. Bits set to 1 are disabled. This
* mask is formed by OR'ing bits from XGPIO_IR* bits which are
* contained in xgpio_l.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpio_InterruptDisable(XGpio * InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
/*
* Read the interrupt enable register and only disable the specified
* interrupts without enabling or disabling any others.
*/
Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
Register & (~Mask));
}
/****************************************************************************/
/**
* Clear pending interrupts with the provided mask. This function should be
* called after the software has serviced the interrupts that are pending.
* This function will assert if the hardware device has not been built with
* interrupt capabilities.
*
* @param InstancePtr is the GPIO instance to operate on.
* @param Mask is the mask to clear pending interrupts for. Bit positions
* of 1 are cleared. This mask is formed by OR'ing bits from
* XGPIO_IR* bits which are contained in xgpio_l.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpio_InterruptClear(XGpio * InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
/*
* Read the interrupt status register and only clear the interrupts
* that are specified without affecting any others. Since the register
* is a toggle on write, make sure any bits to be written are already
* set.
*/
Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET,
Register & Mask);
}
/****************************************************************************/
/**
* Returns the interrupt enable mask. This function will assert if the
* hardware device has not been built with interrupt capabilities.
*
* @param InstancePtr is the GPIO instance to operate on.
*
* @return A mask of bits made from XGPIO_IR* bits which are contained in
* xgpio_l.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
u32 XGpio_InterruptGetEnabled(XGpio * InstancePtr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
}
/****************************************************************************/
/**
* Returns the status of interrupt signals. Any bit in the mask set to 1
* indicates that the channel associated with the bit has asserted an interrupt
* condition. This function will assert if the hardware device has not been
* built with interrupt capabilities.
*
* @param InstancePtr is the GPIO instance to operate on.
*
* @return A pointer to a mask of bits made from XGPIO_IR* bits which are
* contained in xgpio_l.h.
*
* @note
*
* The interrupt status indicates the status of the device irregardless if
* the interrupts from the devices have been enabled or not through
* XGpio_InterruptEnable().
*
*****************************************************************************/
u32 XGpio_InterruptGetStatus(XGpio * InstancePtr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
}

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpio_l.h
*
* This header file contains identifiers and driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
*
* The macros that are available in this file use a multiply to calculate the
* addresses of registers. The user can control whether that multiply is done
* at run time or at compile time. A constant passed as the channel parameter
* will cause the multiply to be done at compile time. A variable passed as the
* channel parameter will cause it to occur at run time.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a jhl 04/24/02 First release of low level driver
* 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This
* change required the functions to be changed such that
* the interface is not compatible with previous versions.
* See the examples in the example directory for macros
* to help compile an application that was designed for
* previous versions of the driver. The interrupt registers
* are accessible using the ReadReg and WriteReg macros and
* a channel parameter was added to the other macros.
* 2.11a mta 03/21/07 Updated to new coding style
* 2.12a sv 11/21/07 Updated driver to support access through DCR bus.
* 3.00a sv 11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
* XGpio_mReadReg to XGpio_ReadReg.
* Removed the macros XGpio_mSetDataDirection,
* XGpio_mGetDataReg and XGpio_mSetDataReg. Users
* should use XGpio_WriteReg/XGpio_ReadReg to achieve the
* same functionality.
* </pre>
*
******************************************************************************/
#ifndef XGPIO_L_H /* prevent circular inclusions */
#define XGPIO_L_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/*
* XPAR_XGPIO_USE_DCR_BRIDGE has to be set to 1 if the GPIO device is
* accessed through a DCR bus connected to a bridge
*/
#define XPAR_XGPIO_USE_DCR_BRIDGE 0
#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0)
#include "xio_dcr.h"
#endif
/************************** Constant Definitions *****************************/
/** @name Registers
*
* Register offsets for this device.
* @{
*/
#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0)
#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
#define XGPIO_TRI_OFFSET 0x1 /**< I/O direction reg for 1st channel */
#define XGPIO_DATA2_OFFSET 0x2 /**< Data register for 2nd channel */
#define XGPIO_TRI2_OFFSET 0x3 /**< I/O direction reg for 2nd channel */
#define XGPIO_GIE_OFFSET 0x47 /**< Global interrupt enable register */
#define XGPIO_ISR_OFFSET 0x48 /**< Interrupt status register */
#define XGPIO_IER_OFFSET 0x4A /**< Interrupt enable register */
#else
#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */
#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
#define XGPIO_TRI2_OFFSET 0xC /**< I/O direction reg for 2nd channel */
#define XGPIO_GIE_OFFSET 0x11C /**< Glogal interrupt enable register */
#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
#endif
/* @} */
/* The following constant describes the offset of each channels data and
* tristate register from the base address.
*/
#define XGPIO_CHAN_OFFSET 8
/** @name Interrupt Status and Enable Register bitmaps and masks
*
* Bit definitions for the interrupt status register and interrupt enable
* registers.
* @{
*/
#define XGPIO_IR_MASK 0x3 /**< Mask of all bits */
#define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */
#define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */
/*@}*/
/** @name Global Interrupt Enable Register bitmaps and masks
*
* Bit definitions for the Global Interrupt Enable register
* @{
*/
#define XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*
* Define the appropriate I/O access method to memory mapped I/O or DCR.
*/
#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0)
#define XGpio_In32 XIo_DcrIn
#define XGpio_Out32 XIo_DcrOut
#else
#define XGpio_In32 Xil_In32
#define XGpio_Out32 Xil_Out32
#endif
/****************************************************************************/
/**
*
* Write a value to a GPIO register. A 32 bit write is performed. If the
* GPIO core is implemented in a smaller width, only the least significant data
* is written.
*
* @param BaseAddress is the base address of the GPIO device.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note C-style signature:
* void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
****************************************************************************/
#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
/****************************************************************************/
/**
*
* Read a value from a GPIO register. A 32 bit read is performed. If the
* GPIO core is implemented in a smaller width, only the least
* significant data is read from the register. The most significant data
* will be read as 0.
*
* @param BaseAddress is the base address of the GPIO device.
* @param RegOffset is the register offset from the base to read from.
*
* @return Data read from the register.
*
* @note C-style signature:
* u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
*
****************************************************************************/
#define XGpio_ReadReg(BaseAddress, RegOffset) \
XGpio_In32((BaseAddress) + (RegOffset))
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio_selftest.c
*
* The implementation of the XGpio driver's self test function.
* See xgpio.h for more information about the driver.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 02/04/02 First release
* 2.00a jhl 01/13/04 Addition of dual channels and interrupts.
* 2.11a mta 03/21/07 Updated to new coding style
* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xgpio.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/******************************************************************************/
/**
* Run a self-test on the driver/device. This function does a minimal test
* in which the data register is read. It only does a read without any kind
* of test because the hardware has been parameterized such that it may be only
* an input such that the state of the inputs won't be known.
*
* All other hardware features of the device are not guaranteed to be in the
* hardware since they are parameterizable.
*
*
* @param InstancePtr is a pointer to the XGpio instance to be worked on.
* This parameter must have been previously initialized with
* XGpio_Initialize().
*
* @return XST_SUCCESS always. If the GPIO device was not present in the
* hardware a bus error could be generated. Other indicators of a
* bus error, such as registers in bridges or buses, may be
* necessary to determine if this function caused a bus error.
*
* @note None.
*
******************************************************************************/
int XGpio_SelfTest(XGpio * InstancePtr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Read from the data register of channel 1 which is always guaranteed
* to be in the hardware device. Since the data may be configured as
* all inputs, there is not way to guarantee the value read so don't
* test it.
*/
(void) XGpio_DiscreteRead(InstancePtr, 1);
return (XST_SUCCESS);
}

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/******************************************************************************
*
* Copyright (C) 2003 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio_sinit.c
*
* The implementation of the XGpio driver's static initialzation
* functionality.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 2.01a jvb 10/13/05 First release
* 2.11a mta 03/21/07 Updated to new coding style
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xstatus.h"
#include "xparameters.h"
#include "xgpio_i.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/******************************************************************************/
/**
* Lookup the device configuration based on the unique device ID. The table
* ConfigTable contains the configuration info for each device in the system.
*
* @param DeviceId is the device identifier to lookup.
*
* @return
* - A pointer of data type XGpio_Config which points to the
* device configuration if DeviceID is found.
* - NULL if DeviceID is not found.
*
* @note None.
*
******************************************************************************/
XGpio_Config *XGpio_LookupConfig(u16 DeviceId)
{
XGpio_Config *CfgPtr = NULL;
int Index;
for (Index = 0; Index < XPAR_XGPIO_NUM_INSTANCES; Index++) {
if (XGpio_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XGpio_ConfigTable[Index];
break;
}
}
return CfgPtr;
}
/****************************************************************************/
/**
* Initialize the XGpio instance provided by the caller based on the
* given DeviceID.
*
* Nothing is done except to initialize the InstancePtr.
*
* @param InstancePtr is a pointer to an XGpio instance. The memory the
* pointer references must be pre-allocated by the caller. Further
* calls to manipulate the instance/driver through the XGpio API
* must be made with this pointer.
* @param DeviceId is the unique id of the device controlled by this XGpio
* instance. Passing in a device id associates the generic XGpio
* instance to a specific device, as chosen by the caller or
* application developer.
*
* @return
* - XST_SUCCESS if the initialization was successfull.
* - XST_DEVICE_NOT_FOUND if the device configuration data was not
* found for a device with the supplied device ID.
*
* @note None.
*
*****************************************************************************/
int XGpio_Initialize(XGpio * InstancePtr, u16 DeviceId)
{
XGpio_Config *ConfigPtr;
/*
* Assert arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
/*
* Lookup configuration data in the device configuration table.
* Use this configuration info down below when initializing this
* driver.
*/
ConfigPtr = XGpio_LookupConfig(DeviceId);
if (ConfigPtr == (XGpio_Config *) NULL) {
InstancePtr->IsReady = 0;
return (XST_DEVICE_NOT_FOUND);
}
return XGpio_CfgInitialize(InstancePtr, ConfigPtr,
ConfigPtr->BaseAddress);
}

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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
LEVEL=0
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling intc"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OUTS}

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc.h
*
* The Xilinx interrupt controller driver component. This component supports the
* Xilinx interrupt controller.
*
* The interrupt controller driver uses the idea of priority for the various
* handlers. Priority is an integer within the range of 0 and 31 inclusive with
* 0 being the highest priority interrupt source.
*
* The Xilinx interrupt controller supports the following features:
*
* - specific individual interrupt enabling/disabling
* - specific individual interrupt acknowledging
* - attaching specific callback function to handle interrupt source
* - master enable/disable
* - single callback per interrupt or all pending interrupts handled for
* each interrupt of the processor
*
* The acknowledgement of the interrupt within the interrupt controller is
* selectable, either prior to the device's handler being called or after
* the handler is called. This is necessary to support interrupt signal inputs
* which are either edge or level signals. Edge driven interrupt signals
* require that the interrupt is acknowledged prior to the interrupt being
* serviced in order to prevent the loss of interrupts which are occurring
* extremely close together. A level driven interrupt input signal requires
* the interrupt to acknowledged after servicing the interrupt to ensure that
* the interrupt only generates a single interrupt condition.
*
* Details about connecting the interrupt handler of the driver are contained
* in the source file specific to interrupt processing, xintc_intr.c.
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads
* or thread mutual exclusion, virtual memory, or cache control must be
* satisfied by the layer above this driver.
*
* <b>Interrupt Vector Tables</b>
*
* The interrupt vector table for each interrupt controller device is declared
* statically in xintc_g.c within the configuration data for each instance.
* The device ID of the interrupt controller device is used by the driver as a
* direct index into the configuration data table - to retrieve the vector table
* for an instance of the interrupt controller. The user should populate the
* vector table with handlers and callbacks at run-time using the XIntc_Connect()
* and XIntc_Disconnect() functions.
*
* Each vector table entry corresponds to a device that can generate an
* interrupt. Each entry contains an interrupt handler function and an argument
* to be passed to the handler when an interrupt occurs. The tools default this
* argument to the base address of the interrupting device. Note that the
* device driver interrupt handlers given in this file do not take a base
* address as an argument, but instead take a pointer to the driver instance.
* This means that although the table is created statically, the user must still
* use XIntc_Connect() when the interrupt handler takes an argument other than
* the base address. This is only to say that the existence of the static vector
* tables should not mislead the user into thinking they no longer need to
* register/connect interrupt handlers with this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 08/16/01 First release
* 1.00a rpm 01/09/02 Removed the AckLocation argument from XIntc_Connect().
* This information is now internal in xintc_g.c.
* 1.00b jhl 02/13/02 Repartitioned the driver for smaller files
* 1.00b jhl 04/24/02 Made LookupConfig function global and relocated config
* data type
* 1.00c rpm 10/17/03 New release. Support the static vector table created
* in the xintc_g.c configuration table. Moved vector
* table and options out of instance structure and into
* the configuration table.
* 1.10c mta 03/21/07 Updated to new coding style
* 1.11a sv 11/21/07 Updated driver to support access through a DCR bridge
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs and _m is removed from
* all the macro names/definitions.
* 2.01a sdm 04/27/10 Updated the tcl so that the defintions are generated in
* the xparameters.h to know whether the optional registers
* SIE, CIE and IVR are enabled in the HW - Refer CR 555392.
* This driver doesnot make use of these definitions and does
* not use the optional registers.
* 2.03a hvm 05/24/11 Updated the tcl to generate vector Ids for external
* interrupts. CR565336
* 2.04a bss 01/13/12 Added XIntc_ConnectFastHandler API for Fast Interrupt
* and XIntc_SetNormalIntrMode for setting to normal
* interrupt mode.
* 2.04a asa 03/19/12 Changed the XIntc_Config struct. The order of entries
* declared in the structure now matches with the
* XIntc_ConfigTable generated by the driver tcl.
* 2.05a bss 08/16/12 Updated to support relocatable vectors in Microblaze,
* added IntVectorAddr to XIntc_Config for this.
* Added XIntc_RegisterFastHandler API to register fast
* interrupt handlers using base address.
* 2.06a bss 01/28/13 To support Cascade mode:
* Added XIN_INTC_NOCASCADE,XIN_INTC_PRIMARY,
* XIN_INTC_SECONDARY,XIN_INTC_LAST and
* XIN_CONTROLLER_MAX_INTRS macros
* Added NumberofIntrs and IntcType fields in XIntc_Config
* structure.
* Modified XIntc_Initialize,XIntc_Start,XIntc_Connect
* XIntc_Disconnect,XIntc_Enable,XIntc_Disable,
* XIntc_Acknowledge,XIntc_ConnectFastHandler and
* XIntc_SetNormalIntrMode APIs.Added XIntc_InitializeSlaves
* API in xintc.c
* Modified XIntc_DeviceInterruptHandler,
* XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
* XIntc_RegisterFastHandler APIs.Added XIntc_CascadeHandler
* API in xintc_l.c.
* Modified XIntc_SetOptions API in xintc_options.c.
* Modified XIntc_SimulateIntr API in xintc_selftest.c.
* Modified driver tcl:
* to check for Cascade mode and generate XPAR_INTC_TYPE
* for each controller.
* Generate XPAR_INTC_MAX_NUM_INTR_INPUTS by adding all
* interrupt sources of all Controllers in Cascade mode.
* 2.07a bss 10/18/13 To support Nested interrupts:
* Modified XIntc_DeviceInterruptHandler API.
* Added XIN_ILR_OFFSET macro in xintc_l.h.
* Modified driver tcl to generate HAS_ILR parameter in
* xparameters.h
* 3.0 bss 01/28/13 Modified xintc.c to initialize IVAR register with
* XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
* CR#765931.
* Modified driver tcl to generate XPAR_AXI_INTC_0_TYPE
* correctly(CR#764865).
*
* @note
* For Cascade mode, Interrupt IDs are generated in xparameters.h
* as shown below:
*
* Master/Primary INTC
* ______
* | |-0 Secondary INTC
* | |-. ______
* | |-. | |-32 Last INTC
* | |-. | |-. ______
* |______|<-31------| |-. | |-64
* | |-. | |-.
* |______|<-63-------| |-.
* | |-.
* |______|-95
*
* All driver functions has to be called using DeviceId/
* InstancePtr/BaseAddress of Primary/Master Controller and
* Interrupts IDs generated in xparameters.h only.
* Driver functions takes care of Slave Controllers based on
* Interrupt ID passed. User must not use Interrupt source/ID
* 31 of Primary and Secondary controllers to call driver
* functions.
*
* For nested interrupts, XIntc_DeviceInterruptHandler saves
* microblaze r14 register on entry and restores on exit. This is
* required since compiler does not support nesting. It enables
* Microblaze interrupts after blocking further interrupts from
* the current interrupt number and interrupts below current
* interrupt proirity by writing to Interrupt Level Register of
* INTC on entry. On exit, it disables microblaze interrupts and
* restores ILR register default value(0xFFFFFFFF)back. It is
* recommended to increase STACK_SIZE in linker script for nested
* interrupts.
* 3.0 adk 12/10/13 Updated as per the New Tcl API's
* 3.0 adk 17/02/14 Fixed the CR:771287 Changes are made in the intc
* driver tcl.
* 3.1 adk 8/4/14 Fixed the CR:783248 Changes are made in
* the test-app tcl
* 3.2 bss 4/8/14 Fixed driver tcl to handle external interrupt pins
* correctly (CR#799609).
*
* </pre>
*
******************************************************************************/
#ifndef XINTC_H /* prevent circular inclusions */
#define XINTC_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xparameters.h"
#include "xstatus.h"
#include "xintc_l.h"
/************************** Constant Definitions *****************************/
/**
* @name Configuration options
* These options are used in XIntc_SetOptions() to configure the device.
* @{
*/
/**
* <pre>
* XIN_SVC_SGL_ISR_OPTION Service the highest priority pending interrupt
* and then return.
* XIN_SVC_ALL_ISRS_OPTION Service all of the pending interrupts and then
* return.
* </pre>
*/
#define XIN_SVC_SGL_ISR_OPTION 1UL
#define XIN_SVC_ALL_ISRS_OPTION 2UL
/*@}*/
/**
* @name Start modes
* One of these values is passed to XIntc_Start() to start the device.
* @{
*/
/** Simulation only mode, no hardware interrupts recognized */
#define XIN_SIMULATION_MODE 0
/** Real mode, no simulation allowed, hardware interrupts recognized */
#define XIN_REAL_MODE 1
/*@}*/
/**
* @name Masks to specify Interrupt Controller Mode
* @{
*/
#define XIN_INTC_NOCASCADE 0 /* Normal - No Cascade Mode */
#define XIN_INTC_PRIMARY 1 /* Master/Primary controller */
#define XIN_INTC_SECONDARY 2 /* Secondary Slave Controllers */
#define XIN_INTC_LAST 3 /* Last Slave Controller */
/*@}*/
/**
* @name Mask to specify maximum number of interrupt sources per controller
* @{
*/
#define XIN_CONTROLLER_MAX_INTRS 32 /* Each Controller has 32
interrupt pins */
/*@}*/
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Register base address */
u32 AckBeforeService; /**< Ack location per interrupt */
int FastIntr; /**< Fast Interrupt enabled */
u32 IntVectorAddr; /**< Interrupt Vector Address */
int NumberofIntrs; /**< Number of Interrupt sources */
u32 Options; /**< Device options */
int IntcType; /**< Intc type 0 - No Cascade Mode
1 - primary instance
2 - secondary instance
3 - last instance */
/** Static vector table of interrupt handlers */
#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
XIntc_VectorTableEntry HandlerTable[XIN_CONTROLLER_MAX_INTRS];
#else
XIntc_VectorTableEntry HandlerTable[XPAR_INTC_MAX_NUM_INTR_INPUTS];
#endif
} XIntc_Config;
/**
* The XIntc driver instance data. The user is required to allocate a
* variable of this type for every intc device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
u32 BaseAddress; /**< Base address of registers */
u32 IsReady; /**< Device is initialized and ready */
u32 IsStarted; /**< Device has been started */
u32 UnhandledInterrupts; /**< Intc Statistics */
XIntc_Config *CfgPtr; /**< Pointer to instance config entry */
} XIntc;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*
* Required functions in xintc.c
*/
int XIntc_Initialize(XIntc * InstancePtr, u16 DeviceId);
int XIntc_Start(XIntc * InstancePtr, u8 Mode);
void XIntc_Stop(XIntc * InstancePtr);
int XIntc_Connect(XIntc * InstancePtr, u8 Id,
XInterruptHandler Handler, void *CallBackRef);
void XIntc_Disconnect(XIntc * InstancePtr, u8 Id);
void XIntc_Enable(XIntc * InstancePtr, u8 Id);
void XIntc_Disable(XIntc * InstancePtr, u8 Id);
void XIntc_Acknowledge(XIntc * InstancePtr, u8 Id);
XIntc_Config *XIntc_LookupConfig(u16 DeviceId);
int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id,
XFastInterruptHandler Handler);
void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id);
/*
* Interrupt functions in xintr_intr.c
*/
void XIntc_VoidInterruptHandler(void);
void XIntc_InterruptHandler(XIntc * InstancePtr);
/*
* Options functions in xintc_options.c
*/
int XIntc_SetOptions(XIntc * InstancePtr, u32 Options);
u32 XIntc_GetOptions(XIntc * InstancePtr);
/*
* Self-test functions in xintc_selftest.c
*/
int XIntc_SelfTest(XIntc * InstancePtr);
int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xintc.h"
extern void XNullHandler (void *);
/*
* The configuration table for devices
*/
XIntc_Config XIntc_ConfigTable[] =
{
{
XPAR_AXI_INTC_0_DEVICE_ID,
XPAR_AXI_INTC_0_BASEADDR,
XPAR_AXI_INTC_0_KIND_OF_INTR,
XPAR_AXI_INTC_0_HAS_FAST,
XPAR_AXI_INTC_0_IVAR_RESET_VALUE,
XPAR_AXI_INTC_0_NUM_INTR_INPUTS,
XIN_SVC_SGL_ISR_OPTION,
XPAR_AXI_INTC_0_TYPE,
{
{
XNullHandler,
(void *) XNULL
},
{
XNullHandler,
(void *) XNULL
},
{
XNullHandler,
(void *) XNULL
}
}
}
};

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_i.h
*
* This file contains data which is shared between files and internal to the
* XIntc component. It is intended for internal use only.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00b jhl 02/06/02 First release
* 1.00b jhl 04/24/02 Moved register definitions to xintc_l.h
* 1.00c rpm 10/17/03 New release. Removed extern of global, single instance
* pointer.
* 1.10c mta 03/21/07 Updated to new coding style
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs.
* </pre>
*
******************************************************************************/
#ifndef XINTC_I_H /* prevent circular inclusions */
#define XINTC_I_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xintc.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern u32 XIntc_BitPosMask[];
extern XIntc_Config XIntc_ConfigTable[];
#ifdef __cplusplus
}
#endif
#endif

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_intr.c
*
* This file contains the interrupt processing for the XIntc component which
* is the driver for the Xilinx Interrupt Controller. The interrupt
* processing is partitioned seperately such that users are not required to
* use the provided interrupt processing. This file requires other files of
* the driver to be linked in also.
*
* Two different interrupt handlers are provided for this driver such that the
* user must select the appropriate handler for the application. The first
* interrupt handler, XIntc_VoidInterruptHandler, is provided for systems
* which use only a single interrupt controller or for systems that cannot
* otherwise provide an argument to the XIntc interrupt handler (e.g., the RTOS
* interrupt vector handler may not provide such a facility). The constant
* XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler to be included in
* the driver. The second interrupt handler, XIntc_InterruptHandler, uses an
* input argument which is an instance pointer to an interrupt controller driver
* such that multiple interrupt controllers can be supported. This handler
* requires the calling function to pass it the appropriate argument, so another
* level of indirection may be required.
*
* Note that both of these handlers are now only provided for backward
* compatibility. The handler defined in xintc_l.c is the recommended handler.
*
* The interrupt processing may be used by connecting one of the interrupt
* handlers to the interrupt system. These handlers do not save and restore
* the processor context but only handle the processing of the Interrupt
* Controller. The two handlers are provided as working examples. The user is
* encouraged to supply their own interrupt handler when performance tuning is
* deemed necessary.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.00b jhl 02/13/02 First release
* 1.00c rpm 10/17/03 New release. Support the static vector table created
* in the xintc_g.c configuration table. Collapse handlers
* to use the XIntc_DeviceInterruptHandler() in xintc_l.c.
* 1.00c rpm 04/09/04 Added conditional compilation around the old handler
* XIntc_VoidInterruptHandler(). This handler will only be
* include/compiled if XPAR_INTC_SINGLE_DEVICE_ID is defined.
* 1.10c mta 03/21/07 Updated to new coding style
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs.
*
* </pre>
*
* @internal
*
* This driver assumes that the context of the processor has been saved prior to
* the calling of the Interrupt Controller interrupt handler and then restored
* after the handler returns. This requires either the running RTOS to save the
* state of the machine or that a wrapper be used as the destination of the
* interrupt vector to save the state of the processor and restore the state
* after the interrupt handler returns.
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xparameters.h"
#include "xintc.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Interrupt handler for the driver used when there can be no argument passed
* to the handler. This function is provided mostly for backward compatibility.
* The user should use XIntc_DeviceInterruptHandler(), defined in xintc_l.c,
* if possible.
*
* The user must connect this function to the interrupt system such that it is
* called whenever the devices which are connected to it cause an interrupt.
*
* @return None.
*
* @note
*
* The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler
* to be included in the driver compilation.
*
******************************************************************************/
#ifdef XPAR_INTC_SINGLE_DEVICE_ID
void XIntc_VoidInterruptHandler(void)
{
/* Use the single instance to call the main interrupt handler */
XIntc_DeviceInterruptHandler((void *) XPAR_INTC_SINGLE_DEVICE_ID);
}
#endif
/*****************************************************************************/
/**
*
* The interrupt handler for the driver. This function is provided mostly for
* backward compatibility. The user should use XIntc_DeviceInterruptHandler(),
* defined in xintc_l.c when possible and pass the device ID of the interrupt
* controller device as its argument.
*
* The user must connect this function to the interrupt system such that it is
* called whenever the devices which are connected to it cause an interrupt.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIntc_InterruptHandler(XIntc * InstancePtr)
{
/* Assert that the pointer to the instance is valid
*/
Xil_AssertVoid(InstancePtr != NULL);
/* Use the instance's device ID to call the main interrupt handler.
* (the casts are to avoid a compiler warning)
*/
XIntc_DeviceInterruptHandler((void *)
((u32) (InstancePtr->CfgPtr->DeviceId)));
}

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_l.c
*
* This file contains low-level driver functions that can be used to access the
* device. The user should refer to the hardware device specification for more
* details of the device operation.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00b jhl 04/24/02 First release
* 1.00c rpm 10/17/03 New release. Support the static vector table created
* in the xintc_g.c configuration table.
* 1.00c rpm 04/09/04 Added conditional compilation around the old handler
* XIntc_LowLevelInterruptHandler(). This handler will only
* be include/compiled if XPAR_INTC_SINGLE_DEVICE_ID is
* defined.
* 1.10c mta 03/21/07 Updated to new coding style
* 1.10c ecm 07/09/07 Read the ISR after the Acknowledge in the interrupt
* handler to support architectures with posted write bus
* access issues.
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs and _m is removed
* from all the macro definitions.
* 2.04a bss 01/13/12 Removed the unused Register variable for warnings.
* 2.05a bss 08/18/12 Added XIntc_RegisterFastHandler API to register fast
* interrupt handlers using base address.
* 2.06a bss 01/28/13 To support Cascade mode:
* Modified XIntc_DeviceInterruptHandler,
* XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
* XIntc_RegisterFastHandler APIs.
* Added XIntc_CascadeHandler API.
* 2.07a bss 10/18/13 Modified XIntc_DeviceInterruptHandler to support
* nested interrupts.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xintc.h"
#include "xintc_i.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static XIntc_Config *LookupConfigByBaseAddress(u32 BaseAddress);
#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
static void XIntc_CascadeHandler(void *DeviceId);
#endif
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* This is the interrupt handler for the driver interface provided in this file
* when there can be no argument passed to the handler. In this case, we just
* use the globally defined device ID for the interrupt controller. This function
* is provided mostly for backward compatibility. The user should use
* XIntc_DeviceInterruptHandler() if possible.
*
* This function does not support multiple interrupt controller instances to be
* handled.
*
* The user must connect this function to the interrupt system such that it is
* called whenever the devices which are connected to it cause an interrupt.
*
* @return None.
*
* @note
*
* The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler
* to be included in the driver compilation.
*
******************************************************************************/
#ifdef XPAR_INTC_SINGLE_DEVICE_ID
void XIntc_LowLevelInterruptHandler(void)
{
/*
* A level of indirection here because the interrupt handler used with
* the driver interface given in this file needs to remain void - no
* arguments. So we need the globally defined device ID of THE
* interrupt controller.
*/
XIntc_DeviceInterruptHandler((void *) XPAR_INTC_SINGLE_DEVICE_ID);
}
#endif
/*****************************************************************************/
/**
*
* This function is the primary interrupt handler for the driver. It must be
* connected to the interrupt source such that is called when an interrupt of
* the interrupt controller is active. It will resolve which interrupts are
* active and enabled and call the appropriate interrupt handler. It uses
* the AckBeforeService flag in the configuration data to determine when to
* acknowledge the interrupt. Highest priority interrupts are serviced first.
* This function assumes that an interrupt vector table has been previously
* initialized.It does not verify that entries in the table are valid before
* calling an interrupt handler. In Cascade mode this function calls
* XIntc_CascadeHandler to handle interrupts of Master and Slave controllers.
* This functions also handles interrupts nesting by saving and restoring link
* register of Microblaze and Interrupt Level register of interrupt controller
* properly.
* @param DeviceId is the zero-based device ID defined in xparameters.h
* of the interrupting interrupt controller. It is used as a direct
* index into the configuration data, which contains the vector
* table for the interrupt controller. Note that even though the
* argument is a void pointer, the value is not a pointer but the
* actual device ID. The void pointer type is necessary to meet
* the XInterruptHandler typedef for interrupt handlers.
*
* @return None.
*
* @note For nested interrupts, this function saves microblaze r14
* register on entry and restores on exit. This is required since
* compiler does not support nesting. This function enables
* Microblaze interrupts after blocking further interrupts
* from the current interrupt number and interrupts below current
* interrupt proirity by writing to Interrupt Level Register of
* INTC on entry. On exit, it disables microblaze interrupts and
* restores ILR register default value(0xFFFFFFFF)back. It is
* recommended to increase STACK_SIZE in linker script for nested
* interrupts.
*
******************************************************************************/
void XIntc_DeviceInterruptHandler(void *DeviceId)
{
u32 IntrStatus;
u32 IntrMask = 1;
int IntrNumber;
XIntc_Config *CfgPtr;
u32 Imr;
/* Get the configuration data using the device ID */
CfgPtr = &XIntc_ConfigTable[(u32)DeviceId];
#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
if (CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
XIntc_CascadeHandler(DeviceId);
}
else
#endif
{ /* This extra brace is required for compilation in Cascade Mode */
#if XPAR_XINTC_HAS_ILR == TRUE
#ifdef __MICROBLAZE__
volatile u32 R14_register;
/* Save r14 register */
R14_register = mfgpr(r14);
#endif
volatile u32 ILR_reg;
/* Save ILR register */
ILR_reg = Xil_In32(CfgPtr->BaseAddress + XIN_ILR_OFFSET);
#endif
/* Get the interrupts that are waiting to be serviced */
IntrStatus = XIntc_GetIntrStatus(CfgPtr->BaseAddress);
/* Mask the Fast Interrupts */
if (CfgPtr->FastIntr == TRUE) {
Imr = XIntc_In32(CfgPtr->BaseAddress + XIN_IMR_OFFSET);
IntrStatus &= ~Imr;
}
/* Service each interrupt that is active and enabled by
* checking each bit in the register from LSB to MSB which
* corresponds to an interrupt input signal
*/
for (IntrNumber = 0; IntrNumber < CfgPtr->NumberofIntrs;
IntrNumber++) {
if (IntrStatus & 1) {
XIntc_VectorTableEntry *TablePtr;
#if XPAR_XINTC_HAS_ILR == TRUE
/* Write to ILR the current interrupt
* number
*/
Xil_Out32(CfgPtr->BaseAddress +
XIN_ILR_OFFSET, IntrNumber);
/* Read back ILR to ensure the value
* has been updated and it is safe to
* enable interrupts
*/
Xil_In32(CfgPtr->BaseAddress +
XIN_ILR_OFFSET);
/* Enable interrupts */
Xil_ExceptionEnable();
#endif
/* If the interrupt has been setup to
* acknowledge it before servicing the
* interrupt, then ack it */
if (CfgPtr->AckBeforeService & IntrMask) {
XIntc_AckIntr(CfgPtr->BaseAddress,
IntrMask);
}
/* The interrupt is active and enabled, call
* the interrupt handler that was setup with
* the specified parameter
*/
TablePtr = &(CfgPtr->HandlerTable[IntrNumber]);
TablePtr->Handler(TablePtr->CallBackRef);
/* If the interrupt has been setup to
* acknowledge it after it has been serviced
* then ack it
*/
if ((CfgPtr->AckBeforeService &
IntrMask) == 0) {
XIntc_AckIntr(CfgPtr->BaseAddress,
IntrMask);
}
#if XPAR_XINTC_HAS_ILR == TRUE
/* Disable interrupts */
Xil_ExceptionDisable();
/* Restore ILR */
Xil_Out32(CfgPtr->BaseAddress + XIN_ILR_OFFSET,
ILR_reg);
#endif
/*
* Read the ISR again to handle architectures
* with posted write bus access issues.
*/
XIntc_GetIntrStatus(CfgPtr->BaseAddress);
/*
* If only the highest priority interrupt is to
* be serviced, exit loop and return after
* servicing
* the interrupt
*/
if (CfgPtr->Options == XIN_SVC_SGL_ISR_OPTION) {
#if XPAR_XINTC_HAS_ILR == TRUE
#ifdef __MICROBLAZE__
/* Restore r14 */
mtgpr(r14, R14_register);
#endif
#endif
return;
}
}
/* Move to the next interrupt to check */
IntrMask <<= 1;
IntrStatus >>= 1;
/* If there are no other bits set indicating that all
* interrupts have been serviced, then exit the loop
*/
if (IntrStatus == 0) {
break;
}
}
#if XPAR_XINTC_HAS_ILR == TRUE
#ifdef __MICROBLAZE__
/* Restore r14 */
mtgpr(r14, R14_register);
#endif
#endif
}
}
/*****************************************************************************/
/**
*
* Set the interrupt service option, which can configure the driver so that it
* services only a single interrupt at a time when an interrupt occurs, or
* services all pending interrupts when an interrupt occurs. The default
* behavior when using the driver interface given in xintc.h file is to service
* only a single interrupt, whereas the default behavior when using the driver
* interface given in this file is to service all outstanding interrupts when an
* interrupt occurs. In Cascade mode same Option is set to Slave controllers.
*
* @param BaseAddress is the unique identifier for a device.
* @param Option is XIN_SVC_SGL_ISR_OPTION if you want only a single
* interrupt serviced when an interrupt occurs, or
* XIN_SVC_ALL_ISRS_OPTION if you want all pending interrupts
* serviced when an interrupt occurs.
*
* @return None.
*
* @note
*
* Note that this function has no effect if the input base address is invalid.
*
******************************************************************************/
void XIntc_SetIntrSvcOption(u32 BaseAddress, int Option)
{
XIntc_Config *CfgPtr;
CfgPtr = LookupConfigByBaseAddress(BaseAddress);
if (CfgPtr != NULL) {
CfgPtr->Options = Option;
/* If Cascade mode set the option for all Slaves */
if (CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
int Index;
for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1;
Index++) {
CfgPtr = XIntc_LookupConfig(Index);
CfgPtr->Options = Option;
}
}
}
}
/*****************************************************************************/
/**
*
* Register a handler function for a specific interrupt ID. The vector table
* of the interrupt controller is updated, overwriting any previous handler.
* The handler function will be called when an interrupt occurs for the given
* interrupt ID.
*
* This function can also be used to remove a handler from the vector table
* by passing in the XIntc_DefaultHandler() as the handler and NULL as the
* callback reference.
* In Cascade mode Interrupt Id is used to set Handler for corresponding Slave
* Controller
*
* @param BaseAddress is the base address of the interrupt controller
* whose vector table will be modified.
* @param InterruptId is the interrupt ID to be associated with the input
* handler.
* @param Handler is the function pointer that will be added to
* the vector table for the given interrupt ID.
* @param CallBackRef is the argument that will be passed to the new
* handler function when it is called. This is user-specific.
*
* @return None.
*
* @note
*
* Note that this function has no effect if the input base address is invalid.
*
******************************************************************************/
void XIntc_RegisterHandler(u32 BaseAddress, int InterruptId,
XInterruptHandler Handler, void *CallBackRef)
{
XIntc_Config *CfgPtr;
CfgPtr = LookupConfigByBaseAddress(BaseAddress);
if (CfgPtr != NULL) {
if (InterruptId > 31) {
CfgPtr = XIntc_LookupConfig(InterruptId/32);
CfgPtr->HandlerTable[InterruptId%32].Handler = Handler;
CfgPtr->HandlerTable[InterruptId%32].CallBackRef =
CallBackRef;
}
else {
CfgPtr->HandlerTable[InterruptId].Handler = Handler;
CfgPtr->HandlerTable[InterruptId].CallBackRef =
CallBackRef;
}
}
}
/*****************************************************************************/
/**
*
* Looks up the device configuration based on the base address of the device.
* A table contains the configuration info for each device in the system.
*
* @param BaseAddress is the unique identifier for a device.
*
* @return
*
* A pointer to the configuration structure for the specified device, or
* NULL if the device was not found.
*
* @note None.
*
******************************************************************************/
static XIntc_Config *LookupConfigByBaseAddress(u32 BaseAddress)
{
XIntc_Config *CfgPtr = NULL;
int Index;
for (Index = 0; Index < XPAR_XINTC_NUM_INSTANCES; Index++) {
if (XIntc_ConfigTable[Index].BaseAddress == BaseAddress) {
CfgPtr = &XIntc_ConfigTable[Index];
break;
}
}
return CfgPtr;
}
/*****************************************************************************/
/**
*
* Register a fast handler function for a specific interrupt ID. The handler
* function will be called when an interrupt occurs for the given interrupt ID.
* In Cascade mode Interrupt Id is used to set Handler for corresponding Slave
* Controller
*
* @param BaseAddress is the base address of the interrupt controller
* whose vector table will be modified.
* @param InterruptId is the interrupt ID to be associated with the input
* handler.
* @param FastHandler is the function pointer that will be called when
* interrupt occurs
*
* @return None.
*
* @note
*
* Note that this function has no effect if the input base address is invalid.
*
******************************************************************************/
void XIntc_RegisterFastHandler(u32 BaseAddress, u8 Id,
XFastInterruptHandler FastHandler)
{
u32 CurrentIER;
u32 Mask;
u32 Imr;
XIntc_Config *CfgPtr;
if (Id > 31) {
/* Enable user required Id in Slave controller */
CfgPtr = XIntc_LookupConfig(Id/32);
/* Get the Enabled Interrupts */
CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
/* Convert from integer id to bit mask */
Mask = XIntc_BitPosMask[(Id%32)];
/* Disable the Interrupt if it was enabled before calling
* this function
*/
if (CurrentIER & Mask) {
XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
(CurrentIER & ~Mask));
}
XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET +
((Id%32) * 4), (u32) FastHandler);
/* Slave controllers in Cascade Mode should have all as Fast
* interrupts or Normal interrupts, mixed interrupts are not
* supported
*/
XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0xFFFFFFFF);
/* Enable the Interrupt if it was enabled before calling this
* function
*/
if (CurrentIER & Mask) {
XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
(CurrentIER | Mask));
}
}
else {
CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
/* Convert from integer id to bit mask */
Mask = XIntc_BitPosMask[Id];
if (CurrentIER & Mask) {
/* Disable Interrupt if it was enabled */
CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
XIntc_Out32(BaseAddress + XIN_IER_OFFSET,
(CurrentIER & ~Mask));
}
XIntc_Out32(BaseAddress + XIN_IVAR_OFFSET + (Id * 4),
(u32) FastHandler);
Imr = XIntc_In32(BaseAddress + XIN_IMR_OFFSET);
XIntc_Out32(BaseAddress + XIN_IMR_OFFSET, Imr | Mask);
/* Enable Interrupt if it was enabled before calling
* this function
*/
if (CurrentIER & Mask) {
CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
XIntc_Out32(BaseAddress + XIN_IER_OFFSET,
(CurrentIER | Mask));
}
}
}
#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
/*****************************************************************************/
/**
*
* This function is called by primary interrupt handler for the driver to handle
* all Controllers in Cascade mode.It will resolve which interrupts are active
* and enabled and call the appropriate interrupt handler. It uses the
* AckBeforeService flag in the configuration data to determine when to
* acknowledge the interrupt. Highest priority interrupts are serviced first.
* This function assumes that an interrupt vector table has been previously
* initialized. It does not verify that entries in the table are valid before
* calling an interrupt handler.This function calls itself recursively to handle
* all interrupt controllers.
*
* @param DeviceId is the zero-based device ID defined in xparameters.h
* of the interrupting interrupt controller. It is used as a direct
* index into the configuration data, which contains the vector
* table for the interrupt controller.
*
* @return None.
*
* @note
*
******************************************************************************/
static void XIntc_CascadeHandler(void *DeviceId)
{
u32 IntrStatus;
u32 IntrMask = 1;
int IntrNumber;
u32 Imr;
XIntc_Config *CfgPtr;
static int Id = 0;
/* Get the configuration data using the device ID */
CfgPtr = &XIntc_ConfigTable[(u32)DeviceId];
/* Get the interrupts that are waiting to be serviced */
IntrStatus = XIntc_GetIntrStatus(CfgPtr->BaseAddress);
/* Mask the Fast Interrupts */
if (CfgPtr->FastIntr == TRUE) {
Imr = XIntc_In32(CfgPtr->BaseAddress + XIN_IMR_OFFSET);
IntrStatus &= ~Imr;
}
/* Service each interrupt that is active and enabled by
* checking each bit in the register from LSB to MSB which
* corresponds to an interrupt input signal
*/
for (IntrNumber = 0; IntrNumber < CfgPtr->NumberofIntrs; IntrNumber++) {
if (IntrStatus & 1) {
XIntc_VectorTableEntry *TablePtr;
/* In Cascade mode call this function recursively
* for interrupt id 31 and until interrupts of last
* instance/controller are handled
*/
if ((IntrNumber == 31) &&
(CfgPtr->IntcType != XIN_INTC_LAST) &&
(CfgPtr->IntcType != XIN_INTC_NOCASCADE)) {
XIntc_CascadeHandler((void *)++Id);
Id--;
}
/* If the interrupt has been setup to
* acknowledge it before servicing the
* interrupt, then ack it */
if (CfgPtr->AckBeforeService & IntrMask) {
XIntc_AckIntr(CfgPtr->BaseAddress, IntrMask);
}
/* Handler of 31 interrupt Id has to be called only
* for Last controller in cascade Mode
*/
if (!((IntrNumber == 31) &&
(CfgPtr->IntcType != XIN_INTC_LAST) &&
(CfgPtr->IntcType != XIN_INTC_NOCASCADE))) {
/* The interrupt is active and enabled, call
* the interrupt handler that was setup with
* the specified parameter
*/
TablePtr = &(CfgPtr->HandlerTable[IntrNumber]);
TablePtr->Handler(TablePtr->CallBackRef);
}
/* If the interrupt has been setup to acknowledge it
* after it has been serviced then ack it
*/
if ((CfgPtr->AckBeforeService & IntrMask) == 0) {
XIntc_AckIntr(CfgPtr->BaseAddress, IntrMask);
}
/*
* Read the ISR again to handle architectures with
* posted write bus access issues.
*/
XIntc_GetIntrStatus(CfgPtr->BaseAddress);
/*
* If only the highest priority interrupt is to be
* serviced, exit loop and return after servicing
* the interrupt
*/
if (CfgPtr->Options == XIN_SVC_SGL_ISR_OPTION) {
return;
}
}
/* Move to the next interrupt to check */
IntrMask <<= 1;
IntrStatus >>= 1;
/* If there are no other bits set indicating that all interrupts
* have been serviced, then exit the loop
*/
if (IntrStatus == 0) {
break;
}
}
}
#endif

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_l.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
*
*
* Note that users of the driver interface given in this file can register
* an interrupt handler dynamically (at run-time) using the
* XIntc_RegisterHandler() function.
* User of the driver interface given in xintc.h should still use
* XIntc_Connect(), as always.
* Also see the discussion of the interrupt vector tables in xintc.h.
*
* There are currently two interrupt handlers specified in this interface.
*
* - XIntc_LowLevelInterruptHandler() is a handler without any arguments that
* is used in cases where there is a single interrupt controller device in
* the system and the handler cannot be passed an argument. This function is
* provided mostly for backward compatibility.
*
* - XIntc_DeviceInterruptHandler() is a handler that takes a device ID as an
* argument, indicating which interrupt controller device in the system is
* causing the interrupt - thereby supporting multiple interrupt controllers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------------
* 1.00b jhl 04/24/02 First release
* 1.00c rpm 10/17/03 New release. Support the static vector table created
* in the xintc_g.c configuration table.
* 1.10c mta 03/21/07 Updated to new coding style
* 1.11a sv 11/21/07 Updated driver to support access through a DCR bridge
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. _m is removed from all
* the macro definitions.
* 2.04a bss 01/13/12 Updated for adding defines for IMR and IVAR for
* the FAST Interrupt
* 2.05a bss 08/18/12 Added XIntc_RegisterFastHandler API to register fast
* interrupt handlers using base address.
* 2.07a bss 10/18/13 Added XIN_ILR_OFFSET macro for nested interrupts.
*
* </pre>
*
******************************************************************************/
#ifndef XINTC_L_H /* prevent circular inclusions */
#define XINTC_L_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xparameters.h"
#include "xil_io.h"
/*
* XPAR_XINTC_USE_DCR_BRIDGE has to be set to 1 if the Intc device will be
* accessed through a DCR bus connected to a bridge.
*/
#define XPAR_XINTC_USE_DCR_BRIDGE 0
#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
#include "xio_dcr.h"
#endif
/************************** Constant Definitions *****************************/
/* define the offsets from the base address for all the registers of the
* interrupt controller, some registers may be optional in the hardware device
*/
#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
#define XIN_ISR_OFFSET 0 /* Interrupt Status Register */
#define XIN_IPR_OFFSET 1 /* Interrupt Pending Register */
#define XIN_IER_OFFSET 2 /* Interrupt Enable Register */
#define XIN_IAR_OFFSET 3 /* Interrupt Acknowledge Register */
#define XIN_SIE_OFFSET 4 /* Set Interrupt Enable Register */
#define XIN_CIE_OFFSET 5 /* Clear Interrupt Enable Register */
#define XIN_IVR_OFFSET 6 /* Interrupt Vector Register */
#define XIN_MER_OFFSET 7 /* Master Enable Register */
#define XIN_IMR_OFFSET 8 /* Interrupt Mode Register , this is present
* only for Fast Interrupt */
#define XIN_IVAR_OFFSET 64 /* Interrupt Vector Address Register
* Interrupt 0 Offest, this is present
* only for Fast Interrupt */
#else /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
#define XIN_ISR_OFFSET 0 /* Interrupt Status Register */
#define XIN_IPR_OFFSET 4 /* Interrupt Pending Register */
#define XIN_IER_OFFSET 8 /* Interrupt Enable Register */
#define XIN_IAR_OFFSET 12 /* Interrupt Acknowledge Register */
#define XIN_SIE_OFFSET 16 /* Set Interrupt Enable Register */
#define XIN_CIE_OFFSET 20 /* Clear Interrupt Enable Register */
#define XIN_IVR_OFFSET 24 /* Interrupt Vector Register */
#define XIN_MER_OFFSET 28 /* Master Enable Register */
#define XIN_IMR_OFFSET 32 /* Interrupt Mode Register , this is present
* only for Fast Interrupt */
#define XIN_ILR_OFFSET 36 /* Interrupt level register */
#define XIN_IVAR_OFFSET 0x100 /* Interrupt Vector Address Register
* Interrupt 0 Offest, this is present
* only for Fast Interrupt */
#endif /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
/* Bit definitions for the bits of the MER register */
#define XIN_INT_MASTER_ENABLE_MASK 0x1UL
#define XIN_INT_HARDWARE_ENABLE_MASK 0x2UL /* once set cannot be cleared */
/**************************** Type Definitions *******************************/
/* The following data type defines each entry in an interrupt vector table.
* The callback reference is the base address of the interrupting device
* for the driver interface given in this file and an instance pointer for the
* driver interface given in xintc.h file.
*/
typedef struct {
XInterruptHandler Handler;
void *CallBackRef;
} XIntc_VectorTableEntry;
typedef void (*XFastInterruptHandler) (void);
/***************** Macros (Inline Functions) Definitions *********************/
/*
* Define the appropriate I/O access method to memory mapped I/O or DCR.
*/
#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
#define XIntc_In32 XIo_DcrIn
#define XIntc_Out32 XIo_DcrOut
#else
#define XIntc_In32 Xil_In32
#define XIntc_Out32 Xil_Out32
#endif
/****************************************************************************/
/**
*
* Enable all interrupts in the Master Enable register of the interrupt
* controller. The interrupt controller defaults to all interrupts disabled
* from reset such that this macro must be used to enable interrupts.
*
* @param BaseAddress is the base address of the device.
*
* @return None.
*
* @note C-style signature:
* void XIntc_MasterEnable(u32 BaseAddress);
*
*****************************************************************************/
#define XIntc_MasterEnable(BaseAddress) \
XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, \
XIN_INT_MASTER_ENABLE_MASK | XIN_INT_HARDWARE_ENABLE_MASK)
/****************************************************************************/
/**
*
* Disable all interrupts in the Master Enable register of the interrupt
* controller.
*
* @param BaseAddress is the base address of the device.
*
* @return None.
*
* @note C-style signature:
* void XIntc_MasterDisable(u32 BaseAddress);
*
*****************************************************************************/
#define XIntc_MasterDisable(BaseAddress) \
XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, 0)
/****************************************************************************/
/**
*
* Enable specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param EnableMask is the 32-bit value to write to the enable register.
* Each bit of the mask corresponds to an interrupt input signal
* that is connected to the interrupt controller (INT0 = LSB).
* Only the bits which are set in the mask will enable interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIntc_EnableIntr(u32 BaseAddress, u32 EnableMask);
*
*****************************************************************************/
#define XIntc_EnableIntr(BaseAddress, EnableMask) \
XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))
/****************************************************************************/
/**
*
* Disable specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param DisableMask is the 32-bit value to write to the enable register.
* Each bit of the mask corresponds to an interrupt input signal
* that is connected to the interrupt controller (INT0 = LSB).
* Only the bits which are set in the mask will disable interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIntc_DisableIntr(u32 BaseAddress, u32 DisableMask);
*
*****************************************************************************/
#define XIntc_DisableIntr(BaseAddress, DisableMask) \
XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))
/****************************************************************************/
/**
*
* Acknowledge specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param AckMask is the 32-bit value to write to the acknowledge
* register. Each bit of the mask corresponds to an interrupt input
* signal that is connected to the interrupt controller (INT0 =
* LSB). Only the bits which are set in the mask will acknowledge
* interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIntc_AckIntr(u32 BaseAddress, u32 AckMask);
*
*****************************************************************************/
#define XIntc_AckIntr(BaseAddress, AckMask) \
XIntc_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))
/****************************************************************************/
/**
*
* Get the interrupt status from the interrupt controller which indicates
* which interrupts are active and enabled.
*
* @param BaseAddress is the base address of the device
*
* @return The 32-bit contents of the interrupt status register. Each bit
* corresponds to an interrupt input signal that is connected to
* the interrupt controller (INT0 = LSB). Bits which are set
* indicate an active interrupt which is also enabled.
*
* @note C-style signature:
* u32 XIntc_GetIntrStatus(u32 BaseAddress);
*
*****************************************************************************/
#define XIntc_GetIntrStatus(BaseAddress) \
(XIntc_In32((BaseAddress) + XIN_ISR_OFFSET) & \
XIntc_In32((BaseAddress) + XIN_IER_OFFSET))
/************************** Function Prototypes ******************************/
/*
* Interrupt controller handlers, to be connected to processor exception
* handling code.
*/
void XIntc_LowLevelInterruptHandler(void);
void XIntc_DeviceInterruptHandler(void *DeviceId);
/* Various configuration functions */
void XIntc_SetIntrSvcOption(u32 BaseAddress, int Option);
void XIntc_RegisterHandler(u32 BaseAddress, int InterruptId,
XInterruptHandler Handler, void *CallBackRef);
void XIntc_RegisterFastHandler(u32 BaseAddress, u8 Id,
XFastInterruptHandler FastHandler);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_options.c
*
* Contains option functions for the XIntc driver. These functions allow the
* user to configure an instance of the XIntc driver. This file requires other
* files of the component to be linked in also.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------------
* 1.00b jhl 02/21/02 First release
* 1.00c rpm 10/17/03 New release. Support the relocation of the options flag
* from the instance structure to the xintc_g.c
* configuration table.
* 1.10c mta 03/21/07 Updated to new coding style
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs
* 2.06a bss 01/28/13 To support Cascade mode:
* Modified XIntc_SetOptions API.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xintc.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Set the options for the interrupt controller driver. In Cascade mode same
* Option is set to Slave controllers.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
* @param Options to be set. The available options are described in
* xintc.h.
*
* @return
* - XST_SUCCESS if the options were set successfully
* - XST_INVALID_PARAM if the specified option was not valid
*
* @note None.
*
****************************************************************************/
int XIntc_SetOptions(XIntc * InstancePtr, u32 Options)
{
XIntc_Config *CfgPtr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Make sure option request is valid
*/
if ((Options == XIN_SVC_SGL_ISR_OPTION) ||
(Options == XIN_SVC_ALL_ISRS_OPTION)) {
InstancePtr->CfgPtr->Options = Options;
/* If Cascade mode set the option for all Slaves */
if (InstancePtr->CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
int Index;
for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1;
Index++) {
CfgPtr = XIntc_LookupConfig(Index);
CfgPtr->Options = Options;
}
}
return XST_SUCCESS;
}
else {
return XST_INVALID_PARAM;
}
}
/*****************************************************************************/
/**
*
* Return the currently set options.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
*
* @return The currently set options. The options are described in xintc.h.
*
* @note None.
*
****************************************************************************/
u32 XIntc_GetOptions(XIntc * InstancePtr)
{
/*
* Assert the arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return InstancePtr->CfgPtr->Options;
}

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_selftest.c
*
* Contains diagnostic self-test functions for the XIntc component. This file
* requires other files of the component to be linked in also.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b jhl 02/21/02 First release
* 1.10c mta 03/21/07 Updated to new coding style
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs
* 2.04a bss 01/16/12 Removed CurrentMIE variable and reading of the
* MER register to remove warnings
* 2.06a bss 01/28/13 To support Cascade mode:
* Modified XIntc_SimulateIntr API.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xintc.h"
#include "xintc_i.h"
/************************** Constant Definitions *****************************/
#define XIN_TEST_MASK 1
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Run a self-test on the driver/device. This is a destructive test.
*
* This involves forcing interrupts into the controller and verifying that they
* are recognized and can be acknowledged. This test will not succeed if the
* interrupt controller has been started in real mode such that interrupts
* cannot be forced.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
*
* @return
* - XST_SUCCESS if self-test is successful.
* - XST_INTC_FAIL_SELFTEST if the Interrupt controller fails the
* self-test. It will fail the self test if the device has
* previously been started in real mode.
*
* @note None.
*
******************************************************************************/
int XIntc_SelfTest(XIntc * InstancePtr)
{
u32 CurrentISR;
u32 Temp;
/*
* Assert the arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Acknowledge all pending interrupts by reading the interrupt status
* register and writing the value to the acknowledge register
*/
Temp = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, Temp);
/*
* Verify that there are no interrupts by reading the interrupt status
*/
CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
/*
* ISR should be zero after all interrupts are acknowledged
*/
if (CurrentISR != 0) {
return XST_INTC_FAIL_SELFTEST;
}
/*
* Set a bit in the ISR which simulates an interrupt
*/
XIntc_Out32(InstancePtr->BaseAddress + XIN_ISR_OFFSET, XIN_TEST_MASK);
/*
* Verify that it was set
*/
CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
if (CurrentISR != XIN_TEST_MASK) {
return XST_INTC_FAIL_SELFTEST;
}
/*
* Acknowledge the interrupt
*/
XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, XIN_TEST_MASK);
/*
* Read back the ISR to verify that the interrupt is gone
*/
CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
if (CurrentISR != 0) {
return XST_INTC_FAIL_SELFTEST;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* Allows software to simulate an interrupt in the interrupt controller. This
* function will only be successful when the interrupt controller has been
* started in simulation mode. Once it has been started in real mode,
* interrupts cannot be simulated. A simulated interrupt allows the interrupt
* controller to be tested without any device to drive an interrupt input
* signal into it. In Cascade mode writes to ISR of appropraite Slave
* controller depending on Id.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
* @param Id is the interrupt ID for which to simulate an interrupt.
*
* @return
* - XST_SUCCESS if successful
* - XST_FAILURE if the interrupt could not be
* simulated because the interrupt controller is or
* has previously been in real mode.
*
* @note None.
*
******************************************************************************/
int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id)
{
u32 Mask;
u32 MasterEnable;
XIntc_Config *CfgPtr;
int Index;
int DeviceId;
/*
* Assert the arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
/* Get the contents of the master enable register and determine if
* hardware interrupts have already been enabled, if so, this is a write
* once bit such that simulation can't be done at this point because
* the ISR register is no longer writable by software
*/
MasterEnable = XIntc_In32(InstancePtr->BaseAddress + XIN_MER_OFFSET);
if (MasterEnable & XIN_INT_HARDWARE_ENABLE_MASK) {
return XST_FAILURE;
}
if (Id > 31) {
DeviceId = Id/32;
CfgPtr = XIntc_LookupConfig(Id/32);
Mask = XIntc_BitPosMask[Id%32];
XIntc_Out32(CfgPtr->BaseAddress + XIN_ISR_OFFSET, Mask);
/* Generate interrupt for 31 by writing to Interrupt Status
* register of parent controllers. Primary controller ISR
* will be written last in the loop
*/
Mask = XIntc_BitPosMask[31];
for (Index = DeviceId - 1; Index >= 0; Index--)
{
CfgPtr = XIntc_LookupConfig(Index);
XIntc_Out32(CfgPtr->BaseAddress + XIN_ISR_OFFSET,
Mask);
}
}
else {
/*
* The Id is used to create the appropriate mask for the
* desired bit position.
*/
Mask = XIntc_BitPosMask[Id];
/*
* Enable the selected interrupt source by reading the interrupt
* enable register and then modifying only the specified
* interrupt id enable
*/
XIntc_Out32(InstancePtr->BaseAddress + XIN_ISR_OFFSET, Mask);
}
/* indicate the interrupt was successfully simulated */
return XST_SUCCESS;
}

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/******************************************************************************
*
* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xmig_7series.h
* This driver exists only to allow the SDK tools to create a memory test
* application and to populate xparameters.h with memory range constants.
* There is no source code.
* VER WHO DATE Changes
* 2.0 adk 19/12/13 Updated as per the New Tcl API's
*
******************************************************************************/

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###############################################################################
#
# Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
######################################################################
# The following are defined in config.make
# LIBSOURCES - Based on if MicroBlaze support Exceptions
# LIBS - Do Build Profile Libraries
include config.make
AS=mb-as
CC=mb-gcc
AR=mb-ar
CP=cp
COMPILER_FLAGS=-O2 -c
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
OUTS = *.o
INCLUDEFILES=*.h
libs: $(LIBS)
standalone_libs: $(LIBSOURCES)
echo "Compiling standalone";
$(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
$(AR) -r ${RELEASEDIR}/${LIB} ${OUTS}
profile_libs:
$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" libs
include: standalone_includes profile_includes
standalone_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
profile_includes:
$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" include
clean:
rm -rf ${OUTS}
$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" clean

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/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include <unistd.h>
/* _exit - Simple implementation. Does not return.
*/
void _exit (int status)
{
(void) status;
while (1);
}

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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Configurations for Standalone BSP
*
*******************************************************************/
#define MICROBLAZE_PVR_NONE

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/*****************************************************************************
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
* 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
* 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but
* cacheable regions
* Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
* generated by the cpu driver, for enabling caches
* 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/
* write-thru caches
* 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC
* Updated the MMU table to mark OCM in high address space
* as inner cacheable and reserved space as Invalid
* 3.03a sdm 08/20/11 Changes to support FreeRTOS
* Updated the MMU table to mark upper half of the DDR as
* non-cacheable
* Setup supervisor and abort mode stacks
* Do not initialize/enable L2CC in case of AMP
* Initialize UART1 for 9600bps in case of AMP
* 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC
* in case of AMP
* 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event
* counters
* 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include
* xparameters.h file for CR630532 - Xil_DCacheFlush()/
* Xil_DCacheFlushRange() functions in standalone BSP v3_02a
* for MicroBlaze will invalidate data in the cache instead
* of flushing it for writeback caches
* 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7
* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
* Remove redundant dsb/dmb instructions in cache maintenance
* APIs
* Remove redundant dsb in mcr instruction
* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
* 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through
* driver tcl in xparameters.h. Update the gcc/translationtable.s
* for the QSPI complete address range - DT644567
* Removed profile directory for armcc compiler and changed
* profiling setting to false in standalone_v2_1_0.tcl file
* Deleting boot.S file after preprocessing for armcc compiler
* 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
* invalidate the caches before enabling back the MMU and
* D cache.
* 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file
* xil_mmu.c. Now we invalidate UTLB, Branch predictor
* array, flush the D-cache before changing the attributes
* in translation table. The user need not call Xil_DisableMMU
* before calling Xil_SetTlbAttributes.
* 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
* sgd initialization is present. Changes for this were done in
* uart.c and xil-crt0.s.
* Made changes in xil_io.c to use volatile pointers.
* Made changes in xil_mmu.c to correct the function
* Xil_SetTlbAttributes.
* Changes are made xil-crt0.s to initialize the static
* C++ constructors.
* Changes are made in boot.s, to fix the TTBR settings,
* correct the L2 Cache Auxiliary register settings, L2 cache
* latency settings.
* 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
* sgd usleep.c to use global timer intstead of CP15.
* Made changes in cortexa9/gcc/translation_table.s to map
* the peripheral devices as shareable device memory.
* Made changes in cortexa9/gcc/xil-crt0.s to initialize
* the global timer.
* Made changes in cortexa9/armcc/boot.S to initialize
* the global timer.
* Made changes in cortexa9/armcc/translation_table.s to
* map the peripheral devices as shareable device memory.
* Made changes in cortexa9/gcc/boot.S to optimize the
* L2 cache settings. Changes the section properties for
* ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
* and cortexa9/gcc/translation_table.S.
* Made changes in cortexa9/xil_cache.c to change the
* cache invalidation order.
* 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove
* compilation/linking issues for C++ compiler.
* Made changes in mb_interface.h to remove compilation/
* linking issues for C++ compiler.
* Added macros for swapb and swaph microblaze instructions
* mb_interface.h
* Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
* for CortexA9.
* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
* 3.07a asa 08/31/12 Added xil_printf.h include
* 3.07a sgd 09/18/12 Corrected the L2 cache enable settings
* Corrected L2 cache sequence disable sequence
* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option
* 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for
* irq/fiq handling.
* Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
* fixes the CR #692094.
* 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
* 3.10a srt 04/18/13 Implemented ARM Erratas.
* Cortex A9 Errata - 742230, 743622, 775420, 794073
* L2Cache PL310 Errata - 588369, 727915, 759370
* Please refer to file 'xil_errata.h' for errata
* description.
* 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
* cache APIs were corresponding to only Layer 1 cache
* memories. New APIs were now added and the existing cache
* related APIs were changed to provide a uniform interface
* to flush/invalidate/enable/disable the complete cache
* system which includes both L1 and L2 caches. The changes
* for these were done in:
* src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
* files.
* Four new files were added for supporting L2 cache. They are:
* microblaze_flush_cache_ext.S-> Flushes L2 cache
* microblaze_flush_cache_ext_range.S -> Flushes a range of
* memory in L2 cache.
* microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
* microblaze_invalidate_cache_ext_range -> Invalidates a
* range of memory in L2 cache.
* These changes are done to implement PR #697214.
* 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
* fix the CR #706464. L2 cache disabling happens independent
* of L1 data cache disable operation. Changes are done in the
* same file in cache handling APIs to do a L2 cache sync
* (poll reg7_?cache_?sync). This fixes CR #700542.
* 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
* interrupts for ARM. These are done to fix the CR#699680.
* 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach
* sync operation. This fixes the CR# 716781.
* 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support
* for armcc toolchain.
* Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
* fix issues related to NEON context saving. The assembly
* routines for IRQ and FIQ handling are modified.
* Deprecated the older BSP (3.10a).
* 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
* various potential issues. Made changes in the function
* Xil_SetAttributes in file xil_mmu.c.
* 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
* in src\cortexa9 and src\microblaze folders.
* 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
* L2 cache sync operation and to fix issues around complete
* L2 cache flush/invalidation by ways.
* 3.12a asa 10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
* to fix linking issues with armcc/DS-5. Modified the armcc
* makefile to fix issues.
* 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
* 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
* 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
* and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
* src\cortexa9\armcc\) to fix CR#767251
* 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
* Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
* Few cache lines were missed to invalidate when unaligned address
* invalidation was accommodated in Xil_DCacheInvalidateRange.
* In Xil_L1DCacheInvalidate, while invalidating all L1D cache
* stack memory (which contains return address) was invalidated. So
* stack memory is flushed first and then L1D cache is invalidated.
* This is done to fix CR #763829
* 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
* mblaze_nt_types.h file and replace uint32_t with u32 in the
* profile_hist.c to fix the above CR.
* 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a
* instead of libxil.a and added prototypes for
* microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
* mb_interface.h
* 4.1 hk 04/18/14 Add sleep function.
* 4.1 asa 04/21/14 Fix for CR#764881. Added support for msrset and msrclr. Renamed
* some of the *.s files inMB BSP source to *.S.
* 4.1 asa 04/28/14 Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
* 4.1 bss 04/29/14 Modified driver tcl to use libxil.a if libgloss.a does not exist
* CR#794205
* 4.1 asa 05/09/14 Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
* common/xil_testcache.c
* Fix for CR#764881.
* 4.1 srt 06/27/14 Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
* output the DEBUG logs when -DDEBUG flag is enabled in BSP.
* 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm.
* Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
* 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
* cortexa9/armcc/boot.s. Added default exception handlers for data
* abort and prefetch abort using handlers called
* DataAbortHandler and PrefetchAbortHandler respectively in
* cortexa9/xil_exception.c to fix CR#802862.
* 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the
* issue of improper linking of translation_table.s
* 4.2 pkp 07/04/14 added weak attribute for the function in BSP which are also present
* in tool chain to avoid conflicts into some special cases
* 4.2 pkp 07/21/14 Corrected reset value of event counter in function
* Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
* 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function
* containing type def u32 defined in xil_types.g to resolve issue of
* CR#805869
* 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as
* it is not possible to generate timer in nanosecond due to limited
* cpu frequency
* 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of
* uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
* and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
* removed function definition of XSmc_NorInit and XSmc_NorInit from
* cortexa9/smc.h
* 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_
* cache_ext_range declarations in mb_interface.h CR#783821.
* Modified profile_mcount_mb.S to fix CR#808412.
* 4.2 pkp 08/21/14 modified makefile of iccarm for proper linking of objectfiles in
* cortexa9/iccarm to fix CR#816701
* 4.2 pkp 09/02/14 modified translation table entries in cortexa9/gcc/translation_table.s,
* armcc/translation_table.s and iccarm/translation_table.s
* to properly defined reserved entries according to address map for
* fixing CR#820146
* 4.2 pkp 09/11/14 modified translation table entries in cortexa9/iccarm/translation_table.s
* and cortexa9/armcc/translation_table.s to resolve compilation
* error for solving CR#822897
******************************************************************************************/

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LIBSOURCES = *.c *.S
PROFILE_ARCH_OBJS = profile_mcount_mb.o
LIBS = standalone_libs

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/* The errno variable is stored in the reentrancy structure. This
function returns its address for use by the macro errno defined in
errno.h. */
#include <errno.h>
#include <reent.h>
int *
__errno ()
{
return &_REENT->_errno;
}

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#include <stdio.h>
/*
* fcntl -- Manipulate a file descriptor.
* We don't have a filesystem, so we do nothing.
*/
int fcntl (int fd, int cmd, long arg)
{
(void) fd;
(void) cmd;
(void) arg;
return 0;
}

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#ifndef _FSL_H
#define _FSL_H
#include "mb_interface.h" /* Legacy reasons. We just have to include this guy who defines the FSL stuff */
#ifdef __cplusplus
extern "C" {
#endif
/* Extended FSL macros. These now replace all of the previous FSL macros */
#define FSL_DEFAULT
#define FSL_NONBLOCKING n
#define FSL_EXCEPTION e
#define FSL_CONTROL c
#define FSL_ATOMIC a
#define FSL_NONBLOCKING_EXCEPTION ne
#define FSL_NONBLOCKING_CONTROL nc
#define FSL_NONBLOCKING_ATOMIC na
#define FSL_EXCEPTION_CONTROL ec
#define FSL_EXCEPTION_ATOMIC ea
#define FSL_CONTROL_ATOMIC ca
#define FSL_NONBLOCKING_EXCEPTION_CONTROL nec
#define FSL_NONBLOCKING_EXCEPTION_ATOMIC nea
#define FSL_NONBLOCKING_CONTROL_ATOMIC nca
#define FSL_EXCEPTION_CONTROL_ATOMIC eca
#define FSL_NONBLOCKING_EXCEPTION_CONTROL_ATOMIC neca
#define getfslx(val, id, flags) asm volatile (stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
#define putfslx(val, id, flags) asm volatile (stringify(flags) "put\t%0,rfsl" stringify(id) :: "d" (val))
#define tgetfslx(val, id, flags) asm volatile ("t" stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
#define tputfslx(id, flags) asm volatile ("t" stringify(flags) "put\trfsl" stringify(id))
#define getdfslx(val, var, flags) asm volatile (stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
#define putdfslx(val, var, flags) asm volatile (stringify(flags) "putd\t%0,%1" :: "d" (val), "d" (var))
#define tgetdfslx(val, var, flags) asm volatile ("t" stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
#define tputdfslx(var, flags) asm volatile ("t" stringify(flags) "putd\t%0" :: "d" (var))
#ifdef __cplusplus
}
#endif
#endif /* _FSL_H */

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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Microblaze HW Exception Handler
* - Non self-modifying exception handler for the following exception conditions
* - Unalignment
* - Instruction bus error
* - Data bus error
* - Illegal instruction opcode
* - Divide-by-zero
* - Stack protection violation
*/
#include "microblaze_exceptions_g.h"
#include "xparameters.h"
/* Helpful Macros */
#define EX_HANDLER_STACK_SIZ (4*21)
#define RMSR_OFFSET (20 * 4)
#define R17_OFFSET (0)
#define REG_OFFSET(regnum) (4 * (regnum + 1))
#define NUM_TO_REG(num) r ## num
#define R3_TO_STACK(regnum) swi r3, r1, REG_OFFSET(regnum)
#define R3_FROM_STACK(regnum) lwi r3, r1, REG_OFFSET(regnum)
#define PUSH_REG(regnum) swi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
#define POP_REG(regnum) lwi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
/* Uses r5 */
#define PUSH_MSR \
mfs r5, rmsr; \
swi r5, r1, RMSR_OFFSET;
#define PUSH_MSR_AND_ENABLE_EXC \
mfs r5, rmsr; \
swi r5, r1, RMSR_OFFSET; \
ori r5, r5, 0x100; /* Turn ON the EE bit*/ \
mts rmsr, r5;
/* Uses r5 */
#define POP_MSR \
lwi r5, r1, RMSR_OFFSET; \
mts rmsr, r5;
/* Push r17 */
#define PUSH_R17 swi r17, r1, R17_OFFSET
/* Pop r17 */
#define POP_R17 lwi r17, r1, R17_OFFSET
#define LWREG_NOP \
bri ex_handler_unhandled; \
nop;
#define SWREG_NOP \
bri ex_handler_unhandled; \
nop;
/* r3 is the source */
#define R3_TO_LWREG_V(regnum) \
R3_TO_STACK (regnum); \
bri ex_handler_done;
/* r3 is the source */
#define R3_TO_LWREG(regnum) \
or NUM_TO_REG (regnum), r0, r3; \
bri ex_handler_done;
/* r3 is the target */
#define SWREG_TO_R3_V(regnum) \
R3_FROM_STACK (regnum); \
bri ex_sw_tail;
/* r3 is the target */
#define SWREG_TO_R3(regnum) \
or r3, r0, NUM_TO_REG (regnum); \
bri ex_sw_tail;
/* regnum is the source */
#define FP_EX_OPB_SAVE(regnum) \
swi NUM_TO_REG (regnum), r0, mb_fpex_op_b; \
nop; \
bri handle_fp_ex_opa;
/* regnum is the source */
#define FP_EX_OPB_SAVE_V(regnum) \
R3_FROM_STACK (regnum); \
swi r3, r0, mb_fpex_op_b; \
bri handle_fp_ex_opa;
/* regnum is the source */
#define FP_EX_OPA_SAVE(regnum) \
swi NUM_TO_REG (regnum), r0, mb_fpex_op_a; \
nop; \
bri handle_fp_ex_done;
/* regnum is the source */
#define FP_EX_OPA_SAVE_V(regnum) \
R3_FROM_STACK (regnum); \
swi r3, r0, mb_fpex_op_a; \
bri handle_fp_ex_done;
#define FP_EX_UNHANDLED \
bri fp_ex_unhandled; \
nop; \
nop;
/* ESR masks */
#define ESR_EXC_MASK 0x0000001F
#define ESR_REG_MASK 0x000003E0
#define ESR_LW_SW_MASK 0x00000400
#define ESR_WORD_MASK 0x00000800
#define ESR_DS_MASK 0x00001000
/* Extern declarations */
.extern XNullHandler
#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
/*
* hw_exception_handler - Handler for unaligned exceptions
* Exception handler notes:
* - Does not handle exceptions other than unaligned exceptions
* - Does not handle exceptions during load into r17, r1, r0.
* - Does not handle exceptions during store from r17 (cannot be done) and r1 (slows down common case)
*
* Relevant register structures
*
* EAR - |----|----|----|----|----|----|----|----|
* - < ## 32 bit faulting address ## >
*
* ESR - |----|----|----|----|----| - | - |-----|-----|
* - W S REG EXC
*
*
* STACK FRAME STRUCTURE
* ---------------------
*
* +-------------+ + 0
* | r17 |
* +-------------+ + 4
* | Args for |
* | next func |
* +-------------+ + 8
* | r1 |
* | . |
* | . |
* | . |
* | . |
* | r18 |
* +-------------+ + 80
* | MSR |
* +-------------+ + 84
* | . |
* | . |
*/
.global _hw_exception_handler
.section .text
.align 2
.ent _hw_exception_handler
.type _hw_exception_handler, @function
_hw_exception_handler:
#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1)
/* Immediately halt for stack protection violation exception without using any stack */
swi r3, r0, mb_sp_save_r3; /* Save temporary register */
mfs r3, resr; /* Extract ESR[DS] */
andi r3, r3, ESR_EXC_MASK;
xori r3, r3, 0x7; /* Check for stack protection violation */
bnei r3, ex_handler_not_sp_violation;
ex_handler_sp_violation:
bri 0; /* Halt here if stack protection violation */
ex_handler_not_sp_violation:
lwi r3, r0, mb_sp_save_r3; /* Restore temporary register */
#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */
addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
PUSH_REG(3);
PUSH_REG(4);
PUSH_REG(5);
PUSH_REG(6);
#ifdef MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS
mfs r6, resr;
andi r6, r6, ESR_DS_MASK;
beqi r6, ex_handler_no_ds;
mfs r17, rbtr;
ex_handler_no_ds:
#endif
PUSH_R17;
PUSH_MSR_AND_ENABLE_EXC; /* Exceptions enabled here. This will allow nested exceptions */
mfs r3, resr;
andi r5, r3, ESR_EXC_MASK; /* Extract ESR[EXC] */
#ifndef NO_UNALIGNED_EXCEPTIONS
xori r6, r5, 1; /* 00001 = Unaligned Exception */
bnei r6, handle_ex_regular;
la r4, r0, MB_ExceptionVectorTable; /* Check if user has registered an unaligned exception handler */
lwi r4, r4, 8;
la r6, r0, XNullHandler; /* If exceptionvectortable entry is still XNullHandler, use */
xor r6, r4, r6; /* the default exception handler */
beqi r6, handle_unaligned_ex ;
handle_ex_regular:
#endif /* ! NO_UNALIGNED_EXCEPTIONS */
#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
xori r6, r5, 6; /* 00110 = FPU exception */
beqi r6, handle_fp_ex; /* Go and decode the FP exception */
#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
handle_other_ex: /* Handle Other exceptions here */
ori r6, r0, 20;
cmp r6, r5, r6; /* >= 20 are exceptions we do not handle. */
blei r6, ex_handler_unhandled;
ori r6, r0, 7;
cmp r6, r5, r6; /* Convert MMU exception indices into an ordinal of 7 */
bgti r6, handle_other_ex_tail;
ori r5, r0, 0x7;
handle_other_ex_tail:
PUSH_REG(7); /* Save other volatiles before we make procedure calls below */
PUSH_REG(8);
PUSH_REG(9);
PUSH_REG(10);
PUSH_REG(11);
PUSH_REG(12);
PUSH_REG(15);
PUSH_REG(18);
la r4, r0, MB_ExceptionVectorTable; /* Load the Exception vector table base address */
addk r7, r5, r5; /* Calculate exception vector offset = r5 * 8 */
addk r7, r7, r7;
addk r7, r7, r7;
addk r7, r7, r4; /* Get pointer to exception vector */
lwi r5, r7, 4; /* Load argument to exception handler from table */
lw r7, r7, r0; /* Load vector itself here */
brald r15, r7; /* Branch to handler */
nop;
POP_REG(7); /* Restore other volatiles */
POP_REG(8);
POP_REG(9);
POP_REG(10);
POP_REG(11);
POP_REG(12);
POP_REG(15);
POP_REG(18);
bri ex_handler_done; /* Complete exception handling */
#ifndef NO_UNALIGNED_EXCEPTIONS
handle_unaligned_ex:
andi r6, r3, ESR_REG_MASK; /* Mask and extract the register operand */
srl r6, r6; /* r6 >> 5 */
srl r6, r6;
srl r6, r6;
srl r6, r6;
srl r6, r6;
sbi r6, r0, ex_reg_op; /* Store the register operand in a temporary location */
mfs r4, rear;
andi r6, r3, ESR_LW_SW_MASK; /* Extract ESR[S] */
bnei r6, ex_sw;
ex_lw:
andi r6, r3, ESR_WORD_MASK; /* Extract ESR[W] */
beqi r6, ex_lhw;
lbui r5, r4, 0; /* Exception address in r4 */
sbi r5, r0, ex_tmp_data_loc_0; /* Load a word, byte-by-byte from destination address and save it in tmp space */
lbui r5, r4, 1;
sbi r5, r0, ex_tmp_data_loc_1;
lbui r5, r4, 2;
sbi r5, r0, ex_tmp_data_loc_2;
lbui r5, r4, 3;
sbi r5, r0, ex_tmp_data_loc_3;
lwi r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
bri ex_lw_tail;
ex_lhw:
lbui r5, r4, 0; /* Exception address in r4 */
sbi r5, r0, ex_tmp_data_loc_0; /* Load a half-word, byte-by-byte from destination address and save it in tmp space */
lbui r5, r4, 1;
sbi r5, r0, ex_tmp_data_loc_1;
lhui r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
ex_lw_tail:
lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
la r6, r0, lw_table; /* Form load_word jump table offset (lw_table + (8 * regnum)) */
addk r5, r5, r5;
addk r5, r5, r5;
addk r5, r5, r5;
addk r5, r5, r6;
bra r5;
ex_lw_end: /* Exception handling of load word, ends */
ex_sw:
lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
la r6, r0, sw_table; /* Form store_word jump table offset (sw_table + (8 * regnum)) */
add r5, r5, r5;
add r5, r5, r5;
add r5, r5, r5;
add r5, r5, r6;
bra r5;
ex_sw_tail:
mfs r6, resr;
andi r6, r6, ESR_WORD_MASK; /* Extract ESR[W] */
beqi r6, ex_shw;
swi r3, r0, ex_tmp_data_loc_0;
lbui r3, r0, ex_tmp_data_loc_0; /* Store the word, byte-by-byte into destination address */
sbi r3, r4, 0;
lbui r3, r0, ex_tmp_data_loc_1;
sbi r3, r4, 1;
lbui r3, r0, ex_tmp_data_loc_2;
sbi r3, r4, 2;
lbui r3, r0, ex_tmp_data_loc_3;
sbi r3, r4, 3;
bri ex_handler_done;
ex_shw:
swi r3, r0, ex_tmp_data_loc_0; /* Store the lower half-word, byte-by-byte into destination address */
#ifdef __LITTLE_ENDIAN__
lbui r3, r0, ex_tmp_data_loc_0;
#else
lbui r3, r0, ex_tmp_data_loc_2;
#endif
sbi r3, r4, 0;
#ifdef __LITTLE_ENDIAN__
lbui r3, r0, ex_tmp_data_loc_1;
#else
lbui r3, r0, ex_tmp_data_loc_3;
#endif
sbi r3, r4, 1;
ex_sw_end: /* Exception handling of store word, ends. */
bri ex_handler_done;
#endif /* !NO_UNALIGNED_EXCEPTIONS */
#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
handle_fp_ex:
addik r3, r17, -4; /* r17 contains (addr of exception causing FP instruction + 4) */
lw r4, r0, r3; /* We might find ourselves in a spot here. Unguaranteed load */
handle_fp_ex_opb:
la r6, r0, fp_table_opb; /* Decode opB and store its value in mb_fpex_op_b */
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
andi r3, r4, 0x1F;
add r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */
add r3, r3, r3;
add r5, r3, r3;
add r5, r5, r3;
add r5, r5, r6;
bra r5;
handle_fp_ex_opa:
la r6, r0, fp_table_opa; /* Decode opA and store its value in mb_fpex_op_a */
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
andi r3, r4, 0x1F;
add r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */
add r3, r3, r3;
add r5, r3, r3;
add r5, r5, r3;
add r5, r5, r6;
bra r5;
handle_fp_ex_done:
ori r5, r0, 6; /* Set exception number back to 6 */
bri handle_other_ex_tail;
fp_ex_unhandled:
bri 0;
#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
ex_handler_done:
POP_R17;
POP_MSR;
POP_REG(3);
POP_REG(4);
POP_REG(5);
POP_REG(6);
rted r17, 0
addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
ex_handler_unhandled:
bri 0 /* UNHANDLED. TRAP HERE */
.end _hw_exception_handler
#ifndef NO_UNALIGNED_EXCEPTIONS
/*
* hw_exception_handler Jump Table
* - Contains code snippets for each register that caused the unaligned exception.
* - Hence exception handler is NOT self-modifying
* - Separate table for load exceptions and store exceptions.
* - Each table is of size: (8 * 32) = 256 bytes
*/
.section .text
.align 4
lw_table:
lw_r0: R3_TO_LWREG (0);
lw_r1: LWREG_NOP;
lw_r2: R3_TO_LWREG (2);
lw_r3: R3_TO_LWREG_V (3);
lw_r4: R3_TO_LWREG_V (4);
lw_r5: R3_TO_LWREG_V (5);
lw_r6: R3_TO_LWREG_V (6);
lw_r7: R3_TO_LWREG (7);
lw_r8: R3_TO_LWREG (8);
lw_r9: R3_TO_LWREG (9);
lw_r10: R3_TO_LWREG (10);
lw_r11: R3_TO_LWREG (11);
lw_r12: R3_TO_LWREG (12);
lw_r13: R3_TO_LWREG (13);
lw_r14: R3_TO_LWREG (14);
lw_r15: R3_TO_LWREG (15);
lw_r16: R3_TO_LWREG (16);
lw_r17: LWREG_NOP;
lw_r18: R3_TO_LWREG (18);
lw_r19: R3_TO_LWREG (19);
lw_r20: R3_TO_LWREG (20);
lw_r21: R3_TO_LWREG (21);
lw_r22: R3_TO_LWREG (22);
lw_r23: R3_TO_LWREG (23);
lw_r24: R3_TO_LWREG (24);
lw_r25: R3_TO_LWREG (25);
lw_r26: R3_TO_LWREG (26);
lw_r27: R3_TO_LWREG (27);
lw_r28: R3_TO_LWREG (28);
lw_r29: R3_TO_LWREG (29);
lw_r30: R3_TO_LWREG (30);
lw_r31: R3_TO_LWREG (31);
sw_table:
sw_r0: SWREG_TO_R3 (0);
sw_r1: SWREG_NOP;
sw_r2: SWREG_TO_R3 (2);
sw_r3: SWREG_TO_R3_V (3);
sw_r4: SWREG_TO_R3_V (4);
sw_r5: SWREG_TO_R3_V (5);
sw_r6: SWREG_TO_R3_V (6);
sw_r7: SWREG_TO_R3 (7);
sw_r8: SWREG_TO_R3 (8);
sw_r9: SWREG_TO_R3 (9);
sw_r10: SWREG_TO_R3 (10);
sw_r11: SWREG_TO_R3 (11);
sw_r12: SWREG_TO_R3 (12);
sw_r13: SWREG_TO_R3 (13);
sw_r14: SWREG_TO_R3 (14);
sw_r15: SWREG_TO_R3 (15);
sw_r16: SWREG_TO_R3 (16);
sw_r17: SWREG_NOP;
sw_r18: SWREG_TO_R3 (18);
sw_r19: SWREG_TO_R3 (19);
sw_r20: SWREG_TO_R3 (20);
sw_r21: SWREG_TO_R3 (21);
sw_r22: SWREG_TO_R3 (22);
sw_r23: SWREG_TO_R3 (23);
sw_r24: SWREG_TO_R3 (24);
sw_r25: SWREG_TO_R3 (25);
sw_r26: SWREG_TO_R3 (26);
sw_r27: SWREG_TO_R3 (27);
sw_r28: SWREG_TO_R3 (28);
sw_r29: SWREG_TO_R3 (29);
sw_r30: SWREG_TO_R3 (30);
sw_r31: SWREG_TO_R3 (31);
/* Temporary data structures used in the handler */
.section .data
.align 2
ex_tmp_data_loc_0:
.byte 0
ex_tmp_data_loc_1:
.byte 0
ex_tmp_data_loc_2:
.byte 0
ex_tmp_data_loc_3:
.byte 0
ex_reg_op:
.byte 0
#endif /* ! NO_UNALIGNED_EXCEPTIONS */
#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
/*
* FP exception decode jump table.
* - Contains code snippets for each register that could have been a source operand for an excepting FP instruction
* - Hence exception handler is NOT self-modifying
* - Separate table for opA and opB
* - Each table is of size: (12 * 32) = 384 bytes
*/
.section .text
.align 4
fp_table_opa:
opa_r0: FP_EX_OPA_SAVE (0);
opa_r1: FP_EX_UNHANDLED;
opa_r2: FP_EX_OPA_SAVE (2);
opa_r3: FP_EX_OPA_SAVE_V (3);
opa_r4: FP_EX_OPA_SAVE_V (4);
opa_r5: FP_EX_OPA_SAVE_V (5);
opa_r6: FP_EX_OPA_SAVE_V (6);
opa_r7: FP_EX_OPA_SAVE (7);
opa_r8: FP_EX_OPA_SAVE (8);
opa_r9: FP_EX_OPA_SAVE (9);
opa_r10: FP_EX_OPA_SAVE (10);
opa_r11: FP_EX_OPA_SAVE (11);
opa_r12: FP_EX_OPA_SAVE (12);
opa_r13: FP_EX_OPA_SAVE (13);
opa_r14: FP_EX_UNHANDLED;
opa_r15: FP_EX_UNHANDLED;
opa_r16: FP_EX_UNHANDLED;
opa_r17: FP_EX_UNHANDLED;
opa_r18: FP_EX_OPA_SAVE (18);
opa_r19: FP_EX_OPA_SAVE (19);
opa_r20: FP_EX_OPA_SAVE (20);
opa_r21: FP_EX_OPA_SAVE (21);
opa_r22: FP_EX_OPA_SAVE (22);
opa_r23: FP_EX_OPA_SAVE (23);
opa_r24: FP_EX_OPA_SAVE (24);
opa_r25: FP_EX_OPA_SAVE (25);
opa_r26: FP_EX_OPA_SAVE (26);
opa_r27: FP_EX_OPA_SAVE (27);
opa_r28: FP_EX_OPA_SAVE (28);
opa_r29: FP_EX_OPA_SAVE (29);
opa_r30: FP_EX_OPA_SAVE (30);
opa_r31: FP_EX_OPA_SAVE (31);
fp_table_opb:
opb_r0: FP_EX_OPB_SAVE (0);
opb_r1: FP_EX_UNHANDLED;
opb_r2: FP_EX_OPB_SAVE (2);
opb_r3: FP_EX_OPB_SAVE_V (3);
opb_r4: FP_EX_OPB_SAVE_V (4);
opb_r5: FP_EX_OPB_SAVE_V (5);
opb_r6: FP_EX_OPB_SAVE_V (6);
opb_r7: FP_EX_OPB_SAVE (7);
opb_r8: FP_EX_OPB_SAVE (8);
opb_r9: FP_EX_OPB_SAVE (9);
opb_r10: FP_EX_OPB_SAVE (10);
opb_r11: FP_EX_OPB_SAVE (11);
opb_r12: FP_EX_OPB_SAVE (12);
opb_r13: FP_EX_OPB_SAVE (13);
opb_r14: FP_EX_UNHANDLED;
opb_r15: FP_EX_UNHANDLED;
opb_r16: FP_EX_UNHANDLED;
opb_r17: FP_EX_UNHANDLED;
opb_r18: FP_EX_OPB_SAVE (18);
opb_r19: FP_EX_OPB_SAVE (19);
opb_r20: FP_EX_OPB_SAVE (20);
opb_r21: FP_EX_OPB_SAVE (21);
opb_r22: FP_EX_OPB_SAVE (22);
opb_r23: FP_EX_OPB_SAVE (23);
opb_r24: FP_EX_OPB_SAVE (24);
opb_r25: FP_EX_OPB_SAVE (25);
opb_r26: FP_EX_OPB_SAVE (26);
opb_r27: FP_EX_OPB_SAVE (27);
opb_r28: FP_EX_OPB_SAVE (28);
opb_r29: FP_EX_OPB_SAVE (29);
opb_r30: FP_EX_OPB_SAVE (30);
opb_r31: FP_EX_OPB_SAVE (31);
#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
#if defined(MICROBLAZE_FP_EXCEPTION_ENABLED) && defined(MICROBLAZE_FP_EXCEPTION_DECODE)
/* This is where we store the opA and opB of the last excepting FP instruction */
.section .data
.align 2
.global mb_fpex_op_a
.global mb_fpex_op_b
mb_fpex_op_a:
.long 0
mb_fpex_op_b:
.long 0
#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1)
/* This is where we store the register used to check which exception occurred */
.section .data
.align 2
mb_sp_save_r3:
.long 0
#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */
/* The exception vector table */
.section .data
.align 2
.global MB_ExceptionVectorTable
MB_ExceptionVectorTable:
.long XNullHandler
.long 0 /* -- FSL Exception -- */
.long XNullHandler
.long 1 /* -- Unaligned Access Exception -- */
.long XNullHandler
.long 2 /* -- Illegal Opcode Exception -- */
.long XNullHandler
.long 3 /* -- Instruction Bus Exception -- */
.long XNullHandler
.long 4 /* -- Data Bus Exception -- */
.long XNullHandler
.long 5 /* -- Div-by-0 Exception -- */
.long XNullHandler
.long 6 /* -- FPU Exception -- */
.long XNullHandler
.long 7 /* -- MMU Exceptions -- */
#else /* Dummy exception handler, in case exceptions are not present in the processor */
.global _hw_exception_handler
.section .text
.align 2
.ent _hw_exception_handler
_hw_exception_handler:
bri 0;
.end _hw_exception_handler
#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */

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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef _MICROBLAZE_INTERFACE_H_
#define _MICROBLAZE_INTERFACE_H_
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_exception.h"
#ifdef __cplusplus
extern "C" {
#endif
extern void microblaze_enable_interrupts(void); /* Enable Interrupts */
extern void microblaze_disable_interrupts(void); /* Disable Interrupts */
extern void microblaze_enable_icache(void); /* Enable Instruction Cache */
extern void microblaze_disable_icache(void); /* Disable Instruction Cache */
extern void microblaze_enable_dcache(void); /* Enable Instruction Cache */
extern void microblaze_disable_dcache(void); /* Disable Instruction Cache */
extern void microblaze_enable_exceptions(void); /* Enable hardware exceptions */
extern void microblaze_disable_exceptions(void); /* Disable hardware exceptions */
extern void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); /* Register top level interrupt handler */
extern void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr); /* Register exception handler */
extern void microblaze_invalidate_icache(void); /* Invalidate the entire icache */
extern void microblaze_invalidate_dcache(void); /* Invalidate the entire dcache */
extern void microblaze_flush_dcache(void); /* Flush the whole dcache */
extern void microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the icache */
extern void microblaze_invalidate_dcache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the dcache */
extern void microblaze_flush_dcache_range(unsigned int cacheaddr, unsigned int len); /* Flush a part of the dcache */
extern void microblaze_scrub(void); /* Scrub LMB and internal BRAM */
extern void microblaze_invalidate_cache_ext(void); /* Invalidate cache ext */
extern void microblaze_flush_cache_ext(void); /* Flush cache ext */
extern void microblaze_flush_cache_ext_range(unsigned int cacheaddr,
unsigned int len); /* Flush cache ext range */
extern void microblaze_invalidate_cache_ext_range(unsigned int cacheaddr,
unsigned int len); /* Invalidate cache ext range */
/* Deprecated */
extern void microblaze_update_icache (int , int , int ) __attribute__((deprecated));
extern void microblaze_init_icache_range (int , int ) __attribute__((deprecated));
extern void microblaze_update_dcache (int , int , int ) __attribute__((deprecated));
extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated));
/* necessary for pre-processor */
#define stringify(s) tostring(s)
#define tostring(s) #s
/* FSL Access Macros */
/* Blocking Data Read and Write to FSL no. id */
#define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
#define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Data Read and Write to FSL no. id */
#define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
#define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
/* Blocking Control Read and Write to FSL no. id */
#define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
#define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Control Read and Write to FSL no. id */
#define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
#define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
/* Polling versions of FSL access macros. This makes the FSL access interruptible */
#define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
#define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
/* FSL valid and error check macros. */
#define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result))
#define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \
"andi\t%0,%0,0x10" : "=d" (error))
/* Pseudo assembler instructions */
#define clz(v) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"clz\t%0,%1\n" : "=d"(_rval): "d" (v) \
); \
_rval; \
})
#define mbar(mask) ({ __asm__ __volatile__ ("mbar\t" stringify(mask) ); })
#define mb_sleep() ({ __asm__ __volatile__ ("sleep\t"); })
#define mb_swapb(v) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"swapb\t%0,%1\n" : "=d"(_rval) : "d" (v) \
); \
_rval; \
})
#define mb_swaph(v) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"swaph\t%0,%1\n" : "=d"(_rval) : "d" (v) \
); \
_rval; \
})
#define mfgpr(rn) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"or\t%0,r0," stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfmsr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rmsr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfear() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rear\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfesr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,resr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mffsr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rfsr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfpvr(rn) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfbtr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rbtr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfedr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,redr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfpid() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rpid\n" : "=d"(_rval)\
); \
_rval; \
})
#define mfzpr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rzpr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlbx() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlbx\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlblo() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlblo\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlbhi() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlbhi\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfslr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rslr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfshr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rshr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mtgpr(rn, v) ({ __asm__ __volatile__ ( \
"or\t" stringify(rn) ",r0,%0\n" :: "d" (v) \
); \
})
#define mtmsr(v) ({ __asm__ __volatile__ ( \
"mts\trmsr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtfsr(v) ({ __asm__ __volatile__ ( \
"mts\trfsr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtpid(v) ({ __asm__ __volatile__ ( \
"mts\trpid,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtzpr(v) ({ __asm__ __volatile__ ( \
"mts\trzpr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbx(v) ({ __asm__ __volatile__ ( \
"mts\trtlbx,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlblo(v) ({ __asm__ __volatile__ ( \
"mts\trtlblo,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbhi(v) ({ __asm__ __volatile__ ( \
"mts\trtlbhi,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbsx(v) ({ __asm__ __volatile__ ( \
"mts\trtlbsx,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtslr(v) ({ __asm__ __volatile__ ( \
"mts\trslr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtshr(v) ({ __asm__ __volatile__ ( \
"mts\trshr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define lwx(address) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"lwx\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lwr(address) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"lwr\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lhur(address) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"lhur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lbur(address) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"lbur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define swx(address, data) ({ __asm__ __volatile__ ( \
"swx\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define swr(address, data) ({ __asm__ __volatile__ ( \
"swr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define shr(address, data) ({ __asm__ __volatile__ ( \
"shr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define sbr(address, data) ({ __asm__ __volatile__ ( \
"sbr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define microblaze_getfpex_operand_a() ({ \
extern unsigned int mb_fpex_op_a; \
mb_fpex_op_a; \
})
#define microblaze_getfpex_operand_b() ({ \
extern unsigned int mb_fpex_op_b; \
mb_fpex_op_b; \
})
/* Deprecated MicroBlaze FSL macros */
#define microblaze_bread_datafsl(val, id) getfsl(val,id)
#define microblaze_bwrite_datafsl(val, id) putfsl(val,id)
#define microblaze_nbread_datafsl(val, id) ngetfsl(val,id)
#define microblaze_nbwrite_datafsl(val, id) nputfsl(val,id)
#define microblaze_bread_cntlfsl(val, id) cgetfsl(val,id)
#define microblaze_bwrite_cntlfsl(val, id) cputfsl(val,id)
#define microblaze_nbread_cntlfsl(val, id) ncgetfsl(val,id)
#define microblaze_nbwrite_cntlfsl(val, id) ncputfsl(val,id)
#ifdef __cplusplus
}
#endif
#endif // _MICROBLAZE_INTERFACE_H_

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FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_dcache.S
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/******************************************************************************
* Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* File : microblaze_disable_dcache.s
* Date : 2002, March 20.
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Disable the L1 dcache on the microblaze.
*
*******************************************************************************/
#include "xparameters.h"
.text
.globl microblaze_disable_dcache
.ent microblaze_disable_dcache
.align 2
microblaze_disable_dcache:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
addik r1, r1, -4
swi r15, r1, 0
brlid r15, microblaze_flush_dcache /* microblaze_flush_dcache does not use r1*/
nop
lwi r15, r1, 0
addi r1, r1, 4
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
rtsd r15, 8
msrclr r0, 0x80
#else /* XPAR_MICROBLAZE_USE_MSR_INSTR == 1 */
addik r1, r1, -4
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
swi r15, r1, 0
brlid r15, microblaze_flush_dcache
nop
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
mfs r11, rmsr
andi r11, r11, ~(0x80)
mts rmsr, r11
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
lwi r15, r1, 0
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
rtsd r15, 8
addi r1, r1, 4
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_disable_dcache

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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#
# Disable exceptions on microblaze.
#
#
####################################################################
#include "xparameters.h"
.text
.globl microblaze_disable_exceptions
.ent microblaze_disable_exceptions
.align 2
microblaze_disable_exceptions:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
msrclr r0, 0x100
#else
mfs r4, rmsr;
andi r4, r4, ~(0x100); /* Turn OFF the EE bit */
mts rmsr, r4;
rtsd r15, 8;
nop;
#endif
.end microblaze_disable_exceptions

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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#
# File : microblaze_disable_icache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Disable L1 icache on the microblaze.
#
#
####################################################################
#include "xparameters.h"
.text
.globl microblaze_disable_icache
.ent microblaze_disable_icache
.align 2
microblaze_disable_icache:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
msrclr r0, 0x20
#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
#Read the MSR register
mfs r8, rmsr
#Clear the icache enable bit
andi r8, r8, ~(0x20)
#Save the MSR register
mts rmsr, r8
#Return
rtsd r15, 8
nop
#endif
.end microblaze_disable_icache

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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#
# File : microblaze_disable_interrupts.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Disable interrupts on the microblaze.
#
#
####################################################################
#include "xparameters.h"
.text
.globl microblaze_disable_interrupts
.ent microblaze_disable_interrupts
.align 2
microblaze_disable_interrupts:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
msrclr r0, 0x2
#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
#Read the MSR register
mfs r12, rmsr
#Clear the interrupt enable bit
andi r12, r12, ~(0x2)
#Save the MSR register
mts rmsr, r12
#Return
rtsd r15, 8
nop
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_disable_interrupts

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FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_dcache.S
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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#
# File : microblaze_enable_dcache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Enable L1 dcache on the microblaze.
#
#
####################################################################
#include "xparameters.h"
.text
.globl microblaze_enable_dcache
.ent microblaze_enable_dcache
.align 2
microblaze_enable_dcache:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
msrset r0, 0x80
#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
#Read the MSR register
mfs r8, rmsr
#Set the interrupt enable bit
ori r8, r8, 0x80
#Save the MSR register
mts rmsr, r8
#Return
rtsd r15, 8
nop
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_enable_dcache

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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#
# Enable exceptions on microblaze.
#
#
####################################################################
#include "xparameters.h"
.text
.globl microblaze_enable_exceptions
.ent microblaze_enable_exceptions
.align 2
microblaze_enable_exceptions:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8;
msrset r0, 0x100
#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
mfs r4, rmsr;
ori r4, r4, 0x100; /* Turn ON the EE bit */
mts rmsr, r4;
rtsd r15, 8;
nop;
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_enable_exceptions

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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#
# File : microblaze_enable_icache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Enable icache on the microblaze.
#
#
####################################################################
#include "xparameters.h"
.text
.globl microblaze_enable_icache
.ent microblaze_enable_icache
.align 2
microblaze_enable_icache:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
msrset r0, 0x20
#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
#Read the MSR register
mfs r8, rmsr
#Set the interrupt enable bit
ori r8, r8, 0x20
#Save the MSR register
mts rmsr, r8
#Return
rtsd r15, 8
nop
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_enable_icache

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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#
# File : microblaze_enable_interrupts.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Enable interrupts on the microblaze.
#
#
####################################################################
#include "xparameters.h"
.text
.globl microblaze_enable_interrupts
.ent microblaze_enable_interrupts
.align 2
microblaze_enable_interrupts:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
msrset r0, 0x2
#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
#Read the MSR register
mfs r12, rmsr
#Set the interrupt enable bit
ori r12, r12, 0x2
#Save the MSR register
mts rmsr, r12
#Return
rtsd r15, 8
nop
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_enable_interrupts

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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_exception_handler.c
*
* This file contains exception handler registration routines for
* the MicroBlaze processor.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 06/24/04 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "microblaze_exceptions_i.h"
#include "microblaze_exceptions_g.h"
#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[];
/****************************************************************************/
/*****************************************************************************/
/**
*
* Registers an exception handler for the MicroBlaze. The
* argument provided in this call as the DataPtr is used as the argument
* for the handler when it is called.
*
* @param ExceptionId is the id of the exception to register this handler
* for.
* @param Top level handler.
* @param DataPtr is a reference to data that will be passed to the handler
* when it gets called.
* @return None.
*
* @note
*
* None.
*
****************************************************************************/
void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr)
{
MB_ExceptionVectorTable[ExceptionId].Handler = Handler;
MB_ExceptionVectorTable[ExceptionId].CallBackRef = DataPtr;
}
#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */

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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Exception Handling Header for MicroBlaze Processor
*
*******************************************************************/
#define MICROBLAZE_EXCEPTIONS_ENABLED 1
#define MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS
#define MICROBLAZE_FP_EXCEPTION_ENABLED 1

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/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_exceptions_i.h
*
* This header file contains defines for structures used by the microblaze
* hardware exception handler.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00a 06/24/04 First release
* </pre>
*
******************************************************************************/
#ifndef MICROBLAZE_EXCEPTIONS_I_H /* prevent circular inclusions */
#define MICROBLAZE_EXCEPTIONS_I_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_exception.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct
{
Xil_ExceptionHandler Handler;
void *CallBackRef;
} MB_ExceptionVectorTableEntry;
/* Exception IDs */
#define XEXC_ID_FSL 0
#define XEXC_ID_UNALIGNED_ACCESS 1
#define XEXC_ID_ILLEGAL_OPCODE 2
#define XEXC_ID_M_AXI_I_EXCEPTION 3
#define XEXC_ID_IPLB_EXCEPTION 3
#define XEXC_ID_M_AXI_D_EXCEPTION 4
#define XEXC_ID_DPLB_EXCEPTION 4
#define XEXC_ID_DIV_BY_ZERO 5
#define XEXC_ID_FPU 6
#define XEXC_ID_STACK_VIOLATION 7
#define XEXC_ID_MMU 7
void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
* microblaze_flush_cache_ext()
*
* Flush the entire L2 Cache
*
*
*******************************************************************************/
#include "xparameters.h"
#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
.text
.globl microblaze_flush_cache_ext
.ent microblaze_flush_cache_ext
.align 2
microblaze_flush_cache_ext:
#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))
addik r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
Loop_start:
wdc.ext.flush r5, r6
bgtid r6,Loop_start
addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
#endif
rtsd r15, 8
nop
.end microblaze_flush_cache_ext

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/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
* microblaze_flush_cache_ext_range (unsigned int cacheaddr, unsigned int len)
*
*Flush a L2 Cache range
*
*Parameters:
* 'cacheaddr' - address in the L2 cache where the flush begins
* 'len ' - length (in bytes) worth of L2 cache to be flushed
*
*******************************************************************************/
#include "xparameters.h"
#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
.text
.globl microblaze_flush_cache_ext_range
.ent microblaze_flush_cache_ext_range
.align 2
microblaze_flush_cache_ext_range:
#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
beqi r6, Loop_done
addik r6, r6, -1
add r6, r5, r6
andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
andi r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
rsubk r6, r5, r6
Loop_start:
wdc.ext.flush r5, r6
bneid r6, Loop_start
addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
Loop_done:
#endif
rtsd r15, 8
nop
.end microblaze_flush_cache_ext_range

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/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
* microblaze_flush_dcache()
*
* Flush the L1 DCache
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
.text
.globl microblaze_flush_dcache
.ent microblaze_flush_dcache
.align 2
microblaze_flush_dcache:
addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Align to cache line */
addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
L_start:
wdc.flush r5, r0 /* Flush the Cache */
cmpu r18, r5, r6 /* Are we at the end? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
rtsd r15, 8 /* Return */
nop
.end microblaze_flush_dcache

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/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
* microblaze_flush_dcache_range (unsigned int cacheaddr, unsigned int len)
*
* Flush a L1 DCache range
*
* Parameters:
* 'cacheaddr' - address in the Dcache where the flush begins
* 'len ' - length (in bytes) worth of Dcache to be flushed
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#define MB_HAS_WRITEBACK_SET 0
#else
#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#endif
.text
.globl microblaze_flush_dcache_range
.ent microblaze_flush_dcache_range
.align 2
microblaze_flush_dcache_range:
#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
beqi r6, L_done /* Skip loop if size is zero */
add r6, r5, r6 /* Compute end address */
addik r6, r6, -1
andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */
andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */
#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */
L_start:
cmpu r18, r5, r6 /* Are we at the end? */
blti r18, L_done
wdc r5, r0 /* Invalidate the cache line */
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
#else
rsubk r6, r5, r6
/* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */
L_start:
wdc.flush r5, r6 /* Flush the cache line */
bneid r6, L_start
addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
#endif
L_done:
rtsd r15, 8
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
.end microblaze_flush_dcache_range

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/******************************************************************************
*
* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
* microblaze_init_dcache_range (unsigned int cache_start, unsigned int cache_len)
*
* Invalidate dcache on the microblaze
*
* Parameters:
* 'cache_start' - address in the Dcache where invalidation begins
* 'cache_len' - length (in bytes) worth of Dcache to be invalidated
*
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
.text
.globl microblaze_init_dcache_range
.ent microblaze_init_dcache_range
.align 2
microblaze_init_dcache_range:
mfs r9, rmsr /* Disable Dcache and interrupts before invalidating */
andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */
add r6, r5, r6 /* Compute end */
andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */
L_start:
wdc r5, r0 /* Invalidate the Cache (delay slot) */
cmpu r18, r5, r6 /* Are we at the end ? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
rtsd r15, 8 /* Return */
mts rmsr, r9
.end microblaze_init_dcache_range

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/******************************************************************************
*
* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*
* microblaze_init_icache_range (unsigned int cache_start, unsigned int cache_len)
*
* Invalidate icache on the microblaze
*
* Parameters:
* 'cache_start' - address in the Icache where invalidation begins
* 'cache_len' - length (in bytes) worth of Icache to be invalidated
*
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
#endif
.text
.globl microblaze_init_icache_range
.ent microblaze_init_icache_range
.align 2
microblaze_init_icache_range:
mfs r9, rmsr /* Disable Icache and interrupts before invalidating */
andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */
add r6, r5, r6 /* Compute end */
andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */
L_start:
wic r5, r0 /* Invalidate the Cache (delay slot) */
cmpu r18, r5, r6 /* Are we at the end ? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
rtsd r15, 8 /* Return */
mts rmsr, r9
.end microblaze_init_icache_range

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/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_interrupt_handler.c
*
* This file contains the standard interrupt handler for the MicroBlaze processor.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 10/03/03 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_exception.h"
#include "microblaze_interrupts_i.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
void __interrupt_handler (void) __attribute__ ((interrupt_handler));
/************************** Variable Definitions *****************************/
extern MB_InterruptVectorTableEntry MB_InterruptVectorTable;
/*****************************************************************************/
/**
*
* This function is the standard interrupt handler used by the MicroBlaze processor.
* It saves all volatile registers, calls the users top level interrupt handler.
* When this returns, it restores all registers, and returns using a rtid instruction.
*
* @param
*
* None
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void __interrupt_handler(void)
{
/* The compiler saves all volatiles and the MSR */
MB_InterruptVectorTable.Handler(MB_InterruptVectorTable.CallBackRef);
/* The compiler restores all volatiles and MSR, and returns from interrupt */
}
/****************************************************************************/
/*****************************************************************************/
/**
*
* Registers a top-level interrupt handler for the MicroBlaze. The
* argument provided in this call as the DataPtr is used as the argument
* for the handler when it is called.
*
* @param Top level handler.
* @param DataPtr is a reference to data that will be passed to the handler
* when it gets called.
* @return None.
*
* @note
*
* None.
*
****************************************************************************/
void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr)
{
MB_InterruptVectorTable.Handler = Handler;
MB_InterruptVectorTable.CallBackRef = DataPtr;
}

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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Interrupt Handler Table for MicroBlaze Processor
*
*******************************************************************/
#include "microblaze_interrupts_i.h"
#include "xparameters.h"
extern void XIntc_DeviceInterruptHandler (void *);
/*
* The interrupt handler table for microblaze processor
*/
MB_InterruptVectorTableEntry MB_InterruptVectorTable[] =
{
{ XIntc_DeviceInterruptHandler,
(void*) XPAR_AXI_INTC_0_DEVICE_ID}
};

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/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_interrupts_i.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
* High-level driver functions are defined in xintc.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 10/03/03 First release
* </pre>
*
******************************************************************************/
#ifndef MICROBLAZE_INTERRUPTS_I_H /* prevent circular inclusions */
#define MICROBLAZE_INTERRUPTS_I_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_exception.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct
{
XInterruptHandler Handler;
void *CallBackRef;
} MB_InterruptVectorTableEntry;
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
* microblaze_invalidate_cache_ext()
*
*Invalidate the entire L2 Cache
*
*
*******************************************************************************/
#include "xparameters.h"
#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
.text
.globl microblaze_invalidate_cache_ext
.ent microblaze_invalidate_cache_ext
.align 2
microblaze_invalidate_cache_ext:
#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN))
addik r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
Loop_start:
wdc.ext.clear r5, r6
bgtid r6,Loop_start
addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
#endif
rtsd r15, 8
nop
.end microblaze_invalidate_cache_ext

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/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
* microblaze_invalidate_cache_ext_range (unsigned int cacheaddr, unsigned int len)
*
*Invalidate an L2 cache range
*
*Parameters:
* 'cacheaddr' - address in the L2 cache where invalidation begins
* 'len ' - length (in bytes) worth of Dcache to be invalidated
*
*******************************************************************************/
#include "xparameters.h"
#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
.text
.globl microblaze_invalidate_cache_ext_range
.ent microblaze_invalidate_cache_ext_range
.align 2
microblaze_invalidate_cache_ext_range:
#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
beqi r6, Loop_done
add r6, r5, r6
addik r6, r6, -1
andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
andi r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
rsubk r6, r5, r6
Loop_start:
wdc.ext.clear r5, r6
bneid r6, Loop_start
addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
Loop_done:
#endif
rtsd r15, 8
nop
.end microblaze_invalidate_cache_ext_range

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/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
* microblaze_invalidate_dcache()
*
* Invalidate the entire L1 DCache
*
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#endif
.text
.globl microblaze_invalidate_dcache
.ent microblaze_invalidate_dcache
.align 2
microblaze_invalidate_dcache:
#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))
addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
L_start:
wdc r5, r0 /* Invalidate the Cache */
cmpu r18, r5, r6 /* Are we at the end? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
rtsd r15, 8 /* Return */
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
.end microblaze_invalidate_dcache

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/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*
* microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len)
*
* Invalidate a Dcache range
*
* Parameters:
* 'cacheaddr' - address in the Dcache where invalidation begins
* 'len ' - length (in bytes) worth of Dcache to be invalidated
*
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#define MB_HAS_WRITEBACK_SET 0
#else
#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#endif
.text
.globl microblaze_invalidate_dcache_range
.ent microblaze_invalidate_dcache_range
.align 2
microblaze_invalidate_dcache_range:
#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
beqi r6, L_done /* Skip loop if size is zero */
add r6, r5, r6 /* Compute end address */
addik r6, r6, -1
andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */
andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */
#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */
L_start:
cmpu r18, r5, r6 /* Are we at the end? */
blti r18, L_done
wdc r5, r0
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
#else
rsubk r6, r5, r6
/* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */
L_start:
wdc.clear r5, r6 /* Invalidate the cache line only if the address matches */
bneid r6, L_start
addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
#endif
L_done:
rtsd r15, 8
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
.end microblaze_invalidate_dcache_range

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/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*
* microblaze_invalidate_icache()
*
* Invalidate the entire ICache
*
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
#endif
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#endif
.text
.globl microblaze_invalidate_icache
.ent microblaze_invalidate_icache
.align 2
microblaze_invalidate_icache:
#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
addik r5, r0, XPAR_MICROBLAZE_ICACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Align to cache line */
addik r6, r5, XPAR_MICROBLAZE_CACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Compute end */
L_start:
wic r5, r0 /* Invalidate the Cache */
cmpu r18, r5, r6 /* Are we at the end? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
rtsd r15, 8 /* Return */
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
.end microblaze_invalidate_icache

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/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*
* microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len)
*
* Invalidate an ICache range
*
* Parameters:
* 'cacheaddr' - address in the Icache where invalidation begins
* 'len' - length (in bytes) worth of Icache to be invalidated
*
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
#endif
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#endif
.text
.globl microblaze_invalidate_icache_range
.ent microblaze_invalidate_icache_range
.align 2
microblaze_invalidate_icache_range:
#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
beqi r6, L_done /* Skip loop if size is zero */
add r6, r5, r6 /* Compute end address */
addik r6, r6, -1
andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align end down to cache line */
andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align start down to cache line */
L_start:
cmpu r18, r5, r6 /* Are we at the end? */
blti r18, L_done
wic r5, r0 /* Invalidate the cache line */
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
rtsd r15, 8 /* Return */
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
.end microblaze_invalidate_icache_range

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/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
* microblaze_scrub ()
*
* Scrub LMB memory and all internal BRAMs (data cache, instruction cache,
* MMU UTLB and branch target cache) in MicroBlaze to reduce the possibility
* of an uncorrectable error when fault tolerance support is enabled.
*
* This routine assumes that the processor is in privileged mode when it is
* called, if the MMU is enabled.
*
* Call this routine regularly from a timer interrupt.
*
* Parameters:
* None
*
*
*******************************************************************************/
#include "xparameters.h"
/* Define if fault tolerance is used */
#ifdef XPAR_MICROBLAZE_FAULT_TOLERANT
#if XPAR_MICROBLAZE_FAULT_TOLERANT > 0
#define FAULT_TOLERANT
#endif
#endif
/* Define if LMB is used and can be scrubbed */
#if defined(XPAR_MICROBLAZE_D_LMB) && \
defined(XPAR_DLMB_CNTLR_BASEADDR) && \
defined(XPAR_DLMB_CNTLR_HIGHADDR)
#if XPAR_MICROBLAZE_D_LMB == 1
#define HAS_SCRUBBABLE_LMB
#define DLMB_MASK (XPAR_DLMB_CNTLR_HIGHADDR - XPAR_DLMB_CNTLR_BASEADDR)
#endif
#endif
/* Set default cache line lengths */
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
#endif
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
#endif
/* Define if internal Data Cache BRAMs are used */
#if defined(XPAR_MICROBLAZE_USE_DCACHE) && defined(XPAR_MICROBLAZE_DCACHE_BYTE_SIZE)
#if XPAR_MICROBLAZE_USE_DCACHE == 1 && XPAR_MICROBLAZE_DCACHE_BYTE_SIZE > 1024
#define HAS_BRAM_DCACHE
#define DCACHE_INCREMENT (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
#define DCACHE_MASK (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE - 1)
#endif
#endif
/* Define if internal Instruction Cache BRAMs are used */
#if defined(XPAR_MICROBLAZE_USE_ICACHE) && defined(XPAR_MICROBLAZE_CACHE_BYTE_SIZE)
#if XPAR_MICROBLAZE_USE_ICACHE == 1 && XPAR_MICROBLAZE_CACHE_BYTE_SIZE > 1024
#define HAS_BRAM_ICACHE
#define ICACHE_INCREMENT (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4)
#define ICACHE_MASK (XPAR_MICROBLAZE_CACHE_BYTE_SIZE - 1)
#endif
#endif
/* Define if internal MMU UTLB BRAM is used */
#ifdef XPAR_MICROBLAZE_USE_MMU
#if XPAR_MICROBLAZE_USE_MMU > 1
#define HAS_BRAM_MMU_UTLB
#endif
#endif
/* Define if internal BTC BRAM is used, and match BTC clear to a complete cache scrub */
#if defined(XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE) && \
defined(XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE)
#if XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE == 1
#if XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE == 0 || \
XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE > 4
#define HAS_BRAM_BRANCH_TARGET_CACHE
#ifdef HAS_BRAM_DCACHE
#define BTC_MASK_D (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE/DCACHE_INCREMENT-1)
#else
#define BTC_MASK_D 256
#endif
#ifdef HAS_BRAM_ICACHE
#define BTC_MASK_I (XPAR_MICROBLAZE_CACHE_BYTE_SIZE/ICACHE_INCREMENT-1)
#else
#define BTC_MASK_I 256
#endif
#if BTC_MASK_D > BTC_MASK_I
#define BTC_MASK BTC_MASK_D
#else
#define BTC_MASK BTC_MASK_I
#endif
#endif
#endif
#endif
/* Define index offsets to persistent data used by this routine */
#define DLMB_INDEX_OFFSET 0
#define DCACHE_INDEX_OFFSET 4
#define ICACHE_INDEX_OFFSET 8
#define MMU_INDEX_OFFSET 12
#define BTC_CALL_COUNT_OFFSET 16
.text
.globl microblaze_scrub
.ent microblaze_scrub
.align 2
microblaze_scrub:
#ifdef FAULT_TOLERANT
la r6, r0, L_persistent_data /* Get pointer to data */
#ifdef HAS_SCRUBBABLE_LMB
L_dlmb:
lwi r5, r6, DLMB_INDEX_OFFSET /* Get dlmb index */
lw r7, r5, r0 /* Load and store */
sw r7, r5, r0
addik r5, r5, 4 /* Increment and save dlmb index */
andi r5, r5, DLMB_MASK
swi r5, r6, DLMB_INDEX_OFFSET
#endif /* HAS_SCRUBBABLE_LMB */
#ifdef HAS_BRAM_DCACHE
L_dcache:
lwi r5, r6, DCACHE_INDEX_OFFSET /* Get dcache line index */
wdc r5, r0 /* Invalidate data cache line */
addik r5, r5, DCACHE_INCREMENT /* Increment and save entry index */
andi r5, r5, DCACHE_MASK
swi r5, r6, DCACHE_INDEX_OFFSET
#endif /* HAS_BRAM_DCACHE */
#ifdef HAS_BRAM_ICACHE
L_icache:
lwi r5, r6, ICACHE_INDEX_OFFSET /* Get icache line index */
wic r5, r0 /* Invalidate data cache line */
addik r5, r5, ICACHE_INCREMENT /* Increment and save entry index */
andi r5, r5, ICACHE_MASK
swi r5, r6, ICACHE_INDEX_OFFSET
#endif /* HAS_BRAM_ICACHE */
#ifdef HAS_BRAM_MMU_UTLB
L_mmu:
lwi r5, r6, MMU_INDEX_OFFSET /* Get UTLB entry index */
mts rtlbx, r5 /* Access next entry in UTLB */
mts rtlbhi, r0 /* Clear the UTLB entry */
addik r5, r5, 1 /* Increment and save entry index */
andi r5, r5, 0x3F
swi r5, r6, MMU_INDEX_OFFSET
#endif /* HAS_BRAM_MMU_UTLB */
#ifdef HAS_BRAM_BRANCH_TARGET_CACHE
L_btc:
lwi r5, r6, BTC_CALL_COUNT_OFFSET /* Get BTC call count offset */
addik r5, r5, 1 /* Increment and save call count */
andi r5, r5, BTC_MASK
swi r5, r6, BTC_CALL_COUNT_OFFSET
bnei r5, L_skip_btc_scrub /* Skip scrub unless count wrap */
bri 4 /* Clear branch target cache */
L_skip_btc_scrub:
#endif /* HAS_BRAM_BRANCH_TARGET_CACHE */
#endif /* FAULT_TOLERANT */
L_done:
rtsd r15, 8 /* Return */
nop
.end microblaze_scrub
/* Persistent data used by this routine */
.data
.align 2
L_persistent_data:
.long 0 /* dlmb index */
.long 0 /* dcache index */
.long 0 /* icache index */
.long 0 /* mmu entry index */
.long 0 /* btc call count */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_sleep.c
*
* Contains implementation of microblaze sleep function.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.1 hk 04/18/14 Add sleep function.
*
* </pre>
*
* @note
*
* This file may contain architecture-dependent code.
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "microblaze_sleep.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* Provides delay for requested duration.
*
* @param Delay time in milliseconds.
*
* @return None.
*
* @note Instruction cache should be enabled for this to work.
*
******************************************************************************/
void MB_Sleep(unsigned int MilliSeconds)
{
if (((mfmsr() & 0x20) == 0)) {
/*
* Instruction cache not enabled.
* Delay will be much higher than expected.
*/
}
asm volatile ("\n"
"1: \n\t"
"addik r7, r0, %0 \n\t"
"2: \n\t"
"addik r7, r7, -1 \n\t"
"bneid r7, 2b \n\t"
"or r0, r0, r0 \n\t"
"bneid %1, 1b \n\t"
"addik %1, %1, -1 \n\t"
:: "i"(ITERS_PER_MSEC), "d" (MilliSeconds));
}

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file microblaze_sleep.h
*
* Contains microblaze sleep function API.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.1 asa 04/18/14 Add sleep function - first release.
*
* </pre>
*
* @note
*
* This file may contain architecture-dependent items.
*
******************************************************************************/
#ifndef MICROBLAZE_SLEEP_H /* prevent circular inclusions */
#define MICROBLAZE_SLEEP_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "mb_interface.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define ITERS_PER_MSEC ((XPAR_CPU_CORE_CLOCK_FREQ_HZ / 1000) / 6)
/************************** Function Prototypes ******************************/
void MB_Sleep(unsigned int MilliSeconds);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*
* File : microblaze_update_dcache.s
* Date : 2003, September 24
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Update dcache on the microblaze.
* Takes in three parameters
* r5 : Cache Tag Line
* r6 : Cache Data
* r7 : Lock/Valid information
* Bit 30 is Lock [ 1 indicates locked ]
* Bit 31 is Valid [ 1 indicates valid ]
*
* --------------------------------------------------------------
* | Lock | Valid | Effect
* --------------------------------------------------------------
* | 0 | 0 | Invalidate Cache
* | 0 | 1 | Valid, but unlocked cacheline
* | 1 | 0 | Invalidate Cache, No effect of lock
* | 1 | 1 | Valid cache. Locked to a
* | | | particular addrees
* --------------------------------------------------------------
*
*
**********************************************************************************/
#include "xparameters.h"
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
.text
.globl microblaze_update_dcache
.ent microblaze_update_dcache
.align 2
microblaze_update_dcache:
#if XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1
/* Read the MSR register into a temp register */
mfs r18, rmsr
/* Clear the dcache enable bit to disable the cache
Register r10,r18 are volatile registers and hence do not need to be saved before use */
andi r10, r18, ~128
mts rmsr, r10
/* Update the lock and valid info */
andi r5, r5, 0xfffffffc
or r5, r5, r7
/* Update dcache */
wdc r5, r6
/* Return */
rtsd r15, 8
mts rmsr, r18
#else
/* The only valid usage of this routine for larger cache line lengths is to invalidate a data cache line
So call microblaze_init_dcache_range appropriately to do the job */
brid microblaze_init_dcache_range
addik r6, r0, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
/* We don't have a return instruction here. This is tail call optimization :) */
#endif /* XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1 */
.end microblaze_update_dcache

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/******************************************************************************
*
* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
* File : microblaze_update_icache.s
* Date : 2003, September 24
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Update icache on the microblaze.
* Takes in three parameters
* r5 : Cache Tag Line
* r6 : Cache Data
* r7 : Lock/Valid information
* Bit 30 is Lock [ 1 indicates locked ]
* Bit 31 is Valid [ 1 indicates valid ]
*
* --------------------------------------------------------------
* | Lock | Valid | Effect
* --------------------------------------------------------------
* | 0 | 0 | Invalidate Cache
* | 0 | 1 | Valid, but unlocked cacheline
* | 1 | 0 | Invalidate Cache, No effect of lock
* | 1 | 1 | Valid cache. Locked to a
* | | | particular addrees
* --------------------------------------------------------------
*
*
**********************************************************************************/
#include "xparameters.h"
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
#endif
.text
.globl microblaze_update_icache
.ent microblaze_update_icache
.align 2
microblaze_update_icache:
#if XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1
/* Read the MSR register into a temp register */
mfs r18, rmsr
/* Clear the icache enable bit to disable the cache
Register r10,r18 are volatile registers and hence do not need to be saved before use */
andi r10, r18, ~32
mts rmsr, r10
/* Update the lock and valid info */
andi r5, r5, 0xfffffffc
or r5, r5, r7
/* Update icache */
wic r5, r6
/* Return */
rtsd r15, 8
mts rmsr, r18
#else
/* The only valid usage of this routine for larger cache line lengths is to invalidate an instruction cache line
So call microblaze_init_icache_range appropriately to do the job */
brid microblaze_init_icache_range
addik r6, r0, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4)
/* We don't have a return instruction here. This is tail call optimization :) */
#endif /* XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1 */
.end microblaze_update_icache

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#$Id: Makefile,v 1.1.2.1 2011/05/17 04:37:55 sadanan Exp $
###############################################################################
#
# Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
###############################################################################
#
# Makefile for profiler
#
#######################################################################
# PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here
include ../config.make
AS=mb-as
COMPILER = mb-gcc
ARCHIVER = mb-ar
CP = cp
COMPILER_FLAGS=-O2
EXTRA_COMPILER_FLAGS=
LIB = libxil.a
DUMMYLIB = libxilprofile.a
CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
RELEASEDIR = ../../../../lib
INCLUDEDIR = ../../../../include
INCLUDES = -I./. -I${INCLUDEDIR}
OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o
DUMMYOBJ = dummy.o
INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h
libs : reallibs dummylibs
reallibs : $(OBJS) $(PROFILE_ARCH_OBJS)
$(ARCHIVER) -r $(RELEASEDIR)/$(LIB) $(OBJS) $(PROFILE_ARCH_OBJS)
dummylibs : $(DUMMYOBJ)
$(ARCHIVER) -r $(RELEASEDIR)/$(DUMMYLIB) $(DUMMYOBJ)
%.o:%.c
$(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
%.o:%.S
$(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
include:
$(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -f $(OBJS) $(PROFILE_ARCH_OBJS) $(LIB)

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// $Id: _profile_clean.c,v 1.1.2.1 2011/05/17 04:37:55 sadanan Exp $
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include "profile.h"
#include "_profile_timer_hw.h"
#include "xil_exception.h"
/*
* This function is the exit routine and is called by the crtinit, when the
* program terminates. The name needs to be changed later..
*/
void _profile_clean( void )
{
Xil_ExceptionDisable();
disable_timer();
}

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// $Id: _profile_init.c,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************
*
* _program_init.c:
* Initialize the Profiling Structures.
*
******************************************************************************/
#include "profile.h"
// XMD Initializes the following Global Variables Value during Program
// Download with appropriate values.
#ifdef PROC_MICROBLAZE
extern int microblaze_init(void);
#elif defined PROC_PPC
extern int powerpc405_init(void);
#else
extern int cortexa9_init(void);
#endif
int profile_version = 1; // Version of S/W Intrusive Profiling library
int binsize = BINSIZE; // Histogram Bin Size
unsigned int cpu_clk_freq = CPU_FREQ_HZ ; // CPU Clock Frequency
unsigned int sample_freq_hz = SAMPLE_FREQ_HZ ; // Histogram Sampling Frequency
unsigned int timer_clk_ticks = TIMER_CLK_TICKS ;// Timer Clock Ticks for the Timer
// Structure for Storing the Profiling Data
struct gmonparam *_gmonparam = (struct gmonparam *)0xffffffff;
int n_gmon_sections = 1;
// This is the initialization code, which is called from the crtinit.
//
void _profile_init( void )
{
/* print("Gmon Init called....\r\n") ; */
/* putnum(n_gmon_sections) ; print("\r\n") ; */
/* if( _gmonparam == 0xffffffff ) */
/* printf("Gmonparam is NULL !!\r\n"); */
/* for( i = 0; i < n_gmon_sections; i++ ){ */
/* putnum(_gmonparam[i].lowpc) ; print("\t") ; */
/* putnum(_gmonparam[i].highpc) ; print("\r\n") ; */
/* putnum( _gmonparam[i].textsize ); print("\r\n") ; */
/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short));print("\r\n"); */
/* } */
#ifdef PROC_MICROBLAZE
microblaze_init();
#elif defined PROC_PPC
powerpc405_init();
#else
cortexa9_init ();
#endif
}

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// $Id: _profile_timer_hw.c,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************
*
* _program_timer_hw.c:
* Timer related functions
*
******************************************************************************/
#include "profile.h"
#include "_profile_timer_hw.h"
#include "xil_exception.h"
#ifdef PROC_PPC
#include "xtime_l.h"
#include "xpseudo_asm.h"
#endif
#ifdef TIMER_CONNECT_INTC
#include "xintc_l.h"
#include "xintc.h"
#endif // TIMER_CONNECT_INTC
//#ifndef PPC_PIT_INTERRUPT
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
#include "xtmrctr_l.h"
#endif
extern unsigned int timer_clk_ticks ;
//--------------------------------------------------------------------
// PowerPC Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_PPC405
//--------------------------------------------------------------------
// PowerPC PIT Timer Init.
// Defined only if PIT Timer is used for Profiling
//
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
int ppc_pit_init( void )
{
// 1. Register Profile_intr_handler as Interrupt handler
// 2. Set PIT Timer Interrupt and Enable it.
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
XTime_PITSetInterval( timer_clk_ticks ) ;
XTime_PITEnableAutoReload() ;
return 0;
}
#endif
//--------------------------------------------------------------------
// PowerPC Timer Initialization functions.
// For PowerPC, PIT and opb_timer can be used for Profiling. This
// is selected by the user in standalone BSP
//
//--------------------------------------------------------------------
int powerpc405_init()
{
Xil_ExceptionInit() ;
Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
// Initialize the Timer.
// 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
// 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC
#ifdef PPC_PIT_INTERRUPT
ppc_pit_init();
#else
#ifdef TIMER_CONNECT_INTC
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,(void*)0);
#else
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
#endif
// Initialize the timer with Timer Ticks
opb_timer_init() ;
#endif
// Enable Interrupts in the System, if Profile Timer is the only Interrupt
// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef PPC_PIT_INTERRUPT
XTime_PITEnableInterrupt() ;
#elif TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
#endif
Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
#endif
return 0;
}
#endif // PROC_PPC
//--------------------------------------------------------------------
// PowerPC440 Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_PPC440
//--------------------------------------------------------------------
// PowerPC DEC Timer Init.
// Defined only if DEC Timer is used for Profiling
//
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
int ppc_dec_init( void )
{
// 1. Register Profile_intr_handler as Interrupt handler
// 2. Set DEC Timer Interrupt and Enable it.
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
XTime_DECSetInterval( timer_clk_ticks ) ;
XTime_DECEnableAutoReload() ;
return 0;
}
#endif
//--------------------------------------------------------------------
// PowerPC Timer Initialization functions.
// For PowerPC, DEC and opb_timer can be used for Profiling. This
// is selected by the user in standalone BSP
//
//--------------------------------------------------------------------
int powerpc405_init(void)
{
Xil_ExceptionInit();
Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
// Initialize the Timer.
// 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
// 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC
#ifdef PPC_PIT_INTERRUPT
ppc_dec_init();
#else
#ifdef TIMER_CONNECT_INTC
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,(void*)0);
#else
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
#endif
// Initialize the timer with Timer Ticks
opb_timer_init() ;
#endif
// Enable Interrupts in the System, if Profile Timer is the only Interrupt
// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef PPC_PIT_INTERRUPT
XTime_DECEnableInterrupt() ;
#elif TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
#endif
Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
#endif
return 0;
}
#endif // PROC_PPC440
//--------------------------------------------------------------------
// opb_timer Initialization for PowerPC and MicroBlaze. This function
// is not needed if DEC timer is used in PowerPC
//
//--------------------------------------------------------------------
//#ifndef PPC_PIT_INTERRUPT
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
int opb_timer_init( void )
{
// set the number of cycles the timer counts before interrupting
XTmrCtr_SetLoadReg(PROFILE_TIMER_BASEADDR, 0, timer_clk_ticks);
// reset the timers, and clear interrupts
XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0,
XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
// start the timers
XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK
| XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
return 0;
}
#endif
//--------------------------------------------------------------------
// MicroBlaze Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_MICROBLAZE
//--------------------------------------------------------------------
// Initialize the Profile Timer for MicroBlaze Target.
// For MicroBlaze, opb_timer is used. The opb_timer can be directly
// connected to MicroBlaze or connected through Interrupt Controller.
//
//--------------------------------------------------------------------
int microblaze_init(void)
{
// Register profile_intr_handler
// 1. If timer is connected to Interrupt Controller, register the handler
// to Interrupt Controllers vector table.
// 2. If timer is directly connected to MicroBlaze, register the handler
// as Interrupt handler
Xil_ExceptionInit();
#ifdef TIMER_CONNECT_INTC
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,(void*)0);
#else
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)profile_intr_handler,
(void *)0) ;
#endif
// Initialize the timer with Timer Ticks
opb_timer_init() ;
// Enable Interrupts in the System, if Profile Timer is the only Interrupt
// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
#endif
#endif
Xil_ExceptionEnable();
return 0;
}
#endif // PROC_MICROBLAZE
//--------------------------------------------------------------------
// Cortex A9 Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_CORTEXA9
//--------------------------------------------------------------------
// Initialize the Profile Timer for Cortex A9 Target.
// The scu private timer is connected to the Scu GIC controller.
//
//--------------------------------------------------------------------
int scu_timer_init( void )
{
// set the number of cycles the timer counts before interrupting
// scu timer runs at half the cpu clock
XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2);
// clear any pending interrupts
XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1);
// enable interrupts, auto-reload mode and start the timer
XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK |
XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK);
return 0;
}
int cortexa9_init(void)
{
Xil_ExceptionInit();
XScuGic_DeviceInitialize(0);
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
(void *)0);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
PROFILE_TIMER_INTR_ID,
(Xil_ExceptionHandler)profile_intr_handler,
(void *)0);
/*
* Enable the interrupt for scu timer.
*/
XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
/*
* Enable interrupts in the Processor.
*/
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
/*
* Initialize the timer with Timer Ticks
*/
scu_timer_init() ;
Xil_ExceptionEnable();
return 0;
}
#endif // PROC_CORTEXA9

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// $Id: _profile_timer_hw.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************
*
* _program_timer_hw.h:
* Timer related functions
*
******************************************************************************/
#ifndef _PROFILE_TIMER_HW_H
#define _PROFILE_TIMER_HW_H
#include "profile.h"
#ifdef PROC_PPC
#if defined __GNUC__
# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
#elif defined __DCC__
# define SYNCHRONIZE_IO __asm volatile(" eieio")
#else
# define SYNCHRONIZE_IO
#endif
#endif
#ifdef PROC_PPC
#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO;
#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
#else
#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); }
#endif
#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
ProfIo_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
(RegOffset)), (ValueToWrite))
#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
ProfIo_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + (RegOffset))
#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
(RegisterValue))
#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
ProfTimerCtr_mReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
#ifdef __cplusplus
extern "C" {
#endif
#ifdef PROC_PPC
#include "xexception_l.h"
#include "xtime_l.h"
#include "xpseudo_asm.h"
#endif
#ifdef TIMER_CONNECT_INTC
#include "xintc_l.h"
#include "xintc.h"
#endif // TIMER_CONNECT_INTC
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
#include "xtmrctr_l.h"
#endif
#ifdef PROC_CORTEXA9
#include "xscutimer_hw.h"
#include "xscugic.h"
#endif
extern unsigned int timer_clk_ticks ;
//--------------------------------------------------------------------
// PowerPC Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_PPC
#ifdef PPC_PIT_INTERRUPT
unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG
#endif
#ifdef PROC_PPC440
#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
#define XREG_SPR_PIT XREG_SPR_DEC
#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
#endif
//--------------------------------------------------------------------
// Disable the Timer - During Profiling
//
// For PIT Timer -
// 1. XTime_PITDisableInterrupt() ;
// 2. Store the remaining timer clk tick
// 3. Stop the PIT Timer
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
#define disable_timer() \
{ \
unsigned long val; \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_TCR, val & ~XREG_TCR_PIT_INTERRUPT_ENABLE); \
timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
mtspr(XREG_SPR_PIT, 0); \
}
#else
#define disable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
#endif
//--------------------------------------------------------------------
// Enable the Timer
//
// For PIT Timer -
// 1. Load the remaining timer clk ticks
// 2. XTime_PITEnableInterrupt() ;
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
#define enable_timer() \
{ \
unsigned long val; \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
}
#else
#define enable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
#endif
//--------------------------------------------------------------------
// Send Ack to Timer Interrupt
//
// For PIT Timer -
// 1. Load the timer clk ticks
// 2. Enable AutoReload and Interrupt
// 3. Clear PIT Timer Status bits
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
#define timer_ack() \
{ \
unsigned long val; \
mtspr(XREG_SPR_PIT, timer_clk_ticks); \
mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
}
#else
#define timer_ack() \
{ \
unsigned int csr; \
csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
}
#endif
//--------------------------------------------------------------------
#endif // PROC_PPC
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// MicroBlaze Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_MICROBLAZE
//--------------------------------------------------------------------
// Disable the Timer during Call-Graph Data collection
//
//--------------------------------------------------------------------
#define disable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
//--------------------------------------------------------------------
// Enable the Timer after Call-Graph Data collection
//
//--------------------------------------------------------------------
#define enable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
//--------------------------------------------------------------------
// Send Ack to Timer Interrupt
//
//--------------------------------------------------------------------
#define timer_ack() \
{ \
unsigned int csr; \
csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
}
//--------------------------------------------------------------------
#endif // PROC_MICROBLAZE
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// Cortex A9 Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_CORTEXA9
//--------------------------------------------------------------------
// Disable the Timer during Call-Graph Data collection
//
//--------------------------------------------------------------------
#define disable_timer() \
{ \
u32 Reg; \
Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
Reg &= ~XSCUTIMER_CONTROL_ENABLE_MASK;\
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
} \
//--------------------------------------------------------------------
// Enable the Timer after Call-Graph Data collection
//
//--------------------------------------------------------------------
#define enable_timer() \
{ \
u32 Reg; \
Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
} \
//--------------------------------------------------------------------
// Send Ack to Timer Interrupt
//
//--------------------------------------------------------------------
#define timer_ack() \
{ \
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_ISR_OFFSET, \
XSCUTIMER_ISR_EVENT_FLAG_MASK);\
}
//--------------------------------------------------------------------
#endif // PROC_CORTEXA9
//--------------------------------------------------------------------
#ifdef __cplusplus
}
#endif
#endif

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FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/dummy.S
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// $Id: dummy.S,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
.globl dummy_f
#ifdef PROC_MICROBLAZE
.text
.align 2
.ent dummy_f
dummy_f:
nop
.end dummy_f
#endif
#ifdef PROC_PPC
.section .text
.align 2
.type dummy_f@function
dummy_f:
b dummy_f
#endif
#ifdef PROC_CORTEXA9
.section .text
.align 2
.type dummy_f, %function
dummy_f:
b dummy_f
#endif

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FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/mblaze_nt_types.h
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// $Id: mblaze_nt_types.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef _MBLAZE_NT_TYPES_H
#define _MBLAZE_NT_TYPES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef char byte;
typedef short half;
typedef int word;
typedef unsigned char ubyte;
typedef unsigned short uhalf;
typedef unsigned int uword;
typedef ubyte boolean;
#ifdef __cplusplus
}
#endif
#endif

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FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile.h
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// $Id: profile.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef _PROFILE_H
#define _PROFILE_H 1
#include <stdio.h>
#include "profile_config.h"
#ifdef PROC_MICROBLAZE
#include "mblaze_nt_types.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
void _system_init( void ) ;
void _system_clean( void ) ;
void mcount(unsigned long frompc, unsigned long selfpc);
void profile_intr_handler( void ) ;
/****************************************************************************
* Profiling on hardware - Hash table maintained on hardware and data sent
* to xmd for gmon.out generation.
****************************************************************************/
/*
* histogram counters are unsigned shorts (according to the kernel).
*/
#define HISTCOUNTER unsigned short
struct tostruct {
unsigned long selfpc;
long count;
short link;
unsigned short pad;
};
struct fromstruct {
unsigned long frompc ;
short link ;
unsigned short pad ;
} ;
/*
* general rounding functions.
*/
#define ROUNDDOWN(x,y) (((x)/(y))*(y))
#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
/*
* The profiling data structures are housed in this structure.
*/
struct gmonparam {
long int state;
// Histogram Information
unsigned short *kcount; /* No. of bins in histogram */
unsigned long kcountsize; /* Histogram samples */
// Call-graph Information
struct fromstruct *froms;
unsigned long fromssize;
struct tostruct *tos;
unsigned long tossize;
// Initialization I/Ps
unsigned long lowpc;
unsigned long highpc;
unsigned long textsize;
//unsigned long cg_froms;
//unsigned long cg_tos;
};
extern struct gmonparam *_gmonparam;
extern int n_gmon_sections;
/*
* Possible states of profiling.
*/
#define GMON_PROF_ON 0
#define GMON_PROF_BUSY 1
#define GMON_PROF_ERROR 2
#define GMON_PROF_OFF 3
/*
* Sysctl definitions for extracting profiling information from the kernel.
*/
#define GPROF_STATE 0 /* int: profiling enabling variable */
#define GPROF_COUNT 1 /* struct: profile tick count buffer */
#define GPROF_FROMS 2 /* struct: from location hash bucket */
#define GPROF_TOS 3 /* struct: destination/count structure */
#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
#ifdef __cplusplus
}
#endif
#endif /* _PROFILE_H */

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FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_cg.c
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// $Id: profile_cg.c,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include "profile.h"
#include "_profile_timer_hw.h"
#ifdef PROC_MICROBLAZE
#include "mblaze_nt_types.h"
#endif
/*
* The mcount fucntion is excluded from the library, if the user defines
* PROFILE_NO_GRAPH.
*/
#ifndef PROFILE_NO_GRAPH
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
extern struct gmonparam *_gmonparam;
#ifdef PROFILE_NO_FUNCPTR
int searchpc( struct fromto_struct *cgtable, int cgtable_size, unsigned long frompc )
{
int index = 0 ;
while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){
index++ ;
}
if( index == cgtable_size )
return -1 ;
else
return index ;
}
#else
int searchpc( struct fromstruct *froms, int fromssize, unsigned long frompc )
{
int index = 0 ;
while( (index < fromssize) && (froms[index].frompc != frompc) ){
index++ ;
}
if( index == fromssize )
return -1 ;
else
return index ;
}
#endif /* PROFILE_NO_FUNCPTR */
void mcount( unsigned long frompc, unsigned long selfpc )
{
register struct gmonparam *p = NULL;
register long toindex, fromindex;
int j;
disable_timer();
//print("CG: "); putnum(frompc); print("->"); putnum(selfpc); print("\r\n");
// check that frompcindex is a reasonable pc value.
// for example: signal catchers get called from the stack,
// not from text space. too bad.
//
for(j = 0; j < n_gmon_sections; j++ ){
if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) {
p = &_gmonparam[j];
break;
}
}
if( j == n_gmon_sections )
goto done;
#ifdef PROFILE_NO_FUNCPTR
fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ;
if( fromindex == -1 ) {
fromindex = p->cgtable_size ;
p->cgtable_size++ ;
p->cgtable[fromindex].frompc = frompc ;
p->cgtable[fromindex].selfpc = selfpc ;
p->cgtable[fromindex].count = 1 ;
goto done ;
}
p->cgtable[fromindex].count++ ;
#else
fromindex = searchpc( p->froms, p->fromssize, frompc ) ;
if( fromindex == -1 ) {
fromindex = p->fromssize ;
p->fromssize++ ;
//if( fromindex >= N_FROMS ) {
//print("Error : From PC table overflow\r\n") ;
//goto overflow ;
//}
p->froms[fromindex].frompc = frompc ;
p->froms[fromindex].link = -1 ;
}else {
toindex = p->froms[fromindex].link ;
while(toindex != -1) {
toindex = (p->tossize - toindex)-1 ;
if( p->tos[toindex].selfpc == selfpc ) {
p->tos[toindex].count++ ;
goto done ;
}
toindex = p->tos[toindex].link ;
}
}
//if( toindex == -1 ) {
p->tos-- ;
p->tossize++ ;
//if( toindex >= N_TOS ) {
//print("Error : To PC table overflow\r\n") ;
//goto overflow ;
//}
p->tos[0].selfpc = selfpc ;
p->tos[0].count = 1 ;
p->tos[0].link = p->froms[fromindex].link ;
p->froms[fromindex].link = p->tossize-1 ;
#endif
done:
p->state = GMON_PROF_ON;
goto enable_timer ;
//overflow:
p->state = GMON_PROF_ERROR;
enable_timer:
enable_timer();
return ;
}
#endif /* PROFILE_NO_GRAPH */

49
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_config.h
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// $Id: profile_config.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef _PROFILE_CONFIG_H
#define _PROFILE_CONFIG_H
#define BINSIZE 4
#define SAMPLE_FREQ_HZ 100000
#define TIMER_CLK_TICKS 1000
#define PROFILE_NO_FUNCPTR_FLAG 0
#define PROFILE_TIMER_BASEADDR 0x00608000
#define PROFILE_TIMER_INTR_ID 0
#define TIMER_CONNECT_INTC
#endif

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FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_hist.c
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// $Id: profile_hist.c,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include "profile.h"
#include "_profile_timer_hw.h"
#ifdef PROC_MICROBLAZE
#include "mblaze_nt_types.h"
#endif
#ifdef PROC_PPC
#include "xpseudo_asm.h"
#define SPR_SRR0 0x01A
#endif
#include "xil_types.h"
extern int binsize ;
u32 prof_pc ;
void profile_intr_handler( void )
{
int j;
#ifdef PROC_MICROBLAZE
asm( "swi r14, r0, prof_pc" ) ;
#elif defined PROC_PPC
prof_pc = mfspr(SPR_SRR0);
#else
// for cortexa9, lr is saved in asm interrupt handler
#endif
//print("PC: "); putnum(prof_pc); print("\r\n");
for(j = 0; j < n_gmon_sections; j++ ){
if((prof_pc >= _gmonparam[j].lowpc) && (prof_pc < _gmonparam[j].highpc)) {
_gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/(4 * binsize)]++;
break;
}
}
// Ack the Timer Interrupt
timer_ack();
}

46
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_mcount_arm.S
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// $Id: profile_mcount_arm.S,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
// based on "ARM Profiling Implementation" from Sourcery G++ Lite for ARM EABI
.globl __gnu_mcount_nc
.type __gnu_mcount_nc, %function
__gnu_mcount_nc:
push {r0, r1, r2, r3, lr}
subs r1, lr, #0 /* callee - current lr */
ldr r0, [sp, #20] /* caller - at the top of the stack */
bl mcount /* when __gnu_mcount_nc is called */
pop {r0, r1, r2, r3, ip, lr}
bx ip
.end __gnu_mcount_nc

70
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_mcount_mb.S
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// $Id: profile_mcount_mb.S,v 1.1.2.1 2011/05/17 04:37:58 sadanan Exp $
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
.globl _mcount
.text
.align 2
.ent _mcount
#ifndef PROFILE_NO_GRAPH
_mcount:
addi r1, r1, -48
swi r11, r1, 44
swi r12, r1, 40
swi r5, r1, 36
swi r6, r1, 32
swi r7, r1, 28
swi r8, r1, 24
swi r9, r1, 20
swi r10, r1, 16
swi r15, r1, 12
add r6, r0, r15
brlid r15, mcount
lwi r5, r1, 48
lwi r11, r1, 44
lwi r12, r1, 40
lwi r5, r1, 36
lwi r6, r1, 32
lwi r7, r1, 28
lwi r8, r1, 24
lwi r9, r1, 20
lwi r10, r1, 16
lwi r15, r1, 12
rtsd r15, 4
addi r1, r1, 48
#endif /* PROFILE_NO_GRAPH */
.end _mcount

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