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New demo for M3 using LM3S811 and IAR tools.

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Richard Barry 18 years ago
parent f20d072c4a
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76
Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h
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/*
FreeRTOS.org V4.1.3 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7000 ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configUSE_CO_ROUTINES 1
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 0
#define INCLUDE_uxTaskPriorityGet 0
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 0
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

39
Demo/CORTEX_LM3S811_IAR/LuminaryCode/DriverLib.h
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#ifndef DRIVER_LIB_H
#define DRIVER_LIB_H
#include "DriverLib.h"
#include "hw_adc.h"
#include "hw_comp.h"
#include "hw_flash.h"
#include "hw_gpio.h"
#include "hw_i2c.h"
#include "hw_ints.h"
#include "hw_memmap.h"
#include "hw_nvic.h"
#include "hw_pwm.h"
#include "hw_qei.h"
#include "hw_ssi.h"
#include "hw_sysctl.h"
#include "hw_timer.h"
#include "hw_types.h"
#include "hw_uart.h"
#include "hw_watchdog.h"
#include "osram96x16.h"
#include "adc.h"
#include "comp.h"
#include "cpu.h"
#include "debug.h"
#include "flash.h"
#include "gpio.h"
#include "i2c.h"
#include "interrupt.h"
#include "pwm.h"
#include "qei.h"
#include "ssi.h"
#include "sysctl.h"
#include "systick.h"
#include "timer.h"
#include "uart.h"
#include "watchdog.h"
#endif

126
Demo/CORTEX_LM3S811_IAR/LuminaryCode/EULA.txt
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IMPORTANT. Read the following LMI Software License Agreement ("Agreement")
completely.
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This is a legal agreement between you (either as an individual or as an
authorized representative of your employer) and Luminary Micro, Inc. ("LMI").
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946
Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.c
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//*****************************************************************************
//
// adc.c - Driver for the ADC.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup adc_api
//! @{
//
//*****************************************************************************
#include "../hw_adc.h"
#include "../hw_ints.h"
#include "../hw_memmap.h"
#include "../hw_types.h"
#include "adc.h"
#include "debug.h"
#include "interrupt.h"
//*****************************************************************************
//
// The currently configured software oversampling factor for each of the ADC
// sequencers.
//
//*****************************************************************************
#if defined(GROUP_pucoverssamplefactor) || defined(BUILD_ALL)
unsigned char g_pucOversampleFactor[3];
#else
extern unsigned char g_pucOversampleFactor[3];
#endif
//*****************************************************************************
//
//! Registers an interrupt handler for an ADC interrupt.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//! \param pfnHandler is a pointer to the function to be called when the
//! ADC sample sequence interrupt occurs.
//!
//! This function sets the handler to be called when a sample sequence
//! interrupt occurs. This will enable the global interrupt in the interrupt
//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It
//! is the interrupt handler's responsibility to clear the interrupt source via
//! ADCIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
void (*pfnHandler)(void))
{
unsigned long ulInt;
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 4);
//
// Determine the interrupt to register based on the sequence number.
//
ulInt = INT_ADC0 + ulSequenceNum;
//
// Register the interrupt handler.
//
IntRegister(ulInt, pfnHandler);
//
// Enable the timer interrupt.
//
IntEnable(ulInt);
}
#endif
//*****************************************************************************
//
//! Unregisters the interrupt handler for an ADC interrupt.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This function unregisters the interrupt handler. This will disable the
//! global interrupt in the interrupt controller; the sequence interrupt must
//! be disabled via ADCIntDisable().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum)
{
unsigned long ulInt;
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 4);
//
// Determine the interrupt to unregister based on the sequence number.
//
ulInt = INT_ADC0 + ulSequenceNum;
//
// Disable the interrupt.
//
IntDisable(ulInt);
//
// Unregister the interrupt handler.
//
IntUnregister(ulInt);
}
#endif
//*****************************************************************************
//
//! Disables a sample sequence interrupt.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This function disables the requested sample sequence interrupt.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 4);
//
// Disable this sample sequence interrupt.
//
HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum);
}
#endif
//*****************************************************************************
//
//! Enables a sample sequence interrupt.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This function enables the requested sample sequence interrupt. Any
//! outstanding interrupts are cleared before enabling the sample sequence
//! interrupt.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 4);
//
// Clear any outstanding interrupts on this sample sequence.
//
HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;
//
// Enable this sample sequence interrupt.
//
HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum;
}
#endif
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the specified sample sequence.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//!
//! \return The current raw or masked interrupt status.
//
//*****************************************************************************
#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 4);
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + ADC_O_ISC) & (1 << ulSequenceNum));
}
else
{
return(HWREG(ulBase + ADC_O_RIS) & (1 << ulSequenceNum));
}
}
#endif
//*****************************************************************************
//
//! Clears sample sequence interrupt source.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! The specified sample sequence interrupt is cleared, so that it no longer
//! asserts. This must be done in the interrupt handler to keep it from being
//! called again immediately upon exit.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)
void
ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arugments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 4);
//
// Clear the interrupt.
//
HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;
}
#endif
//*****************************************************************************
//
//! Enables a sample sequence.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! Allows the specified sample sequence to be captured when its trigger is
//! detected. A sample sequence must be configured before it is enabled.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_sequenceenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arugments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 4);
//
// Enable the specified sequence.
//
HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum;
}
#endif
//*****************************************************************************
//
//! Disables a sample sequence.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! Prevents the specified sample sequence from being captured when its trigger
//! is detected. A sample sequence should be disabled before it is configured.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_sequencedisable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arugments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 4);
//
// Disable the specified sequences.
//
HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum);
}
#endif
//*****************************************************************************
//
//! Configures the trigger source and priority of a sample sequence.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//! \param ulTrigger is the trigger source that initiates the sample sequence;
//! must be one of the \b ADC_TRIGGER_* values.
//! \param ulPriority is the relative priority of the sample sequence with
//! respect to the other sample sequences.
//!
//! This function configures the initiation criteria for a sample sequence.
//! Valid sample sequences range from zero to three; sequence zero will capture
//! up to eight samples, sequences one and two will capture up to four samples,
//! and sequence three will capture a single sample. The trigger condition and
//! priority (with respect to other sample sequence execution) is set.
//!
//! The parameter \b ulTrigger can take on the following values:
//!
//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the
//! ADCProcessorTrigger() function.
//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog
//! comparator; configured with ComparatorConfigure().
//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog
//! comparator; configured with ComparatorConfigure().
//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog
//! comparator; configured with ComparatorConfigure().
//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port
//! B4 pin.
//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with
//! TimerControlTrigger().
//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator;
//! configured with PWMGenIntTrigEnable().
//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator;
//! configured with PWMGenIntTrigEnable().
//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator;
//! configured with PWMGenIntTrigEnable().
//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the
//! sample sequence to capture repeatedly (so long as
//! there is not a higher priority source active).
//!
//! Note that not all trigger sources are available on all Stellaris family
//! members; consult the data sheet for the device in question to determine the
//! availability of triggers.
//!
//! The parameter \b ulPriority is a value between 0 and 3, where 0 represents
//! the highest priority and 3 the lowest. Note that when programming the
//! priority among a set of sample sequences, each must have unique priority;
//! it is up to the caller to guarantee the uniqueness of the priorities.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_sequenceconfigure) || defined(BUILD_ALL) || defined(DOXYGEN)
void
ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
unsigned long ulTrigger, unsigned long ulPriority)
{
//
// Check the arugments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 4);
ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) ||
(ulTrigger == ADC_TRIGGER_COMP0) ||
(ulTrigger == ADC_TRIGGER_COMP1) ||
(ulTrigger == ADC_TRIGGER_COMP2) ||
(ulTrigger == ADC_TRIGGER_EXTERNAL) ||
(ulTrigger == ADC_TRIGGER_TIMER) ||
(ulTrigger == ADC_TRIGGER_PWM0) ||
(ulTrigger == ADC_TRIGGER_PWM1) ||
(ulTrigger == ADC_TRIGGER_PWM2) ||
(ulTrigger == ADC_TRIGGER_ALWAYS));
ASSERT(ulPriority < 4);
//
// Compute the shift for the bits that control this sample sequence.
//
ulSequenceNum *= 4;
//
// Set the trigger event for this sample sequence.
//
HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) &
~(0xf << ulSequenceNum)) |
((ulTrigger & 0xf) << ulSequenceNum));
//
// Set the priority for this sample sequence.
//
HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) &
~(0xf << ulSequenceNum)) |
((ulPriority & 0x3) << ulSequenceNum));
}
#endif
//*****************************************************************************
//
//! Configure a step of the sample sequencer.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//! \param ulStep is the step to be configured.
//! \param ulConfig is the configuration of this step; must be a logical OR of
//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the
//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH7).
//!
//! This function will set the configuration of the ADC for one step of a
//! sample sequence. The ADC can be configured for single-ended or
//! differential operation (the \b ADC_CTL_D bit selects differential
//! operation when set), the channel to be sampled can be chosen (the
//! \b ADC_CTL_CH0 through \b ADC_CTL_CH7 values), and the internal temperature
//! sensor can be selected (the \b ADC_CTL_TS bit). Additionally, this step
//! can be defined as the last in the sequence (the \b ADC_CTL_END bit) and it
//! can be configured to cause an interrupt when the step is complete (the
//! \b ADC_CTL_IE bit). The configuration is used by the ADC at the
//! appropriate time when the trigger for this sequence occurs.
//!
//! The \b ulStep parameter determines the order in which the samples are
//! captured by the ADC when the trigger occurs. It can range from zero to
//! seven for the first sample sequence, from zero to three for the second and
//! third sample sequence, and can only be zero for the fourth sample sequence.
//!
//! Differential mode only works with adjacent channel pairs (e.g. 0 and 1).
//! The channel select must be the number of the channel pair to sample (e.g.
//! \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2 and 3) or undefined
//! results will be returned by the ADC. Additionally, if differential mode is
//! selected when the temperature sensor is being sampled, undefined results
//! will be returned by the ADC.
//!
//! It is the responsibility of the caller to ensure that a valid configuration
//! is specified; this function does not check the validity of the specified
//! configuration.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_sequencestepconfigure) || defined(BUILD_ALL) || \
defined(DOXYGEN)
void
ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
unsigned long ulStep, unsigned long ulConfig)
{
//
// Check the arugments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 4);
ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) ||
((ulSequenceNum == 1) && (ulStep < 4)) ||
((ulSequenceNum == 2) && (ulStep < 4)) ||
((ulSequenceNum == 3) && (ulStep < 1)));
//
// Get the offset of the sequence to be configured.
//
ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum);
//
// Compute the shift for the bits that control this step.
//
ulStep *= 4;
//
// Set the analog mux value for this step.
//
HWREG(ulBase + ADC_O_X_SSMUX) = ((HWREG(ulBase + ADC_O_X_SSMUX) &
~(0x0000000f << ulStep)) |
((ulConfig & 0x0f) << ulStep));
//
// Set the control value for this step.
//
HWREG(ulBase + ADC_O_X_SSCTL) = ((HWREG(ulBase + ADC_O_X_SSCTL) &
~(0x0000000f << ulStep)) |
(((ulConfig & 0xf0) >> 4) << ulStep));
}
#endif
//*****************************************************************************
//
//! Determines if a sample sequence overflow occurred.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This determines if a sample sequence overflow has occurred. This will
//! happen if the captured samples are not read from the FIFO before the next
//! trigger occurs.
//!
//! \return Returns zero if there was not an overflow, and non-zero if there
//! was.
//
//*****************************************************************************
#if defined(GROUP_sequenceoverflow) || defined(BUILD_ALL) || defined(DOXYGEN)
long
ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 4);
//
// Determine if there was an overflow on this sequence.
//
return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum));
}
#endif
//*****************************************************************************
//
//! Determines if a sample sequence underflow occurred.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This determines if a sample sequence underflow has occurred. This will
//! happen if too many samples are read from the FIFO.
//!
//! \return Returns zero if there was not an underflow, and non-zero if there
//! was.
//
//*****************************************************************************
#if defined(GROUP_sequenceunderflow) || defined(BUILD_ALL) || defined(DOXYGEN)
long
ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 4);
//
// Determine if there was an underflow on this sequence.
//
return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum));
}
#endif
//*****************************************************************************
//
//! Gets the captured data for a sample sequence.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//! \param pulBuffer is the address where the data is stored.
//!
//! This function copies data from the specified sample sequence output FIFO to
//! a memory resident buffer. The number of samples available in the hardware
//! FIFO are copied into the buffer, which is assumed to be large enough to
//! hold that many samples. This will only return the samples that are
//! presently available, which may not be the entire sample sequence if it is
//! in the process of being executed.
//!
//! \return Returns the number of samples copied to the buffer.
//
//*****************************************************************************
#if defined(GROUP_sequencedataget) || defined(BUILD_ALL) || defined(DOXYGEN)
long
ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
unsigned long *pulBuffer)
{
unsigned long ulCount;
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 4);
//
// Get the offset of the sequence to be read.
//
ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum);
//
// Read samples from the FIFO until it is empty.
//
ulCount = 0;
while(!(HWREG(ulBase + ADC_O_X_SSFSTAT) & ADC_SSFSTAT_EMPTY) &&
(ulCount < 8))
{
//
// Read the FIFO and copy it to the destination.
//
*pulBuffer++ = HWREG(ulBase + ADC_O_X_SSFIFO);
//
// Increment the count of samples read.
//
ulCount++;
}
//
// Return the number of samples read.
//
return(ulCount);
}
#endif
//*****************************************************************************
//
//! Causes a processor trigger for a sample sequence.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This function triggers a processor-initiated sample sequence if the sample
//! sequence trigger is configured to ADC_TRIGGER_PROCESSOR.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_processortrigger) || defined(BUILD_ALL) || defined(DOXYGEN)
void
ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 4);
//
// Generate a processor trigger for this sample sequence.
//
HWREG(ulBase + ADC_O_PSSI) = 1 << ulSequenceNum;
}
#endif
//*****************************************************************************
//
//! Configures the software oversampling factor of the ADC.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//! \param ulFactor is the number of samples to be averaged.
//!
//! This function configures the software oversampling for the ADC, which can
//! be used to provide better resolution on the sampled data. Oversampling is
//! accomplished by averaging multiple samples from the same analog input.
//! Three different oversampling rates are supported; 2x, 4x, and 8x.
//!
//! Oversampling is only supported on the sample sequencers that are more than
//! one sample in depth (i.e. the fourth sample sequencer is not supported).
//! Oversampling by 2x (for example) divides the depth of the sample sequencer
//! by two; so 2x oversampling on the first sample sequencer can only provide
//! four samples per trigger. This also means that 8x oversampling is only
//! available on the first sample sequencer.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_softwareoversampleconfigure) || defined(BUILD_ALL) || \
defined(DOXYGEN)
void
ADCSoftwareOversampleConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulFactor)
{
unsigned long ulValue;
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 3);
ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) &&
((ulSequenceNum == 0) || (ulFactor != 8)));
//
// Convert the oversampling factor to a shift factor.
//
for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)
{
}
//
// Save the sfiht factor.
//
g_pucOversampleFactor[ulSequenceNum] = ulValue;
}
#endif
//*****************************************************************************
//
//! Configures a step of the software oversampled sequencer.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//! \param ulStep is the step to be configured.
//! \param ulConfig is the configuration of this step.
//!
//! This function configures a step of the sample sequencer when using the
//! software oversampling feature. The number of steps available depends on
//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value
//! of \e ulConfig is the same as defined for ADCSequenceStepConfigure().
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_softwareoversamplestepconfigure) || defined(BUILD_ALL) || \
defined(DOXYGEN)
void
ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig)
{
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 3);
ASSERT(((ulSequenceNum == 0) &&
(ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
(ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum])));
//
// Get the offset of the sequence to be configured.
//
ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum);
//
// Compute the shift for the bits that control this step.
//
ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum];
//
// Loop through the hardware steps that make up this step of the software
// oversampled sequence.
//
for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum];
ulSequenceNum; ulSequenceNum--)
{
//
// Set the analog mux value for this step.
//
HWREG(ulBase + ADC_O_X_SSMUX) = ((HWREG(ulBase + ADC_O_X_SSMUX) &
~(0x0000000f << ulStep)) |
((ulConfig & 0x0f) << ulStep));
//
// Set the control value for this step.
//
HWREG(ulBase + ADC_O_X_SSCTL) = ((HWREG(ulBase + ADC_O_X_SSCTL) &
~(0x0000000f << ulStep)) |
(((ulConfig & 0xf0) >> 4) << ulStep));
if(ulSequenceNum != 1)
{
HWREG(ulBase + ADC_O_X_SSCTL) &= ~((ADC_SSCTL_IE0 |
ADC_SSCTL_END0) << ulStep);
}
//
// Go to the next hardware step.
//
ulStep += 4;
}
}
#endif
//*****************************************************************************
//
//! Gets the captured data for a sample sequence using software oversampling.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//! \param pulBuffer is the address where the data is stored.
//! \param ulCount is the number of samples to be read.
//!
//! This function copies data from the specified sample sequence output FIFO to
//! a memory resident buffer with software oversampling applied. The requested
//! number of samples are copied into the data buffer; if there are not enough
//! samples in the hardware FIFO to satisfy this many oversampled data items
//! then incorrect results will be returned. It is the caller's responsibility
//! to read only the samples that are available and wait until enough data is
//! available, for example as a result of receiving an interrupt.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_softwareoversampledataget) || defined(BUILD_ALL) || \
defined(DOXYGEN)
void
ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
unsigned long *pulBuffer, unsigned long ulCount)
{
unsigned long ulIdx, ulAccum;
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(ulSequenceNum < 3);
ASSERT(((ulSequenceNum == 0) &&
(ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
(ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum])));
//
// Get the offset of the sequence to be read.
//
ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum);
//
// Read the samples from the FIFO until it is empty.
//
while(ulCount--)
{
//
// Compute the sum of the samples.
//
ulAccum = 0;
for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--)
{
//
// Read the FIFO and add it to the accumulator.
//
ulAccum += HWREG(ulBase + ADC_O_X_SSFIFO);
}
//
// Write the averaged sample to the output buffer.
//
*pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum];
}
}
#endif
//*****************************************************************************
//
//! Configures the hardware oversampling factor of the ADC.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulFactor is the number of samples to be averaged.
//!
//! This function configures the hardware oversampling for the ADC, which can
//! be used to provide better resolution on the sampled data. Oversampling is
//! accomplished by averaging multiple samples from the same analog input. Six
//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x.
//! Specifying an oversampling factor of zero will disable the hardware
//! oversampler.
//!
//! Hardware oversampling applies uniformly to all sample sequencers. It does
//! not reduce the depth of the sample sequencers like the software
//! oversampling APIs; each sample written into the sample sequence FIFO is a
//! fully oversampled analog input reading.
//!
//! Enabling hardware averaging increases the precision of the ADC at the cost
//! of throughput. For example, enabling 4x oversampling reduces the
//! throughput of a 250 KSps ADC to 62.5 KSps.
//!
//! \note Hardware oversampling is available beginning with Rev C0 of the
//! Stellaris microcontroller.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_hardwareoversampleconfigure) || defined(BUILD_ALL) || \
defined(DOXYGEN)
void
ADCHardwareOversampleConfigure(unsigned long ulBase,
unsigned long ulFactor)
{
unsigned long ulValue;
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) ||
(ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) ||
(ulFactor == 64)));
//
// Convert the oversampling factor to a shift factor.
//
for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)
{
}
//
// Write the shift factor to the ADC to configure the hardware oversampler.
//
HWREG(ulBase + ADC_O_SAC) = ulValue;
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.h
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//*****************************************************************************
//
// adc.h - ADC headers for using the ADC driver functions.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __ADC_H__
#define __ADC_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ADCSequenceConfigure as the ulTrigger
// parameter.
//
//*****************************************************************************
#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
//*****************************************************************************
//
// Values that can be passed to ADCSequenceStepConfigure as the ulConfig
// parameter.
//
//*****************************************************************************
#define ADC_CTL_TS 0x00000080 // Temperature sensor select
#define ADC_CTL_IE 0x00000040 // Interrupt enable
#define ADC_CTL_END 0x00000020 // Sequence end select
#define ADC_CTL_D 0x00000010 // Differential select
#define ADC_CTL_CH0 0x00000000 // Input channel 0
#define ADC_CTL_CH1 0x00000001 // Input channel 1
#define ADC_CTL_CH2 0x00000002 // Input channel 2
#define ADC_CTL_CH3 0x00000003 // Input channel 3
#define ADC_CTL_CH4 0x00000004 // Input channel 4
#define ADC_CTL_CH5 0x00000005 // Input channel 5
#define ADC_CTL_CH6 0x00000006 // Input channel 6
#define ADC_CTL_CH7 0x00000007 // Input channel 7
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
void (*pfnHandler)(void));
extern void ADCIntUnregister(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);
extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);
extern unsigned long ADCIntStatus(unsigned long ulBase,
unsigned long ulSequenceNum,
tBoolean bMasked);
extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);
extern void ADCSequenceEnable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceDisable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulTrigger,
unsigned long ulPriority);
extern void ADCSequenceStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig);
extern long ADCSequenceOverflow(unsigned long ulBase,
unsigned long ulSequenceNum);
extern long ADCSequenceUnderflow(unsigned long ulBase,
unsigned long ulSequenceNum);
extern long ADCSequenceDataGet(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long *pulBuffer);
extern void ADCProcessorTrigger(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulFactor);
extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig);
extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long *pulBuffer,
unsigned long ulCount);
extern void ADCHardwareOversampleConfigure(unsigned long ulBase,
unsigned long ulFactor);
#ifdef __cplusplus
}
#endif
#endif // __ADC_H__

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//*****************************************************************************
//
// comp.c - Driver for the analog comparator.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup comp_api
//! @{
//
//*****************************************************************************
#include "../hw_comp.h"
#include "../hw_ints.h"
#include "../hw_memmap.h"
#include "../hw_types.h"
#include "comp.h"
#include "debug.h"
#include "interrupt.h"
//*****************************************************************************
//
//! Configures a comparator.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator to configure.
//! \param ulConfig is the configuration of the comparator.
//!
//! This function will configure a comparator. The \e ulConfig parameter is
//! the result of a logical OR operation between the \b COMP_TRIG_xxx,
//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values.
//!
//! The \b COMP_TRIG_xxx term can take on the following values:
//!
//! - \b COMP_TRIG_NONE to have no trigger to the ADC.
//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high.
//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low.
//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low.
//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes
//! high.
//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low
//! or high.
//!
//! The \b COMP_INT_xxx term can take on the following values:
//!
//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is
//! high.
//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is
//! low.
//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes
//! low.
//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes
//! high.
//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes
//! low or high.
//!
//! The \b COMP_ASRCP_xxx term can take on the following values:
//!
//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference
//! voltage.
//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this
//! the same as \b COMP_ASRCP_PIN for the comparator 0).
//! - \b COMP_ASRCP_REF to use the internally generated voltage as the
//! reference voltage.
//!
//! The \b COMP_OUTPUT_xxx term can take on the following values:
//!
//! - \b COMP_OUTPUT_NONE to disable the output from the comparator to a device
//! pin.
//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator
//! to a device pin.
//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to
//! a device pin.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN)
void
ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
unsigned long ulConfig)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Configure this comparator.
//
HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACCTL0) = ulConfig;
}
#endif
//*****************************************************************************
//
//! Sets the internal reference voltage.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulRef is the desired reference voltage.
//!
//! This function will set the internal reference voltage value. The voltage
//! is specified as one of the following values:
//!
//! - \b COMP_REF_OFF to turn off the reference voltage
//! - \b COMP_REF_0V to set the reference voltage to 0 V
//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V
//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V
//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V
//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V
//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V
//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V
//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V
//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V
//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V
//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V
//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V
//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V
//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V
//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V
//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V
//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V
//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V
//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V
//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V
//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V
//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V
//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V
//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V
//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V
//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V
//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V
//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_refset) || defined(BUILD_ALL) || defined(DOXYGEN)
void
ComparatorRefSet(unsigned long ulBase, unsigned long ulRef)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
//
// Set the voltage reference voltage as requested.
//
HWREG(ulBase + COMP_O_REFCTL) = ulRef;
}
#endif
//*****************************************************************************
//
//! Gets the current comparator output value.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! This function retrieves the current value of the comparator output.
//!
//! \return Returns \b true if the comparator output is high and \b false if
//! the comparator output is low.
//
//*****************************************************************************
#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN)
tBoolean
ComparatorValueGet(unsigned long ulBase, unsigned long ulComp)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Return the appropriate value based on the comparator's present output
// value.
//
if(HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACSTAT0) & COMP_ACSTAT_OVAL)
{
return(true);
}
else
{
return(false);
}
}
#endif
//*****************************************************************************
//
//! Registers an interrupt handler for the comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//! \param pfnHandler is a pointer to the function to be called when the
//! comparator interrupt occurs.
//!
//! This sets the handler to be called when the comparator interrupt occurs.
//! This will enable the interrupt in the interrupt controller; it is the
//! interrupt-handler's responsibility to clear the interrupt source via
//! ComparatorIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(INT_COMP0 + ulComp, pfnHandler);
//
// Enable the interrupt in the interrupt controller.
//
IntEnable(INT_COMP0 + ulComp);
//
// Enable the comparator interrupt.
//
HWREG(ulBase + COMP_O_INTEN) |= 1 << ulComp;
}
#endif
//*****************************************************************************
//
//! Unregisters an interrupt handler for a comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! This function will clear the handler to be called when a comparator
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Disable the comparator interrupt.
//
HWREG(ulBase + COMP_O_INTEN) &= ~(1 << ulComp);
//
// Disable the interrupt in the interrupt controller.
//
IntDisable(INT_COMP0 + ulComp);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_COMP0 + ulComp);
}
#endif
//*****************************************************************************
//
//! Enables the comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! This function enables generation of an interrupt from the specified
//! comparator. Only comparators whose interrupts are enabled can be reflected
//! to the processor.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Enable the comparator interrupt.
//
HWREG(ulBase + COMP_O_INTEN) |= 1 << ulComp;
}
#endif
//*****************************************************************************
//
//! Disables the comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! This function disables generation of an interrupt from the specified
//! comparator. Only comparators whose interrupts are enabled can be reflected
//! to the processor.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Disable the comparator interrupt.
//
HWREG(ulBase + COMP_O_INTEN) &= ~(1 << ulComp);
}
#endif
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This returns the interrupt status for the comparator. Either the raw or
//! the masked interrupt status can be returned.
//!
//! \return \b true if the interrupt is asserted and \b false if it is not
//! asserted.
//
//*****************************************************************************
#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
tBoolean
ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(((HWREG(ulBase + COMP_O_MIS) >> ulComp) & 1) ? true : false);
}
else
{
return(((HWREG(ulBase + COMP_O_RIS) >> ulComp) & 1) ? true : false);
}
}
#endif
//*****************************************************************************
//
//! Clears a comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! The comparator interrupt is cleared, so that it no longer asserts. This
//! must be done in the interrupt handler to keep it from being called again
//! immediately upon exit. Note that for a level triggered interrupt, the
//! interrupt cannot be cleared until it stops asserting.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)
void
ComparatorIntClear(unsigned long ulBase, unsigned long ulComp)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Clear the interrupt.
//
HWREG(ulBase + COMP_O_MIS) = 1 << ulComp;
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// comp.h - Prototypes for the analog comparator driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __COMP_H__
#define __COMP_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ComparatorConfigure() as the ulConfig
// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of
// the values may be selected and ORed together will values from the other
// groups.
//
//*****************************************************************************
#define COMP_TRIG_NONE 0x00000000 // No ADC trigger
#define COMP_TRIG_HIGH 0x00000880 // Trigger when high
#define COMP_TRIG_LOW 0x00000800 // Trigger when low
#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge
#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge
#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges
#define COMP_INT_HIGH 0x00000010 // Interrupt when high
#define COMP_INT_LOW 0x00000000 // Interrupt when low
#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_OUTPUT_NONE 0x00000000 // No comparator output
#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal
#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted
//*****************************************************************************
//
// Values that can be passed to ComparatorSetRef() as the ulRef parameter.
//
//*****************************************************************************
#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
#define COMP_REF_0V 0x00000300 // Internal reference of 0V
#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
unsigned long ulConfig);
extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);
extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
void (*pfnHandler)(void));
extern void ComparatorIntUnregister(unsigned long ulBase,
unsigned long ulComp);
extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);
extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
tBoolean bMasked);
extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);
#ifdef __cplusplus
}
#endif
#endif // __COMP_H__

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//*****************************************************************************
//
// cpu.h - Prototypes for the CPU instruction wrapper functions.
//
// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __CPU_H__
#define __CPU_H__
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern void CPUcpsid(void);
extern void CPUcpsie(void);
extern void CPUwfi(void);
#endif // __CPU_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/debug.h
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//*****************************************************************************
//
// debug.h - Macros for assisting debug of the driver library.
//
// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __DEBUG_H__
#define __DEBUG_H__
//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API. This is only used when doing a DEBUG build.
//
//*****************************************************************************
extern void __error__(char *pcFilename, unsigned long ulLine);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#define ASSERT(expr) { \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
}
#else
#define ASSERT(expr)
#endif
#endif // __DEBUG_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/flash.c
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//*****************************************************************************
//
// flash.c - Driver for programming the on-chip flash.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup flash_api
//! @{
//
//*****************************************************************************
#include "../hw_flash.h"
#include "../hw_ints.h"
#include "../hw_memmap.h"
#include "../hw_sysctl.h"
#include "../hw_types.h"
#include "debug.h"
#include "flash.h"
#include "interrupt.h"
//*****************************************************************************
//
//! Gets the number of processor clocks per micro-second.
//!
//! This function returns the number of clocks per micro-second, as presently
//! known by the flash controller.
//!
//! \return Returns the number of processor clocks per micro-second.
//
//*****************************************************************************
#if defined(GROUP_usecget) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
FlashUsecGet(void)
{
//
// Return the number of clocks per micro-second.
//
return(HWREG(FLASH_USECRL) + 1);
}
#endif
//*****************************************************************************
//
//! Sets the number of processor clocks per micro-second.
//!
//! \param ulClocks is the number of processor clocks per micro-second.
//!
//! This function is used to tell the flash controller the number of processor
//! clocks per micro-second. This value must be programmed correctly or the
//! flash most likely will not program correctly; it has no affect on reading
//! flash.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_usecset) || defined(BUILD_ALL) || defined(DOXYGEN)
void
FlashUsecSet(unsigned long ulClocks)
{
//
// Set the number of clocks per micro-second.
//
HWREG(FLASH_USECRL) = ulClocks - 1;
}
#endif
//*****************************************************************************
//
//! Erases a block of flash.
//!
//! \param ulAddress is the start address of the flash block to be erased.
//!
//! This function will erase a 1 kB block of the on-chip flash. After erasing,
//! the block will be filled with 0xFF bytes. Read-only and execute-only
//! blocks cannot be erased.
//!
//! This function will not return until the block has been erased.
//!
//! \return Returns 0 on success, or -1 if an invalid block address was
//! specified or the block is write-protected.
//
//*****************************************************************************
#if defined(GROUP_erase) || defined(BUILD_ALL) || defined(DOXYGEN)
long
FlashErase(unsigned long ulAddress)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1)));
//
// Clear the flash access interrupt.
//
HWREG(FLASH_FCMISC) = FLASH_FCMISC_ACCESS;
//
// Erase the block.
//
HWREG(FLASH_FMA) = ulAddress;
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE;
//
// Wait until the word has been programmed.
//
while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE)
{
}
//
// Return an error if an access violation occurred.
//
if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ACCESS)
{
return(-1);
}
//
// Success.
//
return(0);
}
#endif
//*****************************************************************************
//
//! Programs flash.
//!
//! \param pulData is a pointer to the data to be programmed.
//! \param ulAddress is the starting address in flash to be programmed. Must
//! be a multiple of four.
//! \param ulCount is the number of bytes to be programmed. Must be a multiple
//! of four.
//!
//! This function will program a sequence of words into the on-chip flash.
//! Programming each location consists of the result of an AND operation
//! of the new data and the existing data; in other words bits that contain
//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed
//! to 1. Therefore, a word can be programmed multiple times as long as these
//! rules are followed; if a program operation attempts to change a 0 bit to
//! a 1 bit, that bit will not have its value changed.
//!
//! Since the flash is programmed one word at a time, the starting address and
//! byte count must both be multiples of four. It is up to the caller to
//! verify the programmed contents, if such verification is required.
//!
//! This function will not return until the data has been programmed.
//!
//! \return Returns 0 on success, or -1 if a programming error is encountered.
//
//*****************************************************************************
#if defined(GROUP_program) || defined(BUILD_ALL) || defined(DOXYGEN)
long
FlashProgram(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & 3));
ASSERT(!(ulCount & 3));
//
// Clear the flash access interrupt.
//
HWREG(FLASH_FCMISC) = FLASH_FCMISC_ACCESS;
//
// Loop over the words to be programmed.
//
while(ulCount)
{
//
// Program the next word.
//
HWREG(FLASH_FMA) = ulAddress;
HWREG(FLASH_FMD) = *pulData;
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE;
//
// Wait until the word has been programmed.
//
while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE)
{
}
//
// Increment to the next word.
//
pulData++;
ulAddress += 4;
ulCount -= 4;
}
//
// Return an error if an access violation occurred.
//
if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ACCESS)
{
return(-1);
}
//
// Success.
//
return(0);
}
#endif
//*****************************************************************************
//
//! Gets the protection setting for a block of flash.
//!
//! \param ulAddress is the start address of the flash block to be queried.
//!
//! This function will get the current protection for the specified 2 kB block
//! of flash. Each block can be read/write, read-only, or execute-only.
//! Read/write blocks can be read, executed, erased, and programmed. Read-only
//! blocks can be read and executed. Execute-only blocks can only be executed;
//! processor and debugger data reads are not allowed.
//!
//! \return Returns the protection setting for this block. See
//! FlashProtectSet() for possible values.
//
//*****************************************************************************
#if defined(GROUP_protectget) || defined(BUILD_ALL) || defined(DOXYGEN)
tFlashProtection
FlashProtectGet(unsigned long ulAddress)
{
unsigned long ulFMPRE, ulFMPPE;
//
// Check the argument.
//
ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
//
// Read the flash protection register and get the bits that apply to the
// specified block.
//
ulFMPRE = HWREG(FLASH_FMPRE);
ulFMPPE = HWREG(FLASH_FMPPE);
switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) &
FLASH_FMP_BLOCK_0) << 1) |
((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0))
{
//
// This block is marked as execute only (i.e. it can not be erased or
// programmed, and the only reads allowed are via the instruction fecth
// interface).
//
case 0:
case 1:
{
return(FlashExecuteOnly);
}
//
// This block is marked as read only (i.e. it can not be erased or
// programmed).
//
case 2:
{
return(FlashReadOnly);
}
//
// This block is read/write; it can be read, erased, and programmed.
//
case 3:
default:
{
return(FlashReadWrite);
}
}
}
#endif
//*****************************************************************************
//
//! Sets the protection setting for a block of flash.
//!
//! \param ulAddress is the start address of the flash block to be protected.
//! \param eProtect is the protection to be applied to the block. Can be one
//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly.
//!
//! This function will set the protection for the specified 2 kB block of
//! flash. Blocks which are read/write can be made read-only or execute-only.
//! Blocks which are read-only can be made execute-only. Blocks which are
//! execute-only cannot have their protection modified. Attempts to make the
//! block protection less stringent (i.e. read-only to read/write) will result
//! in a failure (and be prevented by the hardware).
//!
//! Changes to the flash protection are maintained only until the next reset.
//! This allows the application to be executed in the desired flash protection
//! environment to check for inappropriate flash access (via the flash
//! interrupt). To make the flash protection permanent, use the
//! FlashProtectSave() function.
//!
//! \return Returns 0 on success, or -1 if an invalid address or an invalid
//! protection was specified.
//
//*****************************************************************************
#if defined(GROUP_protectset) || defined(BUILD_ALL) || defined(DOXYGEN)
long
FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
{
unsigned long ulProtectRE, ulProtectPE;
//
// Check the argument.
//
ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) ||
(eProtect == FlashExecuteOnly));
//
// Convert the address into a block number.
//
ulAddress /= FLASH_PROTECT_SIZE;
//
// Get the current protection.
//
ulProtectRE = HWREG(FLASH_FMPRE);
ulProtectPE = HWREG(FLASH_FMPPE);
//
// Set the protection based on the requested proection.
//
switch(eProtect)
{
//
// Make this block execute only.
//
case FlashExecuteOnly:
{
//
// Turn off the read and program bits for this block.
//
ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
//
// We're done handling this protection.
//
break;
}
//
// Make this block read only.
//
case FlashReadOnly:
{
//
// The block can not be made read only if it is execute only.
//
if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
FLASH_FMP_BLOCK_0)
{
return(-1);
}
//
// Make this block read only.
//
ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
//
// We're done handling this protection.
//
break;
}
//
// Make this block read/write.
//
case FlashReadWrite:
default:
{
//
// The block can not be made read/write if it is not already
// read/write.
//
if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
FLASH_FMP_BLOCK_0) ||
(((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
FLASH_FMP_BLOCK_0))
{
return(-1);
}
//
// The block is already read/write, so there is nothing to do.
//
return(0);
}
}
//
// Set the new protection.
//
HWREG(FLASH_FMPRE) = ulProtectRE;
HWREG(FLASH_FMPPE) = ulProtectPE;
//
// Success.
//
return(0);
}
#endif
//*****************************************************************************
//
//! Saves the flash protection settings.
//!
//! This function will make the currently programmed flash protection settings
//! permanent. This is a non-reversible operation; a chip reset or power cycle
//! will not change the flash protection.
//!
//! This function will not return until the protection has been saved.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
//*****************************************************************************
#if defined(GROUP_protectsave) || defined(BUILD_ALL) || defined(DOXYGEN)
long
FlashProtectSave(void)
{
//
// Tell the flash controller to write the flash read protection register.
//
HWREG(FLASH_FMA) = 0;
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
//
// Wait until the write has completed.
//
while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
{
}
//
// Tell the flash controller to write the flash program protection
// register.
//
HWREG(FLASH_FMA) = 1;
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
//
// Wait until the write has completed.
//
while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
{
}
//
// Success.
//
return(0);
}
#endif
//*****************************************************************************
//
//! Registers an interrupt handler for the flash interrupt.
//!
//! \param pfnHandler is a pointer to the function to be called when the flash
//! interrupt occurs.
//!
//! This sets the handler to be called when the flash interrupt occurs. The
//! flash controller can generate an interrupt when an invalid flash access
//! occurs, such as trying to program or erase a read-only block, or trying to
//! read from an execute-only block. It can also generate an interrupt when a
//! program or erase operation has completed. The interrupt will be
//! automatically enabled when the handler is registered.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
FlashIntRegister(void (*pfnHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(INT_FLASH, pfnHandler);
//
// Enable the flash interrupt.
//
IntEnable(INT_FLASH);
}
#endif
//*****************************************************************************
//
//! Unregisters the interrupt handler for the flash interrupt.
//!
//! This function will clear the handler to be called when the flash interrupt
//! occurs. This will also mask off the interrupt in the interrupt controller
//! so that the interrupt handler is no longer called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
FlashIntUnregister(void)
{
//
// Disable the interrupt.
//
IntDisable(INT_FLASH);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_FLASH);
}
#endif
//*****************************************************************************
//
//! Enables individual flash controller interrupt sources.
//!
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values.
//!
//! Enables the indicated flash controller interrupt sources. Only the sources
//! that are enabled can be reflected to the processor interrupt; disabled
//! sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
FlashIntEnable(unsigned long ulIntFlags)
{
//
// Enable the specified interrupts.
//
HWREG(FLASH_FCIM) |= ulIntFlags;
}
#endif
//*****************************************************************************
//
//! Disables individual flash controller interrupt sources.
//!
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values.
//!
//! Disables the indicated flash controller interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
FlashIntDisable(unsigned long ulIntFlags)
{
//
// Disable the specified interrupts.
//
HWREG(FLASH_FCIM) &= ~(ulIntFlags);
}
#endif
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the flash controller. Either the raw
//! interrupt status or the status of interrupts that are allowed to reflect to
//! the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! \b FLASH_FCMISC_PROGRAM and \b FLASH_FCMISC_ACCESS.
//
//*****************************************************************************
#if defined(GROUP_intgetstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
FlashIntGetStatus(tBoolean bMasked)
{
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(FLASH_FCMISC));
}
else
{
return(HWREG(FLASH_FCRIS));
}
}
#endif
//*****************************************************************************
//
//! Clears flash controller interrupt sources.
//!
//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
//! Can be any of the \b FLASH_FCMISC_PROGRAM or \b FLASH_FCMISC_ACCESS
//! values.
//!
//! The specified flash controller interrupt sources are cleared, so that they
//! no longer assert. This must be done in the interrupt handler to keep it
//! from being called again immediately upon exit.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)
void
FlashIntClear(unsigned long ulIntFlags)
{
//
// Clear the flash interrupt.
//
HWREG(FLASH_FCMISC) = ulIntFlags;
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// flash.h - Prototypes for the flash driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __FLASH_H__
#define __FLASH_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to FlashProtectSet(), and returned by
// FlashProtectGet().
//
//*****************************************************************************
typedef enum
{
FlashReadWrite, // Flash can be read and written
FlashReadOnly, // Flash can only be read
FlashExecuteOnly // Flash can only be executed
}
tFlashProtection;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long FlashUsecGet(void);
extern void FlashUsecSet(unsigned long ulClocks);
extern long FlashErase(unsigned long ulAddress);
extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount);
extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
extern long FlashProtectSet(unsigned long ulAddress,
tFlashProtection eProtect);
extern long FlashProtectSave(void);
extern void FlashIntRegister(void (*pfnHandler)(void));
extern void FlashIntUnregister(void);
extern void FlashIntEnable(unsigned long ulIntFlags);
extern void FlashIntDisable(unsigned long ulIntFlags);
extern unsigned long FlashIntGetStatus(tBoolean bMasked);
extern void FlashIntClear(unsigned long ulIntFlags);
#ifdef __cplusplus
}
#endif
#endif // __FLASH_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.h
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//*****************************************************************************
//
// gpio.h - Defines and Macros for GPIO API.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __GPIO_H__
#define __GPIO_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following values define the bit field for the ucPins argument to several
// of the APIs.
//
//*****************************************************************************
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
//*****************************************************************************
//
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
// returned from GPIODirModeGet.
//
//*****************************************************************************
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
//*****************************************************************************
//
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
// returned from GPIOIntTypeGet.
//
//*****************************************************************************
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
// and returned by GPIOPadConfigGet in the *pulStrength parameter.
//
//*****************************************************************************
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
// and returned by GPIOPadConfigGet in the *pulPadType parameter.
//
//*****************************************************************************
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulPinIO);
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulIntType);
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulStrength,
unsigned long ulPadType);
extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
unsigned long *pulStrength,
unsigned long *pulPadType);
extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPortIntRegister(unsigned long ulPort,
void (*pfIntHandler)(void));
extern void GPIOPortIntUnregister(unsigned long ulPort);
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
unsigned char ucVal);
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
#ifdef __cplusplus
}
#endif
#endif // __GPIO_H__

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//*****************************************************************************
//
// hw_adc.h - Macros used when accessing the ADC hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_ADC_H__
#define __HW_ADC_H__
//*****************************************************************************
//
// The following define the offsets of the ADC registers.
//
//*****************************************************************************
#define ADC_O_ACTSS 0x00000000 // Active sample register
#define ADC_O_RIS 0x00000004 // Raw interrupt status register
#define ADC_O_IM 0x00000008 // Interrupt mask register
#define ADC_O_ISC 0x0000000C // Interrupt status/clear register
#define ADC_O_OSTAT 0x00000010 // Overflow status register
#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg.
#define ADC_O_USTAT 0x00000018 // Underflow status register
#define ADC_O_SSPRI 0x00000020 // Channel priority register
#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg.
#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg.
#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register
#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg.
#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register
#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register
#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register
#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg.
#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register
#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register
#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register
#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg.
#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register
#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register
#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register
#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg.
#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register
#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register
#define ADC_O_TMLB 0x00000100 // Test mode loopback register
//*****************************************************************************
//
// The following define the offsets of the ADC sequence registers.
//
//*****************************************************************************
#define ADC_O_SEQ 0x00000040 // Offset to the first sequence
#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence
#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register
#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register
#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register
#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register
//*****************************************************************************
//
// The following define the bit fields in the ADC_ACTSS register.
//
//*****************************************************************************
#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable
#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable
#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable
#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable
//*****************************************************************************
//
// The following define the bit fields in the ADC_RIS register.
//
//*****************************************************************************
#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt
#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt
#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt
#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt
//*****************************************************************************
//
// The following define the bit fields in the ADC_IM register.
//
//*****************************************************************************
#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask
#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask
#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask
#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask
//*****************************************************************************
//
// The following define the bit fields in the ADC_ISC register.
//
//*****************************************************************************
#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt
#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt
#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt
#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt
//*****************************************************************************
//
// The following define the bit fields in the ADC_OSTAT register.
//
//*****************************************************************************
#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow
#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow
#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow
#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow
//*****************************************************************************
//
// The following define the bit fields in the ADC_EMUX register.
//
//*****************************************************************************
#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask
#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event
#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event
#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event
#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event
#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event
#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event
#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event
#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event
#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event
#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event
#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask
#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event
#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event
#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event
#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event
#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event
#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event
#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event
#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event
#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event
#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event
#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask
#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event
#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event
#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event
#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event
#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event
#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event
#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event
#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event
#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event
#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event
#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask
#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event
#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event
#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event
#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event
#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event
#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event
#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event
#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event
#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event
#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event
#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event
#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event
#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event
#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event
//*****************************************************************************
//
// The following define the bit fields in the ADC_USTAT register.
//
//*****************************************************************************
#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow
#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow
#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow
#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow
//*****************************************************************************
//
// The following define the bit fields in the ADC_SSPRI register.
//
//*****************************************************************************
#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask
#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask
#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority
#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority
#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority
#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask
#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority
#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority
#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority
#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask
#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority
#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority
#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority
//*****************************************************************************
//
// The following define the bit fields in the ADC_PSSI register.
//
//*****************************************************************************
#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3
#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2
#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1
#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0
//*****************************************************************************
//
// The following define the bit fields in the ADC_SAC register.
//
//*****************************************************************************
#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
//*****************************************************************************
//
// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1,
// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all
// registers.
//
//*****************************************************************************
#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask
#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask
#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask
#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask
#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask
#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask
#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask
#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask
#define ADC_SSMUX_MUX7_SHIFT 28
#define ADC_SSMUX_MUX6_SHIFT 24
#define ADC_SSMUX_MUX5_SHIFT 20
#define ADC_SSMUX_MUX4_SHIFT 16
#define ADC_SSMUX_MUX3_SHIFT 12
#define ADC_SSMUX_MUX2_SHIFT 8
#define ADC_SSMUX_MUX1_SHIFT 4
#define ADC_SSMUX_MUX0_SHIFT 0
//*****************************************************************************
//
// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1,
// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all
// registers.
//
//*****************************************************************************
#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select
#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable
#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select
#define ADC_SSCTL_D7 0x10000000 // 8th differential select
#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select
#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable
#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select
#define ADC_SSCTL_D6 0x01000000 // 7th differential select
#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select
#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable
#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select
#define ADC_SSCTL_D5 0x00100000 // 6th differential select
#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select
#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable
#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select
#define ADC_SSCTL_D4 0x00010000 // 5th differential select
#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select
#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable
#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select
#define ADC_SSCTL_D3 0x00001000 // 4th differential select
#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select
#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable
#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select
#define ADC_SSCTL_D2 0x00000100 // 3rd differential select
#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select
#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable
#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select
#define ADC_SSCTL_D1 0x00000010 // 2nd differential select
#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select
#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable
#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select
#define ADC_SSCTL_D0 0x00000001 // 1st differential select
//*****************************************************************************
//
// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1,
// ADC_SSFIFO2, and ADC_SSFIFO3 registers.
//
//*****************************************************************************
#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data
#define ADC_SSFIFO_DATA_SHIFT 0
//*****************************************************************************
//
// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1,
// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.
//
//*****************************************************************************
#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full
#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty
#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer
#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer
//*****************************************************************************
//
// The following define the bit fields in the ADC_TMLB register.
//
//*****************************************************************************
#define ADC_TMLB_LB 0x00000001 // Loopback control signals
//*****************************************************************************
//
// The following define the bit fields in the loopback ADC data.
//
//*****************************************************************************
#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask
#define ADC_LB_CONT 0x00000020 // Continuation sample
#define ADC_LB_DIFF 0x00000010 // Differential sample
#define ADC_LB_TS 0x00000008 // Temperature sensor sample
#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask
#define ADC_LB_CNT_SHIFT 6 // Sample counter shift
#define ADC_LB_MUX_SHIFT 0 // Input channel number shift
#endif // __HW_ADC_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_comp.h
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//*****************************************************************************
//
// hw_comp.h - Macros used when accessing the comparator hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_COMP_H__
#define __HW_COMP_H__
//*****************************************************************************
//
// The following define the offsets of the comparator registers.
//
//*****************************************************************************
#define COMP_O_MIS 0x00000000 // Interrupt status register
#define COMP_O_RIS 0x00000004 // Raw interrupt status register
#define COMP_O_INTEN 0x00000008 // Interrupt enable register
#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.
#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register
#define COMP_O_ACCTL0 0x00000024 // Comp0 control register
#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register
#define COMP_O_ACCTL1 0x00000044 // Comp1 control register
#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register
#define COMP_O_ACCTL2 0x00000064 // Comp2 control register
//*****************************************************************************
//
// The following define the bit fields in the COMP_MIS, COMP_RIS, and
// COMP_INTEN registers.
//
//*****************************************************************************
#define COMP_INT_2 0x00000004 // Comp2 interrupt
#define COMP_INT_1 0x00000002 // Comp1 interrupt
#define COMP_INT_0 0x00000001 // Comp0 interrupt
//*****************************************************************************
//
// The following define the bit fields in the COMP_REFCTL register.
//
//*****************************************************************************
#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable
#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range
#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask
#define COMP_REFCTL_VREF_SHIFT 0
//*****************************************************************************
//
// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and
// COMP_ACSTAT2 registers.
//
//*****************************************************************************
#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value
//*****************************************************************************
//
// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and
// COMP_ACCTL2 registers.
//
//*****************************************************************************
#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable
#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask
#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved
#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable
#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select
#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask
#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense
#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge
#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge
#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges
#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select
#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask
#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense
#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge
#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge
#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges
#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert
//*****************************************************************************
//
// The following define the reset values for the comparator registers.
//
//*****************************************************************************
#define COMP_RV_MIS 0x00000000 // Interrupt status register
#define COMP_RV_RIS 0x00000000 // Raw interrupt status register
#define COMP_RV_INTEN 0x00000000 // Interrupt enable register
#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.
#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register
#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register
#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register
#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register
#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register
#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register
#endif // __HW_COMP_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_flash.h
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//*****************************************************************************
//
// hw_flash.h - Macros used when accessing the flash controller.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_FLASH_H__
#define __HW_FLASH_H__
//*****************************************************************************
//
// The following define the offsets of the FLASH registers.
//
//*****************************************************************************
#define FLASH_FMA 0x400FD000 // Memory address register
#define FLASH_FMD 0x400FD004 // Memory data register
#define FLASH_FMC 0x400FD008 // Memory control register
#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register
#define FLASH_FCIM 0x400FD010 // Interrupt mask register
#define FLASH_FCMISC 0x400FD014 // Interrupt status register
#define FLASH_FMPRE 0x400FE130 // FLASH read protect register
#define FLASH_FMPPE 0x400FE134 // FLASH program protect register
#define FLASH_USECRL 0x400FE140 // uSec reload register
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FMC register.
//
//*****************************************************************************
#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask
#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
#define FLASH_FMC_COMT 0x00000008 // Commit user register
#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH
#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page
#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FCRIS register.
//
//*****************************************************************************
#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status
#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FCIM register.
//
//*****************************************************************************
#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask
#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FMIS register.
//
//*****************************************************************************
#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status
#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE
// registers.
//
//*****************************************************************************
#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31
#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30
#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29
#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28
#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27
#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26
#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25
#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24
#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23
#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22
#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21
#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20
#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19
#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18
#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17
#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16
#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15
#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14
#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13
#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12
#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11
#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10
#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9
#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8
#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7
#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6
#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5
#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4
#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3
#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2
#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1
#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0
//*****************************************************************************
//
// The following define the bit fields in the FLASH_USECRL register.
//
//*****************************************************************************
#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec
#define FLASH_USECRL_SHIFT 0
//*****************************************************************************
//
// The erase size is the size of the FLASH block that is erased by an erase
// operation, and the protect size is the size of the FLASH block that is
// protected by each protection register.
//
//*****************************************************************************
#define FLASH_ERASE_SIZE 0x00000400
#define FLASH_PROTECT_SIZE 0x00000800
#endif // __HW_FLASH_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_gpio.h
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//*****************************************************************************
//
// hw_gpio.h - Defines and Macros for GPIO hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_GPIO_H__
#define __HW_GPIO_H__
//*****************************************************************************
//
// GPIO Register Offsets.
//
//*****************************************************************************
#define GPIO_O_DATA 0x00000000 // Data register.
#define GPIO_O_DIR 0x00000400 // Data direction register.
#define GPIO_O_IS 0x00000404 // Interrupt sense register.
#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.
#define GPIO_O_IEV 0x0000040C // Intterupt event register.
#define GPIO_O_IM 0x00000410 // Interrupt mask register.
#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.
#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.
#define GPIO_O_ICR 0x0000041C // Interrupt clear register.
#define GPIO_O_AFSEL 0x00000420 // Mode control select register.
#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.
#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.
#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.
#define GPIO_O_ODR 0x0000050C // Open drain select register.
#define GPIO_O_PUR 0x00000510 // Pull up select register.
#define GPIO_O_PDR 0x00000514 // Pull down select register.
#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.
#define GPIO_O_DEN 0x0000051C // Digital input enable register.
#define GPIO_O_PeriphID4 0x00000FD0 //
#define GPIO_O_PeriphID5 0x00000FD4 //
#define GPIO_O_PeriphID6 0x00000FD8 //
#define GPIO_O_PeriphID7 0x00000FDC //
#define GPIO_O_PeriphID0 0x00000FE0 //
#define GPIO_O_PeriphID1 0x00000FE4 //
#define GPIO_O_PeriphID2 0x00000FE8 //
#define GPIO_O_PeriphID3 0x00000FEC //
#define GPIO_O_PCellID0 0x00000FF0 //
#define GPIO_O_PCellID1 0x00000FF4 //
#define GPIO_O_PCellID2 0x00000FF8 //
#define GPIO_O_PCellID3 0x00000FFC //
//*****************************************************************************
//
// GPIO Register reset values.
//
//*****************************************************************************
#define GPIO_RV_DATA 0x00000000 // Data register reset value.
#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.
#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.
#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.
#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.
#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.
#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.
#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.
#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.
#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.
#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.
#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.
#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.
#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.
#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.
#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.
#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.
#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.
#define GPIO_RV_PeriphID4 0x00000000 //
#define GPIO_RV_PeriphID5 0x00000000 //
#define GPIO_RV_PeriphID6 0x00000000 //
#define GPIO_RV_PeriphID7 0x00000000 //
#define GPIO_RV_PeriphID0 0x00000061 //
#define GPIO_RV_PeriphID1 0x00000010 //
#define GPIO_RV_PeriphID2 0x00000004 //
#define GPIO_RV_PeriphID3 0x00000000 //
#define GPIO_RV_PCellID0 0x0000000D //
#define GPIO_RV_PCellID1 0x000000F0 //
#define GPIO_RV_PCellID2 0x00000005 //
#define GPIO_RV_PCellID3 0x000000B1 //
#endif // __HW_GPIO_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_i2c.h
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//*****************************************************************************
//
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_I2C_H__
#define __HW_I2C_H__
//*****************************************************************************
//
// The following defines the offset between the I2C master and slave registers.
//
//*****************************************************************************
#define I2C_O_SLAVE 0x00000800 // Offset from master to slave
//*****************************************************************************
//
// The following define the offsets of the I2C master registers.
//
//*****************************************************************************
#define I2C_MASTER_O_SA 0x00000000 // Slave address register
#define I2C_MASTER_O_CS 0x00000004 // Control and Status register
#define I2C_MASTER_O_DR 0x00000008 // Data register
#define I2C_MASTER_O_TPR 0x0000000C // Timer period register
#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register
#define I2C_MASTER_O_CR 0x00000020 // Configuration register
//*****************************************************************************
//
// The following define the offsets of the I2C slave registers.
//
//*****************************************************************************
#define I2C_SLAVE_O_OAR 0x00000000 // Own address register
#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
#define I2C_SLAVE_O_DR 0x00000008 // Data register
#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register
//*****************************************************************************
//
// The followng define the bit fields in the I2C master slave address register.
//
//*****************************************************************************
#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address
#define I2C_MASTER_SA_RS 0x00000001 // Receive/send
#define I2C_MASTER_SA_SA_SHIFT 1
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Control and Status
// register.
//
//*****************************************************************************
#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
#define I2C_MASTER_CS_STOP 0x00000004 // Stop
#define I2C_MASTER_CS_START 0x00000002 // Start
#define I2C_MASTER_CS_RUN 0x00000001 // Run
#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
#define I2C_MASTER_CS_IDLE 0x00000020 // Idle
#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
#define I2C_MASTER_CS_ERR_MASK 0x0000001C
//*****************************************************************************
//
// The following define values used in determining the contents of the I2C
// Master Timer Period register.
//
//*****************************************************************************
#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
#define I2C_SCL_STANDARD 100000 // SCL standard frequency
#define I2C_SCL_FAST 400000 // SCL fast frequency
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Interrupt Mask
// register.
//
//*****************************************************************************
#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Raw Interrupt Status
// register.
//
//*****************************************************************************
#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Masked Interrupt
// Status register.
//
//*****************************************************************************
#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Interrupt Clear
// register.
//
//*****************************************************************************
#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Configuration
// register.
//
//*****************************************************************************
#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Own Address register.
//
//*****************************************************************************
#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Control/Status
// register.
//
//*****************************************************************************
#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Interrupt Mask
// register.
//
//*****************************************************************************
#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Raw Interrupt Status
// register.
//
//*****************************************************************************
#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Masked Interrupt
// Status register.
//
//*****************************************************************************
#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Interrupt Clear
// register.
//
//*****************************************************************************
#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear
#endif // __HW_I2C_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ints.h
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//*****************************************************************************
//
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_INTS_H__
#define __HW_INTS_H__
//*****************************************************************************
//
// The following define the fault assignments.
//
//*****************************************************************************
#define FAULT_NMI 2 // NMI fault
#define FAULT_HARD 3 // Hard fault
#define FAULT_MPU 4 // MPU fault
#define FAULT_BUS 5 // Bus fault
#define FAULT_USAGE 6 // Usage fault
#define FAULT_SVCALL 11 // SVCall
#define FAULT_DEBUG 12 // Debug monitor
#define FAULT_PENDSV 14 // PendSV
#define FAULT_SYSTICK 15 // System Tick
//*****************************************************************************
//
// The following define the interrupt assignments.
//
//*****************************************************************************
#define INT_GPIOA 16 // GPIO Port A
#define INT_GPIOB 17 // GPIO Port B
#define INT_GPIOC 18 // GPIO Port C
#define INT_GPIOD 19 // GPIO Port D
#define INT_GPIOE 20 // GPIO Port E
#define INT_UART0 21 // UART0 Rx and Tx
#define INT_UART1 22 // UART1 Rx and Tx
#define INT_SSI 23 // SSI Rx and Tx
#define INT_I2C 24 // I2C Master and Slave
#define INT_PWM_FAULT 25 // PWM Fault
#define INT_PWM0 26 // PWM Generator 0
#define INT_PWM1 27 // PWM Generator 1
#define INT_PWM2 28 // PWM Generator 2
#define INT_QEI 29 // Quadrature Encoder
#define INT_ADC0 30 // ADC Sequence 0
#define INT_ADC1 31 // ADC Sequence 1
#define INT_ADC2 32 // ADC Sequence 2
#define INT_ADC3 33 // ADC Sequence 3
#define INT_WATCHDOG 34 // Watchdog timer
#define INT_TIMER0A 35 // Timer 0 subtimer A
#define INT_TIMER0B 36 // Timer 0 subtimer B
#define INT_TIMER1A 37 // Timer 1 subtimer A
#define INT_TIMER1B 38 // Timer 1 subtimer B
#define INT_TIMER2A 39 // Timer 2 subtimer A
#define INT_TIMER2B 40 // Timer 2 subtimer B
#define INT_COMP0 41 // Analog Comparator 0
#define INT_COMP1 42 // Analog Comparator 1
#define INT_COMP2 43 // Analog Comparator 2
#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
#define INT_FLASH 45 // FLASH Control
//*****************************************************************************
//
// The total number of interrupts.
//
//*****************************************************************************
#define NUM_INTERRUPTS 46
//*****************************************************************************
//
// The total number of priority levels.
//
//*****************************************************************************
#define NUM_PRIORITY 8
#define NUM_PRIORITY_BITS 3
#endif // __HW_INTS_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_memmap.h
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//*****************************************************************************
//
// hw_memmap.h - Macros defining the memory map of Stellaris.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_MEMMAP_H__
#define __HW_MEMMAP_H__
//*****************************************************************************
//
// The following define the base address of the memories and peripherals.
//
//*****************************************************************************
#define FLASH_BASE 0x00000000 // FLASH memory
#define SRAM_BASE 0x20000000 // SRAM memory
#define WATCHDOG_BASE 0x40000000 // Watchdog
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
#define SSI_BASE 0x40008000 // SSI
#define UART0_BASE 0x4000C000 // UART0
#define UART1_BASE 0x4000D000 // UART1
#define I2C_MASTER_BASE 0x40020000 // I2C Master
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
#define PWM_BASE 0x40028000 // PWM
#define QEI_BASE 0x4002C000 // QEI
#define TIMER0_BASE 0x40030000 // Timer0
#define TIMER1_BASE 0x40031000 // Timer1
#define TIMER2_BASE 0x40032000 // Timer2
#define ADC_BASE 0x40038000 // ADC
#define COMP_BASE 0x4003C000 // Analog comparators
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
#define SYSCTL_BASE 0x400FE000 // System Control
#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
#endif // __HW_MEMMAP_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_nvic.h
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//*****************************************************************************
//
// hw_nvic.h - Macros used when accessing the NVIC hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_NVIC_H__
#define __HW_NVIC_H__
//*****************************************************************************
//
// The following define the addresses of the NVIC registers.
//
//*****************************************************************************
#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.
#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.
#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register
#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.
#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register
#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.
#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register
#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.
#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register
#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register
#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register
#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register
#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register
#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register
#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register
#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register
#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register
#define NVIC_CPUID 0xE000ED00 // CPUID Base Register
#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register
#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register
#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.
#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register
#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register
#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority
#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority
#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority
#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State
#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.
#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register
#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register
#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register
#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register
#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register
#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register
#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register
#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register
#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.
#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.
#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select
#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data
#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control
#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.
//*****************************************************************************
//
// The following define the bit fields in the NVIC_INT_TYPE register.
//
//*****************************************************************************
#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
#define NVIC_INT_TYPE_LINES_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_ST_CTRL register.
//
//*****************************************************************************
#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag
#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable
#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode
//*****************************************************************************
//
// The following define the bit fields in the NVIC_ST_RELOAD register.
//
//*****************************************************************************
#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value
#define NVIC_ST_RELOAD_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_ST_CURRENT register.
//
//*****************************************************************************
#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value
#define NVIC_ST_CURRENT_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_ST_CAL register.
//
//*****************************************************************************
#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
#define NVIC_ST_CAL_ONEMS_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_EN0 register.
//
//*****************************************************************************
#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DIS0 register.
//
//*****************************************************************************
#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PEND0 register.
//
//*****************************************************************************
#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
//*****************************************************************************
//
// The following define the bit fields in the NVIC_UNPEND0 register.
//
//*****************************************************************************
#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
//*****************************************************************************
//
// The following define the bit fields in the NVIC_ACTIVE0 register.
//
//*****************************************************************************
#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI0 register.
//
//*****************************************************************************
#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask
#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask
#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask
#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask
#define NVIC_PRI0_INT3_S 24
#define NVIC_PRI0_INT2_S 16
#define NVIC_PRI0_INT1_S 8
#define NVIC_PRI0_INT0_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI1 register.
//
//*****************************************************************************
#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask
#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask
#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask
#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask
#define NVIC_PRI1_INT7_S 24
#define NVIC_PRI1_INT6_S 16
#define NVIC_PRI1_INT5_S 8
#define NVIC_PRI1_INT4_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI2 register.
//
//*****************************************************************************
#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask
#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask
#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask
#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask
#define NVIC_PRI2_INT11_S 24
#define NVIC_PRI2_INT10_S 16
#define NVIC_PRI2_INT9_S 8
#define NVIC_PRI2_INT8_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI3 register.
//
//*****************************************************************************
#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask
#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask
#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask
#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask
#define NVIC_PRI3_INT15_S 24
#define NVIC_PRI3_INT14_S 16
#define NVIC_PRI3_INT13_S 8
#define NVIC_PRI3_INT12_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI4 register.
//
//*****************************************************************************
#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask
#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask
#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask
#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask
#define NVIC_PRI4_INT19_S 24
#define NVIC_PRI4_INT18_S 16
#define NVIC_PRI4_INT17_S 8
#define NVIC_PRI4_INT16_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI5 register.
//
//*****************************************************************************
#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask
#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask
#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask
#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask
#define NVIC_PRI5_INT23_S 24
#define NVIC_PRI5_INT22_S 16
#define NVIC_PRI5_INT21_S 8
#define NVIC_PRI5_INT20_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI6 register.
//
//*****************************************************************************
#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask
#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask
#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask
#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask
#define NVIC_PRI6_INT27_S 24
#define NVIC_PRI6_INT26_S 16
#define NVIC_PRI6_INT25_S 8
#define NVIC_PRI6_INT24_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI7 register.
//
//*****************************************************************************
#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask
#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask
#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask
#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask
#define NVIC_PRI7_INT31_S 24
#define NVIC_PRI7_INT30_S 16
#define NVIC_PRI7_INT29_S 8
#define NVIC_PRI7_INT28_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_CPUID register.
//
//*****************************************************************************
#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer
#define NVIC_CPUID_VAR_M 0x00F00000 // Variant
#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number
#define NVIC_CPUID_REV_M 0x0000000F // Revision
//*****************************************************************************
//
// The following define the bit fields in the NVIC_INT_CTRL register.
//
//*****************************************************************************
#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI
#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV
#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV
#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling
#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending
#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception
#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base
#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception
#define NVIC_INT_CTRL_VEC_PEN_S 12
#define NVIC_INT_CTRL_VEC_ACT_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_VTABLE register.
//
//*****************************************************************************
#define NVIC_VTABLE_BASE 0x20000000 // Vector table base
#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset
#define NVIC_VTABLE_OFFSET_S 8
//*****************************************************************************
//
// The following define the bit fields in the NVIC_APINT register.
//
//*****************************************************************************
#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask
#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess
#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group
#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request
#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info
#define NVIC_APINT_VECT_RESET 0x00000001 // System reset
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SYS_CTRL register.
//
//*****************************************************************************
#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend
#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable
#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit
//*****************************************************************************
//
// The following define the bit fields in the NVIC_CFG_CTRL register.
//
//*****************************************************************************
#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault
#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0
#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access
#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger
#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger
#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SYS_PRI1 register.
//
//*****************************************************************************
#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler
#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler
#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler
#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler
#define NVIC_SYS_PRI1_USAGE_S 16
#define NVIC_SYS_PRI1_BUS_S 8
#define NVIC_SYS_PRI1_MEM_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SYS_PRI2 register.
//
//*****************************************************************************
#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler
#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers
#define NVIC_SYS_PRI2_SVC_S 24
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SYS_PRI3 register.
//
//*****************************************************************************
#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler
#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler
#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler
#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler
#define NVIC_SYS_PRI3_TICK_S 24
#define NVIC_SYS_PRI3_PENDSV_S 16
#define NVIC_SYS_PRI3_DEBUG_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SYS_HND_CTRL register.
//
//*****************************************************************************
#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable
#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable
#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable
#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended
#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended
#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active
#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active
#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active
#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active
#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active
#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active
#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active
//*****************************************************************************
//
// The following define the bit fields in the NVIC_FAULT_STAT register.
//
//*****************************************************************************
#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault
#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault
#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault
#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault
#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault
#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault
#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid
#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault
#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault
#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error
#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error
#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault
#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid
#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation
#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation
#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation
#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation
//*****************************************************************************
//
// The following define the bit fields in the NVIC_HFAULT_STAT register.
//
//*****************************************************************************
#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event
#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler
#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DEBUG_STAT register.
//
//*****************************************************************************
#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MM_ADDR register.
//
//*****************************************************************************
#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address
#define NVIC_MM_ADDR_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_FAULT_ADDR register.
//
//*****************************************************************************
#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address
#define NVIC_FAULT_ADDR_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_EXC_STACK register.
//
//*****************************************************************************
#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack
//*****************************************************************************
//
// The following define the bit fields in the NVIC_EXC_NUM register.
//
//*****************************************************************************
#define NVIC_EXC_NUM_M 0x000003FF // Exception number
#define NVIC_EXC_NUM_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_COPRO register.
//
//*****************************************************************************
#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask
#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied
#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess
#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access
#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask
#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied
#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess
#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access
#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask
#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied
#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess
#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access
#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask
#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied
#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess
#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access
#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask
#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied
#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess
#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access
#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask
#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied
#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess
#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access
#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask
#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied
#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess
#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access
#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask
#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied
#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess
#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access
#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask
#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied
#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess
#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access
#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask
#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied
#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess
#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access
#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask
#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied
#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess
#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access
#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask
#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied
#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess
#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access
#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask
#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied
#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess
#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access
#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask
#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied
#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess
#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access
#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask
#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied
#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess
#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access
#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask
#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied
#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess
#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_TYPE register.
//
//*****************************************************************************
#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions
#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions
#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU
#define NVIC_MPU_TYPE_IREGION_S 16
#define NVIC_MPU_TYPE_DREGION_S 8
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_CTRL register.
//
//*****************************************************************************
#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults
#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_NUMBER register.
//
//*****************************************************************************
#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access
#define NVIC_MPU_NUMBER_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_BASE register.
//
//*****************************************************************************
#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address
#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid
#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number
#define NVIC_MPU_BASE_ADDR_S 8
#define NVIC_MPU_BASE_REGION_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_ATTR register.
//
//*****************************************************************************
#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes
#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable
#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DBG_CTRL register.
//
//*****************************************************************************
#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor
#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request
#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable
#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core
#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping
#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt
#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available
#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up
#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core
#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DBG_XFER register.
//
//*****************************************************************************
#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DBG_DATA register.
//
//*****************************************************************************
#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
#define NVIC_DBG_DATA_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DBG_INT register.
//
//*****************************************************************************
#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SW_TRIG register.
//
//*****************************************************************************
#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger
#define NVIC_SW_TRIG_INTID_S 0
#endif // __HW_NVIC_H__

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//*****************************************************************************
//
// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_PWM_H__
#define __HW_PWM_H__
//*****************************************************************************
//
// PWM Module Register Offsets.
//
//*****************************************************************************
#define PWM_O_CTL 0x00000000 // PWM Master Control register
#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register
#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register
#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register
#define PWM_O_FAULT 0x00000010 // PWM Output Fault register
#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register
#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.
#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register
#define PWM_O_STATUS 0x00000020 // PWM Status register
//*****************************************************************************
//
// The following define the bit fields in the PWM Master Control register.
//
//*****************************************************************************
#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2
#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1
#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0
//*****************************************************************************
//
// The following define the bit fields in the PWM Time Base Sync register.
//
//*****************************************************************************
#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter
#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter
#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter
//*****************************************************************************
//
// The following define the bit fields in the PWM Output Enable register.
//
//*****************************************************************************
#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable
#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable
#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable
#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable
#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable
#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable
//*****************************************************************************
//
// The following define the bit fields in the PWM Inversion register.
//
//*****************************************************************************
#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert
#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert
#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert
#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert
#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert
#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert
//*****************************************************************************
//
// The following define the bit fields in the PWM Fault register.
//
//*****************************************************************************
#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault
#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault
#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault
#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault
#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault
#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault
//*****************************************************************************
//
// PWM Interrupt Register bit definitions.
//
//*****************************************************************************
#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending
//*****************************************************************************
//
// The following define the bit fields in the PWM Status register.
//
//*****************************************************************************
#define PWM_STATUS_FAULT 0x00000001 // Fault status
//*****************************************************************************
//
// PWM Generator standard offsets.
//
//*****************************************************************************
#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base
#define PWM_O_X_CTL 0x00000000 // Gen Control Reg
#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg
#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg
#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg
#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg
#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg
#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg
#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg
#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg
#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg
#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg
#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
//*****************************************************************************
//
// PWM_X Control Register bit definitions.
//
//*****************************************************************************
#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block
#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down
#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode
#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg
#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg
#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg
//*****************************************************************************
//
// PWM_X Interrupt/Trigger Enable Register bit definitions.
//
//*****************************************************************************
#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0
#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD
#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U
#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D
#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U
#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D
#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0
#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD
#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U
#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D
#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U
#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D
//*****************************************************************************
//
// PWM_X Raw Interrupt Status Register bit definitions.
//
//*****************************************************************************
#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int
#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int
#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int
#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int
#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int
#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int
//*****************************************************************************
//
// PWM_X Interrupt Status Register bit definitions.
//
//*****************************************************************************
#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received
#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd
#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd
#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd
#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd
#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd
//*****************************************************************************
//
// PWM_X Generator A/B Control Register bit definitions.
//
//*****************************************************************************
#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0
#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD
#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U
#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D
#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U
#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D
//*****************************************************************************
//
// PWM_X Generator A/B Control Register action definitions.
//
//*****************************************************************************
#define PWM_GEN_ACT_NONE 0x0 // Do nothing
#define PWM_GEN_ACT_INV 0x1 // Invert the output signal
#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero
#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one
#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action
#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action
#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action
#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action
#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action
#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action
//*****************************************************************************
//
// PWM_X Dead Band Control Register bit definitions.
//
//*****************************************************************************
#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion
//*****************************************************************************
//
// PWM Register reset values.
//
//*****************************************************************************
#define PWM_RV_CTL 0x00000000 // Master control of the PWM module
#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators
#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM
// output pins
#define PWM_RV_INVERT 0x00000000 // Inversion control for
// PWM output pins
#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM
// output pins
#define PWM_RV_INTEN 0x00000000 // Interrupt enable
#define PWM_RV_RIS 0x00000000 // Raw interrupt status
#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing
#define PWM_RV_STATUS 0x00000000 // Status
#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM
// generator block
#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable
#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status
#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing
#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter
#define PWM_RV_X_COUNT 0x00000000 // The current counter value
#define PWM_RV_X_CMPA 0x00000000 // The comparator A value
#define PWM_RV_X_CMPB 0x00000000 // The comparator B value
#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A
#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B
#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator
#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay
// count
#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay
// count
#endif // __HW_PWM_H__

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//*****************************************************************************
//
// hw_qei.h - Macros used when accessing the QEI hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_QEI_H__
#define __HW_QEI_H__
//*****************************************************************************
//
// The following define the offsets of the QEI registers.
//
//*****************************************************************************
#define QEI_O_CTL 0x00000000 // Configuration and control reg.
#define QEI_O_STAT 0x00000004 // Status register
#define QEI_O_POS 0x00000008 // Current position register
#define QEI_O_MAXPOS 0x0000000C // Maximum position register
#define QEI_O_LOAD 0x00000010 // Velocity timer load register
#define QEI_O_TIME 0x00000014 // Velocity timer register
#define QEI_O_COUNT 0x00000018 // Velocity pulse count register
#define QEI_O_SPEED 0x0000001C // Velocity speed register
#define QEI_O_INTEN 0x00000020 // Interrupt enable register
#define QEI_O_RIS 0x00000024 // Raw interrupt status register
#define QEI_O_ISC 0x00000028 // Interrupt status register
//*****************************************************************************
//
// The following define the bit fields in the QEI_CTL register.
//
//*****************************************************************************
#define QEI_CTL_STALLEN 0x00001000 // Stall enable
#define QEI_CTL_INVI 0x00000800 // Invert Index input
#define QEI_CTL_INVB 0x00000400 // Invert PhB input
#define QEI_CTL_INVA 0x00000200 // Invert PhA input
#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask
#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1
#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2
#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4
#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8
#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16
#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32
#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64
#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128
#define QEI_CTL_VELEN 0x00000020 // Velocity enable
#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode
#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode
#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode
#define QEI_CTL_SWAP 0x00000002 // Swap input signals
#define QEI_CTL_ENABLE 0x00000001 // QEI enable
//*****************************************************************************
//
// The following define the bit fields in the QEI_STAT register.
//
//*****************************************************************************
#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation
#define QEI_STAT_ERROR 0x00000001 // Signalling error detected
//*****************************************************************************
//
// The following define the bit fields in the QEI_POS register.
//
//*****************************************************************************
#define QEI_POS_M 0xFFFFFFFF // Current encoder position
#define QEI_POS_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_MAXPOS register.
//
//*****************************************************************************
#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position
#define QEI_MAXPOS_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_LOAD register.
//
//*****************************************************************************
#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value
#define QEI_LOAD_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_TIME register.
//
//*****************************************************************************
#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value
#define QEI_TIME_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_COUNT register.
//
//*****************************************************************************
#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count
#define QEI_COUNT_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_SPEED register.
//
//*****************************************************************************
#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count
#define QEI_SPEED_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_INTEN register.
//
//*****************************************************************************
#define QEI_INTEN_ERROR 0x00000008 // Phase error detected
#define QEI_INTEN_DIR 0x00000004 // Direction change
#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired
#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following define the bit fields in the QEI_RIS register.
//
//*****************************************************************************
#define QEI_RIS_ERROR 0x00000008 // Phase error detected
#define QEI_RIS_DIR 0x00000004 // Direction change
#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired
#define QEI_RIS_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following define the bit fields in the QEI_ISC register.
//
//*****************************************************************************
#define QEI_INT_ERROR 0x00000008 // Phase error detected
#define QEI_INT_DIR 0x00000004 // Direction change
#define QEI_INT_TIMER 0x00000002 // Velocity timer expired
#define QEI_INT_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following define the reset values for the QEI registers.
//
//*****************************************************************************
#define QEI_RV_CTL 0x00000000 // Configuration and control reg.
#define QEI_RV_STAT 0x00000000 // Status register
#define QEI_RV_POS 0x00000000 // Current position register
#define QEI_RV_MAXPOS 0x00000000 // Maximum position register
#define QEI_RV_LOAD 0x00000000 // Velocity timer load register
#define QEI_RV_TIME 0x00000000 // Velocity timer register
#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register
#define QEI_RV_SPEED 0x00000000 // Velocity speed register
#define QEI_RV_INTEN 0x00000000 // Interrupt enable register
#define QEI_RV_RIS 0x00000000 // Raw interrupt status register
#define QEI_RV_ISC 0x00000000 // Interrupt status register
#endif // __HW_QEI_H__

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//*****************************************************************************
//
// hw_ssi.h - Macros used when accessing the SSI hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_SSI_H__
#define __HW_SSI_H__
//*****************************************************************************
//
// The following define the offsets of the SSI registers.
//
//*****************************************************************************
#define SSI_O_CR0 0x00000000 // Control register 0
#define SSI_O_CR1 0x00000004 // Control register 1
#define SSI_O_DR 0x00000008 // Data register
#define SSI_O_SR 0x0000000C // Status register
#define SSI_O_CPSR 0x00000010 // Clock prescale register
#define SSI_O_IM 0x00000014 // Int mask set and clear register
#define SSI_O_RIS 0x00000018 // Raw interrupt register
#define SSI_O_MIS 0x0000001C // Masked interrupt register
#define SSI_O_ICR 0x00000020 // Interrupt clear register
//*****************************************************************************
//
// The following define the bit fields in the SSI Control register 0.
//
//*****************************************************************************
#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase
#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity
#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format
#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format
#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format
#define SSI_CR0_DSS 0x0000000F // Data size select
#define SSI_CR0_DSS_4 0x00000003 // 4 bit data
#define SSI_CR0_DSS_5 0x00000004 // 5 bit data
#define SSI_CR0_DSS_6 0x00000005 // 6 bit data
#define SSI_CR0_DSS_7 0x00000006 // 7 bit data
#define SSI_CR0_DSS_8 0x00000007 // 8 bit data
#define SSI_CR0_DSS_9 0x00000008 // 9 bit data
#define SSI_CR0_DSS_10 0x00000009 // 10 bit data
#define SSI_CR0_DSS_11 0x0000000A // 11 bit data
#define SSI_CR0_DSS_12 0x0000000B // 12 bit data
#define SSI_CR0_DSS_13 0x0000000C // 13 bit data
#define SSI_CR0_DSS_14 0x0000000D // 14 bit data
#define SSI_CR0_DSS_15 0x0000000E // 15 bit data
#define SSI_CR0_DSS_16 0x0000000F // 16 bit data
//*****************************************************************************
//
// The following define the bit fields in the SSI Control register 1.
//
//*****************************************************************************
#define SSI_CR1_SOD 0x00000008 // Slave mode output disable
#define SSI_CR1_MS 0x00000004 // Master or slave mode select
#define SSI_CR1_SSE 0x00000002 // Sync serial port enable
#define SSI_CR1_LBM 0x00000001 // Loopback mode
//*****************************************************************************
//
// The following define the bit fields in the SSI Status register.
//
//*****************************************************************************
#define SSI_SR_BSY 0x00000010 // SSI busy
#define SSI_SR_RFF 0x00000008 // RX FIFO full
#define SSI_SR_RNE 0x00000004 // RX FIFO not empty
#define SSI_SR_TNF 0x00000002 // TX FIFO not full
#define SSI_SR_TFE 0x00000001 // TX FIFO empty
//*****************************************************************************
//
// The following define the bit fields in the SSI clock prescale register.
//
//*****************************************************************************
#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
//*****************************************************************************
//
// The following define information concerning the SSI Data register.
//
//*****************************************************************************
#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
//*****************************************************************************
//
// The following define the bit fields in the interrupt mask set and clear,
// raw interrupt, masked interrupt, and interrupt clear registers.
//
//*****************************************************************************
#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
#endif // __HW_SSI_H__

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//*****************************************************************************
//
// hw_sysctl.h - Macros used when accessing the system control hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_SYSCTL_H__
#define __HW_SYSCTL_H__
//*****************************************************************************
//
// The following define the offsets of the system control registers.
//
//*****************************************************************************
#define SYSCTL_DID0 0x400fe000 // Device identification register 0
#define SYSCTL_DID1 0x400fe004 // Device identification register 1
#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0
#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1
#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2
#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3
#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4
#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register
#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register
#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0
#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1
#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2
#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register
#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register
#define SYSCTL_MISC 0x400fe058 // Interrupt status register
#define SYSCTL_RESC 0x400fe05c // Reset cause register
#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register
#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register
#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0
#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1
#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2
#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0
#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1
#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2
#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0
#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1
#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2
#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register
#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DID0 register.
//
//*****************************************************************************
#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask
#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0
#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask
#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A
#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B
#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask
#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0
#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DID1 register.
//
//*****************************************************************************
#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask
#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask
#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family
#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask
#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101
#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102
#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301
#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310
#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315
#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316
#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328
#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601
#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610
#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611
#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612
#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613
#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615
#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628
#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801
#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811
#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812
#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815
#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828
#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask
#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)
#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)
#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask
#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC
#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP
#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant
#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask
#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)
#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)
#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified
#define SYSCTL_DID1_PRTNO_SHIFT 16
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC0 register.
//
//*****************************************************************************
#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask
#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM
#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM
#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8kB of SRAM
#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask
#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash
#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash
#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32kB of flash
#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64kB of flash
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC1 register.
//
//*****************************************************************************
#define SYSCTL_DC1_PWM 0x00100000 // PWM module present
#define SYSCTL_DC1_ADC 0x00010000 // ADC module present
#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask
#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask
#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC
#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC
#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC
#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC
#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present
#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present
#define SYSCTL_DC1_PLL 0x00000010 // PLL present
#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present
#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present
#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present
#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC2 register.
//
//*****************************************************************************
#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present
#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present
#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present
#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present
#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present
#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present
#define SYSCTL_DC2_I2C 0x00001000 // I2C present
#define SYSCTL_DC2_QEI 0x00000100 // QEI present
#define SYSCTL_DC2_SSI 0x00000010 // SSI present
#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present
#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC3 register.
//
//*****************************************************************************
#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present
#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present
#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present
#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present
#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present
#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present
#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present
#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present
#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present
#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present
#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present
#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present
#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present
#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present
#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present
#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present
#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present
#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present
#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present
#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present
#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present
#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present
#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present
#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present
#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present
#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present
#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present
#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present
#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present
#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC4 register.
//
//*****************************************************************************
#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present
#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present
#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present
#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present
#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_PBORCTL register.
//
//*****************************************************************************
#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer
#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset
#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise
#define SYSCTL_PBORCTL_BOR_SH 2
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_LDOPCTL register.
//
//*****************************************************************************
#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask
#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V
#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V
#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V
#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V
#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V
#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V
#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V
#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V
#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V
#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V
#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,
// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.
//
//*****************************************************************************
#define SYSCTL_SET0_PWM 0x00100000 // PWM module
#define SYSCTL_SET0_ADC 0x00010000 // ADC module
#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask
#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC
#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC
#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC
#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC
#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,
// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.
//
//*****************************************************************************
#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2
#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1
#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0
#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2
#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1
#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0
#define SYSCTL_SET1_I2C 0x00001000 // I2C module
#define SYSCTL_SET1_QEI 0x00000100 // QEI module
#define SYSCTL_SET1_SSI 0x00000010 // SSI module
#define SYSCTL_SET1_UART1 0x00000002 // UART module 1
#define SYSCTL_SET1_UART0 0x00000001 // UART module 0
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,
// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.
//
//*****************************************************************************
#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module
#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module
#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module
#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module
#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and
// SYSCTL_IMS registers.
//
//*****************************************************************************
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_RESC register.
//
//*****************************************************************************
#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset
#define SYSCTL_RESC_SW 0x00000010 // Software reset
#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset
#define SYSCTL_RESC_POR 0x00000002 // Power on reset
#define SYSCTL_RESC_EXT 0x00000001 // External reset
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_RCC register.
//
//*****************************************************************************
#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating
#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider
#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2
#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3
#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4
#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5
#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6
#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7
#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8
#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9
#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10
#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11
#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12
#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13
#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14
#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15
#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16
#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider
#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider
#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider
#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2
#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4
#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8
#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16
#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32
#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64
#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down
#define SYSCTL_RCC_OE 0x00001000 // PLL output enable
#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass
#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable
#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc
#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal
#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal
#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal
#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal
#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal
#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal
#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal
#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal
#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal
#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal
#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal
#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal
#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select
#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator
#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator
#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4
#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en
#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en
#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable
#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable
#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field
#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field
#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field
#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_PLLCFG register.
//
//*****************************************************************************
#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider
#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1
#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2
#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4
#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier
#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider
#define SYSCTL_PLLCFG_F_SHIFT 5
#define SYSCTL_PLLCFG_R_SHIFT 0
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_CLKVCLR register.
//
//*****************************************************************************
#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_LDOARST register.
//
//*****************************************************************************
#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device
#endif // __HW_SYSCTL_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_timer.h
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//*****************************************************************************
//
// hw_timer.h - Defines and macros used when accessing the timer.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_TIMER_H__
#define __HW_TIMER_H__
//*****************************************************************************
//
// The following define the offsets of the timer registers.
//
//*****************************************************************************
#define TIMER_O_CFG 0x00000000 // Configuration register
#define TIMER_O_TAMR 0x00000004 // TimerA mode register
#define TIMER_O_TBMR 0x00000008 // TimerB mode register
#define TIMER_O_CTL 0x0000000C // Control register
#define TIMER_O_IMR 0x00000018 // Interrupt mask register
#define TIMER_O_RIS 0x0000001C // Interrupt status register
#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.
#define TIMER_O_ICR 0x00000024 // Interrupt clear register
#define TIMER_O_TAILR 0x00000028 // TimerA interval load register
#define TIMER_O_TBILR 0x0000002C // TimerB interval load register
#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register
#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register
#define TIMER_O_TAPR 0x00000038 // TimerA prescale register
#define TIMER_O_TBPR 0x0000003C // TimerB prescale register
#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register
#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register
#define TIMER_O_TAR 0x00000048 // TimerA register
#define TIMER_O_TBR 0x0000004C // TimerB register
//*****************************************************************************
//
// The following define the reset values of the timer registers.
//
//*****************************************************************************
#define TIMER_RV_CFG 0x00000000 // Configuration register RV
#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
#define TIMER_RV_CTL 0x00000000 // Control register RV
#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
//*****************************************************************************
//
// The following define the bit fields in the TIMER_CFG register.
//
//*****************************************************************************
#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers
#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TnMR register.
//
//*****************************************************************************
#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
//*****************************************************************************
//
// The following define the bit fields in the TIMER_CTL register.
//
//*****************************************************************************
#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert
#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable
#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge
#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge
#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable
#define TIMER_CTL_TBEN 0x00000100 // TimerB enable
#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert
#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable
#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable
#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge
#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge
#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable
#define TIMER_CTL_TAEN 0x00000001 // TimerA enable
//*****************************************************************************
//
// The following define the bit fields in the TIMER_IMR register.
//
//*****************************************************************************
#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask
#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask
#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask
#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask
#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask
#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask
#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask
//*****************************************************************************
//
// The following define the bit fields in the TIMER_RIS register.
//
//*****************************************************************************
#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status
#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status
#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status
#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status
#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status
#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status
#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status
//*****************************************************************************
//
// The following define the bit fields in the TIMER_MIS register.
//
//*****************************************************************************
#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
//*****************************************************************************
//
// The following define the bit fields in the TIMER_ICR register.
//
//*****************************************************************************
#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear
#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear
#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear
#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear
#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear
#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear
#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TAILR register.
//
//*****************************************************************************
#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TBILR register.
//
//*****************************************************************************
#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TAMATCHR register.
//
//*****************************************************************************
#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TBMATCHR register.
//
//*****************************************************************************
#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TnPR register.
//
//*****************************************************************************
#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TnPMR register.
//
//*****************************************************************************
#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TAR register.
//
//*****************************************************************************
#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
#define TIMER_TAR_TARL 0x0000FFFF // TimerA value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TBR register.
//
//*****************************************************************************
#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
#endif // __HW_TIMER_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_types.h
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//*****************************************************************************
//
// hw_types.h - Common types and macros.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_TYPES_H__
#define __HW_TYPES_H__
//*****************************************************************************
//
// Define a boolean type, and values for true and false.
//
//*****************************************************************************
typedef unsigned char tBoolean;
#ifndef true
#define true 1
#endif
#ifndef false
#define false 0
#endif
//*****************************************************************************
//
// Macros for hardware access, both direct and via the bit-band region.
//
//*****************************************************************************
#define HWREG(x) \
(*((volatile unsigned long *)(x)))
#define HWREGH(x) \
(*((volatile unsigned short *)(x)))
#define HWREGB(x) \
(*((volatile unsigned char *)(x)))
#define HWREGBITW(x, b) \
HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITH(x, b) \
HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITB(x, b) \
HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#endif // __HW_TYPES_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_uart.h
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//*****************************************************************************
//
// hw_uart.h - Macros and defines used when accessing the UART hardware
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_UART_H__
#define __HW_UART_H__
//*****************************************************************************
//
// UART Register Offsets.
//
//*****************************************************************************
#define UART_O_DR 0x00000000 // Data Register
#define UART_O_RSR 0x00000004 // Receive Status Register (read)
#define UART_O_ECR 0x00000004 // Error Clear Register (write)
#define UART_O_FR 0x00000018 // Flag Register (read only)
#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg
#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg
#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte
#define UART_O_CTL 0x00000030 // Control Register
#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg
#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg
#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register
#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register
#define UART_O_ICR 0x00000044 // Interrupt Clear Register
#define UART_O_PeriphID4 0x00000FD0 //
#define UART_O_PeriphID5 0x00000FD4 //
#define UART_O_PeriphID6 0x00000FD8 //
#define UART_O_PeriphID7 0x00000FDC //
#define UART_O_PeriphID0 0x00000FE0 //
#define UART_O_PeriphID1 0x00000FE4 //
#define UART_O_PeriphID2 0x00000FE8 //
#define UART_O_PeriphID3 0x00000FEC //
#define UART_O_PCellID0 0x00000FF0 //
#define UART_O_PCellID1 0x00000FF4 //
#define UART_O_PCellID2 0x00000FF8 //
#define UART_O_PCellID3 0x00000FFC //
//*****************************************************************************
//
// Data Register bits
//
//*****************************************************************************
#define UART_DR_OE 0x00000800 // Overrun Error
#define UART_DR_BE 0x00000400 // Break Error
#define UART_DR_PE 0x00000200 // Parity Error
#define UART_DR_FE 0x00000100 // Framing Error
#define UART_DR_DATA_MASK 0x000000FF // UART data
//*****************************************************************************
//
// Receive Status Register bits
//
//*****************************************************************************
#define UART_RSR_OE 0x00000008 // Overrun Error
#define UART_RSR_BE 0x00000004 // Break Error
#define UART_RSR_PE 0x00000002 // Parity Error
#define UART_RSR_FE 0x00000001 // Framing Error
//*****************************************************************************
//
// Flag Register bits
//
//*****************************************************************************
#define UART_FR_TXFE 0x00000080 // TX FIFO Empty
#define UART_FR_RXFF 0x00000040 // RX FIFO Full
#define UART_FR_TXFF 0x00000020 // TX FIFO Full
#define UART_FR_RXFE 0x00000010 // RX FIFO Empty
#define UART_FR_BUSY 0x00000008 // UART Busy
//*****************************************************************************
//
// Integer baud-rate divisor
//
//*****************************************************************************
#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor
//*****************************************************************************
//
// Fractional baud-rate divisor
//
//*****************************************************************************
#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor
//*****************************************************************************
//
// Line Control Register High bits
//
//*****************************************************************************
#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select
#define UART_LCR_H_WLEN 0x00000060 // Word length
#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data
#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data
#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data
#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data
#define UART_LCR_H_FEN 0x00000010 // Enable FIFO
#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select
#define UART_LCR_H_EPS 0x00000004 // Even Parity Select
#define UART_LCR_H_PEN 0x00000002 // Parity Enable
#define UART_LCR_H_BRK 0x00000001 // Send Break
//*****************************************************************************
//
// Control Register bits
//
//*****************************************************************************
#define UART_CTL_RXE 0x00000200 // Receive Enable
#define UART_CTL_TXE 0x00000100 // Transmit Enable
#define UART_CTL_LBE 0x00000080 // Loopback Enable
#define UART_CTL_UARTEN 0x00000001 // UART Enable
//*****************************************************************************
//
// Interrupt FIFO Level Select Register bits
//
//*****************************************************************************
#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full
#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full
#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full
#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full
#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full
#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full
#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full
#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full
#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full
#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full
//*****************************************************************************
//
// Interrupt Mask Set/Clear Register bits
//
//*****************************************************************************
#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask
#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask
#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask
#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask
#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask
#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask
#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask
//*****************************************************************************
//
// Raw Interrupt Status Register
//
//*****************************************************************************
#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status
#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status
#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status
#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status
#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status
#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status
#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status
//*****************************************************************************
//
// Masked Interrupt Status Register
//
//*****************************************************************************
#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status
#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status
#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status
#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status
#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status
#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status
#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status
//*****************************************************************************
//
// Interrupt Clear Register bits
//
//*****************************************************************************
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
#define UART_RSR_ANY (UART_RSR_OE | \
UART_RSR_BE | \
UART_RSR_PE | \
UART_RSR_FE)
//*****************************************************************************
//
// Reset Values for UART Registers.
//
//*****************************************************************************
#define UART_RV_DR 0x00000000
#define UART_RV_RSR 0x00000000
#define UART_RV_ECR 0x00000000
#define UART_RV_FR 0x00000090
#define UART_RV_IBRD 0x00000000
#define UART_RV_FBRD 0x00000000
#define UART_RV_LCR_H 0x00000000
#define UART_RV_CTL 0x00000300
#define UART_RV_IFLS 0x00000012
#define UART_RV_IM 0x00000000
#define UART_RV_RIS 0x00000000
#define UART_RV_MIS 0x00000000
#define UART_RV_ICR 0x00000000
#define UART_RV_PeriphID4 0x00000000
#define UART_RV_PeriphID5 0x00000000
#define UART_RV_PeriphID6 0x00000000
#define UART_RV_PeriphID7 0x00000000
#define UART_RV_PeriphID0 0x00000011
#define UART_RV_PeriphID1 0x00000000
#define UART_RV_PeriphID2 0x00000018
#define UART_RV_PeriphID3 0x00000001
#define UART_RV_PCellID0 0x0000000D
#define UART_RV_PCellID1 0x000000F0
#define UART_RV_PCellID2 0x00000005
#define UART_RV_PCellID3 0x000000B1
#endif // __HW_UART_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_watchdog.h
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//*****************************************************************************
//
// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_WATCHDOG_H__
#define __HW_WATCHDOG_H__
//*****************************************************************************
//
// The following define the offsets of the Watchdog Timer registers.
//
//*****************************************************************************
#define WDT_O_LOAD 0x00000000 // Load register
#define WDT_O_VALUE 0x00000004 // Current value register
#define WDT_O_CTL 0x00000008 // Control register
#define WDT_O_ICR 0x0000000C // Interrupt clear register
#define WDT_O_RIS 0x00000010 // Raw interrupt status register
#define WDT_O_MIS 0x00000014 // Masked interrupt status register
#define WDT_O_TEST 0x00000418 // Test register
#define WDT_O_LOCK 0x00000C00 // Lock register
#define WDT_O_PeriphID4 0x00000FD0 //
#define WDT_O_PeriphID5 0x00000FD4 //
#define WDT_O_PeriphID6 0x00000FD8 //
#define WDT_O_PeriphID7 0x00000FDC //
#define WDT_O_PeriphID0 0x00000FE0 //
#define WDT_O_PeriphID1 0x00000FE4 //
#define WDT_O_PeriphID2 0x00000FE8 //
#define WDT_O_PeriphID3 0x00000FEC //
#define WDT_O_PCellID0 0x00000FF0 //
#define WDT_O_PCellID1 0x00000FF4 //
#define WDT_O_PCellID2 0x00000FF8 //
#define WDT_O_PCellID3 0x00000FFC //
//*****************************************************************************
//
// The following define the bit fields in the WDT_CTL register.
//
//*****************************************************************************
#define WDT_CTL_RESEN 0x00000002 // Enable reset output
#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int
//*****************************************************************************
//
// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS
// registers.
//
//*****************************************************************************
#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
//*****************************************************************************
//
// The following define the bit fields in the WDT_TEST register.
//
//*****************************************************************************
#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable
#ifndef DEPRECATED
#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
#endif
//*****************************************************************************
//
// The following define the bit fields in the WDT_LOCK register.
//
//*****************************************************************************
#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked
#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked
#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
//*****************************************************************************
//
// The following define the reset values for the WDT registers.
//
//*****************************************************************************
#define WDT_RV_LOAD 0xFFFFFFFF // Load register
#define WDT_RV_VALUE 0xFFFFFFFF // Current value register
#define WDT_RV_CTL 0x00000000 // Control register
#define WDT_RV_RIS 0x00000000 // Raw interrupt status register
#define WDT_RV_MIS 0x00000000 // Masked interrupt status register
#define WDT_RV_LOCK 0x00000000 // Lock register
#define WDT_RV_PeriphID4 0x00000000 //
#define WDT_RV_PeriphID5 0x00000000 //
#define WDT_RV_PeriphID6 0x00000000 //
#define WDT_RV_PeriphID7 0x00000000 //
#define WDT_RV_PeriphID0 0x00000005 //
#define WDT_RV_PeriphID1 0x00000018 //
#define WDT_RV_PeriphID2 0x00000018 //
#define WDT_RV_PeriphID3 0x00000001 //
#define WDT_RV_PCellID0 0x0000000D //
#define WDT_RV_PCellID1 0x000000F0 //
#define WDT_RV_PCellID2 0x00000005 //
#define WDT_RV_PCellID3 0x000000B1 //
#endif // __HW_WATCHDOG_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.c
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//*****************************************************************************
//
// i2c.c - Driver for Inter-IC (I2C) bus block.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup i2c_api
//! @{
//
//*****************************************************************************
#include "../hw_i2c.h"
#include "../hw_ints.h"
#include "../hw_memmap.h"
#include "../hw_types.h"
#include "debug.h"
#include "i2c.h"
#include "interrupt.h"
#include "sysctl.h"
//*****************************************************************************
//
//! Initializes the I2C Master block.
//!
//! \param ulBase base address of the I2C Master module
//! \param bFast set up for fast data transfers
//!
//! This function initializes operation of the I2C Master block. Upon
//! successful initialization of the I2C block, this function will have
//! set the bus speed for the master, and will have enabled the I2C Master
//! block.
//!
//! If the parameter \e bFast is \b true, then the master block will be
//! set up to transfer data at 400 kbps; otherwise, it will be set up to
//! transfer data at 100 kbps.
//!
//! The I2C clocking is dependent upon the system clock rate returned by
//! SysCtlClockGet(); if it does not return the correct system clock rate then
//! the I2C clock rate will be incorrect.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_masterinit) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CMasterInit(unsigned long ulBase, tBoolean bFast)
{
unsigned long ulSysClk;
unsigned long ulSCLFreq;
unsigned long ulTPR;
//
// Check the arguments.
//
ASSERT(ulBase == I2C_MASTER_BASE);
//
// Must enable the device before doing anything else.
//
I2CMasterEnable(ulBase);
//
// Get the system clock speed.
//
ulSysClk = SysCtlClockGet();
//
// Get the desired SCL speed.
//
if(bFast == true)
{
ulSCLFreq = I2C_SCL_FAST;
}
else
{
ulSCLFreq = I2C_SCL_STANDARD;
}
//
// Compute the clock divider that achieves the fastest speed less than or
// equal to the desired speed. The numerator is biases to favor a larger
// clock divider so that the resulting clock is always less than or equal
// to the desired clock, never greater.
//
ulTPR = (((ulSysClk + (2 * I2C_MASTER_TPR_SCL * ulSCLFreq) - 1) /
(2 * I2C_MASTER_TPR_SCL * ulSCLFreq)) - 1);
HWREG(ulBase + I2C_MASTER_O_TPR) = ulTPR;
}
#endif
//*****************************************************************************
//
//! Initializes the I2C Slave block.
//!
//! \param ulBase base address of the I2C Slave module
//! \param ucSlaveAddr 7-bit slave address
//!
//! This function initializes operation of the I2C Slave block. Upon
//! successful initialization of the I2C blocks, this function will have
//! set the slave address and have enabled the I2C Slave block.
//!
//! The parameter \e ucSlaveAddr is the value that will be compared
//! against the slave address sent by an I2C master.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_slaveinit) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_SLAVE_BASE);
ASSERT(!(ucSlaveAddr & 0x80));
//
// Must enable the device before doing anything else.
//
I2CSlaveEnable(ulBase);
//
// Set up the slave address.
//
HWREG(ulBase + I2C_SLAVE_O_OAR) = ucSlaveAddr;
}
#endif
//*****************************************************************************
//
//! Enables the I2C Master block.
//!
//! \param ulBase base address of the I2C Master module
//!
//! This will enable operation of the I2C Master block.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CMasterEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_MASTER_BASE);
//
// Enable the master block.
//
HWREG(ulBase + I2C_MASTER_O_CR) |= I2C_MASTER_CR_MFE;
}
#endif
//*****************************************************************************
//
//! Enables the I2C Slave block.
//!
//! \param ulBase base address of the I2C Slave module
//!
//! This will enable operation of the I2C Slave block.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_slaveenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CSlaveEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_SLAVE_BASE);
//
// Enable the clock to the slave block.
//
HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) |= I2C_MASTER_CR_SFE;
//
// Enable the slave.
//
HWREG(ulBase + I2C_SLAVE_O_CSR) = I2C_SLAVE_CSR_DA;
}
#endif
//*****************************************************************************
//
//! Disables the I2C master block.
//!
//! \param ulBase base address of the I2C Master module
//!
//! This will disable operation of the I2C master block.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CMasterDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_MASTER_BASE);
//
// Disable the master block.
//
HWREG(ulBase + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_MFE);
}
#endif
//*****************************************************************************
//
//! Disables the I2C slave block.
//!
//! \param ulBase base address of the I2C Slave module
//!
//! This will disable operation of the I2C slave block.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_slavedisable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CSlaveDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_SLAVE_BASE);
//
// Disable the slave.
//
HWREG(ulBase + I2C_SLAVE_O_CSR) = 0;
//
// Disable the clock to the slave block.
//
HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_SFE);
}
#endif
//*****************************************************************************
//
//! Registers an interrupt handler for the I2C module
//!
//! \param ulBase base address of the I2C module
//! \param pfnHandler is a pointer to the function to be called when the
//! synchronous serial interface interrupt occurs.
//!
//! This sets the handler to be called when an I2C interrupt occurs. This
//! will enable the global interrupt in the interrupt controller; specific I2C
//! interrupts must be enabled via I2CMasterIntEnable() and
//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's
//! responsibility to clear the interrupt source via I2CMasterIntClear() and
//! I2CSlaveIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_MASTER_BASE);
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(INT_I2C, pfnHandler);
//
// Enable the I2C interrupt.
//
IntEnable(INT_I2C);
}
#endif
//*****************************************************************************
//
//! Unregisters an interrupt handler for the I2C module.
//!
//! \param ulBase base address of the I2C module
//!
//! This function will clear the handler to be called when an I2C
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CIntUnregister(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_MASTER_BASE);
//
// Disable the interrupt.
//
IntDisable(INT_I2C);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_I2C);
}
#endif
//*****************************************************************************
//
//! Enables the I2C Master interrupt.
//!
//! \param ulBase base address of the I2C Master module
//!
//! Enables the I2C Master interrupt source.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_masterintenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CMasterIntEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_MASTER_BASE);
//
// Enable the master interrupt.
//
HWREG(ulBase + I2C_MASTER_O_IMR) = 1;
}
#endif
//*****************************************************************************
//
//! Enables the I2C Slave interrupt.
//!
//! \param ulBase base address of the I2C Slave module
//!
//! Enables the I2C Slave interrupt source.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_slaveintenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CSlaveIntEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_SLAVE_BASE);
//
// Enable the slave interrupt.
//
HWREG(ulBase + I2C_SLAVE_O_IM) = 1;
}
#endif
//*****************************************************************************
//
//! Disables the I2C Master interrupt.
//!
//! \param ulBase base address of the I2C Master module
//!
//! Disables the I2C Master interrupt source.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_masterintdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CMasterIntDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_MASTER_BASE);
//
// Disable the master interrupt.
//
HWREG(ulBase + I2C_MASTER_O_IMR) = 0;
}
#endif
//*****************************************************************************
//
//! Disables the I2C Slave interrupt.
//!
//! \param ulBase base address of the I2C Slave module
//!
//! Disables the I2C Slave interrupt source.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_slaveintdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CSlaveIntDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_SLAVE_BASE);
//
// Disable the slave interrupt.
//
HWREG(ulBase + I2C_SLAVE_O_IM) = 0;
}
#endif
//*****************************************************************************
//
//! Gets the current I2C Master interrupt status.
//!
//! \param ulBase base address of the I2C Master module
//! \param bMasked is false if the raw interrupt status is requested and
//! true if the masked interrupt status is requested.
//!
//! This returns the interrupt status for the I2C Master module.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//!
//! \return The current interrupt status, returned as \b true if active
//! or \b false if not active.
//
//*****************************************************************************
#if defined(GROUP_masterintstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
tBoolean
I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_MASTER_BASE);
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return((HWREG(ulBase + I2C_MASTER_O_MIS)) ? true : false);
}
else
{
return((HWREG(ulBase + I2C_MASTER_O_RIS)) ? true : false);
}
}
#endif
//*****************************************************************************
//
//! Gets the current I2C Slave interrupt status.
//!
//! \param ulBase base address of the I2C Slave module
//! \param bMasked is false if the raw interrupt status is requested and
//! true if the masked interrupt status is requested.
//!
//! This returns the interrupt status for the I2C Slave module.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//!
//! \return The current interrupt status, returned as \b true if active
//! or \b false if not active.
//
//*****************************************************************************
#if defined(GROUP_slaveintstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
tBoolean
I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_SLAVE_BASE);
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return((HWREG(ulBase + I2C_SLAVE_O_MIS)) ? true : false);
}
else
{
return((HWREG(ulBase + I2C_SLAVE_O_RIS)) ? true : false);
}
}
#endif
//*****************************************************************************
//
//! Clears I2C Master interrupt sources.
//!
//! \param ulBase base address of the I2C Master module
//!
//! The I2C Master interrupt source is cleared, so that it no longer asserts.
//! This must be done in the interrupt handler to keep it from being called
//! again immediately upon exit.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_masterintclear) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CMasterIntClear(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_MASTER_BASE);
//
// Clear the I2C master interrupt source.
//
HWREG(ulBase + I2C_MASTER_O_MICR) = I2C_MASTER_MICR_IC;
//
// Workaround for I2C master interrupt clear errata for rev B Stellaris
// devices. For later devices, this write is ignored and therefore
// harmless (other than the slight performance hit).
//
HWREG(ulBase + I2C_MASTER_O_MIS) = I2C_MASTER_MICR_IC;
}
#endif
//*****************************************************************************
//
//! Clears I2C Slave interrupt sources.
//!
//! \param ulBase base address of the I2C Slave module
//!
//! The I2C Slave interrupt source is cleared, so that it no longer asserts.
//! This must be done in the interrupt handler to keep it from being called
//! again immediately upon exit.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_slaveintclear) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CSlaveIntClear(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_SLAVE_BASE);
//
// Clear the I2C slave interrupt source.
//
HWREG(ulBase + I2C_SLAVE_O_SICR) = I2C_SLAVE_SICR_IC;
}
#endif
//*****************************************************************************
//
//! Sets the address that the I2C Master will place on the bus.
//!
//! \param ulBase base address of the I2C Master module
//! \param ucSlaveAddr 7-bit slave address
//! \param bReceive flag indicating the type of communication with the slave
//!
//! This function will set the address that the I2C Master will place on the
//! bus when initiating a transaction. When the parameter \e bReceive is set
//! to \b true, the address will indicate that the I2C Master is initiating
//! a read from the slave; otherwise the address will indicate that the I2C
//! Master is initiating a write to the slave.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_masterslaveaddrset) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr,
tBoolean bReceive)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_MASTER_BASE);
ASSERT(!(ucSlaveAddr & 0x80));
//
// Set the address of the slave with which the master will communicate.
//
HWREG(ulBase + I2C_MASTER_O_SA) = (ucSlaveAddr << 1) | bReceive;
}
#endif
//*****************************************************************************
//
//! Indicates whether or not the I2C Master is busy.
//!
//! \param ulBase base address of the I2C Master module
//!
//! This function returns an indication of whether or not the I2C Master is
//! busy transmitting or receiving data.
//!
//! \return Returns \b true if the I2C Master is busy; otherwise, returns
//! \b false.
//
//*****************************************************************************
#if defined(GROUP_masterbusy) || defined(BUILD_ALL) || defined(DOXYGEN)
tBoolean
I2CMasterBusy(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_MASTER_BASE);
//
// Return the busy status.
//
if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUSY)
{
return(true);
}
else
{
return(false);
}
}
#endif
//*****************************************************************************
//
//! Indicates whether or not the I2C bus is busy.
//!
//! \param ulBase base address of the I2C Master module
//!
//! This function returns an indication of whether or not the I2C bus is
//! busy. This function can be used in a multi-master environment to
//! determine if another master is currently using the bus.
//!
//! \return Returns \b true if the I2C bus is busy; otherwise, returns
//! \b false.
//
//*****************************************************************************
#if defined(GROUP_masterbusbusy) || defined(BUILD_ALL) || defined(DOXYGEN)
tBoolean
I2CMasterBusBusy(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_MASTER_BASE);
//
// Return the bus busy status.
//
if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUS_BUSY)
{
return(true);
}
else
{
return(false);
}
}
#endif
//*****************************************************************************
//
//! Controls the state of the I2C Master module.
//!
//! \param ulBase base address of the I2C Master module
//! \param ulCmd command to be issued to the I2C Master module
//!
//! This function is used to control the state of the Master module send and
//! receive operations. The parameter \e ucCmd can be one of the following
//! values:
//!
//! - I2C_MASTER_CMD_SINGLE_SEND
//! - I2C_MASTER_CMD_SINGLE_RECEIVE
//! - I2C_MASTER_CMD_BURST_SEND_START
//! - I2C_MASTER_CMD_BURST_SEND_CONT
//! - I2C_MASTER_CMD_BURST_SEND_FINISH
//! - I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
//! - I2C_MASTER_CMD_BURST_RECEIVE_START
//! - I2C_MASTER_CMD_BURST_RECEIVE_CONT
//! - I2C_MASTER_CMD_BURST_RECEIVE_FINISH
//! - I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_mastercontrol) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CMasterControl(unsigned long ulBase, unsigned long ulCmd)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_MASTER_BASE);
ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) ||
(ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) ||
(ulCmd == I2C_MASTER_CMD_BURST_SEND_START) ||
(ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||
(ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||
(ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||
(ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||
(ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||
(ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||
(ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP));
//
// Send the command.
//
HWREG(ulBase + I2C_MASTER_O_CS) = ulCmd;
}
#endif
//*****************************************************************************
//
//! Gets the error status of the I2C Master module.
//!
//! \param ulBase base address of the I2C Master module
//!
//! This function is used to obtain the error status of the Master module
//! send and receive operations. It returns one of the following values:
//!
//! - I2C_MASTER_ERR_NONE
//! - I2C_MASTER_ERR_ADDR_ACK
//! - I2C_MASTER_ERR_DATA_ACK
//! - I2C_MASTER_ERR_ARB_LOST
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_mastererr) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
I2CMasterErr(unsigned long ulBase)
{
unsigned long ulErr;
//
// Check the arguments.
//
ASSERT(ulBase == I2C_MASTER_BASE);
//
// Get the raw error state
//
ulErr = HWREG(ulBase + I2C_MASTER_O_CS);
//
// If the I2C master is busy, then all the other bit are invalid, and
// don't have an error to report.
//
if(ulErr & I2C_MASTER_CS_BUSY)
{
return(I2C_MASTER_ERR_NONE);
}
//
// Check for errors.
//
if(ulErr & I2C_MASTER_CS_ERROR)
{
return(ulErr & (I2C_MASTER_CS_ERR_MASK));
}
else
{
return(I2C_MASTER_ERR_NONE);
}
}
#endif
//*****************************************************************************
//
//! Transmits a byte from the I2C Master.
//!
//! \param ulBase base address of the I2C Master module
//! \param ucData data to be transmitted from the I2C Master
//!
//! This function will place the supplied data into I2C Master Data Register.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_masterdataput) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CMasterDataPut(unsigned long ulBase, unsigned char ucData)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_MASTER_BASE);
//
// Write the byte.
//
HWREG(ulBase + I2C_MASTER_O_DR) = ucData;
}
#endif
//*****************************************************************************
//
//! Receives a byte that has been sent to the I2C Master.
//!
//! \param ulBase base address of the I2C Master module
//!
//! This function reads a byte of data from the I2C Master Data Register.
//!
//! \return Returns the byte received from by the I2C Master, cast as an
//! unsigned long.
//
//*****************************************************************************
#if defined(GROUP_masterdataget) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
I2CMasterDataGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_MASTER_BASE);
//
// Read a byte.
//
return(HWREG(ulBase + I2C_MASTER_O_DR));
}
#endif
//*****************************************************************************
//
//! Gets the I2C Slave module status
//!
//! \param ulBase base address of the I2C Slave module
//!
//! This function will return the action requested from a master, if any. The
//! possible values returned are:
//!
//! - I2C_SLAVE_ACT_NONE
//! - I2C_SLAVE_ACT_RREQ
//! - I2C_SLAVE_ACT_TREQ
//!
//! where I2C_SLAVE_ACT_NONE means that no action has been requested of the
//! I2C Slave module, I2C_SLAVE_ACT_RREQ means that an I2C master has sent
//! data to the I2C Slave module, and I2C_SLAVE_ACT_TREQ means that an I2C
//! master has requested that the I2C Slave module send data.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_slavestatus) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
I2CSlaveStatus(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_SLAVE_BASE);
//
// Return the slave status.
//
return(HWREG(ulBase + I2C_SLAVE_O_CSR));
}
#endif
//*****************************************************************************
//
//! Transmits a byte from the I2C Slave.
//!
//! \param ulBase base address of the I2C Slave module
//! \param ucData data to be transmitted from the I2C Slave
//!
//! This function will place the supplied data into I2C Slave Data Register.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_slavedataput) || defined(BUILD_ALL) || defined(DOXYGEN)
void
I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_SLAVE_BASE);
//
// Write the byte.
//
HWREG(ulBase + I2C_SLAVE_O_DR) = ucData;
}
#endif
//*****************************************************************************
//
//! Receives a byte that has been sent to the I2C Slave.
//!
//! \param ulBase base address of the I2C Slave module
//!
//! This function reads a byte of data from the I2C Slave Data Register.
//!
//! \return Returns the byte received from by the I2C Slave, cast as an
//! unsigned long.
//
//*****************************************************************************
#if defined(GROUP_slavedataget) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
I2CSlaveDataGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == I2C_SLAVE_BASE);
//
// Read a byte.
//
return(HWREG(ulBase + I2C_SLAVE_O_DR));
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.h
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//*****************************************************************************
//
// i2c.h - Prototypes for the I2C Driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __I2C_H__
#define __I2C_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
// Interrupt defines.
//
//*****************************************************************************
#define I2C_INT_MASTER 0x00000001
#define I2C_INT_SLAVE 0x00000002
//*****************************************************************************
//
// I2C Master commands.
//
//*****************************************************************************
#define I2C_MASTER_CMD_SINGLE_SEND \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_SINGLE_RECEIVE \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_SEND_START \
(I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_SEND_CONT \
(I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_SEND_FINISH \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
(I2C_MASTER_CS_STOP)
#define I2C_MASTER_CMD_BURST_RECEIVE_START \
(I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
(I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)
//*****************************************************************************
//
// I2C Master error status.
//
//*****************************************************************************
#define I2C_MASTER_ERR_NONE 0
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
//*****************************************************************************
//
// I2C Slave action requests
//
//*****************************************************************************
#define I2C_SLAVE_ACT_NONE 0
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
//*****************************************************************************
// Miscellaneous I2C driver definitions.
//*****************************************************************************
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));
extern void I2CIntUnregister(unsigned long ulBase);
extern tBoolean I2CMasterBusBusy(unsigned long ulBase);
extern tBoolean I2CMasterBusy(unsigned long ulBase);
extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);
extern unsigned long I2CMasterDataGet(unsigned long ulBase);
extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CMasterDisable(unsigned long ulBase);
extern void I2CMasterEnable(unsigned long ulBase);
extern unsigned long I2CMasterErr(unsigned long ulBase);
extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast);
extern void I2CMasterIntClear(unsigned long ulBase);
extern void I2CMasterIntDisable(unsigned long ulBase);
extern void I2CMasterIntEnable(unsigned long ulBase);
extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void I2CMasterSlaveAddrSet(unsigned long ulBase,
unsigned char ucSlaveAddr,
tBoolean bReceive);
extern unsigned long I2CSlaveDataGet(unsigned long ulBase);
extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CSlaveDisable(unsigned long ulBase);
extern void I2CSlaveEnable(unsigned long ulBase);
extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);
extern void I2CSlaveIntClear(unsigned long ulBase);
extern void I2CSlaveIntDisable(unsigned long ulBase);
extern void I2CSlaveIntEnable(unsigned long ulBase);
extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);
extern unsigned long I2CSlaveStatus(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __I2C_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.c
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//*****************************************************************************
//
// interrupt.c - Driver for the NVIC Interrupt Controller.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup interrupt_api
//! @{
//
//*****************************************************************************
#include "../hw_ints.h"
#include "../hw_nvic.h"
#include "../hw_types.h"
#include "cpu.h"
#include "debug.h"
#include "interrupt.h"
//*****************************************************************************
//
// This is a mapping between priority grouping encodings and the number of
// preemption priority bits.
//
//*****************************************************************************
#if defined(GROUP_pulpriority) || defined(BUILD_ALL)
const unsigned long g_pulPriority[] =
{
NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
};
#else
extern const unsigned long g_pulPriority[];
#endif
//*****************************************************************************
//
// This is a mapping between interrupt number and the register that contains
// the priority encoding for that interrupt.
//
//*****************************************************************************
#if defined(GROUP_pulregs) || defined(BUILD_ALL)
const unsigned long g_pulRegs[12] =
{
0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7
};
#else
extern const unsigned long g_pulRegs[12];
#endif
//*****************************************************************************
//
//! \internal
//! The default interrupt handler.
//!
//! This is the default interrupt handler for all interrupts. It simply loops
//! forever so that the system state is preserved for observation by a
//! debugger. Since interrupts should be disabled before unregistering the
//! corresponding handler, this should never be called.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_defaulthandler) || defined(BUILD_ALL)
void
IntDefaultHandler(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
#else
extern void IntDefaultHandler(void);
#endif
//*****************************************************************************
//
// The processor vector table.
//
// This contains a list of the handlers for the various interrupt sources in
// the system. The layout of this list is defined by the hardware; assertion
// of an interrupt causes the processor to start executing directly at the
// address given in the corresponding location in this list.
//
//*****************************************************************************
#if defined(GROUP_vtable) || defined(BUILD_ALL)
#ifdef ewarm
__no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
#else
__attribute__((section("vtable")))
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
#endif
#else
extern void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
#endif
//*****************************************************************************
//
//! Enables the processor interrupt.
//!
//! Allows the processor to respond to interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
IntMasterEnable(void)
{
//
// Enable processor interrupts.
//
CPUcpsie();
}
#endif
//*****************************************************************************
//
//! Disables the processor interrupt.
//!
//! Prevents the processor from receiving interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
IntMasterDisable(void)
{
//
// Disable processor interrupts.
//
CPUcpsid();
}
#endif
//*****************************************************************************
//
//! Registers a function to be called when an interrupt occurs.
//!
//! \param ulInterrupt specifies the interrupt in question.
//! \param pfnHandler is a pointer to the function to be called.
//!
//! This function is used to specify the handler function to be called when the
//! given interrupt is asserted to the processor. When the interrupt occurs,
//! if it is enabled (via IntEnable()), the handler function will be called in
//! interrupt context. Since the handler function can preempt other code, care
//! must be taken to protect memory or peripherals that are accessed by the
//! handler and other non-handler code.
//!
//! \note The use of this function (directly or indirectly via a peripheral
//! driver interrupt register function) moves the interrupt vector table from
//! flash to SRAM. Therefore, care must be taken when linking the application
//! to ensure that the SRAM vector table is located at the beginning of SRAM;
//! otherwise NVIC will not look in the correct portion of memory for the
//! vector table (it requires the vector table be on a 1 kB memory alignment).
//! Normally, the SRAM vector table is so placed via the use of linker scripts;
//! some tool chains, such as the evaluation version of RV-MDK, do not support
//! linker scripts and therefore will not produce a valid executable. See the
//! discussion of compile-time versus run-time interrupt handler registration
//! in the introduction to this chapter.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_register) || defined(BUILD_ALL) || defined(DOXYGEN)
void
IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
{
unsigned long ulIdx;
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Make sure that the RAM vector table is correctly aligned.
//
ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0);
//
// See if the RAM vector table has been initialized.
//
if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors)
{
//
// Copy the vector table from the beginning of FLASH to the RAM vector
// table.
//
for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++)
{
g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG(ulIdx * 4);
}
//
// Point NVIC at the RAM vector table.
//
HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors;
}
//
// Save the interrupt handler.
//
g_pfnRAMVectors[ulInterrupt] = pfnHandler;
}
#endif
//*****************************************************************************
//
//! Unregisters the function to be called when an interrupt occurs.
//!
//! \param ulInterrupt specifies the interrupt in question.
//!
//! This function is used to indicate that no handler should be called when the
//! given interrupt is asserted to the processor. The interrupt source will be
//! automatically disabled (via IntDisable()) if necessary.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_unregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
IntUnregister(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Reset the interrupt handler.
//
g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler;
}
#endif
//*****************************************************************************
//
//! Sets the priority grouping of the interrupt controller.
//!
//! \param ulBits specifies the number of bits of preemptable priority.
//!
//! This function specifies the split between preemptable priority levels and
//! subpriority levels in the interrupt priority specification. The range of
//! the grouping values are dependent upon the hardware implementation; on
//! the Stellaris family it can range from 0 to 3.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_prioritygroupingset) || defined(BUILD_ALL) || \
defined(DOXYGEN)
void
IntPriorityGroupingSet(unsigned long ulBits)
{
//
// Check the arguments.
//
ASSERT(ulBits < NUM_PRIORITY_BITS);
//
// Set the priority grouping.
//
HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits];
}
#endif
//*****************************************************************************
//
//! Gets the priority grouping of the interrupt controller.
//!
//! This function returns the split between preemptable priority levels and
//! subpriority levels in the interrupt priority specification.
//!
//! \return The number of bits of preemptable priority.
//
//*****************************************************************************
#if defined(GROUP_prioritygroupingget) || defined(BUILD_ALL) || \
defined(DOXYGEN)
unsigned long
IntPriorityGroupingGet(void)
{
unsigned long ulLoop, ulValue;
//
// Read the priority grouping.
//
ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
//
// Loop through the priority grouping values.
//
for(ulLoop = 0; ulLoop < 8; ulLoop++)
{
//
// Stop looping if this value matches.
//
if(ulValue == g_pulPriority[ulLoop])
{
break;
}
}
//
// Return the number of priority bits.
//
return(ulLoop);
}
#endif
//*****************************************************************************
//
//! Sets the priority of an interrupt.
//!
//! \param ulInterrupt specifies the interrupt in question.
//! \param ucPriority specifies the priority of the interrupt.
//!
//! This function is used to set the priority of an interrupt. When multiple
//! interrupts are asserted simultaneously, the ones with the highest priority
//! are processed before the lower priority interrupts. Smaller numbers
//! correspond to higher interrupt priorities; priority 0 is the highest
//! interrupt priority.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! priority level (where N is 3 for the Stellaris family), so any
//! prioritization must be performed in those bits. The remaining bits can be
//! used to sub-prioritize the interrupt sources, and may be used by the
//! hardware priority mechanism on a future part. This arrangement allows
//! priorities to migrate to different NVIC implementations without changing
//! the gross prioritization of the interrupts.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_priorityset) || defined(BUILD_ALL) || defined(DOXYGEN)
void
IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
{
unsigned long ulTemp;
//
// Check the arguments.
//
ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
//
// Set the interrupt priority.
//
ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]);
ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3)));
ulTemp |= ucPriority << (8 * (ulInterrupt & 3));
HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp;
}
#endif
//*****************************************************************************
//
//! Gets the priority of an interrupt.
//!
//! \param ulInterrupt specifies the interrupt in question.
//!
//! This function gets the priority of an interrupt. See IntPrioritySet() for
//! a definition of the priority value.
//!
//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
//! specified.
//
//*****************************************************************************
#if defined(GROUP_priorityget) || defined(BUILD_ALL) || defined(DOXYGEN)
long
IntPriorityGet(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
//
// Return the interrupt priority.
//
return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) &
0xFF);
}
#endif
//*****************************************************************************
//
//! Enables an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be enabled.
//!
//! The specified interrupt is enabled in the interrupt controller. Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
IntEnable(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to enable.
//
if(ulInterrupt == FAULT_MPU)
{
//
// Enable the MemManage interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
}
else if(ulInterrupt == FAULT_BUS)
{
//
// Enable the bus fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
}
else if(ulInterrupt == FAULT_USAGE)
{
//
// Enable the usage fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Enable the System Tick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
else if(ulInterrupt >= INT_GPIOA)
{
//
// Enable the general interrupt.
//
HWREG(NVIC_EN0) = 1 << (ulInterrupt - INT_GPIOA);
}
}
#endif
//*****************************************************************************
//
//! Disables an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be disabled.
//!
//! The specified interrupt is disabled in the interrupt controller. Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
IntDisable(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to disable.
//
if(ulInterrupt == FAULT_MPU)
{
//
// Disable the MemManage interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
}
else if(ulInterrupt == FAULT_BUS)
{
//
// Disable the bus fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
}
else if(ulInterrupt == FAULT_USAGE)
{
//
// Disable the usage fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Disable the System Tick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
}
else if(ulInterrupt >= INT_GPIOA)
{
//
// Disable the general interrupt.
//
HWREG(NVIC_DIS0) = 1 << (ulInterrupt - INT_GPIOA);
}
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void IntMasterEnable(void);
extern void IntMasterDisable(void);
extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
extern void IntUnregister(unsigned long ulInterrupt);
extern void IntPriorityGroupingSet(unsigned long ulBits);
extern unsigned long IntPriorityGroupingGet(void);
extern void IntPrioritySet(unsigned long ulInterrupt,
unsigned char ucPriority);
extern long IntPriorityGet(unsigned long ulInterrupt);
extern void IntEnable(unsigned long ulInterrupt);
extern void IntDisable(unsigned long ulInterrupt);
#ifdef __cplusplus
}
#endif
#endif // __INTERRUPT_H__

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//*****************************************************************************
//
// osram96x16.c - Driver for the OSRAM 96x16 graphical OLED display.
//
// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup ev_lm3s811_api
//! @{
//
//*****************************************************************************
#include "DriverLib.h"
#include "osram96x16.h"
#define ewarm
//*****************************************************************************
//
// The I2C slave address of the SSD0303 controller on the OLED display.
//
//*****************************************************************************
#define SSD0303_ADDR 0x3d
//*****************************************************************************
//
// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this
// table) for displaying text on the OLED display. The data is organized as
// bytes from the left column to the right column, with each byte containing
// the top row in the LSB and the bottom row in the MSB.
//
//*****************************************************************************
static const unsigned char g_pucFont[95][5] =
{
{ 0x00, 0x00, 0x00, 0x00, 0x00 }, // " "
{ 0x00, 0x00, 0x4f, 0x00, 0x00 }, // !
{ 0x00, 0x07, 0x00, 0x07, 0x00 }, // "
{ 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // #
{ 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $
{ 0x23, 0x13, 0x08, 0x64, 0x62 }, // %
{ 0x36, 0x49, 0x55, 0x22, 0x50 }, // &
{ 0x00, 0x05, 0x03, 0x00, 0x00 }, // '
{ 0x00, 0x1c, 0x22, 0x41, 0x00 }, // (
{ 0x00, 0x41, 0x22, 0x1c, 0x00 }, // )
{ 0x14, 0x08, 0x3e, 0x08, 0x14 }, // *
{ 0x08, 0x08, 0x3e, 0x08, 0x08 }, // +
{ 0x00, 0x50, 0x30, 0x00, 0x00 }, // ,
{ 0x08, 0x08, 0x08, 0x08, 0x08 }, // -
{ 0x00, 0x60, 0x60, 0x00, 0x00 }, // .
{ 0x20, 0x10, 0x08, 0x04, 0x02 }, // /
{ 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0
{ 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1
{ 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2
{ 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3
{ 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4
{ 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5
{ 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6
{ 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7
{ 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8
{ 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9
{ 0x00, 0x36, 0x36, 0x00, 0x00 }, // :
{ 0x00, 0x56, 0x36, 0x00, 0x00 }, // ;
{ 0x08, 0x14, 0x22, 0x41, 0x00 }, // <
{ 0x14, 0x14, 0x14, 0x14, 0x14 }, // =
{ 0x00, 0x41, 0x22, 0x14, 0x08 }, // >
{ 0x02, 0x01, 0x51, 0x09, 0x06 }, // ?
{ 0x32, 0x49, 0x79, 0x41, 0x3e }, // @
{ 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A
{ 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B
{ 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C
{ 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D
{ 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E
{ 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F
{ 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G
{ 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H
{ 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I
{ 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J
{ 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K
{ 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L
{ 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M
{ 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N
{ 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O
{ 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P
{ 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q
{ 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R
{ 0x46, 0x49, 0x49, 0x49, 0x31 }, // S
{ 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T
{ 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U
{ 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V
{ 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W
{ 0x63, 0x14, 0x08, 0x14, 0x63 }, // X
{ 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y
{ 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z
{ 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [
{ 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\"
{ 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ]
{ 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^
{ 0x40, 0x40, 0x40, 0x40, 0x40 }, // _
{ 0x00, 0x01, 0x02, 0x04, 0x00 }, // `
{ 0x20, 0x54, 0x54, 0x54, 0x78 }, // a
{ 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b
{ 0x38, 0x44, 0x44, 0x44, 0x20 }, // c
{ 0x38, 0x44, 0x44, 0x48, 0x7f }, // d
{ 0x38, 0x54, 0x54, 0x54, 0x18 }, // e
{ 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f
{ 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g
{ 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h
{ 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i
{ 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j
{ 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k
{ 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l
{ 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m
{ 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n
{ 0x38, 0x44, 0x44, 0x44, 0x38 }, // o
{ 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p
{ 0x08, 0x14, 0x14, 0x18, 0x7c }, // q
{ 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r
{ 0x48, 0x54, 0x54, 0x54, 0x20 }, // s
{ 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t
{ 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u
{ 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v
{ 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w
{ 0x44, 0x28, 0x10, 0x28, 0x44 }, // x
{ 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y
{ 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z
{ 0x00, 0x08, 0x36, 0x41, 0x00 }, // {
{ 0x00, 0x00, 0x7f, 0x00, 0x00 }, // |
{ 0x00, 0x41, 0x36, 0x08, 0x00 }, // }
{ 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~
};
//*****************************************************************************
//
// The sequence of commands used to initialize the SSD0303 controller. Each
// command is described as follows: there is a byte specifying the number of
// bytes in the I2C transfer, followed by that many bytes of command data.
//
//*****************************************************************************
static const unsigned char g_pucOSRAMInit[] =
{
//
// Turn off the panel
//
0x04, 0x80, 0xae, 0x80, 0xe3,
//
// Set lower column address
//
0x04, 0x80, 0x04, 0x80, 0xe3,
//
// Set higher column address
//
0x04, 0x80, 0x12, 0x80, 0xe3,
//
// Set contrast control register
//
0x06, 0x80, 0x81, 0x80, 0x2b, 0x80, 0xe3,
//
// Set segment re-map
//
0x04, 0x80, 0xa1, 0x80, 0xe3,
//
// Set display start line
//
0x04, 0x80, 0x40, 0x80, 0xe3,
//
// Set display offset
//
0x06, 0x80, 0xd3, 0x80, 0x00, 0x80, 0xe3,
//
// Set multiplex ratio
//
0x06, 0x80, 0xa8, 0x80, 0x0f, 0x80, 0xe3,
//
// Set the display to normal mode
//
0x04, 0x80, 0xa4, 0x80, 0xe3,
//
// Non-inverted display
//
0x04, 0x80, 0xa6, 0x80, 0xe3,
//
// Set the page address
//
0x04, 0x80, 0xb0, 0x80, 0xe3,
//
// Set COM output scan direction
//
0x04, 0x80, 0xc8, 0x80, 0xe3,
//
// Set display clock divide ratio/oscillator frequency
//
0x06, 0x80, 0xd5, 0x80, 0x72, 0x80, 0xe3,
//
// Enable mono mode
//
0x06, 0x80, 0xd8, 0x80, 0x00, 0x80, 0xe3,
//
// Set pre-charge period
//
0x06, 0x80, 0xd9, 0x80, 0x22, 0x80, 0xe3,
//
// Set COM pins hardware configuration
//
0x06, 0x80, 0xda, 0x80, 0x12, 0x80, 0xe3,
//
// Set VCOM deslect level
//
0x06, 0x80, 0xdb, 0x80, 0x0f, 0x80, 0xe3,
//
// Set DC-DC on
//
0x06, 0x80, 0xad, 0x80, 0x8b, 0x80, 0xe3,
//
// Turn on the panel
//
0x04, 0x80, 0xaf, 0x80, 0xe3,
};
//*****************************************************************************
//
// The inter-byte delay required by the SSD0303 OLED controller.
//
//*****************************************************************************
static unsigned long g_ulDelay;
//*****************************************************************************
//
//! \internal
//!
//! Provide a small delay.
//!
//! \param ulCount is the number of delay loop iterations to perform.
//!
//! Since the SSD0303 controller needs a delay between bytes written to it over
//! the I2C bus, this function provides a means of generating that delay. It
//! is written in assembly to keep the delay consistent across tool chains,
//! avoiding the need to tune the delay based on the tool chain in use.
//!
//! \return None.
//
//*****************************************************************************
#if defined(ewarm)
static void
OSRAMDelay(unsigned long ulCount)
{
__asm(" subs r0, #1\n"
" bne OSRAMDelay\n"
" bx lr");
}
#endif
#if defined(gcc)
static void __attribute__((naked))
OSRAMDelay(unsigned long ulCount)
{
__asm(" subs r0, #1\n"
" bne OSRAMDelay\n"
" bx lr");
}
#endif
#if defined(rvmdk) || defined(__ARMCC_VERSION)
__asm void
OSRAMDelay(unsigned long ulCount)
{
subs r0, #1;
bne OSRAMDelay;
bx lr;
}
#endif
//*****************************************************************************
//
//! \internal
//!
//! Start a transfer to the SSD0303 controller.
//!
//! \param ucChar is the first byte to be written to the controller.
//!
//! This function will start a transfer to the SSD0303 controller via the I2C
//! bus.
//!
//! The data is written in a polled fashion; this function will not return
//! until the byte has been written to the controller.
//!
//! \return None.
//
//*****************************************************************************
static void
OSRAMWriteFirst(unsigned char ucChar)
{
//
// Set the slave address.
//
I2CMasterSlaveAddrSet(I2C_MASTER_BASE, SSD0303_ADDR, false);
//
// Write the first byte to the controller.
//
I2CMasterDataPut(I2C_MASTER_BASE, ucChar);
//
// Start the transfer.
//
I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START);
}
//*****************************************************************************
//
//! \internal
//!
//! Write a byte to the SSD0303 controller.
//!
//! \param ucChar is the byte to be transmitted to the controller.
//!
//! This function continues a transfer to the SSD0303 controller by writing
//! another byte over the I2C bus. This must only be called after calling
//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal().
//!
//! The data is written in a polled faashion; this function will not return
//! until the byte has been written to the controller.
//!
//! \return None.
//
//*****************************************************************************
static void
OSRAMWriteByte(unsigned char ucChar)
{
//
// Wait until the current byte has been transferred.
//
while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0)
{
}
//
// Provide the required inter-byte delay.
//
OSRAMDelay(g_ulDelay);
//
// Write the next byte to the controller.
//
I2CMasterDataPut(I2C_MASTER_BASE, ucChar);
//
// Continue the transfer.
//
I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT);
}
//*****************************************************************************
//
//! \internal
//!
//! Write a sequence of bytes to the SSD0303 controller.
//!
//! This function continues a transfer to the SSD0303 controller by writing a
//! sequence of bytes over the I2C bus. This must only be called after calling
//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal().
//!
//! The data is written in a polled fashion; this function will not return
//! until the entire byte sequence has been written to the controller.
//!
//! \return None.
//
//*****************************************************************************
static void
OSRAMWriteArray(const unsigned char *pucBuffer, unsigned long ulCount)
{
//
// Loop while there are more bytes left to be transferred.
//
while(ulCount != 0)
{
//
// Wait until the current byte has been transferred.
//
while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0)
{
}
//
// Provide the required inter-byte delay.
//
OSRAMDelay(g_ulDelay);
//
// Write the next byte to the controller.
//
I2CMasterDataPut(I2C_MASTER_BASE, *pucBuffer++);
ulCount--;
//
// Continue the transfer.
//
I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT);
}
}
//*****************************************************************************
//
//! \internal
//!
//! Finish a transfer to the SSD0303 controller.
//!
//! \param ucChar is the final byte to be written to the controller.
//!
//! This function will finish a transfer to the SSD0303 controller via the I2C
//! bus. This must only be called after calling OSRAMWriteFirst().
//!
//! The data is written in a polled fashion; this function will not return
//! until the byte has been written to the controller.
//!
//! \return None.
//
//*****************************************************************************
static void
OSRAMWriteFinal(unsigned char ucChar)
{
//
// Wait until the current byte has been transferred.
//
while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0)
{
}
//
// Provide the required inter-byte delay.
//
OSRAMDelay(g_ulDelay);
//
// Write the final byte to the controller.
//
I2CMasterDataPut(I2C_MASTER_BASE, ucChar);
//
// Finish the transfer.
//
I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_FINISH);
//
// Wait until the final byte has been transferred.
//
while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0)
{
}
//
// Provide the required inter-byte delay.
//
OSRAMDelay(g_ulDelay);
}
//*****************************************************************************
//
//! Clears the OLED display.
//!
//! This function will clear the display. All pixels in the display will be
//! turned off.
//!
//! This function is contained in <tt>osram96x16.c</tt>, with
//! <tt>osram96x16.h</tt> containing the API definition for use by
//! applications.
//!
//! \return None.
//
//*****************************************************************************
void
OSRAMClear(void)
{
static const unsigned char pucRow1[] =
{
0xb0, 0x80, 0x04, 0x80, 0x12, 0x40
};
static const unsigned char pucRow2[] =
{
0xb1, 0x80, 0x04, 0x80, 0x12, 0x40
};
unsigned long ulIdx;
//
// Move the display cursor to the first column of the first row.
//
OSRAMWriteFirst(0x80);
OSRAMWriteArray(pucRow1, sizeof(pucRow1));
//
// Fill this row with zeros.
//
for(ulIdx = 0; ulIdx < 95; ulIdx++)
{
OSRAMWriteByte(0x00);
}
OSRAMWriteFinal(0x00);
//
// Move the display cursor to the first column of the second row.
//
OSRAMWriteFirst(0x80);
OSRAMWriteArray(pucRow2, sizeof(pucRow2));
//
// Fill this row with zeros.
//
for(ulIdx = 0; ulIdx < 95; ulIdx++)
{
OSRAMWriteByte(0x00);
}
OSRAMWriteFinal(0x00);
}
//*****************************************************************************
//
//! Displays a string on the OLED display.
//!
//! \param pcStr is a pointer to the string to display.
//! \param ulX is the horizontal position to display the string, specified in
//! columns from the left edge of the display.
//! \param ulY is the vertical position to display the string, specified in
//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are
//! valid).
//!
//! This function will draw a string on the display. Only the ASCII characters
//! between 32 (space) and 126 (tilde) are supported; other characters will
//! result in random data being draw on the display (based on whatever appears
//! before/after the font in memory). The font is mono-spaced, so characters
//! such as "i" and "l" have more white space around them than characters such
//! as "m" or "w".
//!
//! If the drawing of the string reaches the right edge of the display, no more
//! characters will be drawn. Therefore, special care is not required to avoid
//! supplying a string that is "too long" to display.
//!
//! This function is contained in <tt>osram96x16.c</tt>, with
//! <tt>osram96x16.h</tt> containing the API definition for use by
//! applications.
//!
//! \return None.
//
//*****************************************************************************
void
OSRAMStringDraw(const char *pcStr, unsigned long ulX, unsigned long ulY)
{
//
// Check the arguments.
//
ASSERT(ulX < 96);
ASSERT(ulY < 2);
//
// Move the display cursor to the requested position on the display.
//
OSRAMWriteFirst(0x80);
OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1);
OSRAMWriteByte(0x80);
OSRAMWriteByte((ulX + 36) & 0x0f);
OSRAMWriteByte(0x80);
OSRAMWriteByte(0x10 | (((ulX + 36) >> 4) & 0x0f));
OSRAMWriteByte(0x40);
//
// Loop while there are more characters in the string.
//
while(*pcStr != 0)
{
//
// See if there is enough space on the display for this entire
// character.
//
if(ulX <= 90)
{
//
// Write the contents of this character to the display.
//
OSRAMWriteArray(g_pucFont[*pcStr - ' '], 5);
//
// See if this is the last character to display (either because the
// right edge has been reached or because there are no more
// characters).
//
if((ulX == 90) || (pcStr[1] == 0))
{
//
// Write the final column of the display.
//
OSRAMWriteFinal(0x00);
//
// The string has been displayed.
//
return;
}
//
// Write the inter-character padding column.
//
OSRAMWriteByte(0x00);
}
else
{
//
// Write the portion of the character that will fit onto the
// display.
//
OSRAMWriteArray(g_pucFont[*pcStr - ' '], 95 - ulX);
OSRAMWriteFinal(g_pucFont[*pcStr - ' '][95 - ulX]);
//
// The string has been displayed.
//
return;
}
//
// Advance to the next character.
//
pcStr++;
//
// Increment the X coordinate by the six columns that were just
// written.
//
ulX += 6;
}
}
//*****************************************************************************
//
//! Displays an image on the OLED display.
//!
//! \param pucImage is a pointer to the image data.
//! \param ulX is the horizontal position to display this image, specified in
//! columns from the left edge of the display.
//! \param ulY is the vertical position to display this image, specified in
//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are
//! valid).
//! \param ulWidth is the width of the image, specified in columns.
//! \param ulHeight is the height of the image, specified in eight row blocks
//! (i.e. only 1 and 2 are valid).
//!
//! This function will display a bitmap graphic on the display. The image to
//! be displayed must be a multiple of eight scan lines high (i.e. one row) and
//! will be drawn at a vertical position that is a multiple of eight scan lines
//! (i.e. scan line zero or scan line eight, corresponding to row zero or row
//! one).
//!
//! The image data is organized with the first row of image data appearing left
//! to right, followed immediately by the second row of image data. Each byte
//! contains the data for the eight scan lines of the column, with the top scan
//! line being in the least significant bit of the byte and the bottom scan
//! line being in the most significant bit of the byte.
//!
//! For example, an image four columns wide and sixteen scan lines tall would
//! be arranged as follows (showing how the eight bytes of the image would
//! appear on the display):
//!
//! \verbatim
//! +-------+ +-------+ +-------+ +-------+
//! | | 0 | | | 0 | | | 0 | | | 0 |
//! | B | 1 | | B | 1 | | B | 1 | | B | 1 |
//! | y | 2 | | y | 2 | | y | 2 | | y | 2 |
//! | t | 3 | | t | 3 | | t | 3 | | t | 3 |
//! | e | 4 | | e | 4 | | e | 4 | | e | 4 |
//! | | 5 | | | 5 | | | 5 | | | 5 |
//! | 0 | 6 | | 1 | 6 | | 2 | 6 | | 3 | 6 |
//! | | 7 | | | 7 | | | 7 | | | 7 |
//! +-------+ +-------+ +-------+ +-------+
//!
//! +-------+ +-------+ +-------+ +-------+
//! | | 0 | | | 0 | | | 0 | | | 0 |
//! | B | 1 | | B | 1 | | B | 1 | | B | 1 |
//! | y | 2 | | y | 2 | | y | 2 | | y | 2 |
//! | t | 3 | | t | 3 | | t | 3 | | t | 3 |
//! | e | 4 | | e | 4 | | e | 4 | | e | 4 |
//! | | 5 | | | 5 | | | 5 | | | 5 |
//! | 4 | 6 | | 5 | 6 | | 6 | 6 | | 7 | 6 |
//! | | 7 | | | 7 | | | 7 | | | 7 |
//! +-------+ +-------+ +-------+ +-------+
//! \endverbatim
//!
//! This function is contained in <tt>osram96x16.c</tt>, with
//! <tt>osram96x16.h</tt> containing the API definition for use by
//! applications.
//!
//! \return None.
//
//*****************************************************************************
void
OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX,
unsigned long ulY, unsigned long ulWidth,
unsigned long ulHeight)
{
//
// Check the arguments.
//
ASSERT(ulX < 96);
ASSERT(ulY < 2);
ASSERT((ulX + ulWidth) <= 96);
ASSERT((ulY + ulHeight) <= 2);
//
// The first 36 columns of the LCD buffer are not displayed, so increment
// the X coorddinate by 36 to account for the non-displayed frame buffer
// memory.
//
ulX += 36;
//
// Loop while there are more rows to display.
//
while(ulHeight--)
{
//
// Write the starting address within this row.
//
OSRAMWriteFirst(0x80);
OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1);
OSRAMWriteByte(0x80);
OSRAMWriteByte(ulX & 0x0f);
OSRAMWriteByte(0x80);
OSRAMWriteByte(0x10 | ((ulX >> 4) & 0x0f));
OSRAMWriteByte(0x40);
//
// Write this row of image data.
//
OSRAMWriteArray(pucImage, ulWidth - 1);
OSRAMWriteFinal(pucImage[ulWidth - 1]);
//
// Advance to the next row of the image.
//
pucImage += ulWidth;
ulY++;
}
}
//*****************************************************************************
//
//! Initialize the OLED display.
//!
//! \param bFast is a boolean that is \e true if the I2C interface should be
//! run at 400 kbps and \e false if it should be run at 100 kbps.
//!
//! This function initializes the I2C interface to the OLED display and
//! configures the SSD0303 controller on the panel.
//!
//! This function is contained in <tt>osram96x16.c</tt>, with
//! <tt>osram96x16.h</tt> containing the API definition for use by
//! applications.
//!
//! \return None.
//
//*****************************************************************************
void
OSRAMInit(tBoolean bFast)
{
unsigned long ulIdx;
//
// Enable the I2C and GPIO port B blocks as they are needed by this driver.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
//
// Configure the I2C SCL and SDA pins for I2C operation.
//
GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3);
//
// Initialize the I2C master.
//
I2CMasterInit(I2C_MASTER_BASE, bFast);
//
// Compute the inter-byte delay for the SSD0303 controller. This delay is
// dependent upon the I2C bus clock rate; the slower the clock the longer
// the delay required.
//
// The derivation of this formula is based on a measured delay of
// OSRAMDelay(1700) for a 100 kHz I2C bus with the CPU running at 50 MHz
// (referred to as C). To scale this to the delay for a different CPU
// speed (since this is just a CPU-based delay loop) is:
//
// f(CPU)
// C * ----------
// 50,000,000
//
// To then scale this to the actual I2C rate (since it won't always be
// precisely 100 kHz):
//
// f(CPU) 100,000
// C * ---------- * -------
// 50,000,000 f(I2C)
//
// This equation will give the inter-byte delay required for any
// configuration of the I2C master. But, as arranged it is impossible to
// directly compute in 32-bit arithmetic (without loosing a lot of
// accuracy). So, the equation is simplified.
//
// Since f(I2C) is generated by dividing down from f(CPU), replace it with
// the equivalent (where TPR is the value programmed into the Master Timer
// Period Register of the I2C master, with the 1 added back):
//
// 100,000
// f(CPU) -------
// C * ---------- * f(CPU)
// 50,000,000 ------------
// 2 * 10 * TPR
//
// Inverting the dividend in the last term:
//
// f(CPU) 100,000 * 2 * 10 * TPR
// C * ---------- * ----------------------
// 50,000,000 f(CPU)
//
// The f(CPU) now cancels out.
//
// 100,000 * 2 * 10 * TPR
// C * ----------------------
// 50,000,000
//
// Since there are no clock frequencies left in the equation, this equation
// also works for 400 kHz bus operation as well, since the 100,000 in the
// numerator becomes 400,000 but C is 1/4, which cancel out each other.
// Reducing the constants gives:
//
// TPR TPR TPR
// C * --- = 1700 * --- = 340 * --- = 68 * TPR
// 25 25 5
//
// Note that the constant C is actually a bit larger than it needs to be in
// order to provide some safety margin.
//
g_ulDelay = 68 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1);
//
// Initialize the SSD0303 controller. Loop through the initialization
// sequence doing a single I2C transfer for each command.
//
for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit);
ulIdx += g_pucOSRAMInit[ulIdx] + 1)
{
//
// Send this command.
//
OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]);
OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2);
OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]);
}
//
// Clear the frame buffer.
//
OSRAMClear();
}
//*****************************************************************************
//
//! Turns on the OLED display.
//!
//! This function will turn on the OLED display, causing it to display the
//! contents of its internal frame buffer.
//!
//! This function is contained in <tt>osram96x16.c</tt>, with
//! <tt>osram96x16.h</tt> containing the API definition for use by
//! applications.
//!
//! \return None.
//
//*****************************************************************************
void
OSRAMDisplayOn(void)
{
unsigned long ulIdx;
//
// Re-initialize the SSD0303 controller. Loop through the initialization
// sequence doing a single I2C transfer for each command.
//
for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit);
ulIdx += g_pucOSRAMInit[ulIdx] + 1)
{
//
// Send this command.
//
OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]);
OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2);
OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]);
}
}
//*****************************************************************************
//
//! Turns off the OLED display.
//!
//! This function will turn off the OLED display. This will stop the scanning
//! of the panel and turn off the on-chip DC-DC converter, preventing damage to
//! the panel due to burn-in (it has similar characters to a CRT in this
//! respect).
//!
//! This function is contained in <tt>osram96x16.c</tt>, with
//! <tt>osram96x16.h</tt> containing the API definition for use by
//! applications.
//!
//! \return None.
//
//*****************************************************************************
void
OSRAMDisplayOff(void)
{
//
// Turn off the DC-DC converter and the display.
//
OSRAMWriteFirst(0x80);
OSRAMWriteByte(0xae);
OSRAMWriteByte(0x80);
OSRAMWriteByte(0xad);
OSRAMWriteByte(0x80);
OSRAMWriteFinal(0x8a);
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// osram96x16.h - Prototypes for the driver for the OSRAM 96x16 graphical OLED
// display.
//
// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __OSRAM96X16_H__
#define __OSRAM96X16_H__
//*****************************************************************************
//
// Prototypes for the driver APIs.
//
//*****************************************************************************
extern void OSRAMClear(void);
extern void OSRAMStringDraw(const char *pcStr, unsigned long ulX,
unsigned long ulY);
extern void OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX,
unsigned long ulY, unsigned long ulWidth,
unsigned long ulHeight);
extern void OSRAMInit(tBoolean bFast);
extern void OSRAMDisplayOn(void);
extern void OSRAMDisplayOff(void);
#endif // __OSRAM96X16_H__

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//*****************************************************************************
//
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __PWM_H__
#define __PWM_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are passed to PWMGenConfigure() as the ulConfig
// parameter and specify the configuration of the PWM generator.
//
//*****************************************************************************
#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM generator interrupts and
// triggers.
//
//*****************************************************************************
#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM interrupts.
//
//*****************************************************************************
#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
#define PWM_INT_FAULT 0x00010000 // Fault interrupt
//*****************************************************************************
//
// Defines to identify the generators within a module.
//
//*****************************************************************************
#define PWM_GEN_0 0x00000040 // Offset address of Gen0
#define PWM_GEN_1 0x00000080 // Offset address of Gen1
#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
//*****************************************************************************
//
// Defines to identify the outputs within a module.
//
//*****************************************************************************
#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
unsigned long ulConfig);
extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
unsigned long ulPeriod);
extern unsigned long PWMGenPeriodGet(unsigned long ulBase,
unsigned long ulGen);
extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);
extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);
extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
unsigned long ulWidth);
extern unsigned long PWMPulseWidthGet(unsigned long ulBase,
unsigned long ulPWMOut);
extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
unsigned short usRise, unsigned short usFall);
extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);
extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);
extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);
extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bEnable);
extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bInvert);
extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bFaultKill);
extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
void (*pfnIntHandler)(void));
extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);
extern void PWMFaultIntRegister(unsigned long ulBase,
void (*pfnIntHandler)(void));
extern void PWMFaultIntUnregister(unsigned long ulBase);
extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
unsigned long ulIntTrig);
extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
unsigned long ulIntTrig);
extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,
tBoolean bMasked);
extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,
unsigned long ulInts);
extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);
extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);
extern void PWMFaultIntClear(unsigned long ulBase);
extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);
#ifdef __cplusplus
}
#endif
#endif // __PWM_H__

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//*****************************************************************************
//
// qei.c - Driver for the Quadrature Encoder with Index.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup qei_api
//! @{
//
//*****************************************************************************
#include "../hw_ints.h"
#include "../hw_memmap.h"
#include "../hw_qei.h"
#include "../hw_types.h"
#include "debug.h"
#include "interrupt.h"
#include "qei.h"
//*****************************************************************************
//
//! Enables the quadrature encoder.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will enable operation of the quadrature encoder module. It must be
//! configured before it is enabled.
//!
//! \sa QEIConfigure()
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
QEIEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
//
// Enable the QEI module.
//
HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_ENABLE;
}
#endif
//*****************************************************************************
//
//! Disables the quadrature encoder.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will disable operation of the quadrature encoder module.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
QEIDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
//
// Disable the QEI module.
//
HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_ENABLE);
}
#endif
//*****************************************************************************
//
//! Configures the quadrature encoder.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulConfig is the configuration for the quadrature encoder. See below
//! for a description of this parameter.
//! \param ulMaxPosition specifies the maximum position value.
//!
//! This will configure the operation of the quadrature encoder. The
//! \e ulConfig parameter provides the configuration of the encoder and is the
//! logical OR of several values:
//!
//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges
//! on channel A or on both channels A and B should be counted by the
//! position integrator and velocity accumulator.
//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the
//! position integrator should be reset when the index pulse is detected.
//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if
//! quadrature signals are being provided on ChA and ChB, or if a direction
//! signal and a clock are being provided instead.
//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals
//! provided on ChA and ChB should be swapped before being processed.
//!
//! \e ulMaxPosition is the maximum value of the position integrator, and is
//! the value used to reset the position capture when in index reset mode and
//! moving in the reverse (negative) direction.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN)
void
QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxPosition)
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
//
// Write the new configuration to the hardware.
//
HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) &
~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE |
QEI_CTL_SIGMODE | QEI_CTL_SWAP)) |
ulConfig);
//
// Set the maximum position.
//
HWREG(ulBase + QEI_O_MAXPOS) = ulMaxPosition;
}
#endif
//*****************************************************************************
//
//! Gets the current encoder position.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the current position of the encoder. Depending upon the
//! configuration of the encoder, and the incident of an index pulse, this
//! value may or may not contain the expected data (i.e. if in reset on index
//! mode, if an index pulse has not been encountered, the position counter will
//! not be aligned with the index pulse yet).
//!
//! \return The current position of the encoder.
//
//*****************************************************************************
#if defined(GROUP_positionget) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
QEIPositionGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
//
// Return the current position counter.
//
return(HWREG(ulBase + QEI_O_POS));
}
#endif
//*****************************************************************************
//
//! Sets the current encoder position.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulPosition is the new position for the encoder.
//!
//! This sets the current position of the encoder; the encoder position will
//! then be measured relative to this value.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_positionset) || defined(BUILD_ALL) || defined(DOXYGEN)
void
QEIPositionSet(unsigned long ulBase, unsigned long ulPosition)
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
//
// Set the position counter.
//
HWREG(ulBase + QEI_O_POS) = ulPosition;
}
#endif
//*****************************************************************************
//
//! Gets the current direction of rotation.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the current direction of rotation. In this case, current
//! means the most recently detected direction of the encoder; it may not be
//! presently moving but this is the direction it last moved before it stopped.
//!
//! \return 1 if moving in the forward direction or -1 if moving in the reverse
//! direction.
//
//*****************************************************************************
#if defined(GROUP_directionget) || defined(BUILD_ALL) || defined(DOXYGEN)
long
QEIDirectionGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
//
// Return the direction of rotation.
//
return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1);
}
#endif
//*****************************************************************************
//
//! Gets the encoder error indicator.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the error indicator for the quadrature encoder. It is an
//! error for both of the signals of the quadrature input to change at the same
//! time.
//!
//! \return true if an error has occurred and false otherwise.
//
//*****************************************************************************
#if defined(GROUP_errorget) || defined(BUILD_ALL) || defined(DOXYGEN)
tBoolean
QEIErrorGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
//
// Return the error indicator.
//
return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false);
}
#endif
//*****************************************************************************
//
//! Enables the velocity capture.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will enable operation of the velocity capture in the quadrature
//! encoder module. It must be configured before it is enabled. Velocity
//! capture will not occur if the quadrature encoder is not enabled.
//!
//! \sa QEIVelocityConfigure() and QEIEnable()
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_velocityenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
QEIVelocityEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
//
// Enable the velocity capture.
//
HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_VELEN;
}
#endif
//*****************************************************************************
//
//! Disables the velocity capture.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will disable operation of the velocity capture in the quadrature
//! encoder module.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_velocitydisable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
QEIVelocityDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
//
// Disable the velocity capture.
//
HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_VELEN);
}
#endif
//*****************************************************************************
//
//! Configures the velocity capture.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulPreDiv specifies the predivider applied to the input quadrature
//! signal before it is counted; can be one of QEI_VELDIV_1, QEI_VELDIV_2,
//! QEI_VELDIV_4, QEI_VELDIV_8, QEI_VELDIV_16, QEI_VELDIV_32, QEI_VELDIV_64, or
//! QEI_VELDIV_128.
//! \param ulPeriod specifies the number of clock ticks over which to measure
//! the velocity; must be non-zero.
//!
//! This will configure the operation of the velocity capture portion of the
//! quadrature encoder. The position increment signal is predivided as
//! specified by \e ulPreDiv before being accumulated by the velocity capture.
//! The divided signal is accumulated over \e ulPeriod system clock before
//! being saved and resetting the accumulator.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_velocityconfigure) || defined(BUILD_ALL) || defined(DOXYGEN)
void
QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
unsigned long ulPeriod)
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
ASSERT(!(ulPreDiv & ~(QEI_CTL_VELDIV_M)));
ASSERT(ulPeriod != 0);
//
// Set the velocity predivider.
//
HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) &
~(QEI_CTL_VELDIV_M)) | ulPreDiv);
//
// Set the timer period.
//
HWREG(ulBase + QEI_O_LOAD) = ulPeriod - 1;
}
#endif
//*****************************************************************************
//
//! Gets the current encoder speed.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the current speed of the encoder. The value returned is the
//! number of pulses detected in the specified time period; this number can be
//! multiplied by the number of time periods per second and divided by the
//! number of pulses per revolution to obtain the number of revolutions per
//! second.
//!
//! \return The number of pulses captured in the given time period.
//
//*****************************************************************************
#if defined(GROUP_velocityget) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
QEIVelocityGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
//
// Return the speed capture value.
//
return(HWREG(ulBase + QEI_O_SPEED));
}
#endif
//*****************************************************************************
//
//! Registers an interrupt handler for the quadrature encoder interrupt.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param pfnHandler is a pointer to the function to be called when the
//! quadrature encoder interrupt occurs.
//!
//! This sets the handler to be called when a quadrature encoder interrupt
//! occurs. This will enable the global interrupt in the interrupt controller;
//! specific quadrature encoder interrupts must be enabled via QEIIntEnable().
//! It is the interrupt handler's responsibility to clear the interrupt source
//! via QEIIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(INT_QEI, pfnHandler);
//
// Enable the quadrature encoder interrupt.
//
IntEnable(INT_QEI);
}
#endif
//*****************************************************************************
//
//! Unregisters an interrupt handler for the quadrature encoder interrupt.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This function will clear the handler to be called when a quadrature encoder
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
QEIIntUnregister(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
//
// Disable the interrupt.
//
IntDisable(INT_QEI);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_QEI);
}
#endif
//*****************************************************************************
//
//! Enables individual quadrature encoder interrupt sources.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX
//! values.
//!
//! Enables the indicated quadrature encoder interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
//
// Enable the specified interrupts.
//
HWREG(ulBase + QEI_O_INTEN) |= ulIntFlags;
}
#endif
//*****************************************************************************
//
//! Disables individual quadrature encoder interrupt sources.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX
//! values.
//!
//! Disables the indicated quadrature encoder interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
//
// Disable the specified interrupts.
//
HWREG(ulBase + QEI_O_INTEN) &= ~(ulIntFlags);
}
#endif
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the quadrature encoder module.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, and QEI_INTINDEX.
//
//*****************************************************************************
#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
QEIIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + QEI_O_ISC));
}
else
{
return(HWREG(ulBase + QEI_O_RIS));
}
}
#endif
//*****************************************************************************
//
//! Clears quadrature encoder interrupt sources.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX
//! values.
//!
//! The specified quadrature encoder interrupt sources are cleared, so that
//! they no longer assert. This must be done in the interrupt handler to keep
//! it from being called again immediately upon exit.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)
void
QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(ulBase == QEI_BASE);
//
// Clear the requested interrupt sources.
//
HWREG(ulBase + QEI_O_ISC) = ulIntFlags;
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// qei.h - Prototypes for the Quadrature Encoder Driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __QEI_H__
#define __QEI_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to QEIConfigure as the ulConfig paramater.
//
//*****************************************************************************
#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only
#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges
#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse
#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse
#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature
#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir
#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB
#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB
//*****************************************************************************
//
// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.
//
//*****************************************************************************
#define QEI_VELDIV_1 0x00000000 // Predivide by 1
#define QEI_VELDIV_2 0x00000040 // Predivide by 2
#define QEI_VELDIV_4 0x00000080 // Predivide by 4
#define QEI_VELDIV_8 0x000000C0 // Predivide by 8
#define QEI_VELDIV_16 0x00000100 // Predivide by 16
#define QEI_VELDIV_32 0x00000140 // Predivide by 32
#define QEI_VELDIV_64 0x00000180 // Predivide by 64
#define QEI_VELDIV_128 0x000001C0 // Predivide by 128
//*****************************************************************************
//
// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts
// as the ulIntFlags parameter, and returned by QEIGetIntStatus.
//
//*****************************************************************************
#define QEI_INTERROR 0x00000008 // Phase error detected
#define QEI_INTDIR 0x00000004 // Direction change
#define QEI_INTTIMER 0x00000002 // Velocity timer expired
#define QEI_INTINDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void QEIEnable(unsigned long ulBase);
extern void QEIDisable(unsigned long ulBase);
extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxPosition);
extern unsigned long QEIPositionGet(unsigned long ulBase);
extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);
extern long QEIDirectionGet(unsigned long ulBase);
extern tBoolean QEIErrorGet(unsigned long ulBase);
extern void QEIVelocityEnable(unsigned long ulBase);
extern void QEIVelocityDisable(unsigned long ulBase);
extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
unsigned long ulPeriod);
extern unsigned long QEIVelocityGet(unsigned long ulBase);
extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void QEIIntUnregister(unsigned long ulBase);
extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
#ifdef __cplusplus
}
#endif
#endif // __QEI_H__

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//*****************************************************************************
//
// ssi.c - Driver for Synchronous Serial Interface.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup ssi_api
//! @{
//
//*****************************************************************************
#include "../hw_ints.h"
#include "../hw_memmap.h"
#include "../hw_ssi.h"
#include "../hw_types.h"
#include "debug.h"
#include "interrupt.h"
#include "ssi.h"
#include "sysctl.h"
//*****************************************************************************
//
//! Configures the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulProtocol specifies the data transfer protocol.
//! \param ulMode specifies the mode of operation.
//! \param ulBitRate specifies the clock rate.
//! \param ulDataWidth specifies number of bits transfered per frame.
//!
//! This function configures the synchronous serial interface. It sets
//! the SSI protocol, mode of operation, bit rate, and data width.
//!
//! The parameter \e ulProtocol defines the data frame format. The parameter
//! \e ulProtocol can be one of the following values: SSI_FRF_MOTO_MODE_0,
//! SSI_FRF_MOTO_MODE_1, SSI_FRF_MOTO_MODE_2, SSI_FRF_MOTO_MODE_3,
//! SSI_FRF_TI, or SSI_FRF_NMW. The Motorola frame formats imply the
//! following polarity and phase configurations:
//! <pre>
//! Polarity Phase Mode
//! 0 0 SSI_FRF_MOTO_MODE_0
//! 0 1 SSI_FRF_MOTO_MODE_1
//! 1 0 SSI_FRF_MOTO_MODE_2
//! 1 1 SSI_FRF_MOTO_MODE_3
//! </pre>
//!
//! The parameter \e ulMode defines the operating mode of the SSI module. The
//! SSI module can operate as a master or slave; if a slave, the SSI can be
//! configured to disable output on its serial output line. The parameter
//! \e ulMode can be one of the following values: SSI_MODE_MASTER,
//! SSI_MODE_SLAVE, or SSI_MODE_SLAVE_OD.
//!
//! The parameter \e ulBitRate defines the bit rate for the SSI. This bit rate
//! must satisfy the following clock ratio criteria:
//! - FSSI >= 2 * bit rate (master mode)
//! - FSSI >= 12 * bit rate (slave modes)
//!
//! where FSSI is the frequency of the clock supplied to the SSI module.
//!
//! The parameter \e ulDataWidth defines the width of the data transfers.
//! The parameter \e ulDataWidth can be a value between 4 and 16, inclusive.
//!
//! The SSI clocking is dependent upon the system clock rate returned by
//! SysCtlClockGet(); if it does not return the correct system clock rate then
//! the SSI clock rate will be incorrect.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_config) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SSIConfig(unsigned long ulBase, unsigned long ulProtocol, unsigned long ulMode,
unsigned long ulBitRate, unsigned long ulDataWidth)
{
unsigned long ulMaxBitRate;
unsigned long ulRegVal;
unsigned long ulPreDiv;
unsigned long ulSCR;
unsigned long ulSPH_SPO;
unsigned long ulClock;
//
// Check the arguments.
//
ASSERT(ulBase == SSI_BASE);
ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) ||
(ulProtocol == SSI_FRF_MOTO_MODE_1) ||
(ulProtocol == SSI_FRF_MOTO_MODE_2) ||
(ulProtocol == SSI_FRF_MOTO_MODE_3) ||
(ulProtocol == SSI_FRF_TI) ||
(ulProtocol == SSI_FRF_NMW));
ASSERT((ulMode == SSI_MODE_MASTER) ||
(ulMode == SSI_MODE_SLAVE) ||
(ulMode == SSI_MODE_SLAVE_OD));
ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16));
//
// Get the processor clock rate.
//
ulClock = SysCtlClockGet();
//
// Validate the clock speed.
//
ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulClock / 2))) ||
((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulClock / 12))));
ASSERT((ulClock / ulBitRate) <= (254 * 256));
//
// Set the mode.
//
ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0;
ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS;
HWREG(ulBase + SSI_O_CR1) = ulRegVal;
//
// Set the clock predivider.
//
ulMaxBitRate = ulClock / ulBitRate;
ulPreDiv = 0;
do
{
ulPreDiv += 2;
ulSCR = (ulMaxBitRate / ulPreDiv) - 1;
}
while(ulSCR > 255);
HWREG(ulBase + SSI_O_CPSR) = ulPreDiv;
//
// Set protocol and clock rate.
//
ulSPH_SPO = ulProtocol << 6;
ulProtocol &= SSI_CR0_FRF_MASK;
ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1);
HWREG(ulBase + SSI_O_CR0) = ulRegVal;
}
#endif
//*****************************************************************************
//
//! Enables the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This will enable operation of the synchronous serial interface. It must be
//! configured before it is enabled.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SSIEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == SSI_BASE);
//
// Read-modify-write the enable bit.
//
HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE;
}
#endif
//*****************************************************************************
//
//! Disables the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This will disable operation of the synchronous serial interface.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SSIDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == SSI_BASE);
//
// Read-modify-write the enable bit.
//
HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE);
}
#endif
//*****************************************************************************
//
//! Registers an interrupt handler for the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//! \param pfnHandler is a pointer to the function to be called when the
//! synchronous serial interface interrupt occurs.
//!
//! This sets the handler to be called when an SSI interrupt
//! occurs. This will enable the global interrupt in the interrupt controller;
//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary,
//! it is the interrupt handler's responsibility to clear the interrupt source
//! via SSIIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT(ulBase == SSI_BASE);
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(INT_SSI, pfnHandler);
//
// Enable the synchronous serial interface interrupt.
//
IntEnable(INT_SSI);
}
#endif
//*****************************************************************************
//
//! Unregisters an interrupt handler for the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This function will clear the handler to be called when a SSI
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SSIIntUnregister(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == SSI_BASE);
//
// Disable the interrupt.
//
IntDisable(INT_SSI);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_SSI);
}
#endif
//*****************************************************************************
//
//! Enables individual SSI interrupt sources.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated SSI interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor. The parameter \e ulIntFlags Can be
//! any of the SSI_TXFF, SSI_RXFF, SSI_RXTO, or SSI_RXOR values.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(ulBase == SSI_BASE);
//
// Enable the specified interrupts.
//
HWREG(ulBase + SSI_O_IM) |= ulIntFlags;
}
#endif
//*****************************************************************************
//
//! Disables individual SSI interrupt sources.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//!
//! Disables the indicated SSI interrupt sources. The parameter
//! \e ulIntFlags Can be any of the SSI_TXFF, SSI_RXFF, SSI_RXTO,
//! or SSI_RXOR values.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(ulBase == SSI_BASE);
//
// Disable the specified interrupts.
//
HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags);
}
#endif
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase specifies the SSI module base address.
//! \param bMasked is false if the raw interrupt status is required and
//! true if the masked interrupt status is required.
//!
//! This returns the interrupt status for the SSI module.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! SSI_TXFF, SSI_RXFF, SSI_RXTO, and SSI_RXOR.
//
//*****************************************************************************
#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
SSIIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(ulBase == SSI_BASE);
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + SSI_O_MIS));
}
else
{
return(HWREG(ulBase + SSI_O_RIS));
}
}
#endif
//*****************************************************************************
//
//! Clears SSI interrupt sources.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified SSI interrupt sources are cleared, so that
//! they no longer assert. This must be done in the interrupt handler to
//! keep it from being called again immediately upon exit.
//! The parameter \e ulIntFlags can consist of either or both the SSI_RXTO
//! and SSI_RXOR values.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(ulBase == SSI_BASE);
//
// Clear the requested interrupt sources.
//
HWREG(ulBase + SSI_O_ICR) = ulIntFlags;
}
#endif
//*****************************************************************************
//
//! Puts a data element into the SSI transmit FIFO.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulData data to be transmitted over the SSI interface.
//!
//! This function will place the supplied data into the transmit FIFO of
//! the specified SSI module.
//!
//! \note The upper 32 - N bits of the \e ulData will be discarded by the
//! hardware, where N is the data width as configured by SSIConfig(). For
//! example, if the interface is configured for 8 bit data width, the upper 24
//! bits of \e ulData will be discarded.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_dataput) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SSIDataPut(unsigned long ulBase, unsigned long ulData)
{
//
// Check the arguments.
//
ASSERT(ulBase == SSI_BASE);
ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
SSI_CR0_DSS))) == 0);
//
// Wait until there is space.
//
while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF))
{
}
//
// Write the data to the SSI.
//
HWREG(ulBase + SSI_O_DR) = ulData;
}
#endif
//*****************************************************************************
//
//! Puts a data element into the SSI transmit FIFO.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulData data to be transmitted over the SSI interface.
//!
//! This function will place the supplied data into the transmit FIFO of
//! the specified SSI module. If there is no space in the FIFO, then this
//! function will return a zero.
//!
//! \note The upper 32 - N bits of the \e ulData will be discarded by the
//! hardware, where N is the data width as configured by SSIConfig(). For
//! example, if the interface is configured for 8 bit data width, the upper 24
//! bits of \e ulData will be discarded.
//!
//! \return Returns the number of elements written to the SSI transmit FIFO.
//
//*****************************************************************************
#if defined(GROUP_datanonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN)
long
SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData)
{
//
// Check the arguments.
//
ASSERT(ulBase == SSI_BASE);
ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
SSI_CR0_DSS))) == 0);
//
// Check for space to write.
//
if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)
{
HWREG(ulBase + SSI_O_DR) = ulData;
return(1);
}
else
{
return(0);
}
}
#endif
//*****************************************************************************
//
//! Gets a data element from the SSI receive FIFO.
//!
//! \param ulBase specifies the SSI module base address.
//! \param pulData pointer to a storage location for data that was received
//! over the SSI interface.
//!
//! This function will get received data from the receive FIFO of the specified
//! SSI module, and place that data into the location specified by the
//! \e pulData parameter.
//!
//! \note Only the lower N bits of the value written to \e pulData will contain
//! valid data, where N is the data width as configured by SSIConfig(). For
//! example, if the interface is configured for 8 bit data width, only the
//! lower 8 bits of the value written to \e pulData will contain valid data.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_dataget) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SSIDataGet(unsigned long ulBase, unsigned long *pulData)
{
//
// Check the arguments.
//
ASSERT(ulBase == SSI_BASE);
//
// Wait until there is data to be read.
//
while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE))
{
}
//
// Read data from SSI.
//
*pulData = HWREG(ulBase + SSI_O_DR);
}
#endif
//*****************************************************************************
//
//! Gets a data element from the SSI receive FIFO.
//!
//! \param ulBase specifies the SSI module base address.
//! \param pulData pointer to a storage location for data that was received
//! over the SSI interface.
//!
//! This function will get received data from the receive FIFO of
//! the specified SSI module, and place that data into the location specified
//! by the \e ulData parameter. If there is no data in the FIFO, then this
//! function will return a zero.
//!
//! \note Only the lower N bits of the value written to \e pulData will contain
//! valid data, where N is the data width as configured by SSIConfig(). For
//! example, if the interface is configured for 8 bit data width, only the
//! lower 8 bits of the value written to \e pulData will contain valid data.
//!
//! \return Returns the number of elements read from the SSI receive FIFO.
//
//*****************************************************************************
#if defined(GROUP_datanonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN)
long
SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *pulData)
{
//
// Check the arguments.
//
ASSERT(ulBase == SSI_BASE);
//
// Check for data to read.
//
if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)
{
*pulData = HWREG(ulBase + SSI_O_DR);
return(1);
}
else
{
return(0);
}
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __SSI_H__
#define __SSI_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
// as the ulIntFlags parameter, and returned by SSIIntStatus.
//
//*****************************************************************************
#define SSI_TXFF 0x00000008 // TX FIFO half empty or less
#define SSI_RXFF 0x00000004 // RX FIFO half full or less
#define SSI_RXTO 0x00000002 // RX timeout
#define SSI_RXOR 0x00000001 // RX overrun
//*****************************************************************************
//
// Values that can be passed to SSIConfig.
//
//*****************************************************************************
#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
#define SSI_FRF_TI 0x00000010 // TI frame format
#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
#define SSI_MODE_MASTER 0x00000000 // SSI master
#define SSI_MODE_SLAVE 0x00000001 // SSI slave
#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol,
unsigned long ulMode, unsigned long ulBitRate,
unsigned long ulDataWidth);
extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);
extern long SSIDataNonBlockingGet(unsigned long ulBase,
unsigned long *pulData);
extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);
extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData);
extern void SSIDisable(unsigned long ulBase);
extern void SSIEnable(unsigned long ulBase);
extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void SSIIntUnregister(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __SSI_H__

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//*****************************************************************************
//
// sysctl.h - Prototypes for the system control driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __SYSCTL_H__
#define __SYSCTL_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following are values that can be passed to the
// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
// ulPeripheral parameter. The peripherals in the fourth group (upper nibble
// is 3) can only be used with the SysCtlPeripheralPresent() API.
//
//*****************************************************************************
#define SYSCTL_PERIPH_PWM 0x00100000 // PWM
#define SYSCTL_PERIPH_ADC 0x00010000 // ADC
#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
#define SYSCTL_PERIPH_SSI 0x10000010 // SSI
#define SYSCTL_PERIPH_QEI 0x10000100 // QEI
#define SYSCTL_PERIPH_I2C 0x10001000 // I2C
#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0
#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1
#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2
#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0
#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1
#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2
#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D
#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E
#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPinPresent() API
// as the ulPin parameter.
//
//*****************************************************************************
#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin
#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin
#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin
#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin
#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin
#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin
#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
#define SYSCTL_PIN_C0O 0x00000100 // C0o pin
#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin
#define SYSCTL_PIN_C1O 0x00000800 // C1o pin
#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin
#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin
#define SYSCTL_PIN_C2O 0x00004000 // C2o pin
#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin
#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin
#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin
#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin
#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin
#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin
#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin
#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin
#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin
#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin
#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin
#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin
#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOSet() API as
// the ulVoltage value, or returned by the SysCtlLDOGet() API.
//
//*****************************************************************************
#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOConfigSet() API.
//
//*****************************************************************************
#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlIntEnable(),
// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
// by the SysCtlIntStatus() API.
//
//*****************************************************************************
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlResetCauseClear()
// API or returned by the SysCtlResetCauseGet() API.
//
//*****************************************************************************
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlBrownOutConfigSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPWMClockSet() API
// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
// API.
//
//*****************************************************************************
#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlADCSpeedSet() API
// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
// API.
//
//*****************************************************************************
#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second
#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second
#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second
#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlClockSet() API as
// the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc
#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc
#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long SysCtlSRAMSizeGet(void);
extern unsigned long SysCtlFlashSizeGet(void);
extern tBoolean SysCtlPinPresent(unsigned long ulPin);
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralClockGating(tBoolean bEnable);
extern void SysCtlIntRegister(void (*pfnHandler)(void));
extern void SysCtlIntUnregister(void);
extern void SysCtlIntEnable(unsigned long ulInts);
extern void SysCtlIntDisable(unsigned long ulInts);
extern void SysCtlIntClear(unsigned long ulInts);
extern unsigned long SysCtlIntStatus(tBoolean bMasked);
extern void SysCtlLDOSet(unsigned long ulVoltage);
extern unsigned long SysCtlLDOGet(void);
extern void SysCtlLDOConfigSet(unsigned long ulConfig);
extern void SysCtlReset(void);
extern void SysCtlSleep(void);
extern void SysCtlDeepSleep(void);
extern unsigned long SysCtlResetCauseGet(void);
extern void SysCtlResetCauseClear(unsigned long ulCauses);
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
unsigned long ulDelay);
extern void SysCtlClockSet(unsigned long ulConfig);
extern unsigned long SysCtlClockGet(void);
extern void SysCtlPWMClockSet(unsigned long ulConfig);
extern unsigned long SysCtlPWMClockGet(void);
extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
extern unsigned long SysCtlADCSpeedGet(void);
extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
extern void SysCtlPLLVerificationSet(tBoolean bEnable);
extern void SysCtlClkVerificationClear(void);
#ifdef __cplusplus
}
#endif
#endif // __SYSCTL_H__

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//*****************************************************************************
//
// systick.c - Driver for the SysTick timer in NVIC.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup systick_api
//! @{
//
//*****************************************************************************
#include "../hw_ints.h"
#include "../hw_nvic.h"
#include "../hw_types.h"
#include "debug.h"
#include "interrupt.h"
#include "systick.h"
//*****************************************************************************
//
//! Enables the SysTick counter.
//!
//! This will start the SysTick counter. If an interrupt handler has been
//! registered, it will be called when the SysTick counter rolls over.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SysTickEnable(void)
{
//
// Enable SysTick.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;
}
#endif
//*****************************************************************************
//
//! Disables the SysTick counter.
//!
//! This will stop the SysTick counter. If an interrupt handler has been
//! registered, it will no longer be called until SysTick is restarted.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SysTickDisable(void)
{
//
// Disable SysTick.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);
}
#endif
//*****************************************************************************
//
//! Registers an interrupt handler for the SysTick interrupt.
//!
//! \param pfnHandler is a pointer to the function to be called when the
//! SysTick interrupt occurs.
//!
//! This sets the handler to be called when a SysTick interrupt occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SysTickIntRegister(void (*pfnHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(FAULT_SYSTICK, pfnHandler);
//
// Enable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
#endif
//*****************************************************************************
//
//! Unregisters the interrupt handler for the SysTick interrupt.
//!
//! This function will clear the handler to be called when a SysTick interrupt
//! occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SysTickIntUnregister(void)
{
//
// Disable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
//
// Unregister the interrupt handler.
//
IntUnregister(FAULT_SYSTICK);
}
#endif
//*****************************************************************************
//
//! Enables the SysTick interrupt.
//!
//! This function will enable the SysTick interrupt, allowing it to be
//! reflected to the processor.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SysTickIntEnable(void)
{
//
// Enable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
#endif
//*****************************************************************************
//
//! Disables the SysTick interrupt.
//!
//! This function will disable the SysTick interrupt, preventing it from being
//! reflected to the processor.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SysTickIntDisable(void)
{
//
// Disable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
}
#endif
//*****************************************************************************
//
//! Sets the period of the SysTick counter.
//!
//! \param ulPeriod is the number of clock ticks in each period of the SysTick
//! counter; must be between 1 and 16,777,216, inclusive.
//!
//! This function sets the rate at which the SysTick counter wraps; this
//! equates to the number of processor clocks between interrupts.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_periodset) || defined(BUILD_ALL) || defined(DOXYGEN)
void
SysTickPeriodSet(unsigned long ulPeriod)
{
//
// Check the arguments.
//
ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216));
//
// Set the period of the SysTick counter.
//
HWREG(NVIC_ST_RELOAD) = ulPeriod - 1;
}
#endif
//*****************************************************************************
//
//! Gets the period of the SysTick counter.
//!
//! This function returns the rate at which the SysTick counter wraps; this
//! equates to the number of processor clocks between interrupts.
//!
//! \return Returns the period of the SysTick counter.
//
//*****************************************************************************
#if defined(GROUP_periodget) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
SysTickPeriodGet(void)
{
//
// Return the period of the SysTick counter.
//
return(HWREG(NVIC_ST_RELOAD) + 1);
}
#endif
//*****************************************************************************
//
//! Gets the current value of the SysTick counter.
//!
//! This function returns the current value of the SysTick counter; this will
//! be a value between the period - 1 and zero, inclusive.
//!
//! \return Returns the current value of the SysTick counter.
//
//*****************************************************************************
#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
SysTickValueGet(void)
{
//
// Return the current value of the SysTick counter.
//
return(HWREG(NVIC_ST_CURRENT));
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.h
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//*****************************************************************************
//
// systick.h - Prototypes for the SysTick driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __SYSTICK_H__
#define __SYSTICK_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SysTickEnable(void);
extern void SysTickDisable(void);
extern void SysTickIntRegister(void (*pfnHandler)(void));
extern void SysTickIntUnregister(void);
extern void SysTickIntEnable(void);
extern void SysTickIntDisable(void);
extern void SysTickPeriodSet(unsigned long ulPeriod);
extern unsigned long SysTickPeriodGet(void);
extern unsigned long SysTickValueGet(void);
#ifdef __cplusplus
}
#endif
#endif // __SYSTICK_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.h
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//*****************************************************************************
//
// timer.h - Prototypes for the timer module
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __TIMER_H__
#define __TIMER_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to TimerConfigure as the ulConfig parameter.
//
//*****************************************************************************
#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer
#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer
#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer
#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer
#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
//*****************************************************************************
//
// Values that can be passed to TimerIntEnable, TimerIntDisable, and
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
//
//*****************************************************************************
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
//*****************************************************************************
//
// Values that can be passed to TimerControlEvent as the ulEvent parameter.
//
//*****************************************************************************
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
//*****************************************************************************
//
// Values that can be passed to most of the timer APIs as the ulTimer
// parameter.
//
//*****************************************************************************
#define TIMER_A 0x000000ff // Timer A
#define TIMER_B 0x0000ff00 // Timer B
#define TIMER_BOTH 0x0000ffff // Timer Both
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
tBoolean bInvert);
extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
tBoolean bEnable);
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulEvent);
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
tBoolean bStall);
extern void TimerRTCEnable(unsigned long ulBase);
extern void TimerRTCDisable(unsigned long ulBase);
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
extern unsigned long TimerValueGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
void (*pfnHandler)(void));
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerQuiesce(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __TIMER_H__

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//*****************************************************************************
//
// uart.c - Driver for the UART.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup uart_api
//! @{
//
//*****************************************************************************
#include "../hw_ints.h"
#include "../hw_memmap.h"
#include "../hw_types.h"
#include "../hw_uart.h"
#include "debug.h"
#include "interrupt.h"
#include "sysctl.h"
#include "uart.h"
//*****************************************************************************
//
//! Sets the type of parity.
//!
//! \param ulBase is the base address of the UART port.
//! \param ulParity specifies the type of parity to use.
//!
//! Sets the type of parity to use for transmitting and expect when receiving.
//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE,
//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,
//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the
//! parity bit; it will always be either be one or zero based on the mode.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_paritymodeset) || defined(BUILD_ALL) || defined(DOXYGEN)
void
UARTParityModeSet(unsigned long ulBase, unsigned long ulParity)
{
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
ASSERT((ulParity == UART_CONFIG_PAR_NONE) ||
(ulParity == UART_CONFIG_PAR_EVEN) ||
(ulParity == UART_CONFIG_PAR_ODD) ||
(ulParity == UART_CONFIG_PAR_ONE) ||
(ulParity == UART_CONFIG_PAR_ZERO));
//
// Set the parity mode.
//
HWREG(ulBase + UART_O_LCR_H) = ((HWREG(ulBase + UART_O_LCR_H) &
~(UART_LCR_H_SPS | UART_LCR_H_EPS |
UART_LCR_H_PEN)) | ulParity);
}
#endif
//*****************************************************************************
//
//! Gets the type of parity currently being used.
//!
//! \param ulBase is the base address of the UART port.
//!
//! \return The current parity settings, specified as one of
//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.
//
//*****************************************************************************
#if defined(GROUP_paritymodeget) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
UARTParityModeGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// Return the current parity setting.
//
return(HWREG(ulBase + UART_O_LCR_H) &
(UART_LCR_H_SPS | UART_LCR_H_EPS | UART_LCR_H_PEN));
}
#endif
//*****************************************************************************
//
//! Sets the configuration of a UART.
//!
//! \param ulBase is the base address of the UART port.
//! \param ulBaud is the desired baud rate.
//! \param ulConfig is the data format for the port (number of data bits,
//! number of stop bits, and parity).
//!
//! This function will configure the UART for operation in the specified data
//! format. The baud rate is provided in the \e ulBaud parameter and the
//! data format in the \e ulConfig parameter.
//!
//! The \e ulConfig parameter is the logical OR of three values: the number of
//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8,
//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5
//! select from eight to five data bits per byte (respectively).
//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop
//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN,
//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO
//! select the parity mode (no parity bit, even parity bit, odd parity bit,
//! parity bit always one, and parity bit always zero, respectively).
//!
//! The baud rate is dependent upon the system clock rate returned by
//! SysCtlClockGet(); if it does not return the correct system clock rate then
//! the baud rate will be incorrect.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_configset) || defined(BUILD_ALL) || defined(DOXYGEN)
void
UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,
unsigned long ulConfig)
{
unsigned long ulUARTClk, ulInt, ulFrac;
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// Stop the UART.
//
UARTDisable(ulBase);
//
// Determine the UART clock rate.
//
ulUARTClk = SysCtlClockGet();
//
// Compute the fractional baud rate divider.
//
ulInt = ulUARTClk / (16 * ulBaud);
ulFrac = ulUARTClk % (16 * ulBaud);
ulFrac = ((((2 * ulFrac * 4) / ulBaud) + 1) / 2);
//
// Set the baud rate.
//
HWREG(ulBase + UART_O_IBRD) = ulInt;
HWREG(ulBase + UART_O_FBRD) = ulFrac;
//
// Set parity, data length, and number of stop bits.
//
HWREG(ulBase + UART_O_LCR_H) = ulConfig;
//
// Clear the flags register.
//
HWREG(ulBase + UART_O_FR) = 0;
//
// Start the UART.
//
UARTEnable(ulBase);
}
#endif
//*****************************************************************************
//
//! Gets the current configuration of a UART.
//!
//! \param ulBase is the base address of the UART port.
//! \param pulBaud is a pointer to storage for the baud rate.
//! \param pulConfig is a pointer to storage for the data format.
//!
//! The baud rate and data format for the UART is determined. The returned
//! baud rate is the actual baud rate; it may not be the exact baud rate
//! requested or an ``official'' baud rate. The data format returned in
//! \e pulConfig is enumerated the same as the \e ulConfig parameter of
//! UARTConfigSet().
//!
//! The baud rate is dependent upon the system clock rate returned by
//! SysCtlClockGet(); if it does not return the correct system clock rate then
//! the baud rate will be computed incorrectly.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_configget) || defined(BUILD_ALL) || defined(DOXYGEN)
void
UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,
unsigned long *pulConfig)
{
unsigned long ulInt, ulFrac;
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// Compute the baud rate.
//
ulInt = HWREG(ulBase + UART_O_IBRD);
ulFrac = HWREG(ulBase + UART_O_FBRD);
*pulBaud = (SysCtlClockGet() * 4) / ((64 * ulInt) + ulFrac);
//
// Get the parity, data length, and number of stop bits.
//
*pulConfig = (HWREG(ulBase + UART_O_LCR_H) &
(UART_LCR_H_SPS | UART_LCR_H_WLEN | UART_LCR_H_STP2 |
UART_LCR_H_EPS | UART_LCR_H_PEN));
}
#endif
//*****************************************************************************
//
//! Enables transmitting and receiving.
//!
//! \param ulBase is the base address of the UART port.
//!
//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive
//! FIFOs.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
UARTEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// Enable the FIFO.
//
HWREG(ulBase + UART_O_LCR_H) |= UART_LCR_H_FEN;
//
// Enable RX, TX, and the UART.
//
HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE |
UART_CTL_RXE);
}
#endif
//*****************************************************************************
//
//! Disables transmitting and receiving.
//!
//! \param ulBase is the base address of the UART port.
//!
//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of
//! transmission of the current character, and flushes the transmit FIFO.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
UARTDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// Wait for end of TX.
//
while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY)
{
}
//
// Disable the FIFO.
//
HWREG(ulBase + UART_O_LCR_H) &= ~(UART_LCR_H_FEN);
//
// Disable the UART.
//
HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE |
UART_CTL_RXE);
}
#endif
//*****************************************************************************
//
//! Determines if there are any characters in the receive FIFO.
//!
//! \param ulBase is the base address of the UART port.
//!
//! This function returns a flag indicating whether or not there is data
//! available in the receive FIFO.
//!
//! \return Returns \b true if there is data in the receive FIFO, and \b false
//! if there is no data in the receive FIFO.
//
//*****************************************************************************
#if defined(GROUP_charsavail) || defined(BUILD_ALL) || defined(DOXYGEN)
tBoolean
UARTCharsAvail(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// Return the availability of characters.
//
return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true);
}
#endif
//*****************************************************************************
//
//! Determines if there is any space in the transmit FIFO.
//!
//! \param ulBase is the base address of the UART port.
//!
//! This function returns a flag indicating whether or not there is space
//! available in the transmit FIFO.
//!
//! \return Returns \b true if there is space available in the transmit FIFO,
//! and \b false if there is no space available in the transmit FIFO.
//
//*****************************************************************************
#if defined(GROUP_spaceavail) || defined(BUILD_ALL) || defined(DOXYGEN)
tBoolean
UARTSpaceAvail(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// Return the availability of space.
//
return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true);
}
#endif
//*****************************************************************************
//
//! Receives a character from the specified port.
//!
//! \param ulBase is the base address of the UART port.
//!
//! Gets a character from the receive FIFO for the specified port.
//!
//! \return Returns the character read from the specified port, cast as a
//! \e long. A \b -1 will be returned if there are no characters present in
//! the receive FIFO. The UARTCharsAvail() function should be called before
//! attempting to call this function.
//
//*****************************************************************************
#if defined(GROUP_charnonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN)
long
UARTCharNonBlockingGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// See if there are any characters in the receive FIFO.
//
if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE))
{
//
// Read and return the next character.
//
return(HWREG(ulBase + UART_O_DR));
}
else
{
//
// There are no characters, so return a failure.
//
return(-1);
}
}
#endif
//*****************************************************************************
//
//! Waits for a character from the specified port.
//!
//! \param ulBase is the base address of the UART port.
//!
//! Gets a character from the receive FIFO for the specified port. If there
//! are no characters available, this function will wait until a character is
//! received before returning.
//!
//! \return Returns the character read from the specified port, cast as an
//! \e int.
//
//*****************************************************************************
#if defined(GROUP_charget) || defined(BUILD_ALL) || defined(DOXYGEN)
long
UARTCharGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// Wait until a char is available.
//
while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)
{
}
//
// Now get the char.
//
return(HWREG(ulBase + UART_O_DR));
}
#endif
//*****************************************************************************
//
//! Sends a character to the specified port.
//!
//! \param ulBase is the base address of the UART port.
//! \param ucData is the character to be transmitted.
//!
//! Writes the character \e ucData to the transmit FIFO for the specified port.
//! This function does not block, so if there is no space available, then a
//! \b false is returned, and the application will have to retry the function
//! later.
//!
//! \return Returns \b true if the character was successfully placed in the
//! transmit FIFO, and \b false if there was no space available in the transmit
//! FIFO.
//
//*****************************************************************************
#if defined(GROUP_charnonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN)
tBoolean
UARTCharNonBlockingPut(unsigned long ulBase, unsigned char ucData)
{
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// See if there is space in the transmit FIFO.
//
if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF))
{
//
// Write this character to the transmit FIFO.
//
HWREG(ulBase + UART_O_DR) = ucData;
//
// Success.
//
return(true);
}
else
{
//
// There is no space in the transmit FIFO, so return a failure.
//
return(false);
}
}
#endif
//*****************************************************************************
//
//! Waits to send a character from the specified port.
//!
//! \param ulBase is the base address of the UART port.
//! \param ucData is the character to be transmitted.
//!
//! Sends the character \e ucData to the transmit FIFO for the specified port.
//! If there is no space available in the transmit FIFO, this function will
//! wait until there is space available before returning.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_charput) || defined(BUILD_ALL) || defined(DOXYGEN)
void
UARTCharPut(unsigned long ulBase, unsigned char ucData)
{
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// Wait until space is available.
//
while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)
{
}
//
// Send the char.
//
HWREG(ulBase + UART_O_DR) = ucData;
}
#endif
//*****************************************************************************
//
//! Causes a BREAK to be sent.
//!
//! \param ulBase is the base address of the UART port.
//! \param bBreakState controls the output level.
//!
//! Calling this function with \e bBreakState set to \b true will assert a
//! break condition on the UART. Calling this function with \e bBreakState set
//! to \b false will remove the break condition. For proper transmission of a
//! break command, the break must be asserted for at least two complete frames.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_breakctl) || defined(BUILD_ALL) || defined(DOXYGEN)
void
UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState)
{
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// Set the break condition as requested.
//
HWREG(ulBase + UART_O_LCR_H) =
(bBreakState ?
(HWREG(ulBase + UART_O_LCR_H) | UART_LCR_H_BRK) :
(HWREG(ulBase + UART_O_LCR_H) & ~(UART_LCR_H_BRK)));
}
#endif
//*****************************************************************************
//
//! Registers an interrupt handler for a UART interrupt.
//!
//! \param ulBase is the base address of the UART port.
//! \param pfnHandler is a pointer to the function to be called when the
//! UART interrupt occurs.
//!
//! This function does the actual registering of the interrupt handler. This
//! will enable the global interrupt in the interrupt controller; specific UART
//! interrupts must be enabled via UARTIntEnable(). It is the interrupt
//! handler's responsibility to clear the interrupt source.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
unsigned long ulInt;
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// Determine the interrupt number based on the UART port.
//
ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1;
//
// Register the interrupt handler.
//
IntRegister(ulInt, pfnHandler);
//
// Enable the UART interrupt.
//
IntEnable(ulInt);
}
#endif
//*****************************************************************************
//
//! Unregisters an interrupt handler for a UART interrupt.
//!
//! \param ulBase is the base address of the UART port.
//!
//! This function does the actual unregistering of the interrupt handler. It
//! will clear the handler to be called when a UART interrupt occurs. This
//! will also mask off the interrupt in the interrupt controller so that the
//! interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
UARTIntUnregister(unsigned long ulBase)
{
unsigned long ulInt;
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// Determine the interrupt number based on the UART port.
//
ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1;
//
// Disable the interrupt.
//
IntDisable(ulInt);
//
// Unregister the interrupt handler.
//
IntUnregister(ulInt);
}
#endif
//*****************************************************************************
//
//! Enables individual UART interrupt sources.
//!
//! \param ulBase is the base address of the UART port.
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated UART interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor.
//!
//! The parameter \e ulIntFlags is the logical OR of any of the following:
//!
//! - UART_INT_OE - Overrun Error interrupt
//! - UART_INT_BE - Break Error interrupt
//! - UART_INT_PE - Parity Error interrupt
//! - UART_INT_FE - Framing Error interrupt
//! - UART_INT_RT - Receive Timeout interrupt
//! - UART_INT_TX - Transmit interrupt
//! - UART_INT_RX - Receive interrupt
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// Enable the specified interrupts.
//
HWREG(ulBase + UART_O_IM) |= ulIntFlags;
}
#endif
//*****************************************************************************
//
//! Disables individual UART interrupt sources.
//!
//! \param ulBase is the base address of the UART port.
//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
//!
//! Disables the indicated UART interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor.
//!
//! The parameter \e ulIntFlags has the same definition as the same parameter
//! to UARTIntEnable().
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// Disable the specified interrupts.
//
HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags);
}
#endif
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase is the base address of the UART port.
//! \param bMasked is false if the raw interrupt status is required and true
//! if the masked interrupt status is required.
//!
//! This returns the interrupt status for the specified UART. Either the raw
//! interrupt status or the status of interrupts that are allowed to reflect to
//! the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! values described in UARTIntEnable().
//
//*****************************************************************************
#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
UARTIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + UART_O_MIS));
}
else
{
return(HWREG(ulBase + UART_O_RIS));
}
}
#endif
//*****************************************************************************
//
//! Clears UART interrupt sources.
//!
//! \param ulBase is the base address of the UART port.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified UART interrupt sources are cleared, so that they no longer
//! assert. This must be done in the interrupt handler to keep it from being
//! called again immediately upon exit.
//!
//! The parameter \e ulIntFlags has the same definition as the same parameter
//! to UARTIntEnable().
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)
void
UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
//
// Clear the requested interrupt sources.
//
HWREG(ulBase + UART_O_ICR) = ulIntFlags;
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// uart.h - Defines and Macros for the UART.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __UART_H__
#define __UART_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
// as the ulIntFlags parameter, and returned from UARTIntStatus.
//
//*****************************************************************************
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
#define UART_INT_TX 0x020 // Transmit Interrupt Mask
#define UART_INT_RX 0x010 // Receive Interrupt Mask
//*****************************************************************************
//
// Values that can be passed to UARTConfigSet as the ulConfig parameter and
// returned by UARTConfigGet in the pulConfig parameter. Additionally, the
// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity
// parameter, and are returned by UARTParityModeGet.
//
//*****************************************************************************
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one
#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
extern unsigned long UARTParityModeGet(unsigned long ulBase);
extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,
unsigned long ulConfig);
extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,
unsigned long *pulConfig);
extern void UARTEnable(unsigned long ulBase);
extern void UARTDisable(unsigned long ulBase);
extern tBoolean UARTCharsAvail(unsigned long ulBase);
extern tBoolean UARTSpaceAvail(unsigned long ulBase);
extern long UARTCharNonBlockingGet(unsigned long ulBase);
extern long UARTCharGet(unsigned long ulBase);
extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase,
unsigned char ucData);
extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void UARTIntUnregister(unsigned long ulBase);
extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
#ifdef __cplusplus
}
#endif
#endif // __UART_H__

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.c
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//*****************************************************************************
//
// watchdog.c - Driver for the Watchdog Timer Module.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup watchdog_api
//! @{
//
//*****************************************************************************
#include "../hw_ints.h"
#include "../hw_memmap.h"
#include "../hw_types.h"
#include "../hw_watchdog.h"
#include "debug.h"
#include "interrupt.h"
#include "watchdog.h"
//*****************************************************************************
//
//! Determines if the watchdog timer is enabled.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This will check to see if the watchdog timer is enabled.
//!
//! \return Returns \b true if the watchdog timer is enabled, and \b false
//! if it is not.
//
//*****************************************************************************
#if defined(GROUP_running) || defined(BUILD_ALL) || defined(DOXYGEN)
tBoolean
WatchdogRunning(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// See if the watchdog timer module is enabled, and return.
//
return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN);
}
#endif
//*****************************************************************************
//
//! Enables the watchdog timer.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This will enable the watchdog timer counter and interrupt.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock()
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
WatchdogEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// Enable the watchdog timer module.
//
HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
}
#endif
//*****************************************************************************
//
//! Enables the watchdog timer reset.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Enables the capability of the watchdog timer to issue a reset to the
//! processor upon a second timeout condition.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock()
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_resetenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
WatchdogResetEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// Enable the watchdog reset.
//
HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN;
}
#endif
//*****************************************************************************
//
//! Disables the watchdog timer reset.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Disables the capability of the watchdog timer to issue a reset to the
//! processor upon a second timeout condition.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock()
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_resetdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
WatchdogResetDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// Disable the watchdog reset.
//
HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN);
}
#endif
//*****************************************************************************
//
//! Enables the watchdog timer lock mechanism.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Locks out write access to the watchdog timer configuration registers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_lock) || defined(BUILD_ALL) || defined(DOXYGEN)
void
WatchdogLock(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// Lock out watchdog register writes. Writing anything to the WDT_O_LOCK
// register causes the lock to go into effect.
//
HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED;
}
#endif
//*****************************************************************************
//
//! Disables the watchdog timer lock mechanism.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Enables write access to the watchdog timer configuration registers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_unlock) || defined(BUILD_ALL) || defined(DOXYGEN)
void
WatchdogUnlock(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// Unlock watchdog register writes.
//
HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
}
#endif
//*****************************************************************************
//
//! Gets the state of the watchdog timer lock mechanism.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Returns the lock state of the watchdog timer registers.
//!
//! \return Returns \b true if the watchdog timer registers are locked, and
//! \b false if they are not locked.
//
//*****************************************************************************
#if defined(GROUP_lockstate) || defined(BUILD_ALL) || defined(DOXYGEN)
tBoolean
WatchdogLockState(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// Get the lock state.
//
return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
}
#endif
//*****************************************************************************
//
//! Sets the watchdog timer reload value.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param ulLoadVal is the load value for the watchdog timer.
//!
//! This function sets the value to load into the watchdog timer when the count
//! reaches zero for the first time; if the watchdog timer is running when this
//! function is called, then the value will be immediately loaded into the
//! watchdog timer counter. If the parameter \e ulLoadVal is 0, then an
//! interrupt is immediately generated.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet()
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_reloadset) || defined(BUILD_ALL) || defined(DOXYGEN)
void
WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal)
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// Set the load register.
//
HWREG(ulBase + WDT_O_LOAD) = ulLoadVal;
}
#endif
//*****************************************************************************
//
//! Gets the watchdog timer reload value.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function gets the value that is loaded into the watchdog timer when
//! the count reaches zero for the first time.
//!
//! \sa WatchdogReloadSet()
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_reloadget) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
WatchdogReloadGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// Get the load register.
//
return(HWREG(ulBase + WDT_O_LOAD));
}
#endif
//*****************************************************************************
//
//! Gets the current watchdog timer value.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function reads the current value of the watchdog timer.
//!
//! \return Returns the current value of the watchdog timer.
//
//*****************************************************************************
#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
WatchdogValueGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// Get the current watchdog timer register value.
//
return(HWREG(ulBase + WDT_O_VALUE));
}
#endif
//*****************************************************************************
//
//! Registers an interrupt handler for watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param pfnHandler is a pointer to the function to be called when the
//! watchdog timer interrupt occurs.
//!
//! This function does the actual registering of the interrupt handler. This
//! will enable the global interrupt in the interrupt controller; the watchdog
//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt
//! handler's responsibility to clear the interrupt source via
//! WatchdogIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// Register the interrupt handler.
//
IntRegister(INT_WATCHDOG, pfnHandler);
//
// Enable the watchdog timer interrupt.
//
IntEnable(INT_WATCHDOG);
}
#endif
//*****************************************************************************
//
//! Unregisters an interrupt handler for the watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function does the actual unregistering of the interrupt handler. This
//! function will clear the handler to be called when a watchdog timer
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
void
WatchdogIntUnregister(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// Disable the interrupt.
//
IntDisable(INT_WATCHDOG);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_WATCHDOG);
}
#endif
//*****************************************************************************
//
//! Enables the watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Enables the watchdog timer interrupt.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable()
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
WatchdogIntEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// Enable the watchdog interrupt.
//
HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
}
#endif
//*****************************************************************************
//
//! Gets the current watchdog timer interrupt status.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This returns the interrupt status for the watchdog timer module. Either
//! the raw interrupt status or the status of interrupt that is allowed to
//! reflect to the processor can be returned.
//!
//! \return The current interrupt status, where a 1 indicates that the watchdog
//! interrupt is active, and a 0 indicates that it is not active.
//
//*****************************************************************************
#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
unsigned long
WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + WDT_O_MIS));
}
else
{
return(HWREG(ulBase + WDT_O_RIS));
}
}
#endif
//*****************************************************************************
//
//! Clears the watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! The watchdog timer interrupt source is cleared, so that it no longer
//! asserts.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)
void
WatchdogIntClear(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// Clear the interrupt source.
//
HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT;
}
#endif
//*****************************************************************************
//
//! Enables stalling of the watchdog timer during debug events.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function allows the watchdog timer to stop counting when the processor
//! is stopped by the debugger. By doing so, the watchdog is prevented from
//! expiring (typically almost immediately from a human time perspective) and
//! resetting the system (if reset is enabled). The watchdog will instead
//! expired after the appropriate number of processor cycles have been executed
//! while debugging (or at the appropriate time after the processor has been
//! restarted).
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_stallenable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
WatchdogStallEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// Enable timer stalling.
//
HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL;
}
#endif
//*****************************************************************************
//
//! Disables stalling of the watchdog timer during debug events.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function disables the debug mode stall of the watchdog timer. By
//! doing so, the watchdog timer continues to count regardless of the processor
//! debug state.
//!
//! \return None.
//
//*****************************************************************************
#if defined(GROUP_stalldisable) || defined(BUILD_ALL) || defined(DOXYGEN)
void
WatchdogStallDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == WATCHDOG_BASE);
//
// Disable timer stalling.
//
HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL);
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.h
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//*****************************************************************************
//
// watchdog.h - Prototypes for the Watchdog Timer API
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __WATCHDOG_H__
#define __WATCHDOG_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean WatchdogRunning(unsigned long ulBase);
extern void WatchdogEnable(unsigned long ulBase);
extern void WatchdogResetEnable(unsigned long ulBase);
extern void WatchdogResetDisable(unsigned long ulBase);
extern void WatchdogLock(unsigned long ulBase);
extern void WatchdogUnlock(unsigned long ulBase);
extern tBoolean WatchdogLockState(unsigned long ulBase);
extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
extern unsigned long WatchdogReloadGet(unsigned long ulBase);
extern unsigned long WatchdogValueGet(unsigned long ulBase);
extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void WatchdogIntUnregister(unsigned long ulBase);
extern void WatchdogIntEnable(unsigned long ulBase);
extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void WatchdogIntClear(unsigned long ulBase);
extern void WatchdogStallDisable(unsigned long ulBase);
extern void WatchdogStallDisable(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __WATCHDOG_H__

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Demo/CORTEX_LM3S811_IAR/RTOSDemo.dep
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<?xml version="1.0" encoding="iso-8859-1"?>
<project>
<fileVersion>2</fileVersion>
<configuration>
<name>Debug</name>
<outputs>
<file>$PROJ_DIR$\ewarm\Exe\RTOSDemo.sim</file>
<file>$PROJ_DIR$\LuminaryCode\osram96x16.h</file>
<file>$PROJ_DIR$\ewarm\Obj\main.pbi</file>
<file>$TOOLKIT_DIR$\lib\dl7mptnnl8f.h</file>
<file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portmacro.h</file>
<file>$PROJ_DIR$\LuminaryCode\pwm.h</file>
<file>$PROJ_DIR$\ewarm\Obj\BlockQ.r79</file>
<file>$PROJ_DIR$\ewarm\Obj\heap_1.pbi</file>
<file>$PROJ_DIR$\LuminaryCode\interrupt.h</file>
<file>$PROJ_DIR$\LuminaryCode\watchdog.h</file>
<file>$TOOLKIT_DIR$\inc\DLib_Threads.h</file>
<file>$PROJ_DIR$\..\..\Source\include\portable.h</file>
<file>$PROJ_DIR$\ewarm\Obj\list.r79</file>
<file>$PROJ_DIR$\LuminaryCode\driverlib.r79</file>
<file>$PROJ_DIR$\LuminaryCode\debug.h</file>
<file>$PROJ_DIR$\..\Common\include\semtest.h</file>
<file>$PROJ_DIR$\LuminaryCode\timer.h</file>
<file>$PROJ_DIR$\..\Common\include\PollQ.h</file>
<file>$PROJ_DIR$\ewarm\Obj\tasks.pbi</file>
<file>$PROJ_DIR$\ewarm\Obj\osram96x16.r79</file>
<file>$PROJ_DIR$\..\..\Source\list.c</file>
<file>$PROJ_DIR$\ewarm\List\RTOSDemo.map</file>
<file>$PROJ_DIR$\LuminaryCode\hw_types.h</file>
<file>$PROJ_DIR$\LuminaryCode\hw_timer.h</file>
<file>$PROJ_DIR$\LuminaryCode\systick.h</file>
<file>$PROJ_DIR$\LuminaryCode\adc.h</file>
<file>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</file>
<file>$PROJ_DIR$\LuminaryCode\ssi.h</file>
<file>$PROJ_DIR$\ewarm\Exe\RTOSDemo.d79</file>
<file>$PROJ_DIR$\LuminaryCode\hw_watchdog.h</file>
<file>$PROJ_DIR$\LuminaryCode\hw_gpio.h</file>
<file>$PROJ_DIR$\ewarm\Obj\startup.r79</file>
<file>$PROJ_DIR$\LuminaryCode\hw_ints.h</file>
<file>$PROJ_DIR$\startup.c</file>
<file>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c</file>
<file>$PROJ_DIR$\..\Common\include\integer.h</file>
<file>$PROJ_DIR$\FreeRTOSConfig.h</file>
<file>$PROJ_DIR$\LuminaryCode\flash.h</file>
<file>$PROJ_DIR$\ewarm\Obj\startup.pbi</file>
<file>$PROJ_DIR$\..\..\Source\include\croutine.h</file>
<file>$PROJ_DIR$\ewarm\Obj\heap_1.r79</file>
<file>$TOOLKIT_DIR$\lib\dl7mptnnl8f.r79</file>
<file>$PROJ_DIR$\LuminaryCode\qei.h</file>
<file>$PROJ_DIR$\LuminaryCode\DriverLib.h</file>
<file>$PROJ_DIR$\..\..\Source\include\semphr.h</file>
<file>$PROJ_DIR$\LuminaryCode\osram96x16.c</file>
<file>$PROJ_DIR$\ewarm\Obj\PollQ.r79</file>
<file>$PROJ_DIR$\LuminaryCode\hw_ssi.h</file>
<file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</file>
<file>$PROJ_DIR$\ewarm\Obj\main.r79</file>
<file>$PROJ_DIR$\..\..\Source\queue.c</file>
<file>$TOOLKIT_DIR$\inc\yvals.h</file>
<file>$TOOLKIT_DIR$\inc\stdlib.h</file>
<file>$PROJ_DIR$\LuminaryCode\hw_pwm.h</file>
<file>$PROJ_DIR$\..\..\Source\include\task.h</file>
<file>$PROJ_DIR$\LuminaryCode\hw_uart.h</file>
<file>$PROJ_DIR$\..\Common\Minimal\PollQ.c</file>
<file>$PROJ_DIR$\LuminaryCode\gpio.h</file>
<file>$PROJ_DIR$\LuminaryCode\hw_comp.h</file>
<file>$PROJ_DIR$\ewarm\Obj\port.r79</file>
<file>$PROJ_DIR$\ewarm\Obj\tasks.r79</file>
<file>$PROJ_DIR$\LuminaryCode\hw_i2c.h</file>
<file>$PROJ_DIR$\ewarm\Obj\PollQ.pbi</file>
<file>$PROJ_DIR$\ewarm\Obj\queue.pbi</file>
<file>$PROJ_DIR$\ewarm\Obj\integer.pbi</file>
<file>$TOOLKIT_DIR$\inc\string.h</file>
<file>$TOOLKIT_DIR$\inc\stddef.h</file>
<file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
<file>$PROJ_DIR$\LuminaryCode\cpu.h</file>
<file>$PROJ_DIR$\ewarm\Obj\semtest.pbi</file>
<file>$PROJ_DIR$\LuminaryCode\hw_memmap.h</file>
<file>$PROJ_DIR$\ewarm\Obj\BlockQ.pbi</file>
<file>$PROJ_DIR$\..\Common\Minimal\integer.c</file>
<file>$PROJ_DIR$\LuminaryCode\hw_qei.h</file>
<file>$PROJ_DIR$\LuminaryCode\hw_adc.h</file>
<file>$TOOLKIT_DIR$\inc\ysizet.h</file>
<file>$PROJ_DIR$\ewarm\Obj\RTOSDemo.pbd</file>
<file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
<file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
<file>$PROJ_DIR$\standalone.xcl</file>
<file>$PROJ_DIR$\main.c</file>
<file>$PROJ_DIR$\..\Common\Minimal\semtest.c</file>
<file>$PROJ_DIR$\LuminaryCode\comp.h</file>
<file>$PROJ_DIR$\..\..\Source\tasks.c</file>
<file>$PROJ_DIR$\LuminaryCode\hw_flash.h</file>
<file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</file>
<file>$PROJ_DIR$\..\..\Source\include\list.h</file>
<file>$PROJ_DIR$\ewarm\Obj\queue.r79</file>
<file>$PROJ_DIR$\..\..\Source\include\FreeRTOS.h</file>
<file>$PROJ_DIR$\LuminaryCode\hw_nvic.h</file>
<file>$PROJ_DIR$\ewarm\Obj\portasm.r79</file>
<file>$PROJ_DIR$\ewarm\Obj\semtest.r79</file>
<file>$TOOLKIT_DIR$\inc\stdio.h</file>
<file>$PROJ_DIR$\..\..\Source\include\projdefs.h</file>
<file>$PROJ_DIR$\LuminaryCode\i2c.h</file>
<file>$PROJ_DIR$\ewarm\Obj\list.pbi</file>
<file>$PROJ_DIR$\ewarm\Obj\osram96x16.pbi</file>
<file>$PROJ_DIR$\ewarm\Obj\integer.r79</file>
<file>$PROJ_DIR$\LuminaryCode\uart.h</file>
<file>$PROJ_DIR$\ewarm\Obj\port.pbi</file>
<file>$PROJ_DIR$\..\..\Source\include\queue.h</file>
<file>$PROJ_DIR$\LuminaryCode\sysctl.h</file>
<file>$PROJ_DIR$\..\Common\include\BlockQ.h</file>
<file>$PROJ_DIR$\LuminaryCode\hw_sysctl.h</file>
</outputs>
<file>
<name>$PROJ_DIR$\..\..\Source\list.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 12</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 95</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 52 51 77 3 67 78 10 75 88 66 93 36 11 4 86</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 52 51 77 67 78 10 75 88 66 93 36 11 4 86</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 6</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 71</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 52 51 77 3 67 78 10 75 88 66 93 36 11 4 54 86 100 102</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 52 51 77 67 78 10 75 88 66 93 36 11 4 54 86 100 102</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\ewarm\Exe\RTOSDemo.d79</name>
<outputs>
<tool>
<name>XLINK</name>
<file> 21 0</file>
</tool>
</outputs>
<inputs>
<tool>
<name>XLINK</name>
<file> 79 13 6 46 40 97 12 49 19 59 90 87 91 31 60 41</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\startup.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 31</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 38</file>
</tool>
</outputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 40</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 7</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 52 51 77 3 67 78 10 75 88 66 93 36 11 4 54 86</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 52 51 77 67 78 10 75 88 66 93 36 11 4 54 86</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\LuminaryCode\osram96x16.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 19</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 96</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 43 74 58 84 30 61 32 70 89 53 73 47 103 23 22 55 29 1 25 82 68 14 37 57 94 8 5 42 27 101 24 16 98 9</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 43 74 58 84 30 61 32 70 89 53 73 47 103 23 22 55 29 1 25 82 68 14 37 57 94 8 5 42 27 101 24 16 98 9</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>
<outputs>
<tool>
<name>AARM</name>
<file> 90</file>
</tool>
</outputs>
<inputs>
<tool>
<name>AARM</name>
<file> 36</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\queue.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 87</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 63</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 52 51 77 3 67 78 10 75 65 88 66 93 36 11 4 54 86 39</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 52 51 77 67 78 10 75 65 88 66 93 36 11 4 54 86 39</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 46</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 62</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 52 51 77 3 67 78 10 75 88 66 93 36 11 4 54 86 100 17</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 52 51 77 67 78 10 75 88 66 93 36 11 4 54 86 100 17</file>
</tool>
</inputs>
</file>
<file>
<name>[ROOT_NODE]</name>
<outputs>
<tool>
<name>XLINK</name>
<file> 28 21 0</file>
</tool>
</outputs>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\integer.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 97</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 64</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 52 51 77 3 67 78 10 75 88 66 93 36 11 4 54 86 35</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 52 51 77 67 78 10 75 88 66 93 36 11 4 54 86 35</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\ewarm\Obj\RTOSDemo.pbd</name>
<inputs>
<tool>
<name>BILINK</name>
<file> 71 62 7 64 95 2 96 99 63 69 38 18</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\main.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 49</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 2</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 43 74 58 84 30 61 32 70 89 53 73 47 103 23 22 55 29 1 25 82 68 14 37 57 94 8 5 42 27 101 24 16 98 9 88 66 51 77 3 67 78 10 75 93 36 11 4 54 86 100 44 35 17 15 102</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 43 74 58 84 30 61 32 70 89 53 73 47 103 23 22 55 29 1 25 82 68 14 37 57 94 8 5 42 27 101 24 16 98 9 88 66 51 77 67 78 10 75 93 36 11 4 54 86 100 44 35 17 15 102</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 91</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 69</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 52 51 77 3 67 78 10 75 88 66 93 36 11 4 54 86 44 100 15</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 52 51 77 67 78 10 75 88 66 93 36 11 4 54 86 44 100 15</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\tasks.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 60</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 18</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 92 51 77 3 67 78 10 75 52 65 88 66 93 36 11 4 54 86</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 92 51 77 67 78 10 75 52 65 88 66 93 36 11 4 54 86</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 59</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 99</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 88 66 51 77 3 67 78 10 75 93 36 11 4 54 86</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 88 66 51 77 67 78 10 75 93 36 11 4 54 86</file>
</tool>
</inputs>
</file>
</configuration>
</project>

570
Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewd
Unescape Escape View File

@ -0,0 +1,570 @@
<?xml version="1.0" encoding="iso-8859-1"?>
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<name>CCLmiftdiUpdateBreakpoints</name>
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<name>TCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
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<option>
<name>DoLogfile</name>
<state>0</state>
</option>
<option>
<name>LogFile</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
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<name>DoEmuMultiTarget</name>
<state>0</state>
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<name>EmuMultiTarget</name>
<state>0@ARM7TDMI</state>
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<name>EmuHWReset</name>
<state>0</state>
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<name>CEmuCommBaud</name>
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<state>0</state>
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<name>jtago</name>
<version>0</version>
<state>0</state>
</option>
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<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>UnusedAddr</name>
<state>0x00800000</state>
</option>
<option>
<name>CCMacraigorHWResetDelay</name>
<state></state>
</option>
<option>
<name>CCJTagBreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCJTagDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCJTagUpdateBreakpoints</name>
<state>main</state>
</option>
</data>
</settings>
<settings>
<name>RDI_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CRDIDriverDll</name>
<state>Browse to your RDI driver</state>
</option>
<option>
<name>CRDILogFileCheck</name>
<state>0</state>
</option>
<option>
<name>CRDILogFileEdit</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCRDIHWReset</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchReset</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchUndef</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchSWI</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchData</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchPrefetch</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchIRQ</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchFIQ</name>
<state>0</state>
</option>
<option>
<name>CCRDIUseETM</name>
<state>0</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>THIRDPARTY_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CThirdPartyDriverDll</name>
<state>Browse to your third-party driver</state>
</option>
<option>
<name>CThirdPartyLogFileCheck</name>
<state>0</state>
</option>
<option>
<name>CThirdPartyLogFileEditB</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
</data>
</settings>
<debuggerPlugins>
<plugin>
<file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>
<loadFlag>0</loadFlag>
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<plugin>
<file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>
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<plugin>
<file>$EW_DIR$\common\plugins\Stack\Stack.ewplugin</file>
<loadFlag>1</loadFlag>
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<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
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<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
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<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
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<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
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<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
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886
Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewp
Unescape Escape View File

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<name>Debug</name>
<toolchain>
<name>ARM</name>
</toolchain>
<debug>1</debug>
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<name>General</name>
<archiveVersion>2</archiveVersion>
<data>
<version>9</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>GProcessorMode</name>
<state>1</state>
</option>
<option>
<name>ExePath</name>
<state>ewarm\Exe</state>
</option>
<option>
<name>ObjPath</name>
<state>ewarm\Obj</state>
</option>
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<name>ListPath</name>
<state>ewarm\List</state>
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<option>
<name>Variant</name>
<version>5</version>
<state>25</state>
</option>
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<name>GEndianMode</name>
<state>0</state>
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<name>GInterwork</name>
<state>0</state>
</option>
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<name>GStackAlign</name>
<state>0</state>
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<name>Input variant</name>
<version>1</version>
<state>0</state>
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<name>Input description</name>
<state>Full formatting.</state>
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<name>Output variant</name>
<version>0</version>
<state>0</state>
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<name>Output description</name>
<state>Full formatting.</state>
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<state>0</state>
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<name>FPU</name>
<version>0</version>
<state>0</state>
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<name>OGCoreOrChip</name>
<state>1</state>
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<name>GRuntimeLibSelect</name>
<version>0</version>
<state>2</state>
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<option>
<name>GRuntimeLibSelectSlave</name>
<version>0</version>
<state>2</state>
</option>
<option>
<name>RTDescription</name>
<state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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<option>
<name>RTConfigPath</name>
<state>$TOOLKIT_DIR$\LIB\dl7mptnnl8f.h</state>
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<option>
<name>RTLibraryPath</name>
<state>$TOOLKIT_DIR$\LIB\dl7mptnnl8f.r79</state>
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<name>GeneralMisraVerbose</name>
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<option>
<name>OGChipSelectEditMenu</name>
<state>LM3S811 Luminary LM3S811</state>
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<name>CCListCFile</name>
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<name>CCListCMnemonics</name>
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<name>CCListCMessages</name>
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<name>CCListAssFile</name>
<state>0</state>
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<option>
<name>CCListAssSource</name>
<state>0</state>
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<name>CCEnableRemarks</name>
<state>0</state>
</option>
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<name>CCDiagSuppress</name>
<state>Pa050, Pa082</state>
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<option>
<name>CCDiagRemark</name>
<state></state>
</option>
<option>
<name>CCDiagWarning</name>
<state></state>
</option>
<option>
<name>CCDiagError</name>
<state></state>
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<option>
<name>CCObjPrefix</name>
<state>1</state>
</option>
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<name>CCOptSizeSpeed</name>
<state>0</state>
</option>
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<name>CCOptimization</name>
<version>0</version>
<state>1</state>
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<name>CCAllowList</name>
<version>1</version>
<state>0000000</state>
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<name>CCObjUseModuleName</name>
<state>0</state>
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<option>
<name>CCObjModuleName</name>
<state></state>
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<name>CCDebugInfo</name>
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<state>1</state>
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<name>IInterwork</name>
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<name>IExtraOptionsCheck</name>
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<name>IExtraOptions</name>
<state></state>
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<option>
<name>CCLangConformance</name>
<state>0</state>
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<option>
<name>CCSignedPlainChar</name>
<state>1</state>
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<name>CCRequirePrototypes</name>
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<name>CCMultibyteSupport</name>
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<name>CCDiagWarnAreErr</name>
<state>0</state>
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<name>CCCompilerRuntimeInfo</name>
<state>0</state>
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<name>IFpuProcessor</name>
<state>1</state>
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<name>OutputFile</name>
<state>$FILE_BNAME$.r79</state>
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<option>
<name>CCLangSelect</name>
<state>0</state>
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<name>CCLibConfigHeader</name>
<state>1</state>
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<name>CCOptSizeSpeedSlave</name>
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<name>CCOptimizationSlave</name>
<version>0</version>
<state>1</state>
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<option>
<name>CCCodeFunctions</name>
<state>CODE</state>
</option>
<option>
<name>CCData</name>
<state>DATA</state>
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<option>
<name>PreInclude</name>
<state></state>
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<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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<name>CCModuleType</name>
<state>0</state>
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<name>CCModuleTypeCmdlineProducer</name>
<state>0</state>
</option>
<option>
<name>CCIncludePath2</name>
<state>$PROJ_DIR$\LuminaryCode</state>
<state>$PROJ_DIR$\..\..\Source\include</state>
<state>$PROJ_DIR$\..\Common\include</state>
<state>$PROJ_DIR$\.</state>
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<option>
<name>CCStdIncCheck</name>
<state>0</state>
</option>
<option>
<name>CCStdIncludePath</name>
<state>$TOOLKIT_DIR$\INC\</state>
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<name>CCInlineThreshold</name>
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<state>1</state>
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<name>ACaseSensitivity</name>
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<name>MacroChars</name>
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<state>0</state>
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<name>AWarnEnable</name>
<state>0</state>
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<name>AWarnWhat</name>
<state>0</state>
</option>
<option>
<name>AWarnOne</name>
<state></state>
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<name>AWarnRange1</name>
<state></state>
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<name>AWarnRange2</name>
<state></state>
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<name>ADebug</name>
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<name>AltRegisterNames</name>
<state>0</state>
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<name>ADefines</name>
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<state>DEBUG</state>
<state>ewarm</state>
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<name>AList</name>
<state>0</state>
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<name>AListHeader</name>
<state>1</state>
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<name>AListing</name>
<state>1</state>
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<name>Includes</name>
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<state>1</state>
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<name>MacExec</name>
<state>0</state>
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<name>OnlyAssed</name>
<state>0</state>
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<name>PageLength</name>
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<state>8</state>
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<name>AXRefDefines</name>
<state>0</state>
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<name>AXRefInternal</name>
<state>0</state>
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<name>AXRefDual</name>
<state>0</state>
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<name>AProcessor</name>
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<name>AFpuProcessor</name>
<state>1</state>
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<name>AOutputFile</name>
<state>$FILE_BNAME$.r79</state>
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<name>AMultibyteSupport</name>
<state>0</state>
</option>
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<name>ALimitErrorsCheck</name>
<state>0</state>
</option>
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<name>ALimitErrorsEdit</name>
<state>100</state>
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<name>AIgnoreStdInclude</name>
<state>0</state>
</option>
<option>
<name>AStdIncludes</name>
<state>$TOOLKIT_DIR$\INC\</state>
</option>
<option>
<name>AUserIncludes</name>
<state>$PROJ_DIR$\.</state>
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<name>AExtraOptionsCheckV2</name>
<state>0</state>
</option>
<option>
<name>AExtraOptionsV2</name>
<state></state>
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<name>CUSTOM</name>
<archiveVersion>3</archiveVersion>
<data>
<extensions></extensions>
<cmdline></cmdline>
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<name>BICOMP</name>
<archiveVersion>0</archiveVersion>
<data/>
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<settings>
<name>BUILDACTION</name>
<archiveVersion>1</archiveVersion>
<data>
<prebuild></prebuild>
<postbuild></postbuild>
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<name>XLINK</name>
<archiveVersion>2</archiveVersion>
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<wantNonLocal>1</wantNonLocal>
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<name>OutputFile</name>
<state>RTOSDemo.d79</state>
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<name>OutputFormat</name>
<version>11</version>
<state>16</state>
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<state>16</state>
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<state>(None for the selected format)</state>
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<name>XDefines</name>
<state></state>
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<state>0</state>
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<name>OverlapWarnings</name>
<state>0</state>
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<name>NoGlobalCheck</name>
<state>0</state>
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<name>XList</name>
<state>1</state>
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<state>1</state>
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<name>ListSymbols</name>
<state>2</state>
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<name>PageLengthCheck</name>
<state>0</state>
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<name>PageLength</name>
<state>80</state>
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<option>
<name>XIncludes</name>
<state>$TOOLKIT_DIR$\LIB\</state>
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<name>ModuleStatus</name>
<state>0</state>
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<name>XclOverride</name>
<state>1</state>
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<name>XclFile</name>
<state>$PROJ_DIR$\standalone.xcl</state>
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<name>XclFileSlave</name>
<state></state>
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<name>DoFill</name>
<state>0</state>
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<name>FillerByte</name>
<state>0xFF</state>
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<version>0</version>
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<state>1</state>
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<state>0x11021</state>
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<state>0</state>
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<state>0</state>
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<state>w6</state>
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<state></state>
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<state></state>
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<name>ModuleLocalSym</name>
<version>0</version>
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<state></state>
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<state>0</state>
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<state>1</state>
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<state>RTOSDemo.sim</state>
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<option>
<name>RawBinarySymbol</name>
<state></state>
</option>
<option>
<name>RawBinarySegment</name>
<state></state>
</option>
<option>
<name>RawBinaryAlign</name>
<state></state>
</option>
<option>
<name>XLinkMisraHandler</name>
<state>0</state>
</option>
<option>
<name>CrcAlign</name>
<state>1</state>
</option>
<option>
<name>CrcInitialValue</name>
<state>0x0</state>
</option>
</data>
</settings>
<settings>
<name>XAR</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>XARInputs</name>
<state></state>
</option>
<option>
<name>XAROverride</name>
<state>0</state>
</option>
<option>
<name>XAROutput</name>
<state>###Unitialized###</state>
</option>
</data>
</settings>
<settings>
<name>BILINK</name>
<archiveVersion>0</archiveVersion>
<data/>
</settings>
</configuration>
<group>
<name>Demo Source</name>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\integer.c</name>
</file>
<file>
<name>$PROJ_DIR$\main.c</name>
</file>
<file>
<name>$PROJ_DIR$\LuminaryCode\osram96x16.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>
</file>
<file>
<name>$PROJ_DIR$\startup.c</name>
</file>
</group>
<group>
<name>Libraries</name>
<file>
<name>$PROJ_DIR$\LuminaryCode\driverlib.r79</name>
</file>
</group>
<group>
<name>Scheduler Source</name>
<file>
<name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\list.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\queue.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\tasks.c</name>
</file>
</group>
</project>

54
Demo/CORTEX_LM3S811_IAR/RTOSDemo.eww
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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\RTOSDemo.ewp</path>
</project>
<batchBuild>
<batchDefinition>
<name>All Examples</name>
<member>
<project>driverlib</project>
<configuration>Debug</configuration>
</member>
<member>
<project>bitband</project>
<configuration>Debug</configuration>
</member>
<member>
<project>gpio_jtag</project>
<configuration>Debug</configuration>
</member>
<member>
<project>hello</project>
<configuration>Debug</configuration>
</member>
<member>
<project>interrupts</project>
<configuration>Debug</configuration>
</member>
<member>
<project>pwmgen</project>
<configuration>Debug</configuration>
</member>
<member>
<project>qs_ev-lm3s811</project>
<configuration>Debug</configuration>
</member>
<member>
<project>timers</project>
<configuration>Debug</configuration>
</member>
<member>
<project>uart_echo</project>
<configuration>Debug</configuration>
</member>
<member>
<project>watchdog</project>
<configuration>Debug</configuration>
</member>
</batchDefinition>
</batchBuild>
</workspace>

362
Demo/CORTEX_LM3S811_IAR/main.c
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/*
FreeRTOS.org V4.1.3 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
* This project contains an application demonstrating the use of the
* FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval
* board. See http://www.FreeRTOS.org for more information.
*
* main() simply sets up the hardware, creates all the demo application tasks,
* then starts the scheduler. http://www.freertos.org/a00102.html provides
* more information on the standard demo tasks.
*
* In addition to a subset of the standard demo application tasks, main.c also
* defines the following tasks:
*
* + A 'Print' task. The print task is the only task permitted to access the
* LCD - thus ensuring mutual exclusion and consistent access to the resource.
* Other tasks do not access the LCD directly, but instead send the text they
* wish to display to the print task. The print task spends most of its time
* blocked - only waking when a message is queued for display.
*
* + A 'Button handler' task. The eval board contains a user push button that
* is configured to generate interrupts. The interrupt handler uses a
* semaphore to wake the button handler task - demonstrating how the priority
* mechanism can be used to defer interrupt processing to the task level. The
* button handler task sends a message both to the LCD (via the print task) and
* the UART where it can be viewed using a dumb terminal (via the UART to USB
* converter on the eval board). NOTES: The dumb terminal must be closed in
* order to reflash the microcontroller. A very basic interrupt driven UART
* driver is used that does not use the FIFO. 19200 baud is used.
*
* + A 'check' task. The check task only executes every five seconds but has a
* high priority so is guaranteed to get processor time. Its function is to
* check that all the other tasks are still operational and that no errors have
* been detected at any time. If no errors have every been detected 'PASS' is
* written to the display (via the print task) - if an error has ever been
* detected the message is changed to 'FAIL'. The position of the message is
* changed for each write.
*/
/* Environment includes. */
#include "DriverLib.h"
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"
/* Demo app includes. */
#include "integer.h"
#include "PollQ.h"
#include "semtest.h"
#include "BlockQ.h"
/* Delay between cycles of the 'check' task. */
#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS )
/* UART configuration - note this does not use the FIFO so is not very
efficient. */
#define mainBAUD_RATE ( 19200 )
#define mainFIFO_SET ( 0x10 )
/* Demo task priorities. */
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* Demo board specifics. */
#define mainPUSH_BUTTON GPIO_PIN_4
/* Misc. */
#define mainQUEUE_SIZE ( 3 )
#define mainDEBOUNCE_DELAY ( ( portTickType ) 150 / portTICK_RATE_MS )
#define mainNO_DELAY ( ( portTickType ) 0 )
/*
* Configure the processor and peripherals for this demo.
*/
static void prvSetupHardware( void );
/*
* The 'check' task, as described at the top of this file.
*/
static void vCheckTask( void *pvParameters );
/*
* The task that is woken by the ISR that processes GPIO interrupts originating
* from the push button.
*/
static void vButtonHandlerTask( void *pvParameters );
/*
* The task that controls access to the LCD.
*/
static void vPrintTask( void *pvParameter );
/* String that is transmitted on the UART. */
static portCHAR *cMessage = "Task woken by button interrupt! --- ";
static volatile portCHAR *pcNextChar;
/* The semaphore used to wake the button handler task from within the GPIO
interrupt handler. */
xSemaphoreHandle xButtonSemaphore;
/* The queue used to send strings to the print task for display on the LCD. */
xQueueHandle xPrintQueue;
/*-----------------------------------------------------------*/
int main( void )
{
/* Configure the clocks, UART and GPIO. */
prvSetupHardware();
/* Create the semaphore used to wake the button handler task from the GPIO
ISR. */
vSemaphoreCreateBinary( xButtonSemaphore );
xSemaphoreTake( xButtonSemaphore, 0 );
/* Create the queue used to pass message to vPrintTask. */
xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( portCHAR * ) );
/* Start the standard demo tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
/* Start the tasks defined within the file. */
xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL );
xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );
/* Start the scheduler. */
vTaskStartScheduler();
/* Will only get here if there was insufficient heap to start the
scheduler. */
return 0;
}
/*-----------------------------------------------------------*/
static void vCheckTask( void *pvParameters )
{
portBASE_TYPE xErrorOccurred = pdFALSE;
portTickType xLastExecutionTime;
const portCHAR *pcPassMessage = "PASS";
const portCHAR *pcFailMessage = "FAIL";
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
works correctly. */
xLastExecutionTime = xTaskGetTickCount();
for( ;; )
{
/* Perform this check every mainCHECK_DELAY milliseconds. */
vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY );
/* Has an error been found in any task? */
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
xErrorOccurred = pdTRUE;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
xErrorOccurred = pdTRUE;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
xErrorOccurred = pdTRUE;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
xErrorOccurred = pdTRUE;
}
/* Send either a pass or fail message. If an error is found it is
never cleared again. We do not write directly to the LCD, but instead
queue a message for display by the print task. */
if( xErrorOccurred == pdTRUE )
{
xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY );
}
else
{
xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY );
}
}
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Setup the PLL. */
SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );
/* Setup the push button. */
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
GPIODirModeSet(GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN);
GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON,GPIO_FALLING_EDGE );
GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON );
IntEnable( INT_GPIOC );
/* Enable the UART. */
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
/* Set GPIO A0 and A1 as peripheral function. They are used to output the
UART signals. */
GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW );
/* Configure the UART for 8-N-1 operation. */
UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE );
/* We don't want to use the fifo. This is for test purposes to generate
as many interrupts as possible. */
HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET;
/* Enable Tx interrupts. */
HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX;
IntEnable( INT_UART0 );
/* Initialise the LCD> */
OSRAMInit( false );
OSRAMStringDraw("www.FreeRTOS.org", 0, 0);
OSRAMStringDraw("LM3S811 demo", 16, 1);
}
/*-----------------------------------------------------------*/
static void vButtonHandlerTask( void *pvParameters )
{
const portCHAR *pcInterruptMessage = "Int";
for( ;; )
{
/* Wait for a GPIO interrupt to wake this task. */
while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS );
/* Start the Tx of the message on the UART. */
UARTIntDisable( UART0_BASE, UART_INT_TX );
{
pcNextChar = cMessage;
/* Send the first character. */
if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )
{
HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar;
}
pcNextChar++;
}
UARTIntEnable(UART0_BASE, UART_INT_TX);
/* Queue a message for the print task to display on the LCD. */
xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY );
/* Make sure we don't process bounces. */
vTaskDelay( mainDEBOUNCE_DELAY );
xSemaphoreTake( xButtonSemaphore, mainNO_DELAY );
}
}
/*-----------------------------------------------------------*/
void vUART_ISR(void)
{
unsigned portLONG ulStatus;
/* What caused the interrupt. */
ulStatus = UARTIntStatus( UART0_BASE, pdTRUE );
/* Clear the interrupt. */
UARTIntClear( UART0_BASE, ulStatus );
/* Was a Tx interrupt pending? */
if( ulStatus & UART_INT_TX )
{
/* Send the next character in the string. We are not using the FIFO. */
if( *pcNextChar != NULL )
{
if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )
{
HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar;
}
pcNextChar++;
}
}
}
/*-----------------------------------------------------------*/
void vGPIO_ISR( void )
{
/* Clear the interrupt. */
GPIOPinIntClear(GPIO_PORTC_BASE, mainPUSH_BUTTON);
/* Wake the button handler task. */
if( xSemaphoreGiveFromISR( xButtonSemaphore, pdFALSE ) )
{
portEND_SWITCHING_ISR( pdTRUE );
}
}
/*-----------------------------------------------------------*/
static void vPrintTask( void *pvParameters )
{
portCHAR *pcMessage;
unsigned portBASE_TYPE uxLine = 0, uxRow = 0;
for( ;; )
{
/* Wait for a message to arrive. */
xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY );
/* Write the message to the LCD. */
uxRow++;
uxLine++;
OSRAMClear();
OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01);
}
}

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Demo/CORTEX_LM3S811_IAR/standalone.xcl
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//*****************************************************************************
//
// standalone.xcl - Linker script for EW-ARM.
//
// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
//
//*****************************************************************************
//
// Set the CPU type to ARM.
//
-carm
//
// Define the size of flash and SRAM.
//
-DROMSTART=00000000
-DROMEND=0000FFFF
-DRAMSTART=20000000
-DRAMEND=20001FFF
//
// Define the sections to place into flash, and the order to place them.
//
-Z(CODE)INTVEC=ROMSTART-ROMEND
-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
-Z(CODE)CODE=ROMSTART-ROMEND
-Z(CONST)CODE_ID=ROMSTART-ROMEND
-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
-Z(CONST)CHECKSUM=ROMSTART-ROMEND
//
// Define the sections to place into SRAM, and the order to place them.
//
-Z(DATA)VTABLE=RAMSTART-RAMEND
-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
-Z(DATA)CODE_I=RAMSTART-RAMEND

249
Demo/CORTEX_LM3S811_IAR/startup.c
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//*****************************************************************************
//
// startup_ewarm.c - Boot code for Stellaris.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 991 of the Stellaris Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
// Enable the IAR extensions for this source file.
//
//*****************************************************************************
#pragma language=extended
//*****************************************************************************
//
// Forward declaration of the default fault handlers.
//
//*****************************************************************************
void ResetISR(void);
static void NmiSR(void);
static void FaultISR(void);
static void IntDefaultHandler(void);
//*****************************************************************************
//
// The entry point for the application.
//
//*****************************************************************************
extern int main(void);
//*****************************************************************************
//
// External declaration for the interrupt handler used by the application.
//
//*****************************************************************************
extern void xPortPendSVHandler(void);
extern void xPortSysTickHandler(void);
extern void vGPIO_ISR(void);
extern void vUART_ISR(void);
//*****************************************************************************
//
// Reserve space for the system stack.
//
//*****************************************************************************
#ifndef STACK_SIZE
#define STACK_SIZE 64
#endif
static unsigned long pulStack[STACK_SIZE];
//*****************************************************************************
//
// A union that describes the entries of the vector table. The union is needed
// since the first entry is the stack pointer and the remainder are function
// pointers.
//
//*****************************************************************************
typedef union
{
void (*pfnHandler)(void);
unsigned long ulPtr;
}
uVectorEntry;
//*****************************************************************************
//
// The minimal vector table for a Cortex M3. Note that the proper constructs
// must be placed on this to ensure that it ends up at physical address
// 0x0000.0000.
//
//*****************************************************************************
__root const uVectorEntry g_pfnVectors[] @ "INTVEC" =
{
{ .ulPtr = (unsigned long)pulStack + sizeof(pulStack) },
// The initial stack pointer
ResetISR, // The reset handler
NmiSR, // The NMI handler
FaultISR, // The hard fault handler
IntDefaultHandler, // The MPU fault handler
IntDefaultHandler, // The bus fault handler
IntDefaultHandler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
IntDefaultHandler, // SVCall handler
IntDefaultHandler, // Debug monitor handler
0, // Reserved
xPortPendSVHandler, // The PendSV handler
xPortSysTickHandler, // The SysTick handler
IntDefaultHandler, // GPIO Port A
IntDefaultHandler, // GPIO Port B
vGPIO_ISR, // GPIO Port C
IntDefaultHandler, // GPIO Port D
IntDefaultHandler, // GPIO Port E
vUART_ISR, // UART0 Rx and Tx
IntDefaultHandler, // UART1 Rx and Tx
IntDefaultHandler, // SSI Rx and Tx
IntDefaultHandler, // I2C Master and Slave
IntDefaultHandler, // PWM Fault
IntDefaultHandler, // PWM Generator 0
IntDefaultHandler, // PWM Generator 1
IntDefaultHandler, // PWM Generator 2
IntDefaultHandler, // Quadrature Encoder
IntDefaultHandler, // ADC Sequence 0
IntDefaultHandler, // ADC Sequence 1
IntDefaultHandler, // ADC Sequence 2
IntDefaultHandler, // ADC Sequence 3
IntDefaultHandler, // Watchdog timer
IntDefaultHandler, // Timer 0 subtimer A
IntDefaultHandler, // Timer 0 subtimer B
IntDefaultHandler, // Timer 1 subtimer A
IntDefaultHandler, // Timer 1 subtimer B
IntDefaultHandler, // Timer 2 subtimer A
IntDefaultHandler, // Timer 2 subtimer B
IntDefaultHandler, // Analog Comparator 0
IntDefaultHandler, // Analog Comparator 1
IntDefaultHandler, // Analog Comparator 2
IntDefaultHandler, // System Control (PLL, OSC, BO)
IntDefaultHandler // FLASH Control
};
//*****************************************************************************
//
// The following are constructs created by the linker, indicating where the
// the "data" and "bss" segments reside in memory. The initializers for the
// for the "data" segment resides immediately following the "text" segment.
//
//*****************************************************************************
#pragma segment="DATA_ID"
#pragma segment="DATA_I"
#pragma segment="DATA_Z"
//*****************************************************************************
//
// This is the code that gets called when the processor first starts execution
// following a reset event. Only the absolutely necessary set is performed,
// after which the application supplied entry() routine is called. Any fancy
// actions (such as making decisions based on the reset cause register, and
// resetting the bits in that register) are left solely in the hands of the
// application.
//
//*****************************************************************************
void
ResetISR(void)
{
unsigned long *pulSrc, *pulDest, *pulEnd;
//
// Copy the data segment initializers from flash to SRAM.
//
pulSrc = __segment_begin("DATA_ID");
pulDest = __segment_begin("DATA_I");
pulEnd = __segment_end("DATA_I");
while(pulDest < pulEnd)
{
*pulDest++ = *pulSrc++;
}
//
// Zero fill the bss segment.
//
pulDest = __segment_begin("DATA_Z");
pulEnd = __segment_end("DATA_Z");
while(pulDest < pulEnd)
{
*pulDest++ = 0;
}
//
// Call the application's entry point.
//
main();
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives a NMI. This
// simply enters an infinite loop, preserving the system state for examination
// by a debugger.
//
//*****************************************************************************
static void
NmiSR(void)
{
//
// Enter an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives a fault
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
static void
FaultISR(void)
{
//
// Enter an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives an unexpected
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
static void
IntDefaultHandler(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
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