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Expand RV32E demo support, prevent 'ebreak' looping (#883)

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* Expand RV32E demo support, prevent 'ebreak' looping

The RegTest tests are modified in the Qemu and HiFive demos
to support RV32E and its limited set of registers.

'ebreak' call looping is removed in RegTest. This produces
a lot of noise when debugging.

* Correct whitespace

* Remove 'ebreak' instruction calls

The ebreak instruction sets and exception
which leads to jumping around the binary. This
can make debugging difficult.

* Fix whitespace formatting
pull/922/head
Kody Stribrny 2 years ago committed by GitHub
parent fe9322ca23
commit 2f3e5235aa
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
10 changed files with 942 additions and 949 deletions
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10
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S
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@ -187,9 +187,7 @@ reg1_loop:
jal reg1_loop jal reg1_loop
reg1_error_loop: reg1_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop /* Busy loop which holds the task. */
counter being incremented so the check task knows an error was found. */
ebreak
jal reg1_error_loop jal reg1_error_loop
.align( 4 ) .align( 4 )
@ -334,12 +332,8 @@ Reg2_loop:
jal Reg2_loop jal Reg2_loop
reg2_error_loop: reg2_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop /* Busy loop which holds the task. */
counter being incremented so the check task knows an error was found. */
ebreak
jal reg2_error_loop jal reg2_error_loop
.align( 4 ) .align( 4 )
ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter

136
FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/RegTest.S
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@ -51,7 +51,7 @@ vRegTest1Implementation:
li x12, 0xc li x12, 0xc
li x13, 0xd li x13, 0xd
li x14, 0xe li x14, 0xe
li x15, 0xf #ifndef __riscv_32e
li x16, 0x10 li x16, 0x10
li x17, 0x11 li x17, 0x11
li x18, 0x12 li x18, 0x12
@ -67,73 +67,77 @@ vRegTest1Implementation:
li x28, 0x1c li x28, 0x1c
li x29, 0x1d li x29, 0x1d
li x30, 0x1e li x30, 0x1e
li x31, 0x1f
#endif
reg1_loop: reg1_loop:
/* Check each register still contains the expected known value. /* Check each register still contains the expected known value.
vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation vRegTest1Implementation uses x15 as the temporary, vRegTest2Implementation
uses x5 as the temporary. */ uses x5 as the temporary. */
li x31, 0x5 li x15, 0x5
bne x31, x5, reg1_error_loop bne x15, x5, reg1_error_loop
li x31, 0x6 li x15, 0x6
bne x31, x6, reg1_error_loop bne x15, x6, reg1_error_loop
li x31, 0x7 li x15, 0x7
bne x31, x7, reg1_error_loop bne x15, x7, reg1_error_loop
li x31, 0x8 li x15, 0x8
bne x31, x8, reg1_error_loop bne x15, x8, reg1_error_loop
li x31, 0x9 li x15, 0x9
bne x31, x9, reg1_error_loop bne x15, x9, reg1_error_loop
li x31, 0xa li x15, 0xa
bne x31, x10, reg1_error_loop bne x15, x10, reg1_error_loop
li x31, 0xb li x15, 0xb
bne x31, x11, reg1_error_loop bne x15, x11, reg1_error_loop
li x31, 0xc li x15, 0xc
bne x31, x12, reg1_error_loop bne x15, x12, reg1_error_loop
li x31, 0xd li x15, 0xd
bne x31, x13, reg1_error_loop bne x15, x13, reg1_error_loop
li x31, 0xe li x15, 0xe
bne x31, x14, reg1_error_loop bne x15, x14, reg1_error_loop
li x31, 0xf #ifndef __riscv_32e
bne x31, x15, reg1_error_loop li x15, 0x10
li x31, 0x10 bne x15, x16, reg1_error_loop
bne x31, x16, reg1_error_loop li x15, 0x11
li x31, 0x11 bne x15, x17, reg1_error_loop
bne x31, x17, reg1_error_loop li x15, 0x12
li x31, 0x12 bne x15, x18, reg1_error_loop
bne x31, x18, reg1_error_loop li x15, 0x13
li x31, 0x13 bne x15, x19, reg1_error_loop
bne x31, x19, reg1_error_loop li x15, 0x14
li x31, 0x14 bne x15, x20, reg1_error_loop
bne x31, x20, reg1_error_loop li x15, 0x15
li x31, 0x15 bne x15, x21, reg1_error_loop
bne x31, x21, reg1_error_loop li x15, 0x16
li x31, 0x16 bne x15, x22, reg1_error_loop
bne x31, x22, reg1_error_loop li x15, 0x17
li x31, 0x17 bne x15, x23, reg1_error_loop
bne x31, x23, reg1_error_loop li x15, 0x18
li x31, 0x18 bne x15, x24, reg1_error_loop
bne x31, x24, reg1_error_loop li x15, 0x19
li x31, 0x19 bne x15, x25, reg1_error_loop
bne x31, x25, reg1_error_loop li x15, 0x1a
li x31, 0x1a bne x15, x26, reg1_error_loop
bne x31, x26, reg1_error_loop li x15, 0x1b
li x31, 0x1b bne x15, x27, reg1_error_loop
bne x31, x27, reg1_error_loop li x15, 0x1c
li x31, 0x1c bne x15, x28, reg1_error_loop
bne x31, x28, reg1_error_loop li x15, 0x1d
li x31, 0x1d bne x15, x29, reg1_error_loop
bne x31, x29, reg1_error_loop li x15, 0x1e
li x31, 0x1e bne x15, x30, reg1_error_loop
bne x31, x30, reg1_error_loop li x15, 0x1f
bne x15, x31, reg1_error_loop
#endif
/* Everything passed, increment the loop counter. */ /* Everything passed, increment the loop counter. */
lw x31, ulRegTest1LoopCounterConst lw x15, ulRegTest1LoopCounterConst
lw x30, 0(x31) lw x14, 0(x15)
addi x30, x30, 1 addi x14, x14, 1
sw x30, 0(x31) sw x14, 0(x15)
/* Restore clobbered register reading for next loop. */ /* Restore clobbered register reading for next loop. */
li x30, 0x1e li x14, 0xe
/* Yield to increase code coverage. */ /* Yield to increase code coverage. */
ecall ecall
@ -142,9 +146,7 @@ reg1_loop:
jal reg1_loop jal reg1_loop
reg1_error_loop: reg1_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop /* Busy loop which holds the task. */
counter being incremented so the check task knows an error was found. */
ebreak
jal reg1_error_loop jal reg1_error_loop
.align( 4 ) .align( 4 )
@ -166,6 +168,7 @@ vRegTest2Implementation:
li x13, 0xd1 li x13, 0xd1
li x14, 0xe1 li x14, 0xe1
li x15, 0xf1 li x15, 0xf1
#ifndef __riscv_32e
li x16, 0x20 li x16, 0x20
li x17, 0x21 li x17, 0x21
li x18, 0x22 li x18, 0x22
@ -182,6 +185,7 @@ vRegTest2Implementation:
li x29, 0x2d li x29, 0x2d
li x30, 0x2e li x30, 0x2e
li x31, 0x2f li x31, 0x2f
#endif
Reg2_loop: Reg2_loop:
@ -208,6 +212,7 @@ Reg2_loop:
bne x5, x14, reg2_error_loop bne x5, x14, reg2_error_loop
li x5, 0xf1 li x5, 0xf1
bne x5, x15, reg2_error_loop bne x5, x15, reg2_error_loop
#ifndef __riscv_32e
li x5, 0x20 li x5, 0x20
bne x5, x16, reg2_error_loop bne x5, x16, reg2_error_loop
li x5, 0x21 li x5, 0x21
@ -240,6 +245,7 @@ Reg2_loop:
bne x5, x30, reg2_error_loop bne x5, x30, reg2_error_loop
li x5, 0x2f li x5, 0x2f
bne x5, x31, reg2_error_loop bne x5, x31, reg2_error_loop
#endif
/* Everything passed, increment the loop counter. */ /* Everything passed, increment the loop counter. */
lw x5, ulRegTest2LoopCounterConst lw x5, ulRegTest2LoopCounterConst
@ -254,12 +260,8 @@ Reg2_loop:
jal Reg2_loop jal Reg2_loop
reg2_error_loop: reg2_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop /* Busy loop which holds the task. */
counter being incremented so the check task knows an error was found. */
ebreak
jal reg2_error_loop jal reg2_error_loop
.align( 4 ) .align( 4 )
ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter

133
FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/full_demo/RegTest.S
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@ -52,6 +52,7 @@ vRegTest1Implementation:
li x13, 0xd li x13, 0xd
li x14, 0xe li x14, 0xe
li x15, 0xf li x15, 0xf
#ifndef __riscv_32e
li x16, 0x10 li x16, 0x10
li x17, 0x11 li x17, 0x11
li x18, 0x12 li x18, 0x12
@ -67,73 +68,77 @@ vRegTest1Implementation:
li x28, 0x1c li x28, 0x1c
li x29, 0x1d li x29, 0x1d
li x30, 0x1e li x30, 0x1e
li x31, 0x1f
#endif
reg1_loop: reg1_loop:
/* Check each register still contains the expected known value. /* Check each register still contains the expected known value.
vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation vRegTest1Implementation uses x15 as the temporary, vRegTest2Implementation
uses x5 as the temporary. */ uses x5 as the temporary. */
li x31, 0x5 li x15, 0x5
bne x31, x5, reg1_error_loop bne x15, x5, reg1_error_loop
li x31, 0x6 li x15, 0x6
bne x31, x6, reg1_error_loop bne x15, x6, reg1_error_loop
li x31, 0x7 li x15, 0x7
bne x31, x7, reg1_error_loop bne x15, x7, reg1_error_loop
li x31, 0x8 li x15, 0x8
bne x31, x8, reg1_error_loop bne x15, x8, reg1_error_loop
li x31, 0x9 li x15, 0x9
bne x31, x9, reg1_error_loop bne x15, x9, reg1_error_loop
li x31, 0xa li x15, 0xa
bne x31, x10, reg1_error_loop bne x15, x10, reg1_error_loop
li x31, 0xb li x15, 0xb
bne x31, x11, reg1_error_loop bne x15, x11, reg1_error_loop
li x31, 0xc li x15, 0xc
bne x31, x12, reg1_error_loop bne x15, x12, reg1_error_loop
li x31, 0xd li x15, 0xd
bne x31, x13, reg1_error_loop bne x15, x13, reg1_error_loop
li x31, 0xe li x15, 0xe
bne x31, x14, reg1_error_loop bne x15, x14, reg1_error_loop
li x31, 0xf #ifndef __riscv_32e
bne x31, x15, reg1_error_loop li x15, 0x10
li x31, 0x10 bne x15, x16, reg1_error_loop
bne x31, x16, reg1_error_loop li x15, 0x11
li x31, 0x11 bne x15, x17, reg1_error_loop
bne x31, x17, reg1_error_loop li x15, 0x12
li x31, 0x12 bne x15, x18, reg1_error_loop
bne x31, x18, reg1_error_loop li x15, 0x13
li x31, 0x13 bne x15, x19, reg1_error_loop
bne x31, x19, reg1_error_loop li x15, 0x14
li x31, 0x14 bne x15, x20, reg1_error_loop
bne x31, x20, reg1_error_loop li x15, 0x15
li x31, 0x15 bne x15, x21, reg1_error_loop
bne x31, x21, reg1_error_loop li x15, 0x16
li x31, 0x16 bne x15, x22, reg1_error_loop
bne x31, x22, reg1_error_loop li x15, 0x17
li x31, 0x17 bne x15, x23, reg1_error_loop
bne x31, x23, reg1_error_loop li x15, 0x18
li x31, 0x18 bne x15, x24, reg1_error_loop
bne x31, x24, reg1_error_loop li x15, 0x19
li x31, 0x19 bne x15, x25, reg1_error_loop
bne x31, x25, reg1_error_loop li x15, 0x1a
li x31, 0x1a bne x15, x26, reg1_error_loop
bne x31, x26, reg1_error_loop li x15, 0x1b
li x31, 0x1b bne x15, x27, reg1_error_loop
bne x31, x27, reg1_error_loop li x15, 0x1c
li x31, 0x1c bne x15, x28, reg1_error_loop
bne x31, x28, reg1_error_loop li x15, 0x1d
li x31, 0x1d bne x15, x29, reg1_error_loop
bne x31, x29, reg1_error_loop li x15, 0x1e
li x31, 0x1e bne x15, x30, reg1_error_loop
bne x31, x30, reg1_error_loop li x15, 0x1f
bne x15, x31, reg1_error_loop
#endif
/* Everything passed, increment the loop counter. */ /* Everything passed, increment the loop counter. */
lw x31, ulRegTest1LoopCounterConst lw x15, ulRegTest1LoopCounterConst
lw x30, 0(x31) lw x14, 0(x15)
addi x30, x30, 1 addi x14, x14, 1
sw x30, 0(x31) sw x14, 0(x15)
/* Restore clobbered register reading for next loop. */ /* Restore clobbered register reading for next loop. */
li x30, 0x1e li x14, 0xe
/* Yield to increase code coverage. */ /* Yield to increase code coverage. */
ecall ecall
@ -142,9 +147,7 @@ reg1_loop:
jal reg1_loop jal reg1_loop
reg1_error_loop: reg1_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop /* Busy loop which holds the task. */
counter being incremented so the check task knows an error was found. */
ebreak
jal reg1_error_loop jal reg1_error_loop
.align( 4 ) .align( 4 )
@ -166,6 +169,7 @@ vRegTest2Implementation:
li x13, 0xd1 li x13, 0xd1
li x14, 0xe1 li x14, 0xe1
li x15, 0xf1 li x15, 0xf1
#ifdef __riscv_32e
li x16, 0x20 li x16, 0x20
li x17, 0x21 li x17, 0x21
li x18, 0x22 li x18, 0x22
@ -182,6 +186,7 @@ vRegTest2Implementation:
li x29, 0x2d li x29, 0x2d
li x30, 0x2e li x30, 0x2e
li x31, 0x2f li x31, 0x2f
#endif
Reg2_loop: Reg2_loop:
@ -208,6 +213,7 @@ Reg2_loop:
bne x5, x14, reg2_error_loop bne x5, x14, reg2_error_loop
li x5, 0xf1 li x5, 0xf1
bne x5, x15, reg2_error_loop bne x5, x15, reg2_error_loop
#ifndef __riscv_32e
li x5, 0x20 li x5, 0x20
bne x5, x16, reg2_error_loop bne x5, x16, reg2_error_loop
li x5, 0x21 li x5, 0x21
@ -240,6 +246,7 @@ Reg2_loop:
bne x5, x30, reg2_error_loop bne x5, x30, reg2_error_loop
li x5, 0x2f li x5, 0x2f
bne x5, x31, reg2_error_loop bne x5, x31, reg2_error_loop
#endif
/* Everything passed, increment the loop counter. */ /* Everything passed, increment the loop counter. */
lw x5, ulRegTest2LoopCounterConst lw x5, ulRegTest2LoopCounterConst
@ -254,9 +261,7 @@ Reg2_loop:
jal Reg2_loop jal Reg2_loop
reg2_error_loop: reg2_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop /* Busy loop which holds the task. */
counter being incremented so the check task knows an error was found. */
ebreak
jal reg2_error_loop jal reg2_error_loop
.align( 4 ) .align( 4 )

2
FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/FreeRTOSConfig.h
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@ -94,7 +94,7 @@
/* Normal assert() semantics without relying on the provision of an assert.h /* Normal assert() semantics without relying on the provision of an assert.h
* header file. */ * header file. */
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); __asm volatile( "ebreak" ); for( ;; ); } #define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
/* Map to the platform write function. */ /* Map to the platform write function. */
extern void vSendString( const char * const pcString ); extern void vSendString( const char * const pcString );

136
FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/full_demo/RegTest.s
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@ -54,7 +54,7 @@ vRegTest1Implementation:
li x12, 0xc li x12, 0xc
li x13, 0xd li x13, 0xd
li x14, 0xe li x14, 0xe
li x15, 0xf #ifndef __riscv_32e
li x16, 0x10 li x16, 0x10
li x17, 0x11 li x17, 0x11
li x18, 0x12 li x18, 0x12
@ -70,73 +70,77 @@ vRegTest1Implementation:
li x28, 0x1c li x28, 0x1c
li x29, 0x1d li x29, 0x1d
li x30, 0x1e li x30, 0x1e
li x31, 0x1f
#endif
reg1_loop: reg1_loop:
/* Check each register still contains the expected known value. /* Check each register still contains the expected known value.
* vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation * vRegTest1Implementation uses x15 as the temporary, vRegTest2Implementation
* uses x5 as the temporary. */ * uses x5 as the temporary. */
li x31, 0x5 li x15, 0x5
bne x31, x5, reg1_error_loop bne x15, x5, reg1_error_loop
li x31, 0x6 li x15, 0x6
bne x31, x6, reg1_error_loop bne x15, x6, reg1_error_loop
li x31, 0x7 li x15, 0x7
bne x31, x7, reg1_error_loop bne x15, x7, reg1_error_loop
li x31, 0x8 li x15, 0x8
bne x31, x8, reg1_error_loop bne x15, x8, reg1_error_loop
li x31, 0x9 li x15, 0x9
bne x31, x9, reg1_error_loop bne x15, x9, reg1_error_loop
li x31, 0xa li x15, 0xa
bne x31, x10, reg1_error_loop bne x15, x10, reg1_error_loop
li x31, 0xb li x15, 0xb
bne x31, x11, reg1_error_loop bne x15, x11, reg1_error_loop
li x31, 0xc li x15, 0xc
bne x31, x12, reg1_error_loop bne x15, x12, reg1_error_loop
li x31, 0xd li x15, 0xd
bne x31, x13, reg1_error_loop bne x15, x13, reg1_error_loop
li x31, 0xe li x15, 0xe
bne x31, x14, reg1_error_loop bne x15, x14, reg1_error_loop
li x31, 0xf #ifndef __riscv_32e
bne x31, x15, reg1_error_loop li x15, 0x10
li x31, 0x10 bne x15, x16, reg1_error_loop
bne x31, x16, reg1_error_loop li x15, 0x11
li x31, 0x11 bne x15, x17, reg1_error_loop
bne x31, x17, reg1_error_loop li x15, 0x12
li x31, 0x12 bne x15, x18, reg1_error_loop
bne x31, x18, reg1_error_loop li x15, 0x13
li x31, 0x13 bne x15, x19, reg1_error_loop
bne x31, x19, reg1_error_loop li x15, 0x14
li x31, 0x14 bne x15, x20, reg1_error_loop
bne x31, x20, reg1_error_loop li x15, 0x15
li x31, 0x15 bne x15, x21, reg1_error_loop
bne x31, x21, reg1_error_loop li x15, 0x16
li x31, 0x16 bne x15, x22, reg1_error_loop
bne x31, x22, reg1_error_loop li x15, 0x17
li x31, 0x17 bne x15, x23, reg1_error_loop
bne x31, x23, reg1_error_loop li x15, 0x18
li x31, 0x18 bne x15, x24, reg1_error_loop
bne x31, x24, reg1_error_loop li x15, 0x19
li x31, 0x19 bne x15, x25, reg1_error_loop
bne x31, x25, reg1_error_loop li x15, 0x1a
li x31, 0x1a bne x15, x26, reg1_error_loop
bne x31, x26, reg1_error_loop li x15, 0x1b
li x31, 0x1b bne x15, x27, reg1_error_loop
bne x31, x27, reg1_error_loop li x15, 0x1c
li x31, 0x1c bne x15, x28, reg1_error_loop
bne x31, x28, reg1_error_loop li x15, 0x1d
li x31, 0x1d bne x15, x29, reg1_error_loop
bne x31, x29, reg1_error_loop li x15, 0x1e
li x31, 0x1e bne x15, x30, reg1_error_loop
bne x31, x30, reg1_error_loop li x15, 0x1f
bne x15, x31, reg1_error_loop
#endif
/* Everything passed, increment the loop counter. */ /* Everything passed, increment the loop counter. */
lw x31, pulRegTest1LoopCounter lw x15, pulRegTest1LoopCounter
lw x30, 0(x31) lw x14, 0(x15)
addi x30, x30, 1 addi x14, x14, 1
sw x30, 0(x31) sw x14, 0(x15)
/* Restore clobbered register reading for next loop. */ /* Restore clobbered register reading for next loop. */
li x30, 0x1e li x14, 0xe
/* Yield to increase code coverage. */ /* Yield to increase code coverage. */
ecall ecall
@ -145,9 +149,7 @@ reg1_loop:
jal reg1_loop jal reg1_loop
reg1_error_loop: reg1_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop /* Busy loop which holds the task. */
* counter being incremented so the check task knows an error was found. */
ebreak
jal reg1_error_loop jal reg1_error_loop
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@ -166,6 +168,7 @@ vRegTest2Implementation:
li x13, 0xd1 li x13, 0xd1
li x14, 0xe1 li x14, 0xe1
li x15, 0xf1 li x15, 0xf1
#ifndef __riscv_32e
li x16, 0x20 li x16, 0x20
li x17, 0x21 li x17, 0x21
li x18, 0x22 li x18, 0x22
@ -182,12 +185,13 @@ vRegTest2Implementation:
li x29, 0x2d li x29, 0x2d
li x30, 0x2e li x30, 0x2e
li x31, 0x2f li x31, 0x2f
#endif
Reg2_loop: Reg2_loop:
/* Check each register still contains the expected known value. /* Check each register still contains the expected known value.
* vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation * vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
* uses x31 as the temporary. */ * uses x15 as the temporary. */
li x5, 0x61 li x5, 0x61
bne x5, x6, reg2_error_loop bne x5, x6, reg2_error_loop
li x5, 0x71 li x5, 0x71
@ -208,6 +212,7 @@ Reg2_loop:
bne x5, x14, reg2_error_loop bne x5, x14, reg2_error_loop
li x5, 0xf1 li x5, 0xf1
bne x5, x15, reg2_error_loop bne x5, x15, reg2_error_loop
#ifndef __riscv_32e
li x5, 0x20 li x5, 0x20
bne x5, x16, reg2_error_loop bne x5, x16, reg2_error_loop
li x5, 0x21 li x5, 0x21
@ -240,6 +245,7 @@ Reg2_loop:
bne x5, x30, reg2_error_loop bne x5, x30, reg2_error_loop
li x5, 0x2f li x5, 0x2f
bne x5, x31, reg2_error_loop bne x5, x31, reg2_error_loop
#endif
/* Everything passed, increment the loop counter. */ /* Everything passed, increment the loop counter. */
lw x5, pulRegTest2LoopCounter lw x5, pulRegTest2LoopCounter
@ -254,9 +260,7 @@ Reg2_loop:
jal Reg2_loop jal Reg2_loop
reg2_error_loop: reg2_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop /* Busy loop which holds the task. */
* counter being incremented so the check task knows an error was found. */
ebreak
jal reg2_error_loop jal reg2_error_loop
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/

2
FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/main.c
Unescape Escape View File

@ -242,7 +242,6 @@ void vApplicationMallocFailedHook( void )
* to query the size of free heap space that remains (although it does not * to query the size of free heap space that remains (although it does not
* provide information on how the remaining heap might be fragmented). */ * provide information on how the remaining heap might be fragmented). */
taskDISABLE_INTERRUPTS(); taskDISABLE_INTERRUPTS();
__asm volatile( "ebreak" );
for( ;; ); for( ;; );
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@ -270,7 +269,6 @@ void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
* configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
* function is called if a stack overflow is detected. */ * function is called if a stack overflow is detected. */
taskDISABLE_INTERRUPTS(); taskDISABLE_INTERRUPTS();
__asm volatile( "ebreak" );
for( ;; ); for( ;; );
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/

8
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/full_demo/RegTest.S
Unescape Escape View File

@ -142,9 +142,7 @@ reg1_loop:
jal reg1_loop jal reg1_loop
reg1_error_loop: reg1_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop /* Busy loop which holds the task. */
* counter being incremented so the check task knows an error was found. */
ebreak
jal reg1_error_loop jal reg1_error_loop
.align( 4 ) .align( 4 )
@ -254,9 +252,7 @@ Reg2_loop:
jal Reg2_loop jal Reg2_loop
reg2_error_loop: reg2_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop /* Busy loop which holds the task. */
* counter being incremented so the check task knows an error was found. */
ebreak
jal reg2_error_loop jal reg2_error_loop
.align( 4 ) .align( 4 )

2
FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/FreeRTOSConfig.h
Unescape Escape View File

@ -98,7 +98,7 @@ to exclude the API function. */
/* Normal assert() semantics without relying on the provision of an assert.h /* Normal assert() semantics without relying on the provision of an assert.h
header file. */ header file. */
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); __asm volatile( "ebreak" ); for( ;; ); } #define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
/* Defined in main.c and used in main_blinky.c and main_full.c. */ /* Defined in main.c and used in main_blinky.c and main_full.c. */
void vSendString( const char * const pcString ); void vSendString( const char * const pcString );

8
FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/RegTest.S
Unescape Escape View File

@ -142,9 +142,7 @@ reg1_loop:
jal reg1_loop jal reg1_loop
reg1_error_loop: reg1_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop /* Busy loop which holds the task. */
counter being incremented so the check task knows an error was found. */
ebreak
jal reg1_error_loop jal reg1_error_loop
.align( 4 ) .align( 4 )
@ -254,9 +252,7 @@ Reg2_loop:
jal Reg2_loop jal Reg2_loop
reg2_error_loop: reg2_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop /* Busy loop which holds the task. */
counter being incremented so the check task knows an error was found. */
ebreak
jal reg2_error_loop jal reg2_error_loop
.align( 4 ) .align( 4 )

2
FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/main.c
Unescape Escape View File

@ -137,7 +137,6 @@ void vApplicationMallocFailedHook( void )
to query the size of free heap space that remains (although it does not to query the size of free heap space that remains (although it does not
provide information on how the remaining heap might be fragmented). */ provide information on how the remaining heap might be fragmented). */
taskDISABLE_INTERRUPTS(); taskDISABLE_INTERRUPTS();
__asm volatile( "ebreak" );
for( ;; ); for( ;; );
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@ -165,7 +164,6 @@ void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
function is called if a stack overflow is detected. */ function is called if a stack overflow is detected. */
taskDISABLE_INTERRUPTS(); taskDISABLE_INTERRUPTS();
__asm volatile( "ebreak" );
for( ;; ); for( ;; );
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/

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