SAMA5D3 Xplained demo blinky running.
Richard Barry
11 years ago
parent
f4a1a7d577
commit
29336e35b5
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/* ----------------------------------------------------------------------------
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* SAM Software Package License
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* ----------------------------------------------------------------------------
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* Copyright (c) 2012, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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//------------------------------------------------------------------------------
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// Definitions
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//------------------------------------------------------------------------------
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#define AIC 0xFFFFF000
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#define AIC_IVR 0x10
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#define AIC_EOICR 0x38
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#define IRQ_STACK_SIZE 8*3*4
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#define ARM_MODE_ABT 0x17
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#define ARM_MODE_FIQ 0x11
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#define ARM_MODE_IRQ 0x12
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#define ARM_MODE_SVC 0x13
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#define ARM_MODE_SYS 0x1F
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#define I_BIT 0x80
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#define F_BIT 0x40
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//------------------------------------------------------------------------------
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// Startup routine
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//------------------------------------------------------------------------------
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.align 4
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.arm
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/* Exception vectors
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*******************/
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.section .vectors, "a", %progbits
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resetVector:
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ldr pc, =resetHandler /* Reset */
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undefVector:
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b undefVector /* Undefined instruction */
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swiVector:
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b swiVector /* Software interrupt */
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prefetchAbortVector:
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b prefetchAbortVector /* Prefetch abort */
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dataAbortVector:
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b dataAbortVector /* Data abort */
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reservedVector:
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b reservedVector /* Reserved for future use */
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irqVector:
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b irqHandler /* Interrupt */
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fiqVector:
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/* Fast interrupt */
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//------------------------------------------------------------------------------
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/// Handles a fast interrupt request by branching to the address defined in the
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/// AIC.
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//------------------------------------------------------------------------------
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fiqHandler:
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b fiqHandler
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//------------------------------------------------------------------------------
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/// Handles incoming interrupt requests by branching to the corresponding
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/// handler, as defined in the AIC. Supports interrupt nesting.
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//------------------------------------------------------------------------------
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irqHandler:
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/* Save interrupt context on the stack to allow nesting */
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SUB lr, lr, #4
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STMFD sp!, {lr}
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MRS lr, SPSR
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STMFD sp!, {r0, lr}
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/* Write in the IVR to support Protect Mode */
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LDR lr, =AIC
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LDR r0, [r14, #AIC_IVR]
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STR lr, [r14, #AIC_IVR]
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/* Branch to interrupt handler in Supervisor mode */
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MSR CPSR_c, #ARM_MODE_SVC
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STMFD sp!, {r1-r3, r4, r12, lr}
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/* Check for 8-byte alignment and save lr plus a */
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/* word to indicate the stack adjustment used (0 or 4) */
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AND r1, sp, #4
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SUB sp, sp, r1
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STMFD sp!, {r1, lr}
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BLX r0
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LDMIA sp!, {r1, lr}
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ADD sp, sp, r1
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LDMIA sp!, {r1-r3, r4, r12, lr}
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MSR CPSR_c, #ARM_MODE_IRQ | I_BIT
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/* Acknowledge interrupt */
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LDR lr, =AIC
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STR lr, [r14, #AIC_EOICR]
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/* Restore interrupt context and branch back to calling code */
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LDMIA sp!, {r0, lr}
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MSR SPSR_cxsf, lr
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LDMIA sp!, {pc}^
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//------------------------------------------------------------------------------
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/// Initializes the chip and branches to the main() function.
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//------------------------------------------------------------------------------
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.section .textEntry
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.global entry
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entry:
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resetHandler:
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CPSIE A
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/* Enable VFP */
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/* - Enable access to CP10 and CP11 in CP15.CACR */
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mrc p15, 0, r0, c1, c0, 2
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orr r0, r0, #0xf00000
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mcr p15, 0, r0, c1, c0, 2
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/* - Enable access to CP10 and CP11 in CP15.NSACR */
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/* - Set FPEXC.EN (B30) */
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fmrx r0, fpexc
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orr r0, r0, #0x40000000
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fmxr fpexc, r0
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/* Useless instruction for referencing the .vectors section */
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ldr r0, =resetVector
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/* Set pc to actual code location (i.e. not in remap zone) */
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ldr pc, =1f
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/* Initialize the prerelocate segment */
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1:
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ldr r0, =_efixed
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ldr r1, =_sprerelocate
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ldr r2, =_eprerelocate
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1:
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cmp r1, r2
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ldrcc r3, [r0], #4
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strcc r3, [r1], #4
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bcc 1b
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/* Perform low-level initialization of the chip using LowLevelInit() */
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ldr sp, =_sstack
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stmfd sp!, {r0}
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ldr r0, =LowLevelInit
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blx r0
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/* Initialize the postrelocate segment */
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ldmfd sp!, {r0}
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ldr r1, =_spostrelocate
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ldr r2, =_epostrelocate
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1:
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cmp r1, r2
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ldrcc r3, [r0], #4
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strcc r3, [r1], #4
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bcc 1b
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/* Clear the zero segment */
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ldr r0, =_szero
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ldr r1, =_ezero
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mov r2, #0
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1:
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cmp r0, r1
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strcc r2, [r0], #4
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bcc 1b
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/* Setup stacks
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**************/
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/* IRQ mode */
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msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
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ldr sp, =_sstack
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sub r4, sp, #IRQ_STACK_SIZE
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/* Supervisor mode (interrupts enabled) */
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msr CPSR_c, #ARM_MODE_SVC | F_BIT
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mov sp, r4
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/*Initialize the C library */
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ldr r3, =__libc_init_array
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mov lr, pc
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bx r3
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/* Branch to main()
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******************/
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ldr r0, =main
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blx r0
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/* Loop indefinitely when program is finished */
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1:
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b 1b
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@ -1,2 +1,2 @@
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[MainWindow]
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WindowPlacement=_ 66 66 1326 815 3
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WindowPlacement=_ 67 68 1327 817 3
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