Richard Barry
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61a003088d
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Update RISK-V GCC port to ensure the first task starts with interrupts enabled - previously its interrupts were only enabled after it yielded for the first time.
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5 years ago |
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Richard Barry
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80c1cb5de1
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Correct code comments that referred to taskYIELD_FROM_ISR to portYIELD_FROM_ISR.
Update RV32 port to use 16 byte-alignment all the time (only strictly necessary when using FLOP instructions).
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5 years ago |
Yuhui.Zheng
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74df636c78
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sync from github to svn: documentation for RISC-V. This may be a temporary parking location.
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5 years ago |
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Richard Barry
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da3d370ff7
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RISC-V port updates: The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores.
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6 years ago |
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Richard Barry
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973a4f9869
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Correct alignment of stack top in RISC-V port when configISR_STACK_SIZE_WORDS is defined to a non zero value.
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6 years ago |
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Richard Barry
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fb3eaeac40
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Added additional xMessageBufferSpacesAvailable() (plural) to existing xMessageBufferSpaceAvailable() (singular) macro as the documentation muddled both.
Added #define portPOINTER_SIZE_TYPE uint64_t to the 64-bit RISC-V port layer.
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6 years ago |
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Richard Barry
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b51529a284
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Update version number ready for next release.
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6 years ago |
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Richard Barry
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079d081346
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Basic 64-bit RISC-V port now functional. RISC-V port layer automatically switches between 32-bit and 64-bit.
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6 years ago |
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Richard Barry
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84377442fc
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Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM GCC ports to assist with link time optimisation.
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6 years ago |
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Richard Barry
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606845492b
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Fix potential memory leak in the Win32 FreeRTOS+TCP network interface initialisation sequence.
Introduce portMEMORY_BARRIER() macro to assist with memory access ordering when suspending the scheduler if link time optimization is used.
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6 years ago |
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Richard Barry
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2265d70499
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Correcting spelling mistakes in comments only.
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6 years ago |
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Richard Barry
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06596c3192
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Prepare the RISC-V port layer for addition of 64-bit port.
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6 years ago |
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Richard Barry
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58ba10eee8
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Update version number in readiness for V10.2.0 release.
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6 years ago |
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Richard Barry
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6844bef74f
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Replace the pdf RISC-V documentation with links to the documentation web pages.
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6 years ago |
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Richard Barry
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b2b1b09ea5
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Fix bug in core_cm3.c atomic macros.
Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
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6 years ago |