df5952f655
Add xTaskGetIdleRunTimeCounter() API function to return the run time stats counter for the idle task - useful for POSIX time implementations.
6 years ago
11d9c440b8
Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason).
...
Add a project for the Vega board's RI5CY core.
6 years ago
e2af102c80
Re-org of RISC-V file structure and naming step 2.
6 years ago
818eeccc0c
Re-org of RISC-V file structure and naming step 1.
6 years ago
db750d0c82
Update RSIC-V port layer after testing saving and receiving of chip specific registers.
6 years ago
60b133b2c6
Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.
6 years ago
d369110167
Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings.
...
Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.
6 years ago
ce36928ea8
Rename directories in the RISC-V port.
6 years ago
101806906d
Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT.
6 years ago
7cc42b2ab6
Save changes to the RISC-V port layer before making changes necessary to support pulpino too:
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+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other.
+ Handle external interrupts (working with Renode emulator).
+ The _sp linker variable is now called __freertos_irq_stack_top.
6 years ago
65f7a2dc19
Update RISC-V port to use a separate interrupt stack.
6 years ago
e85ea96f78
Some efficiency improvements in Risc-V port.
6 years ago
dc99300fa9
First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo.
6 years ago
db64297487
Provide each Risc V task with an initial mstatus register value.
6 years ago
8cef339aec
Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress.
6 years ago
baee711cb6
Continue work on Risc V port.
6 years ago
e3dc5e934b
RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet.
6 years ago
2bcb1ab02b
Add trap handler to RISC-V port so there is no dependency on third party code.
6 years ago
32f35e9130
RISC-V:
...
Added code to setup the timer interrupt - not tested yet.
Added the taskYIELD() implementation - so far just checked it generates an interrupt.
7 years ago
b11eb3a59c
RISC-V work in progress:
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+ Initialise task stack.
+ Successfully jump to start of first task.
7 years ago
92ae8e7aff
Update version numbers ready for release.
7 years ago
3a1631fda3
Update copyright date ready for tagging V10.1.0.
7 years ago
fb9de58f56
Update version numbers in preparation for a new release.
7 years ago
f6cbf20019
Update RISC-V project to used official port stubs in place of third party port.
7 years ago
3bfc32d444
Add stubs for official RISC-V RV32 port.
7 years ago
5bebf10fa4
Minor updates to comments only.
7 years ago
7ddb8b342d
Microblaze port: Place critical section around XIntc_Enable() to protect read/modify/write operation performed inside the library.
7 years ago
13651934be
Roll up the minor changes checked into svn since V10.0.0 into new V10.0.1 ready for release.
7 years ago
cfc268814a
Update to MIT licensed FreeRTOS V10.0.0 - see https://www.freertos.org/History.txt
7 years ago
037abdddf2
Update TriCore port to work with latest GCC compiler.
8 years ago
6eea3d8d4b
Correct long time mis-spelled portINITIAL_EXEC_RETURN to portINITIAL_EXC_RETURN
8 years ago
b080f13543
Add more "memory" clobbers into the MPU ports to make them robust to more aggressive optimisation in newer GCC version.
8 years ago
0f85ead175
Add more "memory" clobbers into asm code of GCC/ARM_CRx_No_GIC port to make it robust with higher optimisation in newer versions of GCC.
8 years ago
0a7a0a79d6
Updates to prevent warnings when compiled with LLVM.
8 years ago
464c2660ad
Updates to the Cortex-M tickless idle code to reduce clock slippage.
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Updates to prevent the vTaskSwitchContext() function being removed from GCC builds when link time optimisation is used.
8 years ago
b9fe24962e
Add additional memory barriers into ARM GCC asm code to ensure no re-ordering across asm code as optimisers get more aggressive.
8 years ago
c3acc441ac
Introduce vTaskInternalSetTimeOutState() which does not have a critical section, and add a critical section to the public version of the same.
8 years ago
8d041c8e21
Update version number in preparation for maintenance release.
8 years ago
992a3c8c71
Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to the 2016.4 versions.
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Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
8 years ago
6ffaa6f018
Correct alignment issue in GCC and RVDS Cortex-A9 port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
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Update the Zynq demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
8 years ago
75ffac21d7
Changes to core code and port layer:
...
+ Add configASSERT() into ARM Cortex-M ports to check the number of priority
bit settings.
+ Clear the 'control' register before starting ARM Cortex-M4F ports in case
the FPU is used before the scheduler is started. This just saves a few
bytes on the main stack as it prevents space being left for a later save
of FPU registers.
+ Added xSemaphoreGetMutexHolderFromISR().
+ Corrected use of portNVIC_PENDSVSET to portNVIC_PENDSVSET_BIT in MPU ports.
9 years ago
bdbf347c22
Remove clrex instruction from Cortex-M ports again as it is implicit in interrupt entry.
9 years ago
c296e2cff8
Improvements to the Cortex-M ports:
...
- Clear the SysTick current value register before starting the SysTick (only required if something uses SysTick before starting the scheduler).
- Ensure atomic operations are thread safe by executing clrex in the context switch.
9 years ago
2bd7884ace
Prepare for V9.0.0 release:
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+ Change version number from V9.0.0rc2 to V9.0.0.
9 years ago
0063b29cdf
Prepare for V9.0.0 release.
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+ Set flash wait states on MSP432 demos.
+ Remove use of obsolete IO library in PIC32 demos.
+ Remove obsolete item left on stack of first task to run in the Cortex-M0 ports.
+ Correct IA32 GCC vPortExitCritical() implementation when configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY.
9 years ago
ee9cd40b6d
Add GCC ARM Cortex-M4F MPU port.
...
Add RVDS ARM Cortex-M4F MPU port.
Increase the size of each buffer allocated to pbufs in the Microblaze lwIP demo to prevent pbufs chaining.
Use _start as the top of the stack for each Microblaze task, rather than NULL, as NULL was causing the Xilinx SDK to try and unwind the stack too far.
9 years ago
fedb98c5f6
Recreated MicroBlaze example using Vivado 2016.1 - the Microblaze project is still a work in progress - not yet fully functional.
9 years ago
324127837c
Update some more standard demos for use on 64-bit architectures.
...
Update the Xilinx Ultrascale+ Cortex-A53 (64-bit) and Cortex-R5 (32-bit) demos to use version 2016.1 of the SDK.
9 years ago
0721cf102a
Completely re-generate the Zynq 7000 demo using the 2016.1 SDK tools.
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Introduce configUSE_TASK_FPU_SUPPORT into the GCC Cortex-A9 port to allow tasks to have an FPU context by default.
Add MikroC Cortex-M4F port.
9 years ago
0b5906d404
Remove obsolete MPU demos.
...
Separate the MPU wrappers into their own file so they can be used from future MPU ports.
9 years ago
Richard Barry