c3c9c12ce2
Update the common demo death.c to use the updated macro name to give it a secure context.
6 years ago
ce576f3683
First Official Release of ARMV8M Support. This release removes Pre-Release from all the ARMv8M files licensees.
6 years ago
58ba10eee8
Update version number in readiness for V10.2.0 release.
6 years ago
55ad3861c5
Sync the Renesas port to AFR Git Repo
6 years ago
0de2a2758a
Fix definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE
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tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE was not correctly defined resulting in
dynamically allocated TCB not being freed when MPU was enabled. This commit fixes
the definition to ensure that dynamically allocated RAM (Stack and TCB) is freed
always.
6 years ago
2c88fb7fa1
Fix build failure when dynamic allocation is not enabled.
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When dynamic allocation is not enabled, vPortFree is not available. The current code used
vPortFree and this resulted in linker error. This commit removes the use of vPortFree when
dynamic allocation is not enabled.
6 years ago
6844bef74f
Replace the pdf RISC-V documentation with links to the documentation web pages.
6 years ago
b2b1b09ea5
Fix bug in core_cm3.c atomic macros.
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Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
6 years ago
3153131fa7
Add Dornerworks attribution to makefiles that build the Freedom Studio RISC-V project.
6 years ago
7e08fd6d07
Add makefiles that build the FreedomStudio project (provided by Dornerworks - thanks).
6 years ago
fb73829148
Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState().
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Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task.
Add a PDF of the RISC-V documentation into the repo as the web page is not yet live.
6 years ago
df5952f655
Add xTaskGetIdleRunTimeCounter() API function to return the run time stats counter for the idle task - useful for POSIX time implementations.
6 years ago
817783d75c
Copyright updates from Cadence.
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e1df894752
6 years ago
a4941ac5db
Update main.c() for the WIN32-MingW project so the trace recorder is initialized even when the simple blinky demo is used - otherwise the trace recorder causes an exception as it is used without first being initialized.
6 years ago
80df5cd517
Update the pin mux setup on the Vega board demo to enable the LED.
6 years ago
11d9c440b8
Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason).
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Add a project for the Vega board's RI5CY core.
6 years ago
e2af102c80
Re-org of RISC-V file structure and naming step 2.
6 years ago
818eeccc0c
Re-org of RISC-V file structure and naming step 1.
6 years ago
3474e750fa
Create folder to hold RISC-V chip specific extensions.
6 years ago
db750d0c82
Update RSIC-V port layer after testing saving and receiving of chip specific registers.
6 years ago
60b133b2c6
Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.
6 years ago
911a1de273
Correct accidental deletion in GenQTest.c.
6 years ago
d369110167
Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings.
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Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.
6 years ago
178fe4f143
Update the Freedom Studio RISC-V project so the gdbinit options are now specified on the command line.
6 years ago
e5daf23d75
Update Freedom Studio RISC-V demo for the latest GCC RISC-V port - not yet tested.
6 years ago
80f6f3e59b
Retarget Softconsole RISC-V demo from IGLOO2 to Renode as it can have more RAM and therefore have more test tasks running.
6 years ago
ce36928ea8
Rename directories in the RISC-V port.
6 years ago
2181c0375e
Backup Microsemi Renode project before adding a build configuration for the target hardware.
6 years ago
8d213b42f2
Add vTimerSetReloadMode() calls to the code coverage tests.
6 years ago
6edabbe7ea
Update the the MPU simulator project to exercise the timer API.
6 years ago
148f588f56
Remove "FromISR' functions from the list of functions that switch to a privileged mode as IRQs are privileged already.
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Add the vTimerSetReloadMode() API function.
6 years ago
8285ca6b5f
Update RISC-V_IGLOO2_Creative_SoftConsole demo to make use of new RISC-V porting layer structure and exercise some external interrupts - all tests currently passing in Renode.
6 years ago
101806906d
Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT.
6 years ago
7cc42b2ab6
Save changes to the RISC-V port layer before making changes necessary to support pulpino too:
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+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other.
+ Handle external interrupts (working with Renode emulator).
+ The _sp linker variable is now called __freertos_irq_stack_top.
6 years ago
866635d2ad
Microsemi RISC-V project:
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Reorganize project to separate Microsemi code into its own directory.
Add many more demo and tests.
6 years ago
6b37800ade
Backup checkin of MiFive demo running in ReNode emulator.
6 years ago
9a136a52df
Backup check in of the Microsemi IGLOO2 Creative Board RISC-V demo - still a work in progress.
6 years ago
4b9dd38d1c
Backup checking of the Freedom Studio RISC-V project - still a work in progress.
6 years ago
65f7a2dc19
Update RISC-V port to use a separate interrupt stack.
6 years ago
e85ea96f78
Some efficiency improvements in Risc-V port.
6 years ago
dc99300fa9
First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo.
6 years ago
d0ef322b13
Add kernel code to the RISC-V-Qemu-sifive_e-FreedomStudio demo.
6 years ago
f7102f2342
Add a starting point for a Freedom Studio Risc V project.
6 years ago
db64297487
Provide each Risc V task with an initial mstatus register value.
6 years ago
8cef339aec
Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress.
6 years ago
baee711cb6
Continue work on Risc V port.
6 years ago
74d0d16aab
Update xTaskRemoveFromEventList() so when tickless idle is used prvResetNextTaskUnblockTime() only gets called if the scheduler is not locked, as it would get called when the scheduler is unlocked in any case.
6 years ago
55ff89373a
Update the method used to detect if a timer is active. Previously the timer was deemed to be inactive if it was not referenced from a list. However, when a timer is updated it is temporarily removed from, then re-added to a list, so now the timer's active status is stored separately.
6 years ago
6fab2b9e0d
Add xTaskGetApplicationTaskTagFromISR(), which is an interrupt safe version of xTaskGetApplicationTaskTagFrom().
6 years ago
1af80854e6
Fix Xtensa project file and some documentation improvements.
6 years ago
Richard Barry
Gaurav Aggarwal