Commit Graph

32 Commits (a22d5ff5a57ca4e4e42d4157ed39ef5a21cca578)

Author SHA1 Message Date
Richard Barry 0cd79ad81d Change version numbers in preparation for V7.6.0 release. 11 years ago
Richard Barry b181a3af99 Ensure the definition of prvTaskExitError()does not result in a compiler warning in ports where its use can be overridden (GCC Cortex-M ports).
Remove duplicate save/restore of r14 in Cortex-M4F ports.
11 years ago
Richard Barry a12ea2d212 Update FreeRTOS version number to V7.5.3
Update FreeRTOS+CLI version number to V1.0.2
Update FreeRTOS+UDP version number to V1.0.1
11 years ago
Richard Barry 0c56f5018d Add some defensive programming in the default tickless mode in case the application supplied post tick hook takes a long time to complete. 11 years ago
Richard Barry aedf7824cb Introduce the prvTaskExitError() function for all ARM_CMn ports.
Introduce the configTASK_RETURN_ADDRESS macro for the GCC ARM_CMn ports.
Improve time slippage penalty when entering tickless mode is abandoned.
11 years ago
Richard Barry 2f754d9b0c Add additional critical section to the default tickless implementations.
Update version number for maintenance release.
12 years ago
Richard Barry 3cbe0a724d Update version number. 12 years ago
Richard Barry 679a3c670c Update the Cortex-M vPortValidateInterruptPriority() implementation to ensure compatibility with the STM32 standard peripheral library. 12 years ago
Richard Barry 7d6758ee1a Minor updates and change version number for V7.5.0 release. 12 years ago
Richard Barry 65704174c9 Add portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to the RX ports that use the Renesas compiler.
Add portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to the Cortex-A9 ports.
12 years ago
Richard Barry c4eef61d39 Added portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to Cortex-M3 and Cortex-M4F ports. 12 years ago
Richard Barry 0c0b54c175 Refine the default tickless idle implementation in the Cortex-M3 port layers. 12 years ago
Richard Barry a7c47131fa Remove portALIGNMENT_ASSERT_pxCurrentTCB() macro, which serves no purpose. 12 years ago
Richard Barry 686d190798 Convert some ports to use xTaskIncrementTick() in place of vTaskIncrementTick().
Move DSB instructions to before WFI instructions in line with ARM recommendations.
12 years ago
Richard Barry a03b171992 Fix compiler warning in psp_test.c when compiled with ARM compiler.
Add portYIELD_FROM_ISR() macros to Cortex-M ports.  The new macro just calls the exiting portEND_SWITCHING_ISR() macro.
Remove code from the MSVC port layer that was left over from a previous implementation and become obsolete.
12 years ago
Richard Barry 96ceae8edd Update version number ready to release the FAT file system demo. 12 years ago
Richard Barry f9918345e1 Update version numbers to V7.4.1. 12 years ago
Richard Barry 0527099b51 Add barrier instructions to the GCC CM3 ports. 12 years ago
Richard Barry a5d0e3f0c1 Prepare for V7.4.0 release. 12 years ago
Richard Barry 902f9e1a58 Update PIC32 demo application to remove reliance on PLIB functions.
Update the default low power implementation in all the Cortex-M port layers to add a small critical section.
12 years ago
Richard Barry ac78adae4b Added INCLUDE_xSemaphoreGetMutexHolder() default.
Changed eTaskStateGet() to eTaskGetState() and added #define to ensure backward compatibility.
Added configEXPECTED_IDLE_TIME_BEFORE_SLEEP definition - was previously hard coded to 2.
Slight change to the default CM3 tickless sleep function to allow the idle time to be set to zero in the pre-sleep processing macro.
Changed stack alignment for the FreeRTOS-MPU port to ensure it didn't trigger the assert() in the generic create function.
12 years ago
Richard Barry ba686260ca Make CM3/4 tick configuration a weak function to allow application writers to use an alternative tick source. 12 years ago
Richard Barry f5c52bdb1d Re-jig some of the new functions to correctly assign them public or private linkage, and remove some functions that were added in but never used. 12 years ago
Richard Barry f06a945444 Prepare for V7.3.0 release. 12 years ago
Richard Barry e03ab659f3 Add tickless idle support in Cortex-M ports.
Change CCS R4 directory name.
12 years ago
Richard Barry c403e974ee Update PIC32 port to make use of configUSE_PORT_OPTIMISED_TASK_SELECTION.
Make small modification in GCC CM3 port when configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 to remove compiler warning.
13 years ago
Richard Barry 87f663a461 Correct #if( configMAX_PRIORITIES >= 32 ) check performed when configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 to instead be #if( configMAX_PRIORITIES > 32 ). 13 years ago
Richard Barry 92f1699055 Added Cortex-M optimised code to the IAR, GCC and Keil Cortex-M port layers.
Tested and updated a few Cortex-M projects to use configUSE_PORT_OPTIMISED_TASK_SELECTION set to 1.
13 years ago
Richard Barry 0c7af1c2d3 Put comments in the code that give a reference to people who think that setting BASE_PRI to zero is the wrong thing to to in an ISR. 13 years ago
Richard Barry e0bab5981a Prepare for V7.2.0 release. 13 years ago
Richard Barry 73ad4387e2 Remove the remnants of the legacy trace functionality (since replaced with FreeRTOS+Trace).
Replaced the #error that traps configMAX_SYSCALL_INTERRUPT_PRIORITY being set to 0 with a configASSERT() for GCC Cortex-M3/4 ports as the #error does not work if configMAX_SYSCALL_INTERRUPT_PRIORITY includes any casting.  Not a problem for other compilers as they cannot have casting anyway as that would break the assembly code.
13 years ago
Richard Barry f508a5f653 Add FreeRTOS-Plus directory. 13 years ago