Commit Graph

137 Commits (96bad0f6c3de6e36b2a5ece64e830966c77561b6)

Author SHA1 Message Date
Richard Barry 85fb1cc024 + New feature added: Task notifications.
+ Optimise Cortex-M4F ports by inlining some critical section macros.
+ Original ports used a #define to set the path to portmacro.h - that method has been obsolete for years and now all the old definitions have been moved into a separate header files called deprecated_definitions.h.
+ Cortex-M port now check the active vector bits against 0xff when determining if a function is called from an interrupt - previously only a subset of the bits (0x1f) were checked.
+ Add in new standard demo/test files TaskNotify.c/h and include the files in the simulator demos.
+ Update trace recorder code, and some demos to use the new version (more to do).
+ Introduce uxTaskPriorityGetFromISR().
+ Minor typo corrections.
+ Update MingW simulator demo to match the MSVC simulator demo.
10 years ago
Richard Barry ca22607d14 Core kernel code:
Allow the stats formatting functions to be built in without stdio.h being included inside tasks.c.

Kernel port code:
- Slight change to the Cortex-A GIC-less port to move all non portable code to the application level.

SAMA5D4 demo project:
- Update the Atmel provided library to V1.1.
- Create a DDR build configuration.
- Ensure interrupts are all edge sensitive.
- Update the regtest code to use all 32 flop registers.
11 years ago
Richard Barry 9e66637bec Core kernel files:
+ Change how queues are allocated and deleted so only one pvPortMalloc() or vPortFree() is required in place of the previous 2.
+ Where the TCB is allocated in relation to the stack is now dependent on the stack growth direction.  The stack will not grow into the TCB.
+ Introduce the configAPPLICATION_ALLOCATED_HEAP constant to allow the application to provide the array used by heap_4.c as its heap.  This allows the application writer to use qualifiers on the array to, for example, force the memory into faster RAM.

Demo application:
+ Add demo for SAMA5D4 using IAR.
11 years ago
Richard Barry d55e7e77a2 Update version number to 8.1.2 after moving the defaulting of configUSE_PORT_OPTIMISED_TASK_SELECTION into individual port layers so it does not affect ports that do not support the definition. 11 years ago
Richard Barry a60ce58731 Update version number to 8.1.1 for patch release that re-enables mutexes to be given from an interrupt. 11 years ago
Richard Barry d33a14b5fb ***IMMINENT RELEASE NOTICE***
Update version numbers ready for FreeRTOS V8.1.0 release in about 10 days.
11 years ago
Richard Barry 52e687086c Demo application related:
+ Update the RZ IAR project so it targets the RZ RSK rather than custom hardware.
+ Update the RZ ARM/DS-5 project so it targets the RZ RSK rather than custom hardware.
+ Updated RX64M demos to use the new iodefine.h naming.

Cortex-A9 port related:
+ Update IAR, ARM and GCC Cortex-A9 port layers to include a 'task exit error' function which is called if a task attempts to incorrectly exit its implementing function.
+ Moved the instruction which switches into system mode out of the restore context macro, as it is only needed when starting the first task.

Core kernel files related:
+ Ensure there are no references to the mutexes held count when mutexes are excluded from the build.
11 years ago
Richard Barry 162448f06b General maintenance - changing comments and correcting spellings only. 11 years ago
Richard Barry 47f895cb34 Cortex-A5 IAR port:
- Removed SAMA5 specifics from the port layer, and instead call a generic ISR callback as per Cortex-A9 ports.
11 years ago
Richard Barry b2e739495a Cortex-A5 IAR port baseline prior to removing all SAMA5 specifics to make it generic.:
- Slight improvement to the save context macro.
- Remove some #warning remarks.
- Enable interrupts before calling the ISR handler rather than in the ISR handler.
11 years ago
Richard Barry 3a3d061cc5 Continue working on the GIC-less Cortex-A5 port for IAR:
- Add in the assert when a task attempts to exit its implementing function without deleting itself.
- Remove obsolete code from the context switch asm code (obsoleted by the fact that there is no mask register).
- Attempt to make code more generic by using definitions for additional register addresses.
11 years ago
Richard Barry 8ad9b75810 Rename ARM_CAx_No_GIC ARM_CA5_No_GIC and add FreeRTOSConfig setting to specify the number of registers in the FPU unit. 11 years ago
Richard Barry f4a1a7d577 Add new port layer for Cortex-A devices without the means to mask interrupt priorities. 11 years ago
Richard Barry 583b144bc3 Default the definition of portASSERT_IF_IN_ISR() to nothing if it is not defined.
Helper updates to allow a count of the number of mutexes held to be added.
Updates to the CCS Cortex-R4 implementation necessitated by a change in compiler semantics.
Update PIC32MX and MZ ports to assert if a non ISR safe function is called from an ISR.
11 years ago
Richard Barry 113220628f Add code to assert() if non ISR safe API function is called from ISR in IAR and GCC CM3 and CM4F ports - Keil and tasking to follow. 11 years ago
Richard Barry 0bb794301a Update version number ready for release. 11 years ago
Richard Barry 29a08b5e24 Update Cortex-A port layers to ensure the ICCRPR and ICCPMR registers are always accessed as 32-bit values. 11 years ago
Richard Barry e101e7e437 Update version number to V8.0.0 (without the release candidate number). 11 years ago
Richard Barry d12ec14160 Add configCLEAR_TICK_INTERRUPT() to the IAR and RVDS Cortex-A9 ports.
Replace LDMFD with POP instructions in IAR and RVDS Cortex-A9 ports.
Replace branch to address with indirect branch and exchange to address in register in the IAR and RVDS Cortex-A9 ports.
11 years ago
Richard Barry 6130fec60e Introduce xTimerPendFunctionCall().
Change INCLUDE_xTimerPendFunctionCallFromISR to INCLUDE_xTimerPendFunctionCall
Update event group trace macros to match the new trace recorder code.
Ensure parameter name consistency by renaming any occurrences of xBlockTime and xBlockTimeTicks to xTicksToWait.
Continue work on GCC/RL78 port - still a work in progress.
Adjust how the critical section was used in xQueueAddToSet.
11 years ago
Richard Barry d8c135e2dc Add extern 'C' to FreeRTOS.h.
Remove obsolete extern declaration of vTaskSwitchContext() from the MPX430X IAR portmacro.h (other older portmacro.h header files contain the same declaration).
11 years ago
Richard Barry a1b8079df1 Introduce configENABLE_BACKWARD_COMPATIBILITY to allow the #defines that provide backward compatibility with FreeRTOS version prior to V8 to be optionally omitted. 11 years ago
Richard Barry f01bf9fdc3 Add additional NOP after EINT instruction in MSP430 ports. 11 years ago
Richard Barry 1aaa80fba6 Map portTICK_RATE_MS to portTICK_PERIOD_MS. 11 years ago
Richard Barry a56d4b998c Minor tidy ups that don't effect code generation, plus:
When a task is unblocked the need for a context switch is only signalled if the unblocked task has a priority higher than the currently running task, instead of higher than or equal to the priority of the currently running task.
11 years ago
Richard Barry a8836b5c43 Change version numbers ready for V8.0.0 release candidate 1 tag. 11 years ago
Richard Barry 2aa19f1a14 Add xEventGroupClearBitsFromISR() and xEventGroupGetBitsFromISR() functions.
Move some types defines out of generic kernel headers into feature specific headers.
Convert the function prototype dypedefs to the new _t naming.
11 years ago
Richard Barry e95b482f56 Minor updates to demo projects to ensure correct building with V8 rc1. 11 years ago
Richard Barry 2b6eb1c5ab Revert some library files back to using standard types as they are not FreeRTOS files. 11 years ago
Richard Barry 3e20aa7d60 Replace standard types with stdint.h types.
Replace #define types with typedefs.
Rename all typedefs to have a _t extension.
Add #defines to automatically convert old FreeRTOS specific types to their new names (with the _t).
11 years ago
Richard Barry 4b2f9dad42 Force the SysTick clock bit to be set in Cortex-M3 and Cortex-M4F bits if configSYSTICK_CLOCK_HZ is not defined, otherwise leave the bit as it is found as the SysTick may use a divided clock. 11 years ago
Richard Barry 0d1e12522b Update Cortex-M3 and Cortex-M4F ports to allow the SysTick to be clocked at a different speed than the system clock (as is done in the recent STM32L demo. ).
Add additional asserts and isb instructions into the Cortex-M3 and Cortex-M4F ports.
11 years ago
Richard Barry 00ad1a0200 Multiple tidy up, documentation corrections and typo corrections highlighted by Tamas Kleiber's diligent review. 11 years ago
Richard Barry 0cd79ad81d Change version numbers in preparation for V7.6.0 release. 11 years ago
Richard Barry b181a3af99 Ensure the definition of prvTaskExitError()does not result in a compiler warning in ports where its use can be overridden (GCC Cortex-M ports).
Remove duplicate save/restore of r14 in Cortex-M4F ports.
11 years ago
Richard Barry dcd261bb8b Update the Keil and IAR CM0 port layers to match the changes made to the GCC version. 12 years ago
Richard Barry a12ea2d212 Update FreeRTOS version number to V7.5.3
Update FreeRTOS+CLI version number to V1.0.2
Update FreeRTOS+UDP version number to V1.0.1
12 years ago
Richard Barry 0c56f5018d Add some defensive programming in the default tickless mode in case the application supplied post tick hook takes a long time to complete. 12 years ago
Richard Barry aedf7824cb Introduce the prvTaskExitError() function for all ARM_CMn ports.
Introduce the configTASK_RETURN_ADDRESS macro for the GCC ARM_CMn ports.
Improve time slippage penalty when entering tickless mode is abandoned.
12 years ago
Richard Barry eaacbb099a Clear up a few compiler warnings.
Correct header comments in the UARTCommandConsole.c file used in the SmartFusion2 demo.
Exercise the new xQueueSpacesAvailable() function in the MSVC demo.
Add defaults for the new traceMALLOC and traceFREE trace macros.
Catch tasks trying to exit their functions in the Cortex-M0 ports.
Add additional comments to timers.c in response to a support forum question.
Initialise _impure_ptr prior to the first task being started.
Prior to V7.5.0 a yield pended in the tick hook would have occurred during the same tick interrupt.  Return pdTRUE from xTaskIncrementTick() if a yield is pending to revert to that behaviour.
12 years ago
Richard Barry 73606369c4 Make Cortex-M0 set/clear interrupt flag from ISR functions nestable.
Don't reset the stack location when starting the scheduler in Cortex-M0 ports as the vector offset register is not implemented and XMC1000 devices have their application vector address somewhere other than 0x00.
12 years ago
Richard Barry c40370e96a Fix a few typos and remove the "register" keyword. 12 years ago
Richard Barry 2f754d9b0c Add additional critical section to the default tickless implementations.
Update version number for maintenance release.
12 years ago
Richard Barry 3cbe0a724d Update version number. 12 years ago
Richard Barry 679a3c670c Update the Cortex-M vPortValidateInterruptPriority() implementation to ensure compatibility with the STM32 standard peripheral library. 12 years ago
Richard Barry 7d6758ee1a Minor updates and change version number for V7.5.0 release. 12 years ago
Richard Barry 7d1292ced2 Linting and MISRA checking 12 years ago
Richard Barry e5d9640863 Update RX ports to only include additional check on the existing IPL (so it is not lowered) if configASSERT() is defined. 12 years ago
Richard Barry ad8fa53043 Kernel optimisations. 12 years ago
Richard Barry 5d902f2b9c Complete additions of portASSERT_IF_INTERRUPT_PRIORITY_INVALID() for all RX compiler ports. 12 years ago
Richard Barry 65704174c9 Add portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to the RX ports that use the Renesas compiler.
Add portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to the Cortex-A9 ports.
12 years ago
Richard Barry 0f6b0d3a59 Enhance heap_4.c to prevent blocks accidentally being freed twice, or blocks that don't have a valid block link descriptor being freed.
Update the Cortex-A9 port to include asserts if an ISR safe FreeRTOS function is called from an interrupt that has a higher logical priority than configMAX_SYSCALL_INTERRUPT_PRIORITY (or whatever the CA9 equivalent is called), and also assert if the binary point is not set correctly.
12 years ago
Richard Barry c4eef61d39 Added portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to Cortex-M3 and Cortex-M4F ports. 12 years ago
Richard Barry 0c0b54c175 Refine the default tickless idle implementation in the Cortex-M3 port layers. 12 years ago
Richard Barry a7c47131fa Remove portALIGNMENT_ASSERT_pxCurrentTCB() macro, which serves no purpose. 12 years ago
Richard Barry 04dafed839 IAR ARM Cortex-A port layer. 12 years ago
Richard Barry 2fd431e971 Modify the GCC/AVR port to make use of the xTaskIncrementTick return value.
Add pre-processor directives in the dsPIC and PIC24 port layers that allows both port files to be included in the same project.
12 years ago
Richard Barry 62c0ae0926 Update port layers to make better use of the xTaskIncrementTick() return value. 12 years ago
Richard Barry c04b074707 Convert the remaining ports to use xTaskIncrementTick() in place of vTaskIncremenTick(). 12 years ago
Richard Barry f904d26957 Convert more ports to use xTaskIncrementTick() in place of vTaskIncrementTick(). 12 years ago
Richard Barry 15ec6c87f7 Convert mpre ports to use xTaskIncrementTick() in place of vTaskIncrementTick(). 12 years ago
Richard Barry 686d190798 Convert some ports to use xTaskIncrementTick() in place of vTaskIncrementTick().
Move DSB instructions to before WFI instructions in line with ARM recommendations.
12 years ago
Richard Barry a03b171992 Fix compiler warning in psp_test.c when compiled with ARM compiler.
Add portYIELD_FROM_ISR() macros to Cortex-M ports.  The new macro just calls the exiting portEND_SWITCHING_ISR() macro.
Remove code from the MSVC port layer that was left over from a previous implementation and become obsolete.
12 years ago
Richard Barry fb9662009a Update comments in Atmel Studio CreateProjectDirectoryStructure.bat files to remove references to replace references to Eclipse with references to Atmel Studio.
Update the tickless idle implementations that use up counters for tick interrupt generate to ensure they remain in low power mode for the desired time instead of one tick less than the desired time.
12 years ago
Richard Barry 96ceae8edd Update version number ready to release the FAT file system demo. 12 years ago
Richard Barry f9918345e1 Update version numbers to V7.4.1. 12 years ago
Richard Barry 0013028c7a Update yield code in RX600/IAR compiler port. 12 years ago
Richard Barry 74290b4425 Add RX100 IAR port layer. 12 years ago
Richard Barry 895ee2bb3e Add barrier instructions to IAR CM3 ports. 12 years ago
Richard Barry 3762630f27 RL78/IAR port - Allow the end user to define their own tick interrupt configuration by defining configSETUP_TIMER_INTERRUPT(). 12 years ago
Richard Barry caf1fbc899 Ensure IAR RL port layer works on devices using two different naming conventions for the interval timer registers. 12 years ago
Richard Barry 8c66fdbb8c Updated IAR RL78 port layer. 12 years ago
Richard Barry 17bba16fa6 Added YRDKRL78G14 build configuration to the IAR RL78 demo. 12 years ago
Richard Barry a5d0e3f0c1 Prepare for V7.4.0 release. 12 years ago
Richard Barry 902f9e1a58 Update PIC32 demo application to remove reliance on PLIB functions.
Update the default low power implementation in all the Cortex-M port layers to add a small critical section.
12 years ago
Richard Barry ac78adae4b Added INCLUDE_xSemaphoreGetMutexHolder() default.
Changed eTaskStateGet() to eTaskGetState() and added #define to ensure backward compatibility.
Added configEXPECTED_IDLE_TIME_BEFORE_SLEEP definition - was previously hard coded to 2.
Slight change to the default CM3 tickless sleep function to allow the idle time to be set to zero in the pre-sleep processing macro.
Changed stack alignment for the FreeRTOS-MPU port to ensure it didn't trigger the assert() in the generic create function.
12 years ago
Richard Barry 96f93690ce Add warning suppression to IAR header. 12 years ago
Richard Barry ba686260ca Make CM3/4 tick configuration a weak function to allow application writers to use an alternative tick source. 12 years ago
Richard Barry f5c52bdb1d Re-jig some of the new functions to correctly assign them public or private linkage, and remove some functions that were added in but never used. 13 years ago
Richard Barry f06a945444 Prepare for V7.3.0 release. 13 years ago
Richard Barry e03ab659f3 Add tickless idle support in Cortex-M ports.
Change CCS R4 directory name.
13 years ago
Richard Barry 87f663a461 Correct #if( configMAX_PRIORITIES >= 32 ) check performed when configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 to instead be #if( configMAX_PRIORITIES > 32 ). 13 years ago
Richard Barry 92f1699055 Added Cortex-M optimised code to the IAR, GCC and Keil Cortex-M port layers.
Tested and updated a few Cortex-M projects to use configUSE_PORT_OPTIMISED_TASK_SELECTION set to 1.
13 years ago
Richard Barry 0c7af1c2d3 Put comments in the code that give a reference to people who think that setting BASE_PRI to zero is the wrong thing to to in an ISR. 13 years ago
Richard Barry e0bab5981a Prepare for V7.2.0 release. 13 years ago
Richard Barry 73ad4387e2 Remove the remnants of the legacy trace functionality (since replaced with FreeRTOS+Trace).
Replaced the #error that traps configMAX_SYSCALL_INTERRUPT_PRIORITY being set to 0 with a configASSERT() for GCC Cortex-M3/4 ports as the #error does not work if configMAX_SYSCALL_INTERRUPT_PRIORITY includes any casting.  Not a problem for other compilers as they cannot have casting anyway as that would break the assembly code.
13 years ago
Richard Barry f508a5f653 Add FreeRTOS-Plus directory. 13 years ago