Commit Graph

170 Commits (911a1de27330d1faff9166b03ae0b8267c5777b0)

Author SHA1 Message Date
Richard Barry d369110167 Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings.
Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.
6 years ago
Richard Barry ce36928ea8 Rename directories in the RISC-V port. 6 years ago
Richard Barry 101806906d Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT. 6 years ago
Richard Barry 7cc42b2ab6 Save changes to the RISC-V port layer before making changes necessary to support pulpino too:
+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other.
+ Handle external interrupts (working with Renode emulator).
+ The _sp linker variable is now called __freertos_irq_stack_top.
6 years ago
Richard Barry 65f7a2dc19 Update RISC-V port to use a separate interrupt stack. 6 years ago
Richard Barry e85ea96f78 Some efficiency improvements in Risc-V port. 6 years ago
Richard Barry dc99300fa9 First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo. 6 years ago
Richard Barry db64297487 Provide each Risc V task with an initial mstatus register value. 6 years ago
Richard Barry 8cef339aec Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress. 6 years ago
Richard Barry baee711cb6 Continue work on Risc V port. 6 years ago
Richard Barry e3dc5e934b RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet. 6 years ago
Richard Barry 2bcb1ab02b Add trap handler to RISC-V port so there is no dependency on third party code. 6 years ago
Richard Barry 32f35e9130 RISC-V:
Added code to setup the timer interrupt - not tested yet.
Added the taskYIELD() implementation - so far just checked it generates an interrupt.
7 years ago
Richard Barry b11eb3a59c RISC-V work in progress:
+ Initialise task stack.
    + Successfully jump to start of first task.
7 years ago
Richard Barry 92ae8e7aff Update version numbers ready for release. 7 years ago
Richard Barry 3a1631fda3 Update copyright date ready for tagging V10.1.0. 7 years ago
Richard Barry fb9de58f56 Update version numbers in preparation for a new release. 7 years ago
Richard Barry f6cbf20019 Update RISC-V project to used official port stubs in place of third party port. 7 years ago
Richard Barry 3bfc32d444 Add stubs for official RISC-V RV32 port. 7 years ago
Richard Barry 5bebf10fa4 Minor updates to comments only. 7 years ago
Richard Barry 7ddb8b342d Microblaze port: Place critical section around XIntc_Enable() to protect read/modify/write operation performed inside the library. 7 years ago
Richard Barry 13651934be Roll up the minor changes checked into svn since V10.0.0 into new V10.0.1 ready for release. 7 years ago
Richard Barry cfc268814a Update to MIT licensed FreeRTOS V10.0.0 - see https://www.freertos.org/History.txt 7 years ago
Richard Barry 037abdddf2 Update TriCore port to work with latest GCC compiler. 8 years ago
Richard Barry 6eea3d8d4b Correct long time mis-spelled portINITIAL_EXEC_RETURN to portINITIAL_EXC_RETURN 8 years ago
Richard Barry b080f13543 Add more "memory" clobbers into the MPU ports to make them robust to more aggressive optimisation in newer GCC version. 8 years ago
Richard Barry 0f85ead175 Add more "memory" clobbers into asm code of GCC/ARM_CRx_No_GIC port to make it robust with higher optimisation in newer versions of GCC. 8 years ago
Richard Barry 0a7a0a79d6 Updates to prevent warnings when compiled with LLVM. 8 years ago
Richard Barry 464c2660ad Updates to the Cortex-M tickless idle code to reduce clock slippage.
Updates to prevent the vTaskSwitchContext() function being removed from GCC builds when link time optimisation is used.
8 years ago
Richard Barry b9fe24962e Add additional memory barriers into ARM GCC asm code to ensure no re-ordering across asm code as optimisers get more aggressive. 8 years ago
Richard Barry c3acc441ac Introduce vTaskInternalSetTimeOutState() which does not have a critical section, and add a critical section to the public version of the same. 8 years ago
Richard Barry 8d041c8e21 Update version number in preparation for maintenance release. 8 years ago
Richard Barry 992a3c8c71 Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to the 2016.4 versions.
Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
8 years ago
Richard Barry 6ffaa6f018 Correct alignment issue in GCC and RVDS Cortex-A9 port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
Update the Zynq demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
8 years ago
Richard Barry 75ffac21d7 Changes to core code and port layer:
+ Add configASSERT() into ARM Cortex-M ports to check the number of priority
      bit settings.
    + Clear the 'control' register before starting ARM Cortex-M4F ports in case
      the FPU is used before the scheduler is started.  This just saves a few
      bytes on the main stack as it prevents space being left for a later save
      of FPU registers.
    + Added xSemaphoreGetMutexHolderFromISR().
    + Corrected use of portNVIC_PENDSVSET to portNVIC_PENDSVSET_BIT in MPU ports.
9 years ago
Richard Barry bdbf347c22 Remove clrex instruction from Cortex-M ports again as it is implicit in interrupt entry. 9 years ago
Richard Barry c296e2cff8 Improvements to the Cortex-M ports:
- Clear the SysTick current value register before starting the SysTick (only required if something uses SysTick before starting the scheduler).
- Ensure atomic operations are thread safe by executing clrex in the context switch.
9 years ago
Richard Barry 2bd7884ace Prepare for V9.0.0 release:
+ Change version number from V9.0.0rc2 to V9.0.0.
9 years ago
Richard Barry 0063b29cdf Prepare for V9.0.0 release.
+ Set flash wait states on MSP432 demos.
+ Remove use of obsolete IO library in PIC32 demos.
+ Remove obsolete item left on stack of first task to run in the Cortex-M0 ports.
+ Correct IA32 GCC vPortExitCritical() implementation when configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY.
9 years ago
Richard Barry ee9cd40b6d Add GCC ARM Cortex-M4F MPU port.
Add RVDS ARM Cortex-M4F MPU port.
Increase the size of each buffer allocated to pbufs in the Microblaze lwIP demo to prevent pbufs chaining.
Use _start as the top of the stack for each Microblaze task, rather than NULL, as NULL was causing the Xilinx SDK to try and unwind the stack too far.
9 years ago
Richard Barry fedb98c5f6 Recreated MicroBlaze example using Vivado 2016.1 - the Microblaze project is still a work in progress - not yet fully functional. 9 years ago
Richard Barry 324127837c Update some more standard demos for use on 64-bit architectures.
Update the Xilinx Ultrascale+ Cortex-A53 (64-bit) and Cortex-R5 (32-bit) demos to use version 2016.1 of the SDK.
9 years ago
Richard Barry 0721cf102a Completely re-generate the Zynq 7000 demo using the 2016.1 SDK tools.
Introduce configUSE_TASK_FPU_SUPPORT into the GCC Cortex-A9 port to allow tasks to have an FPU context by default.
Add MikroC Cortex-M4F port.
9 years ago
Richard Barry 0b5906d404 Remove obsolete MPU demos.
Separate the MPU wrappers into their own file so they can be used from future MPU ports.
9 years ago
Richard Barry afd4b432f6 Improve coverage of the MPU API in the new MPU demo, fixing typos in the MPU port layer as they are found. 9 years ago
Richard Barry 345819d550 Update the GCC Cortex-A9 port to introduce a version of the IRQ handler that saves the FPU registers. 9 years ago
Richard Barry ac67c39be9 Update the MPU port so it supports all the public functions found in V9.0.0rc2. 9 years ago
Richard Barry 057b38ad23 Updates to support FreeRTOS MPU in FreeRTOS V9.0.0 - including a GCC project that runs in the Keil simulator to allow development and testing. 9 years ago
Richard Barry 255145bde1 xTaskGetTaskHandle() changed to xTaskGetHandle().
Tidy up CEC1302 demo.
Ensure bit 0 of the task address is clear when setting up stack of initial Cortex-M3/4/7 stacks (for strict compliance, although not practically necessary).
vTaskGetTaskInfo() changed to vTaskGetInfo() - with a macro added for backward compatibility.
9 years ago
Richard Barry f1725afbe5 Remove compiler warning by ensure prvInitialiseMutex() is not included if configUSE_MUTEXES is 0.
Reduce the number of xTaskCreateStatic() parameters by having the function return the task handle, rather than pass the task handle out using a parameter.  This is also consistent with other objectCreate() functions.
9 years ago