Exclude the entire croutine.c file when configUSE_CO_ROUTINES is 0.
New ports:
Added Cortex-M7 IAR and Keil port layers that include a minor errata workaround r0p1 Cortex-M7 devices.
Added Cortex-M4F port layer for CCS.
New demo applications:
Added demo application for STM32F7.
Added demo application for SAMv71.
+ Added mtCOVERAGE_TEST_DELAY() macro to facilitate getting better code coverage during testing.
+ Update prvNotifyQueueSetContainer() so it does not call xTaskRemoveFromEventList() if it is called from an interrupt, and the queue is locked.
Demo apps:
Added QueueSetPolling.c/h demo/test functions.
+ Added vTimerSetTimerID() to compliment vTimerGetTimerID(). Now the timer ID can be used as timer local storage.
+ Updated comments and added some additional assert() calls.
Win32 port:
+ Some changes to allow easier 64-bit builds
PIC24/dsPIC port:
+ Added NOP after disable interrupt instruction.
Add a "query heap" command to the standard sample CLI commands.
Remove casting from configMAX_PRIORITIES setting in Win32 simulator demos as it was preventing a clean build.
Source code changes.
General tidy up and addition of assert points.
+ Made xTaskNotifyGiveFromISR() its own function, rather than a macro that calls xTaskNotifyFromISR() (minor performance improvement).
+ GCC and Keil Cortex-M4F ports now use vPortRaiseBASEPRI() in place of ulPortRaiseBASEPRI() where the return value is not required (minor performance improvement).
Demo changes:
Change the [very basic] FreeRTOS+UDP SAM4E driver to use task notifications rather than a semaphore (execution time now 55% what it was in FreeRTOS V8.1.2!).
Robustness improvements to IntQueue.c standard demo task.h.
Added the latest standard demo tasks, reg test tasks and int q tasks to the SAM4E demo.
+ Do not attempt to free the stack of a deleted task if the stack was statically allocated.
+ Introduce configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES - which optionally writes known values into the list and list item data structures in order to assist with the detection of memory corruptions.
Microblase port:
+Change occurrences of #if XPAR_MICROBLAZE_0_USE_FPU == 1 to #if XPAR_MICROBLAZE_0_USE_FPU != 0 as the value can also be 2 or 3.
Demo app modifications:
+ Update Zynq project to use the 2014.4 tools and add in tests for the new task notification feature.
+ Update SAM4S project to include tests for the new task notification feature.
+ Fix a few compiler warnings.
+ Add TickType_t specific critical sections so critical sections are not used when accessing the tick count in cases where the access is atomic (32-bit tick count, 32-bit architecture).
+ Optimise Cortex-M4F ports by inlining some critical section macros.
+ Original ports used a #define to set the path to portmacro.h - that method has been obsolete for years and now all the old definitions have been moved into a separate header files called deprecated_definitions.h.
+ Cortex-M port now check the active vector bits against 0xff when determining if a function is called from an interrupt - previously only a subset of the bits (0x1f) were checked.
+ Add in new standard demo/test files TaskNotify.c/h and include the files in the simulator demos.
+ Update trace recorder code, and some demos to use the new version (more to do).
+ Introduce uxTaskPriorityGetFromISR().
+ Minor typo corrections.
+ Update MingW simulator demo to match the MSVC simulator demo.
Allow the stats formatting functions to be built in without stdio.h being included inside tasks.c.
Kernel port code:
- Slight change to the Cortex-A GIC-less port to move all non portable code to the application level.
SAMA5D4 demo project:
- Update the Atmel provided library to V1.1.
- Create a DDR build configuration.
- Ensure interrupts are all edge sensitive.
- Update the regtest code to use all 32 flop registers.
+ Change how queues are allocated and deleted so only one pvPortMalloc() or vPortFree() is required in place of the previous 2.
+ Where the TCB is allocated in relation to the stack is now dependent on the stack growth direction. The stack will not grow into the TCB.
+ Introduce the configAPPLICATION_ALLOCATED_HEAP constant to allow the application to provide the array used by heap_4.c as its heap. This allows the application writer to use qualifiers on the array to, for example, force the memory into faster RAM.
Demo application:
+ Add demo for SAMA5D4 using IAR.
+ Introduce xSemaphoreGenericGiveFromISR() as an optimisation when giving semaphores and mutexes from an interrupt.
Demo applications:
+ Update IntSemTest.c to provide more code coverage in xSemaphoreGenericGiveFromISR().
+ Ensure the MMU is turned on in the RZ IAR demo. It was already on in the RZ ARM demo.
- Re-introduce the ability to give a mutex from an ISR.
Common demo code:
- Add additional tests into the GenQTest files for priority inheritance and using a mutex from an ISR.
+ Update the RZ IAR project so it targets the RZ RSK rather than custom hardware.
+ Update the RZ ARM/DS-5 project so it targets the RZ RSK rather than custom hardware.
+ Updated RX64M demos to use the new iodefine.h naming.
Cortex-A9 port related:
+ Update IAR, ARM and GCC Cortex-A9 port layers to include a 'task exit error' function which is called if a task attempts to incorrectly exit its implementing function.
+ Moved the instruction which switches into system mode out of the restore context macro, as it is only needed when starting the first task.
Core kernel files related:
+ Ensure there are no references to the mutexes held count when mutexes are excluded from the build.
- Add additional tests to GenQTest.c to test the updated priority inheritance mechanism.
- Slightly increase some delays in recmutex.c to prevent it reporting false errors in high load test cases.
SAMA5D3 Xplained IAR demo:
- Remove space being allocated for stacks that are not used.
- Remove explicit enabling of interrupts in ISR handers as this is now done from the central ISR callback before the individual handers are invoked.
- Reduce both the allocated heap size and the stack allocated to each task.
- Enable I cache.
- Slight improvement to the save context macro.
- Remove some #warning remarks.
- Enable interrupts before calling the ISR handler rather than in the ISR handler.
- Add in the assert when a task attempts to exit its implementing function without deleting itself.
- Remove obsolete code from the context switch asm code (obsoleted by the fact that there is no mask register).
- Attempt to make code more generic by using definitions for additional register addresses.
- Add full interrupt nesting tests.
- Add additional critical section/context switching tests.
- Set interrupt priorities so everything can run at once without any software watchdog errors.
- Re-enable interrupts in each IRQ handler.
- Add in run-time stats.
Add additional asserts to the Keil CM3 and CM4F ports (other CM3/4 ports already updated).
Add the additional yield necessitated by the mutex held count to the case when configUSE_QUEUE_SETS is 0.
Remove some apparently obsolete code from xTaskPriorityDisinherit() (a task cannot be both blocked and giving bac a mutex at the same time].
Update the new "mutex held count" increment and decrement functions to allow mutexes to be created before the scheduler is started.
Helper updates to allow a count of the number of mutexes held to be added.
Updates to the CCS Cortex-R4 implementation necessitated by a change in compiler semantics.
Update PIC32MX and MZ ports to assert if a non ISR safe function is called from an ISR.
Richard Barry