Commit Graph

2938 Commits (3a413d1022a4ff60ffc9631877992ac08affcc21)
 

Author SHA1 Message Date
Sachin Parekh 8e3cf978c4 Xtensa_ESP32: Change _iram_end to _iram_text_end
xtensa_loadstore_handler.S uses _iram_end to prevent modification of IRAM
code. With the LoadStore exception handler in place, IRAM can also be
used for .bss and .data section. Hence the sanity check should be based
upon _iram_text_end and not _iram_end
5 years ago
RichardBarry e1b98f0b4b This change prevents tickless idle mode potentially sleeping for an extra tick in the corer case that a tick interrupt occurred between the scheduler being suspended and the expected idle time being checked for a second time (within the idle task) - as described by the sequence below. Th change updates eTaskConfirmSleepModeStatus() to specifically check if a tick is pending, and if so, abort entering sleep mode.
+ The idle task decides to enter sleep mode on the following line.
```
if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
```

+ The scheduler is suspended, preventing any context switches.

[Potentially a tick interrupt could occur here.  That could happen if other tasks executing consumed a lot of time since the above code line executed.  If a tick interrupt occurs here the interrupt will be entered but the interrupt will not do anything other than increment xPendedTicks.]

+ The expected idle time is checked again.  No context switches can occur now so the code will execute until the scheduler is unsuspended.  Assuming configEXPECTED_IDLE_TIME_BEFORE_SLEEP is set to a sensible value, a tick interrupt won't occur for some time.

+ portSUPPRESS_TICKS_AND_SLEEP() is called.

+ The default implementation of the tickless function calls eTaskConfirmSleep() - which prior to this change does not return eAbortSleep even though xPendedTicks is not 0, and after this change does return eAbortSleep.
5 years ago
Yuhui.Zheng 499e55a03c
Bring license in sync with FreeRTOS/FreeRTOS. (#20) 5 years ago
ribarry 078b400aff Updates vCoRoutineSchedule() so it returns without doing anything if if the co-routine internal data structures have not been initialised. The internal data structures are initialised when the first co-routine is created.
NOTE: Co-routines are a deprecated feature.  This change was made to close off an old ticket as the source control transitions from SourceForge to Github.
5 years ago
lundinc2 326d88f429
Added CONTRIBUTING (#18)
.md
5 years ago
AniruddhaKanhere c246922ea1
Small typo on L1287 (#14)
Added a missing ')'
5 years ago
Yuhui.Zheng 88e32327e9
version bump to v10.3.1 (#16)
* Verion bump from 10.3.0 to 10.3.1.
* version bump in task.h
* change history for 10.3.1.
5 years ago
Yuhui.Zheng 87beba4a4a
Removing License/license.txt and add LICENSE under root. (#12) 5 years ago
Yuhui.Zheng 08c9c9151a
Replacing readme.txt with README.md. (#11) 5 years ago
Yuhui.Zheng 10bbbcf0b9
Correct the xTimerCreate() documentation which said NULL was returned if the timer period was passed into the function as 0, whereas that is not the case. (#10)
Add a note to the documentation for both the xTimerCreate() and xTimerCreateStatic() functions that the timer period must be greater than 0.
5 years ago
Yuhui Zheng 210b1ffcc8 Re-sync with upstream and stripping away none kernel related. 5 years ago
Richard Barry 9c0c37ab9b Added back some TCP/IP stack port layer files. 5 years ago
Richard Barry 7cf721ccf7 5 years ago
Yuhui.Zheng 589dd9f149 Update version number in readiness for V10.3.0 release. Sync SVN with reviewed release candidate. 5 years ago
Yuhui.Zheng f988394e0d Fix spelling issues. 5 years ago
Richard Barry 28efb5449c Add "is inside interrupt" function to MPU ports.
Make clock setup functions weak symbols in ARMv8-M ports.
Update Cortex-M33 ports to use an interrupt mask in place of globally disabling interrupts, as per the other Cortex-M ports.
5 years ago
Richard Barry 8e5addee1e Update TCP to last release versions in preparation for kernel V10.3.0 release. 5 years ago
Richard Barry 7bea399061 Update libraries and sundry check-ins ready for the V10.3.0 kernel release. 5 years ago
Yuhui.Zheng d319bb0c71 ESP GCC port -- Added LoadStore Exception handlers.
https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/9 -- Handles LoadStoreErrorCause and LoadStoreAlignmentCause allowing to use 32-bit memory region (IRAM) as 8-bit or 16-bit memory region
5 years ago
Yuhui.Zheng 9fdfbf33e9 Sync FreeRTOS-Labs -CLI -TCP -Trace with the version in FreeRTOS-Plus.
Projects under FreeRTOS-Labs directory are in beta, developers updating projects please make sure you are using the correct version of -CLI -TCP -Trace. If you must edit -CLI -TCP and -Trace, please ensure the copies are synced.
5 years ago
Yuhui.Zheng ec6f3d77c3 Sync FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP with the version in GitHub at (23665258cabe49d5d68ba23968b6845a7c80eb34).
Notes: 
- header has version 2.2.0. 
- This sync did not bring in ./test directory, though we should. 
- New NetworkInterfaces are introduced by this merge.
- Keil compiler support. 
- FreeRTOS_IP.h new API xApplicationGetRandomNumber().
- FreeRTOS_IP_Private.h new eIPEvent_t eNetworkTxEvent. 
- FreeRTOS_Stream_Buffer.h removing static xStreamBufferIsEmpty() and xStreamBufferIsFull().
- FreeRTOSConfigDefaults.h provides default ipconfigDNS_RECEIVE_BLOCK_TIME_TICKS. 
- other type changes.
5 years ago
Yuhui.Zheng 0c1c85a9dd Removing RISC-V port under ThirdParty.
RISC-V ports for IAR and GCC can now be found under \FreeRTOS\Source\portable\GCC\RISC-V and \FreeRTOS\Source\portable\IAR\RISC-V.
5 years ago
Yuhui.Zheng 99e796eb01 Removing unnecessary ThirdParty ports -- Wiced_CY and nrf52840-dk.
For projects depending on either of these two ports, please update your projects according to below:
Wiced_CY -- Use GCC/ARM_CRx_No_GIC instead. 
nrf52840-dk -- Use GCC/ARM_CM7/r0p1 instead. Please note that, kernel port shall only take dependency on MCU core, not MCU peripherals. (Please take out RTC related from kernel port.) For low power feature (tickless) in FreeRTOS, please follow this page https://www.freertos.org/low-power-ARM-cortex-rtos.html. In case ARM_CM7/rop1 is missing any feature, reach out to us.
5 years ago
Richard Barry 4d4493e61a Remove the FreeRTOS-IoT-Libraries from FreeRTOS-Plus as it was an old copy with a newer copy in FreeRTOS-Labs. 5 years ago
Richard Barry 0d54d1c4dc Correct an err in queue.c introduced when previously updating behaviour when queue sets are used in combination with queue overwrites. 5 years ago
Yuhui.Zheng f5b5b2db04 Cleaning up LPC51U68 projects:
- user playable settings are all in FreeRTOSConfig.h.
- removed reference to IntQueue.h in main_full.c
- readme.txt wording.
5 years ago
Richard Barry 2415dc26b0 Introduce the portSOFTWARE_BARRIER macro which thus far is only used by the Win32 demo to hold execution up in case a simulated interrupt is executing simultaneously. That should never happen as all threads should execute on the same core, but we have had numerous reports that this and other Win32 port changes we have made fixed these issues - although we have not been able to replicate them ourselves. 5 years ago
Gaurav Aggarwal 18f87e8c33 Add MPU demo project for Nulceo-L152RE which is Coretx-M3. 5 years ago
Gaurav Aggarwal e058a65b16 Updates to CM3_MPU GCC port
- System calls are now only allowed from kernel code. This change can be turned on
  or off using configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY.
- MPU is disabled before reprogramming it and enabled afterwards to be compliant
  with ARM recommendations.
5 years ago
Richard Barry 42a0eaafdc Ensure both one-shot and auto-reload are written consistently with a hyphen in comments. 5 years ago
Richard Barry 9456992c1f Added uxTimerGetReloadMode() API function. 5 years ago
Gaurav Aggarwal c472c5b04f Add MPU demo project for LPC54018 board. 5 years ago
Yuhui.Zheng 0d95aca202 Introduce a port for T-HEAD CK802. A simple demo for T-HEAD CB2201 is also included. 5 years ago
Richard Barry d2914041f8 Update the GCC and IAR SiFive HiFive rev-b demos to use the new configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS constants in place of the deprecated configCLINT_BASE_ADDRESS constant.
Update the IAR RISC-V HiFive demo to use the latest IAR Embedded Workbench version.
5 years ago
Richard Barry 066e2bc7d2 Replace portasmHAS_CLINT with configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions in the IAR RISC-V port - portasmHAS_CLIT will still work by deriving the new definitions from the old. 5 years ago
Richard Barry 75b81a1fab Work in progress update of LPC51U68 MCUXpresso project to rearrange the folder structure and names. 5 years ago
Richard Barry fbb23055cd Replace portasmHAS_CLINT with configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions in the GCC RISC-V port - portasmHAS_CLIT will still work by deriving the new definitions from the old. 5 years ago
Richard Barry eaf9318df8 Add Source/portable/ARMClang file that directs users to the GCC port if they which to use the ARMClang compiler. 5 years ago
Richard Barry 881958514b If tickless idle mode is in use then ensure prvResetNextTaskUnblockTime() is called after a task is unblocked due to a bit being set in an event group. This allows the MCU to re-enter sleep mode at the earliest possible time (rather than waiting until the timeout that would occur had the task not being unblocked be the event group) and matches a similar change made for queues and derivative objects (semaphores, etc.) some time ago. 5 years ago
Richard Barry 853856e8cc Correct #error text in multiple fat file system files. 5 years ago
Richard Barry 9e86cb95a7 Add xPortIsInsideInterrupt() to the IAR ARMv7-M ports. 5 years ago
Richard Barry be3561ed53 Added xTaskAbortDelayFromISR() and ulTaskNotifyValueClear() API functions.
Added tests for xTaskAbortDelayFromISR() into Demo/Common/Minimal/AbortDelay.c.
Added tests for ulTaskNotifyValueClear() into Demo/Common/Minimal/TaskNotify.c.
5 years ago
Richard Barry 0a29d350b1 Renamed RISC-V_RV32_SiFive_HiFive1_IAR directory to RISC-V_RV32_SiFive_HiFive1-RevB_IAR as it targets the RevB hardware. 5 years ago
Richard Barry 62b413627a Minor updates to comment block for xTaskCheckForTimeOut(). 5 years ago
Richard Barry dfc1bf8ec3 Rename RISC-V_RV32_SiFive_HiFive1-FreedomStudio directory to RISC-V_RV32_SiFive_HiFive1-RevB-FreedomStudio as it targets Rev B of the hardware. 5 years ago
Richard Barry 4b943b35e0 Update RISCC-V-RV32-SiFive_HiFive1_FreedomStudio project to latest tools and metal library versions. 5 years ago
Gaurav Aggarwal cfa83672ef Rename STM32Cube to GCC for STM32L4 Discovery projects as GCC is
the compiler used.
5 years ago
Gaurav Aggarwal 474182ab39 Make vSetupTimerInterrupt weak in the RVDS M4 MPU port to give the
application writer a chance to override this function. This gives
the application write ability to use a different timer.
5 years ago
Gaurav Aggarwal 22dd9a55ab Update documentation of xTaskCheckForTimeOut function to reflect the
intended use of this API.
5 years ago
Yuhui.Zheng 8f0eaf274c - Updates to projects due to demo folder name change. (IAR source file paths and assembler path were fixed. Keil source file paths were fixed.)
- Added back power static library for GCC and IAR. (Power management related interface definitions are in drivers/fsl_power.h. power.c is empty due to "implementation is in header file and power library")
- Note for GCC link: the command used for linking is `arm-none-eabi-gcc -nostdlib -L<additional lib search path> -Xlinker ... -o "CORTEX_M0+_LPC51U68_LPCXpresso.axf" <all *.o> -lpower`. Per GCC doc, static library name in file system is libpower.a.
5 years ago