Commit Graph

95 Commits (2d958d3d2c983ec03c1bd066e2a0957e5982ebe5)

Author SHA1 Message Date
Richard Barry 2d958d3d2c Set ARM byte alignment to 8. 16 years ago
Richard Barry 4640196beb Add CM3 MPU port. 16 years ago
Richard Barry ed06a0400a Update to V5.4.2. See http://www.freertos.org/History.txt . 16 years ago
Richard Barry d2a9f9624b Rename Nios2 to NiosII. 16 years ago
Richard Barry 5d6acacd7a Correct spelling error in comment only. 16 years ago
Richard Barry 6358344ea1 Added new Nios2 port layer. 16 years ago
Richard Barry 3a883a776c Update to V5.4.1 16 years ago
Richard Barry f312118bf9 Ensure LPC1768 demos are correct prior to V5.4.0 release. 16 years ago
Richard Barry fdcc3676cd Update version number. 16 years ago
Richard Barry e36ece8d42 Add support for double precision floating point. 16 years ago
Richard Barry 09f991277e Add PPC440 port layer code. 16 years ago
Richard Barry 7818ed5a97 Prepare for V5.3.1 release. 16 years ago
Richard Barry 8f26ec2474 Replaced asm statements with __asm for building with CrossWorks V2. 16 years ago
Richard Barry 4bf5521db6 Prepare for V5.3.0 release. 16 years ago
Richard Barry 2f40ad7393 Ready for V5.2.0 release. 16 years ago
Richard Barry 52ba0e651e Update to V5.1.2. 16 years ago
Richard Barry d28eda8634 Ready for V5.1.1 release. 16 years ago
Richard Barry 758b1c7c59 Update ready for V5.1.0 release. 17 years ago
Richard Barry de519dd34e Update to allow low power mode to be used with the RTOS. 17 years ago
Richard Barry 799cccac42 Use the low force register. 17 years ago
Richard Barry 130e2f2c0a Prepare for V5.0.4 release. 17 years ago
Richard Barry 1d0cf84e80 Change the default vector used for context switching. 17 years ago
Richard Barry 3b34009b75 Tidy up. 17 years ago
Richard Barry 223bd9c75f BUG FIX: Changed
*(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;
to
*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
17 years ago
Richard Barry aeea09e21e Minor changes only. 17 years ago
Richard Barry 6eec108bdd Ensure a yield cannot be pended simultaneously with a critical section being entered. 17 years ago
Richard Barry f68aab980d Interrupt nesting and cache support added. 17 years ago
Richard Barry 431d1c009d Update to allow interrupt nesting (not yet complete). 17 years ago
Richard Barry 181889d6b1 Basic demo up and running. 17 years ago
Richard Barry 4953c7d030 First task starting. 17 years ago
Richard Barry 35be76b9b7 Added function stubs. 17 years ago
Richard Barry 216fcb10c9 17 years ago
Richard Barry 5d60a388e0 17 years ago
Richard Barry 1c3c04f121 Prepare for V2 port. 17 years ago
Richard Barry 16b6baf10c Update to V5.0.3. 17 years ago
Richard Barry 32592e1385 Improve efficiency even further. Introduce the configMAX_SYSCALL_INTERRUPT_PRIORITY feature. 17 years ago
Richard Barry 90064444af Update to V5.0.2 17 years ago
Richard Barry eb9d172082 Remove compiler warnings. 17 years ago
Richard Barry b9b3e521f7 Bug fix - allocate 2 extra words at the bottom of the task stack to account for the back chain and saved LR. 17 years ago
Richard Barry 45fceb4bdd Update to include the option of saving/restoring the floating point context. 17 years ago
Richard Barry 019ab1b908 Remove inline keyword. 17 years ago
Richard Barry b08411ec5a Correct timer calculation. 17 years ago
Richard Barry e939542f32 Update to V5.0.0. 17 years ago
Richard Barry a6053582fc Update the sys tick to be more efficient. 17 years ago
Richard Barry 24cb048892 Ensure the first task starts with interrupts enabled. 17 years ago
Richard Barry 7ed94acdff Corrected SysTick interval calculation. 17 years ago
Richard Barry d1b9463e29 Changes required to build with the latest Xilinx tools. 17 years ago
Richard Barry 9596b04eff Small mods, and update file headers. 17 years ago
Richard Barry 527fb6a907 Update version numbers to V4.8.0 17 years ago
Richard Barry 5024d47769 17 years ago