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pull/4/head
Richard Barry 17 years ago
parent 3f2375c020
commit 4953c7d030
5 changed files with 88 additions and 471 deletions
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52
Source/portable/GCC/ColdFire_V2/mcf5xxx.S
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@ -1,52 +0,0 @@
/*
* File: mcf5xxx.s
* Purpose: Lowest level routines for all ColdFire processors.
*
* Notes:
*
* Function copied from mcf5xxx.S provided by FreeScale.
*/
.global french_cheese
.text
/********************************************************************/
/*
* This routines changes the IPL to the value passed into the routine.
* It also returns the old IPL value back.
* Calling convention from C:
* old_ipl = asm_set_ipl(new_ipl);
* For the Diab Data C compiler, it passes return value thru D0.
* Note that only the least significant three bits of the passed
* value are used.
*/
portSET_IPL:
link A6,#-8
movem.l D6-D7,(SP)
move.w SR,D7 /* current sr */
move.l D7,D0 /* prepare return value */
andi.l #0x0700,D0 /* mask out IPL */
lsr.l #8,D0 /* IPL */
move.l 8(A6),D6 /* get argument */
andi.l #0x07,D6 /* least significant three bits */
lsl.l #8,D6 /* move over to make mask */
andi.l #0x0000F8FF,D7 /* zero out current IPL */
or.l D6,D7 /* place new IPL in sr */
move.w D7,SR
movem.l (SP),D6-D7
lea 8(SP),SP
unlk A6
rts
/********************************************************************/
.end

402
Source/portable/GCC/ColdFire_V2/mcf5xxx_lo.S
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@ -1,402 +0,0 @@
/*
* File: mcf5xxx.s
* Purpose: Lowest level routines for all ColdFire processors.
*
* Notes:
*
* File provided by FreeScale.
*/
.global french_cheese
.text
/********************************************************************
* This routine is the lowest-level exception handler.
*/
/*
asm_exception_handler:
_asm_exception_handler:
lea -16(SP),SP
movem.l D0-D1/A0-A1,(SP)
lea 16(SP),A1
move.l A1,-(SP)
jsr mcf5xxx_exception_handler
lea 4(SP),SP
movem.l (SP),D0-D1/A0-A1
lea 16(SP),SP
rte
/********************************************************************/
/*
* This routines changes the IPL to the value passed into the routine.
* It also returns the old IPL value back.
* Calling convention from C:
* old_ipl = asm_set_ipl(new_ipl);
* For the Diab Data C compiler, it passes return value thru D0.
* Note that only the least significant three bits of the passed
* value are used.
*/
french_cheese:
link A6,#-8
movem.l D6-D7,(SP)
move.w SR,D7 /* current sr */
move.l D7,D0 /* prepare return value */
andi.l #0x0700,D0 /* mask out IPL */
lsr.l #8,D0 /* IPL */
move.l 8(A6),D6 /* get argument */
andi.l #0x07,D6 /* least significant three bits */
lsl.l #8,D6 /* move over to make mask */
andi.l #0x0000F8FF,D7 /* zero out current IPL */
or.l D6,D7 /* place new IPL in sr */
move.w D7,SR
movem.l (SP),D6-D7
lea 8(SP),SP
unlk A6
rts
/********************************************************************/
.end
#if 0
/*
* File: mcf5xxx.s
* Purpose: Lowest level routines for all ColdFire processors.
*
* Notes:
*
*/
#define mcf5xxx_exception_handler _mcf5xxx_exception_handler
.extern mcf5xxx_exception_handler
//.global asm_exception_handler
//.global _asm_exception_handler
.global asm_set_ipl
.global _asm_set_ipl
.global mcf5xxx_exe_wdebug
.global _mcf5xxx_exe_wdebug
//.global mcf5xxx_wr_cacr
//.global _mcf5xxx_wr_cacr
.global mcf5xxx_wr_asid
.global _mcf5xxx_wr_asid
.global mcf5xxx_wr_acr0
.global _mcf5xxx_wr_acr0
.global mcf5xxx_wr_acr1
.global _mcf5xxx_wr_acr1
.global mcf5xxx_wr_acr2
.global _mcf5xxx_wr_acr2
.global mcf5xxx_wr_acr3
.global _mcf5xxx_wr_acr3
.global mcf5xxx_wr_mmubar
.global _mcf5xxx_wr_mmubar
.global mcf5xxx_wr_other_a7
.global _mcf5xxx_wr_other_a7
// .global mcf5xxx_wr_vbr
// .global _mcf5xxx_wr_vbr
.global mcf5xxx_wr_macsr
.global _mcf5xxx_wr_macsr
.global mcf5xxx_wr_mask
.global _mcf5xxx_wr_mask
.global mcf5xxx_wr_acc0
.global _mcf5xxx_wr_acc0
.global mcf5xxx_wr_accext01
.global _mcf5xxx_wr_accext01
.global mcf5xxx_wr_accext23
.global _mcf5xxx_wr_accext23
.global mcf5xxx_wr_acc1
.global _mcf5xxx_wr_acc1
.global mcf5xxx_wr_acc2
.global _mcf5xxx_wr_acc2
.global mcf5xxx_wr_acc3
.global _mcf5xxx_wr_acc3
.global mcf5xxx_wr_sr
.global _mcf5xxx_wr_sr
.global mcf5xxx_wr_pc
.global _mcf5xxx_wr_pc
.global mcf5xxx_wr_rombar0
.global _mcf5xxx_wr_rombar0
.global mcf5xxx_wr_rombar1
.global _mcf5xxx_wr_rombar1
.global mcf5xxx_wr_rambar0
.global _mcf5xxx_wr_rambar0
.global mcf5xxx_wr_rambar1
.global _mcf5xxx_wr_rambar1
.global mcf5xxx_wr_mpcr
.global _mcf5xxx_wr_mpcr
.global mcf5xxx_wr_secmbar
.global _mcf5xxx_wr_secmbar
.global mcf5xxx_wr_mbar
.global _mcf5xxx_wr_mbar
.text
/********************************************************************
* This routine is the lowest-level exception handler.
*/
/*
asm_exception_handler:
_asm_exception_handler:
lea -16(SP),SP
movem.l D0-D1/A0-A1,(SP)
lea 16(SP),A1
move.l A1,-(SP)
jsr mcf5xxx_exception_handler
lea 4(SP),SP
movem.l (SP),D0-D1/A0-A1
lea 16(SP),SP
rte
/********************************************************************/
/*
* This routines changes the IPL to the value passed into the routine.
* It also returns the old IPL value back.
* Calling convention from C:
* old_ipl = asm_set_ipl(new_ipl);
* For the Diab Data C compiler, it passes return value thru D0.
* Note that only the least significant three bits of the passed
* value are used.
*/
asm_set_ipl:
_asm_set_ipl:
link A6,#-8
movem.l D6-D7,(SP)
move.w SR,D7 /* current sr */
move.l D7,D0 /* prepare return value */
andi.l #0x0700,D0 /* mask out IPL */
lsr.l #8,D0 /* IPL */
move.l 8(A6),D6 /* get argument */
andi.l #0x07,D6 /* least significant three bits */
lsl.l #8,D6 /* move over to make mask */
andi.l #0x0000F8FF,D7 /* zero out current IPL */
or.l D6,D7 /* place new IPL in sr */
move.w D7,SR
movem.l (SP),D6-D7
lea 8(SP),SP
unlk A6
rts
/********************************************************************/
/*
* These routines execute special ColdFire instructions
*/
mcf5xxx_exe_wdebug:
_mcf5xxx_exe_wdebug:
move.l 4(sp),a0
wdebug.l (a0)
rts
/********************************************************************/
/*
* These routines write to the special purpose registers in the ColdFire
* core. Since these registers are write-only in the supervisor model,
* no corresponding read routines exist.
*/
mcf5xxx_wr_sr:
_mcf5xxx_wr_sr:
move.l 4(SP),D0
move.w D0,SR
rts
/*
mcf5xxx_wr_cacr:
_mcf5xxx_wr_cacr:
move.l 4(SP),D0
.long 0x4e7b0002 /* movec d0,cacr */
/*
nop
rts
*/
mcf5xxx_wr_asid:
_mcf5xxx_wr_asid:
move.l 4(SP),D0
.long 0x4e7b0003 /* movec d0,asid */
nop
rts
mcf5xxx_wr_acr0:
_mcf5xxx_wr_acr0:
move.l 4(SP),D0
.long 0x4e7b0004 /* movec d0,ACR0 */
nop
rts
mcf5xxx_wr_acr1:
_mcf5xxx_wr_acr1:
move.l 4(SP),D0
.long 0x4e7b0005 /* movec d0,ACR1 */
nop
rts
mcf5xxx_wr_acr2:
_mcf5xxx_wr_acr2:
move.l 4(SP),D0
.long 0x4e7b0006 /* movec d0,ACR2 */
nop
rts
mcf5xxx_wr_acr3:
_mcf5xxx_wr_acr3:
move.l 4(SP),D0
.long 0x4e7b0007 /* movec d0,ACR3 */
nop
rts
mcf5xxx_wr_mmubar:
_mcf5xxx_wr_mmubar:
move.l 4(SP),D0
.long 0x4e7b0008 /* movec d0,MBAR */
nop
rts
mcf5xxx_wr_other_a7:
_mcf5xxx_wr_other_a7:
move.l 4(SP),D0
.long 0x4e7b0800 /* movec d0,OTHER_A7 */
nop
rts
/*
mcf5xxx_wr_vbr:
_mcf5xxx_wr_vbr:
move.l 4(SP),D0
.long 0x4e7b0801 /* movec d0,VBR */
/*
nop
rts
*/
mcf5xxx_wr_macsr:
_mcf5xxx_wr_macsr:
move.l 4(SP),D0
.long 0x4e7b0804 /* movec d0,MACSR */
nop
rts
mcf5xxx_wr_mask:
_mcf5xxx_wr_mask:
move.l 4(SP),D0
.long 0x4e7b0805 /* movec d0,MASK */
nop
rts
mcf5xxx_wr_acc0:
_mcf5xxx_wr_acc0:
move.l 4(SP),D0
.long 0x4e7b0806 /* movec d0,ACC0 */
nop
rts
mcf5xxx_wr_accext01:
_mcf5xxx_wr_accext01:
move.l 4(SP),D0
.long 0x4e7b0807 /* movec d0,ACCEXT01 */
nop
rts
mcf5xxx_wr_accext23:
_mcf5xxx_wr_accext23:
move.l 4(SP),D0
.long 0x4e7b0808 /* movec d0,ACCEXT23 */
nop
rts
mcf5xxx_wr_acc1:
_mcf5xxx_wr_acc1:
move.l 4(SP),D0
.long 0x4e7b0809 /* movec d0,ACC1 */
nop
rts
mcf5xxx_wr_acc2:
_mcf5xxx_wr_acc2:
move.l 4(SP),D0
.long 0x4e7b080A /* movec d0,ACC2 */
nop
rts
mcf5xxx_wr_acc3:
_mcf5xxx_wr_acc3:
move.l 4(SP),D0
.long 0x4e7b080B /* movec d0,ACC3 */
nop
rts
mcf5xxx_wr_pc:
_mcf5xxx_wr_pc:
move.l 4(SP),D0
.long 0x4e7b080F /* movec d0,PC */
nop
rts
mcf5xxx_wr_rombar0:
_mcf5xxx_wr_rombar0:
move.l 4(SP),D0
.long 0x4e7b0C00 /* movec d0,ROMBAR0 */
nop
rts
mcf5xxx_wr_rombar1:
_mcf5xxx_wr_rombar1:
move.l 4(SP),D0
.long 0x4e7b0C01 /* movec d0,ROMBAR1 */
nop
rts
mcf5xxx_wr_rambar0:
_mcf5xxx_wr_rambar0:
move.l 4(SP),D0
.long 0x4e7b0C04 /* movec d0,RAMBAR0 */
nop
rts
mcf5xxx_wr_rambar1:
_mcf5xxx_wr_rambar1:
move.l 4(SP),D0
.long 0x4e7b0C05 /* movec d0,RAMBAR1 */
nop
rts
mcf5xxx_wr_mpcr:
_mcf5xxx_wr_mpcr:
move.l 4(SP),D0
.long 0x4e7b0C0C /* movec d0,MPCR */
nop
rts
mcf5xxx_wr_secmbar:
_mcf5xxx_wr_secmbar:
move.l 4(SP),D0
.long 0x4e7b0C0E /* movec d0,MBAR1 */
nop
rts
mcf5xxx_wr_mbar:
_mcf5xxx_wr_mbar:
move.l 4(SP),D0
.long 0x4e7b0C0F /* movec d0,MBAR0 */
nop
rts
/********************************************************************/
.end
#endif

76
Source/portable/GCC/ColdFire_V2/port.c
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@ -52,18 +52,92 @@
#include "FreeRTOS.h"
#include "task.h"
#define portINITIAL_FORMAT_VECTOR ( ( portSTACK_TYPE ) 0x4000 )
/* Supervisor mode set. */
#define portINITIAL_STATUS_REGISTER ( ( portSTACK_TYPE ) 0x2000)
static unsigned portLONG ulCriticalNesting = 0x9999UL;
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
return NULL;
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters;
pxTopOfStack--;
*pxTopOfStack = (portSTACK_TYPE) 0xDEADBEEF;
pxTopOfStack--;
/* Exception stack frame starts with the return address. */
*pxTopOfStack = ( portSTACK_TYPE ) pxCode;
pxTopOfStack--;
*pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x0; /*FP*/
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xA5A5A5A5;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xA4A4A4A4;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xA3A3A3A3;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xA2A2A2A2;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xA1A1A1A1;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xA0A0A0A0;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xD7D7D7D7;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xD6D6D6D6;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xD5D5D5D5;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xD4D4D4D4;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xD3D3D3D3;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xD2D2D2D2;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xD1D1D1D1;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xD0D0D0D0;
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortStartScheduler( void )
{
ulCriticalNesting = 0UL;
vApplicationSetupInterrupts();
asm volatile(
"move.l pxCurrentTCB, %sp \n\t"\
"move.l (%sp), %sp \n\t"\
"movem.l (%sp), %d0-%fp \n\t"\
"lea.l %sp@(60), %sp \n\t"\
"rte "
);
return pdFALSE;
}
/*-----------------------------------------------------------*/

4
Source/portable/GCC/ColdFire_V2/portasm.S
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@ -8,7 +8,7 @@
* Function copied from mcf5xxx.S provided by FreeScale.
*/
.global french_cheese
.global ulPortSetIPL
.text
@ -23,7 +23,7 @@
* value are used.
*/
portSET_IPL:
ulPortSetIPL:
link A6,#-8
movem.l D6-D7,(SP)

25
Source/portable/GCC/ColdFire_V2/portmacro.h
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@ -19,7 +19,7 @@
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
@ -37,28 +37,25 @@
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
/* System include files */
#include <plib.h>
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------
* Port specific definitions.
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
@ -88,15 +85,15 @@ extern "C" {
/* Hardware specifics. */
#define portBYTE_ALIGNMENT 4
#define portSTACK_GROWTH -4
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
#define portDISABLE_INTERRUPTS()
#define portENABLE_INTERRUPTS()
unsigned portLONG ulPortSetIPL( unsigned portLONG );
#define portDISABLE_INTERRUPTS() ulPortSetIPL( configKERNEL_INTERRUPT_PRIORITY )
#define portENABLE_INTERRUPTS() ulPortSetIPL( 0 )
extern void vTaskEnterCritical( void );
extern void vTaskExitCritical( void );
extern void vPortEnterCritical( void );
extern void vPortExitCritical( void );
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()

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