#include "xil_types.h"
@@ -51,3 +51,4 @@ __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
errno = EIO;
return (-1);
}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/_sbrk.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/_sbrk.c
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/_sbrk.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/_sbrk.c
index bcec069c8..2a069ec06 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/_sbrk.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/_sbrk.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/abort.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/abort.c
similarity index 96%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/abort.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/abort.c
index 122c25bbd..e8988c048 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/abort.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/abort.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/asm_vectors.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/asm_vectors.S
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/asm_vectors.S
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/asm_vectors.S
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/boot.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/boot.S
similarity index 86%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/boot.S
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/boot.S
index 992b65efe..ed2d09843 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/boot.S
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/boot.S
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -34,8 +34,12 @@
* @file boot.S
*
* This file contains the initial startup code for the Cortex A53 processor
-* Currently the processor starts at EL3 and boot code, startup and main
-* code will run on secure EL3.
+* It checks the current exception level and if it matches with selected
+* exception level, then only it initializes the required system registers and
+* executes the code further, otherwise it will loop busy loop around error.
+* If the selected exception level is EL3, execution of the processor has to
+* be in EL3. If the selected exception level is EL1 non-secure, execution of
+* the processor can be EL2 or EL1.
*
*
*
@@ -43,7 +47,8 @@
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
-* 5.00 pkp 5/21/14 Initial version
+* 5.00 pkp 05/21/14 Initial version
+* 6.00 pkp 07/25/16 Program the counter frequency
*
* @note
*
@@ -52,6 +57,7 @@
******************************************************************************/
#include "xparameters.h"
+#include "bspconfig.h"
.globl MMUTableL0
.globl MMUTableL1
@@ -65,7 +71,6 @@
.global __el0_stack
.global _vector_table
-
.set EL3_stack, __el3_stack
.set EL2_stack, __el2_stack
.set EL1_stack, __el1_stack
@@ -80,6 +85,10 @@
.set vector_base, _vector_table
.set rvbar_base, 0xFD5C0040
+.set counterfreq, XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
+.set MODE_EL1, 0x5
+.set DAIF_BIT, 0x1C0
+
.section .boot,"ax"
@@ -122,7 +131,7 @@ _boot:
//Which core am I
// ----------------
mrs x0, MPIDR_EL1
- and x0, x0, #0xFF //Mask off to leave Aff0
+ and x0, x0, #0xFF //Mask off to leave Aff0
cbz x0, OKToRun //If core 0, run the primary init code
EndlessLoop0:
wfi
@@ -151,12 +160,10 @@ OKToRun:
ldr x2,=EL3_stack
mov sp,x2
-
/* Disable trapping of CPTR_EL3 accesses or use of Adv.SIMD/FPU*/
mov x0, #0 // Clear all trap bits
msr CPTR_EL3, x0
-
/* Configure SCR_EL3 */
mov w1, #0 //; Initial value of register is unknown
orr w1, w1, #(1 << 11) //; Set ST bit (Secure EL1 can access CNTPS_TVAL_EL1, CNTPS_CTL_EL1 & CNTPS_CVAL_EL1)
@@ -170,11 +177,13 @@ OKToRun:
mrs x0, S3_1_C11_C0_2 // register L2CTLR_EL1
orr x0, x0, #(1<<22)
msr S3_1_C11_C0_2, x0
-
/*configure cpu auxiliary control register EL1 */
ldr x0,=0x80CA000 // L1 Data prefetch control - 5, Enable device split throttle, 2 independent data prefetch streams
msr S3_1_C15_C2_0, x0 //CPUACTLR_EL1
+ /* program the counter frequency */
+ ldr x0,=counterfreq
+ msr CNTFRQ_EL0, x0
/*Enable hardware coherency between cores*/
mrs x0, S3_1_c15_c2_1 //Read EL1 CPU Extended Control Register
@@ -188,9 +197,8 @@ OKToRun:
dsb sy
isb
- ldr x1, =L0Table //; Get address of level 0 for TTBR0_EL1
- msr TTBR0_EL3, x1 //; Set TTBR0_EL3 (NOTE: There is no TTBR1 at EL1)
-
+ ldr x1, =L0Table //; Get address of level 0 for TTBR0_EL3
+ msr TTBR0_EL3, x1 //; Set TTBR0_EL3
/**********************************************
* Set up memory attributes
@@ -204,19 +212,19 @@ OKToRun:
ldr x1, =0x000000BB0400FF44
msr MAIR_EL3, x1
- /**********************************************
- * Set up TCR_EL3
- * Physical Address Size PS = 010 -> 40bits 1TB
- * Granual Size TG0 = 00 -> 4KB
- * size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40)
- ***************************************************/
- ldr x1,=0x80823518
- msr TCR_EL3, x1
- isb
+ /**********************************************
+ * Set up TCR_EL3
+ * Physical Address Size PS = 010 -> 40bits 1TB
+ * Granual Size TG0 = 00 -> 4KB
+ * size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40)
+ ***************************************************/
+ ldr x1,=0x80823518
+ msr TCR_EL3, x1
+ isb
/* Enable SError Exception for asynchronous abort */
mrs x1,DAIF
- bic x1,x1,#(0x1<<8)
+ bic x1,x1,#(0x1<<8)
msr DAIF,x1
/* Configure SCTLR_EL3 */
@@ -229,11 +237,10 @@ OKToRun:
dsb sy
isb
- bl _startup //jump to start
+ b _startup //jump to start
loop: b loop
-
invalidate_dcaches:
dmb ISH
@@ -283,4 +290,4 @@ invalidateCaches_next_level:
invalidateCaches_end:
ret
-.end
+.end
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/bspconfig.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/bspconfig.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/bspconfig.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/bspconfig.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/changelog.txt b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/changelog.txt
similarity index 77%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/changelog.txt
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/changelog.txt
index ad9c771e1..f663af134 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/changelog.txt
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/changelog.txt
@@ -321,4 +321,82 @@
* the fault log to avoid intervention for lock-step mode and cortexr5/
* _exit.c to enable the dbg_lpd_reset once the fault log is disabled
* to fix CR#947335
+ * 5.5 pkp 04/11/16 Modified cortexr5/boot.S to enable comparators for non-JTAG bootmode
+ * in lock-step to avoid resetting the debug logic which restricts the
+ * access for debugger and removed enabling back of debug modules in
+ * cortexr5/_exit.c
+ * 5.5 pkp 04/13/16 Modified cortexa9/gcc/read.c to return correct number of bytes when
+ * read buffer is filled and removed the redundant NULL checking for
+ * buffer to simplify the code
+ * 5.5 pkp 04/13/16 Modified cortexa53/64bit/gcc/read.c and cortexa53/32bit/gcc/read.c
+ * to return correct number of bytes when read buffer is filled and
+ * removed the redundant NULL checking for buffer to simplify the code
+ * 5.5 pkp 04/13/16 Modified cortexr5/gcc/read.c to return correct number of bytes when
+ * read buffer is filled and removed the redundant NULL checking for
+ * buffer to simplify the code
+ * 5.5 pkp 04/13/16 Modified cortexa53/64bit/xpseudo_asm_gcc.h to add volatile to asm
+ * instruction macros to disable certain optimizations which may move
+ * code out of loops if optimizers believe that the code will always
+ * return the same result or discard asm statements if optimizers
+ * determine there is no need for the output variables
+ * 5.5 pkp 04/13/16 Modified cortexa53/64bit/xtime_l.c to add XTime_StartTimer which
+ * starts the timer if it is disabled and modified XTime_GetTime to
+ * enable the timer if it is not enabled. Also modified cortexa53/64bit/
+ * sleep.c and cortexa53/64bit/usleep.c to enable the timer if it is
+ * disabled and read the counter value directly from register instead
+ * of using XTime_GetTime for optimization
+ * 5.5 pkp 04/13/16 Modified cortexa53/32bit/xtime_l.c to add XTime_StartTimer which
+ * starts the timer if it is disabled and modified XTime_GetTime to
+ * enable the timer if it is not enabled. Also modified cortexa53/32bit/
+ * sleep.c and cortexa53/32bit/usleep.c to enable the timer if it is
+ * disabled and read the counter value directly from register instead
+ * of using XTime_GetTime for optimization
+ * 5.5 pkp 04/13/16 Modified cortexa53/32bit/xil_cache.c and cortexa53/64bit/xil_cache.c
+ * to update the Xil_DCacheInvalidate, Xil_DCacheInvalidateLine and
+ * Xil_DCacheInvalidateRange functions description for proper
+ * explaination to fix CR#949801
+ * 5.5 asa 04/20/16 Added missing macros for hibernate and suspend in Microblaze BSP
+ * file mb_interface.h. This fixes the CR#949503.
+ * 5.5 asa 04/29/16 Fix for CR#951080. Updated cache APIs for HW designs where cache
+ * memory is not included for MicroBlaze.
+ * 5.5 pkp 05/06/16 Modified the cortexa9/xil_exception.h to update the macros
+ * Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ * the issue of lr being corrupted to resolve CR#950468
+ * 5.5 pkp 05/06/16 Modified the cortexr5/xil_exception.h to update the macros
+ * Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ * the issue of lr being corrupted to resolve CR#950468
+ * 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
+ * 6.0 pkp 06/27/16 Updated cortexr5/mpu.c to move the code related to Init_MPU to .boot
+ * section since it is part of boot process to fix CR#949555
+ * hk 07/12/16 Correct masks for IOU SLCR GEM registers
+ * 6.0 pkp 07/25/16 Program the counter frequency in boot code for CortexA53
+ * 6.0 asa 08/03/16 Updated sleep_common function in microblaze_sleep.c to improve the
+ * the accuracy of MB sleep functionality. This fixes the CR#954191.
+ * 6.0 mus 08/03/16 Restructured the BSP to avoid code duplication across all BSPs.
+ * Source code directories specific to ARM processor's are moved to src/arm
+ * directory(i.e. src/cortexa53,src/cortexa9 and src/cortexr5 moved to src/arm/cortexa53,
+ * src/arm/cortexa9 and src/arm/cortexr5 respectively).Files xil_printf.c,xil_printf.h,
+ * print.c,xil_io.c and xil_io.h are consolidated across all BSPs into common file each and
+ * consolidated files are kept at src/common directory.Files putnum.c,vectors.c,vectors.h,
+ * xil_exception.c and xil_exception.h are consolidated across all ARM BSPs
+ * into common file each and consolidated files are kept at src/arm/common directory.
+ * GCC source files related to file operations are consolidated and kept
+ * at src/arm/common/gcc directory.
+ * All io interfacing functions (i.e. All variants of xil_out, xil_in )
+ * are made as static inline and implementation is kept in consolidated common/xil_io.h,
+ * xil_io.h must be included as a header file to access io interfacing functions.
+ * Added undefined exception handler for A53 32 bit and R5 processor
+ * 6.0 mus 08/11/16 Updated xtime_l.c in R5 BSP to remove implementation of XTime_SetTime API, since
+ * TTC counter value register is read only.
+ * 6.0 asa 08/15/16 Modified the signatures for functions sleep and usleep. This fixes
+ * the CR#956899.
+ * 6.0 mus 08/18/16 Defined ARMA53_32 flag in cortexa53/32bit/xparameters_ps.h and ARMR5 flag
+ * in cortexr5/xparameters_ps.h
+ * 6.0 mus 08/18/16 Added support for the the Zynq 7000s devices
+ * 6.0 mus 08/18/16 Removed unused variables from xil_printf.c and xplatform_info.c
+ * 6.0 mus 08/19/16 Modified xil_io.h to remove __LITTLE_ENDIAN__ flag check for all ARM processors
+ * 6.1 mus 11/03/16 Added APIs handle_stdin_parameter and handle_stdout_parameter in standalone tcl.
+ * ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for
+ * these APIs and modifications are done on top of it to handle stdout/stdin
+ * parameters for design which doesnt have UART.It fixes CR#953681
*****************************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/close.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/close.c
similarity index 95%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/close.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/close.c
index e42a1ff36..dbbe0d4fd 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/close.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/close.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -29,6 +29,7 @@
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
@@ -45,3 +46,4 @@ __attribute__((weak)) s32 _close(s32 fd)
(void)fd;
return (0);
}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/config.make b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/config.make
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/config.make
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/config.make
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/errno.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/errno.c
similarity index 96%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/errno.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/errno.c
index daaa1212d..df0218e86 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/errno.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/errno.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/fcntl.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/fcntl.c
similarity index 93%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/fcntl.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/fcntl.c
index 4c5de40fd..e58221a14 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/fcntl.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/fcntl.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -37,7 +37,7 @@
* fcntl -- Manipulate a file descriptor.
* We don't have a filesystem, so we do nothing.
*/
-__attribute__((weak)) s32 fcntl (s32 fd, s32 cmd, s32 arg)
+__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg)
{
(void)fd;
(void)cmd;
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/fstat.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/fstat.c
similarity index 96%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/fstat.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/fstat.c
index 6271cfa84..c5a31f31b 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/fstat.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/fstat.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/getpid.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/getpid.c
similarity index 96%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/getpid.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/getpid.c
index c2a84cb7f..d02df5ce2 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/getpid.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/getpid.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/inbyte.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/inbyte.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/inbyte.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/inbyte.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu0_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu0_cfg.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu0_cfg.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu0_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu1_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu1_cfg.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu1_cfg.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu1_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu2_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu2_cfg.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu2_cfg.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu2_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu3_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu3_cfg.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu3_cfg.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu3_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu4_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu4_cfg.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu4_cfg.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu4_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu5_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu5_cfg.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu5_cfg.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu5_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr_secure.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr_secure.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr_secure.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_cfg.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_cfg.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_sink.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_sink.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_sink.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_sink.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xiou_secure_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xiou_secure_slcr.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xiou_secure_slcr.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xiou_secure_slcr.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xiou_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xiou_slcr.h
similarity index 77%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xiou_slcr.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xiou_slcr.h
index d81d178d3..c53954c97 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xiou_slcr.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xiou_slcr.h
@@ -2769,85 +2769,85 @@ extern "C" {
#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_MASK 0x00300000UL
#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_DEFVAL 0x0UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 18UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00040000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 17UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00020000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 16UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00010000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 15UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00008000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 13UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00002000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 12UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00001000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 11UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000800UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 10UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000400UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 8UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00000100UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 7UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00000080UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 6UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000040UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 5UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000020UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 3UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00000008UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 2UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00000004UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000002UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 0UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000001UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 18UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00040000UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL
+
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 17UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00020000UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL
+
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 16UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00010000UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL
+
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 15UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00008000UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL
+
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 13UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00002000UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL
+
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 12UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00001000UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL
+
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 11UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000800UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL
+
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 10UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000400UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL
+
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 8UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00000100UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL
+
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 7UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00000080UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL
+
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 6UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000040UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL
+
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 5UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000020UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL
+
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 3UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00000008UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL
+
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 2UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00000004UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL
+
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 1UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000002UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL
+
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 0UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000001UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL
/**
* Register: XiouSlcrSdioClkCtrl
@@ -2881,15 +2881,15 @@ extern "C" {
#define XIOU_SLCR_CTRL_REG_SD ( ( XIOU_SLCR_BASEADDR ) + 0x00000310UL )
#define XIOU_SLCR_CTRL_REG_SD_RSTVAL 0x00000000UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT 15UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH 1UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK 0x00008000UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL 0x0UL
+#define XIOU_SLCR_CTRL_REG_SD1_XSDPS_EMMC_SEL_SHIFT 15UL
+#define XIOU_SLCR_CTRL_REG_SD1_XSDPS_EMMC_SEL_WIDTH 1UL
+#define XIOU_SLCR_CTRL_REG_SD1_XSDPS_EMMC_SEL_MASK 0x00008000UL
+#define XIOU_SLCR_CTRL_REG_SD1_XSDPS_EMMC_SEL_DEFVAL 0x0UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT 0UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH 1UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK 0x00000001UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL 0x0UL
+#define XIOU_SLCR_CTRL_REG_SD0_XSDPS_EMMC_SEL_SHIFT 0UL
+#define XIOU_SLCR_CTRL_REG_SD0_XSDPS_EMMC_SEL_WIDTH 1UL
+#define XIOU_SLCR_CTRL_REG_SD0_XSDPS_EMMC_SEL_MASK 0x00000001UL
+#define XIOU_SLCR_CTRL_REG_SD0_XSDPS_EMMC_SEL_DEFVAL 0x0UL
/**
* Register: XiouSlcrSdItapdly
@@ -2897,35 +2897,35 @@ extern "C" {
#define XIOU_SLCR_SD_ITAPDLY ( ( XIOU_SLCR_BASEADDR ) + 0x00000314UL )
#define XIOU_SLCR_SD_ITAPDLY_RSTVAL 0x00000000UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT 25UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH 1UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK 0x02000000UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL 0x0UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT 25UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH 1UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPCHGWIN_MASK 0x02000000UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT 24UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH 1UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK 0x01000000UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL 0x0UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT 24UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH 1UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYENA_MASK 0x01000000UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT 16UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH 8UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK 0x00ff0000UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL 0x0UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT 16UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH 8UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYSEL_MASK 0x00ff0000UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT 9UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH 1UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK 0x00000200UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL 0x0UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT 9UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH 1UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPCHGWIN_MASK 0x00000200UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT 8UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH 1UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK 0x00000100UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL 0x0UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT 8UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH 1UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYENA_MASK 0x00000100UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT 0UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH 8UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK 0x000000ffUL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL 0x0UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT 0UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH 8UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYSEL_MASK 0x000000ffUL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL 0x0UL
/**
* Register: XiouSlcrSdOtapdlysel
@@ -2933,25 +2933,25 @@ extern "C" {
#define XIOU_SLCR_SD_OTAPDLYSEL ( ( XIOU_SLCR_BASEADDR ) + 0x00000318UL )
#define XIOU_SLCR_SD_OTAPDLYSEL_RSTVAL 0x00000000UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT 22UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH 1UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK 0x00400000UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL 0x0UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT 22UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH 1UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK 0x00400000UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT 16UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH 6UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK 0x003f0000UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL 0x0UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_SHIFT 16UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_WIDTH 6UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_MASK 0x003f0000UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT 6UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH 1UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK 0x00000040UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL 0x0UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT 6UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH 1UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK 0x00000040UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT 0UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH 6UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK 0x0000003fUL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL 0x0UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_SHIFT 0UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_WIDTH 6UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_MASK 0x0000003fUL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_DEFVAL 0x0UL
/**
* Register: XiouSlcrSdCfgReg1
@@ -2959,35 +2959,35 @@ extern "C" {
#define XIOU_SLCR_SD_CFG_REG1 ( ( XIOU_SLCR_BASEADDR ) + 0x0000031CUL )
#define XIOU_SLCR_SD_CFG_REG1_RSTVAL 0x32403240UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT 23UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH 8UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK 0x7f800000UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL 0x64UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_BASECLK_SHIFT 23UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_BASECLK_WIDTH 8UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_BASECLK_MASK 0x7f800000UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_BASECLK_DEFVAL 0x64UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT 17UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH 6UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK 0x007e0000UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL 0x20UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT 17UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH 6UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_TUNIGCOUNT_MASK 0x007e0000UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL 0x20UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT 16UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK 0x00010000UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL 0x0UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT 16UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_ASYNCWKPENA_MASK 0x00010000UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT 7UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH 8UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK 0x00007f80UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL 0x64UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_BASECLK_SHIFT 7UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_BASECLK_WIDTH 8UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_BASECLK_MASK 0x00007f80UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_BASECLK_DEFVAL 0x64UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT 1UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH 6UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK 0x0000007eUL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL 0x20UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT 1UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH 6UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_TUNIGCOUNT_MASK 0x0000007eUL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL 0x20UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT 0UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK 0x00000001UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL 0x0UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT 0UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_ASYNCWKPENA_MASK 0x00000001UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL 0x0UL
/**
* Register: XiouSlcrSdCfgReg2
@@ -2995,125 +2995,125 @@ extern "C" {
#define XIOU_SLCR_SD_CFG_REG2 ( ( XIOU_SLCR_BASEADDR ) + 0x00000320UL )
#define XIOU_SLCR_SD_CFG_REG2_RSTVAL 0x0ffc0ffcUL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT 28UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH 2UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK 0x30000000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL 0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT 27UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK 0x08000000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT 26UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK 0x04000000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT 25UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK 0x02000000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT 24UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK 0x01000000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT 23UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK 0x00800000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT 22UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK 0x00400000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT 21UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK 0x00200000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT 20UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK 0x00100000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT 19UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK 0x00080000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT 18UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK 0x00040000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT 16UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH 2UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK 0x00030000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL 0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT 12UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH 2UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK 0x00003000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL 0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT 11UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK 0x00000800UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT 10UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK 0x00000400UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT 9UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK 0x00000200UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT 8UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK 0x00000100UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT 7UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK 0x00000080UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT 6UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK 0x00000040UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT 5UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK 0x00000020UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT 4UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK 0x00000010UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT 3UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK 0x00000008UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT 2UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK 0x00000004UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT 0UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH 2UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK 0x00000003UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL 0x0UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SLOTTYPE_SHIFT 28UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SLOTTYPE_WIDTH 2UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SLOTTYPE_MASK 0x30000000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL 0x0UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ASYCINTR_SHIFT 27UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ASYCINTR_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ASYCINTR_MASK 0x08000000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ASYCINTR_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_64BIT_SHIFT 26UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_64BIT_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_64BIT_MASK 0x04000000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_64BIT_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_1P8V_SHIFT 25UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_1P8V_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_1P8V_MASK 0x02000000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_1P8V_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P0V_SHIFT 24UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P0V_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P0V_MASK 0x01000000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P0V_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P3V_SHIFT 23UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P3V_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P3V_MASK 0x00800000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P3V_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SUSPRES_SHIFT 22UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SUSPRES_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SUSPRES_MASK 0x00400000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SUSPRES_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SDMA_SHIFT 21UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SDMA_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SDMA_MASK 0x00200000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SDMA_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_HIGHSPEED_SHIFT 20UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_HIGHSPEED_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_HIGHSPEED_MASK 0x00100000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ADMA2_SHIFT 19UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ADMA2_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ADMA2_MASK 0x00080000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ADMA2_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_8BIT_SHIFT 18UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_8BIT_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_8BIT_MASK 0x00040000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_8BIT_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_MAXBLK_SHIFT 16UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_MAXBLK_WIDTH 2UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_MAXBLK_MASK 0x00030000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_MAXBLK_DEFVAL 0x0UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SLOTTYPE_SHIFT 12UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SLOTTYPE_WIDTH 2UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SLOTTYPE_MASK 0x00003000UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL 0x0UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ASYCINTR_SHIFT 11UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ASYCINTR_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ASYCINTR_MASK 0x00000800UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ASYCINTR_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_64BIT_SHIFT 10UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_64BIT_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_64BIT_MASK 0x00000400UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_64BIT_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_1P8V_SHIFT 9UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_1P8V_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_1P8V_MASK 0x00000200UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_1P8V_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P0V_SHIFT 8UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P0V_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P0V_MASK 0x00000100UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P0V_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P3V_SHIFT 7UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P3V_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P3V_MASK 0x00000080UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P3V_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SUSPRES_SHIFT 6UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SUSPRES_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SUSPRES_MASK 0x00000040UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SUSPRES_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SDMA_SHIFT 5UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SDMA_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SDMA_MASK 0x00000020UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SDMA_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_HIGHSPEED_SHIFT 4UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_HIGHSPEED_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_HIGHSPEED_MASK 0x00000010UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ADMA2_SHIFT 3UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ADMA2_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ADMA2_MASK 0x00000008UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ADMA2_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_8BIT_SHIFT 2UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_8BIT_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_8BIT_MASK 0x00000004UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_8BIT_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_MAXBLK_SHIFT 0UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_MAXBLK_WIDTH 2UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_MAXBLK_MASK 0x00000003UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_MAXBLK_DEFVAL 0x0UL
/**
* Register: XiouSlcrSdCfgReg3
@@ -3121,85 +3121,85 @@ extern "C" {
#define XIOU_SLCR_SD_CFG_REG3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000324UL )
#define XIOU_SLCR_SD_CFG_REG3_RSTVAL 0x06070607UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT 26UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK 0x04000000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT 22UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH 4UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK 0x03c00000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL 0x8UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT 21UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK 0x00200000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL 0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT 20UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK 0x00100000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL 0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT 19UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK 0x00080000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL 0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT 18UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK 0x00040000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT 17UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK 0x00020000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT 16UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK 0x00010000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT 10UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK 0x00000400UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT 6UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH 4UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK 0x000003c0UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL 0x8UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT 5UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK 0x00000020UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL 0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT 4UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK 0x00000010UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL 0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT 3UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK 0x00000008UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL 0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT 2UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK 0x00000004UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT 1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK 0x00000002UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL 0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT 0UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH 1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK 0x00000001UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL 0x1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT 26UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_TUNINGSDR50_MASK 0x04000000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_RETUNETMR_SHIFT 22UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_RETUNETMR_WIDTH 4UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_RETUNETMR_MASK 0x03c00000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_RETUNETMR_DEFVAL 0x8UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDRIVER_SHIFT 21UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDRIVER_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDRIVER_MASK 0x00200000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDRIVER_DEFVAL 0x0UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_CDRIVER_SHIFT 20UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_CDRIVER_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_CDRIVER_MASK 0x00100000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_CDRIVER_DEFVAL 0x0UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_ADRIVER_SHIFT 19UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_ADRIVER_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_ADRIVER_MASK 0x00080000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_ADRIVER_DEFVAL 0x0UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDR50_SHIFT 18UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDR50_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDR50_MASK 0x00040000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDR50_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR104_SHIFT 17UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR104_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR104_MASK 0x00020000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR104_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR50_SHIFT 16UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR50_WIDTH 1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR50_MASK 0x00010000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR50_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT 10UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_TUNINGSDR50_MASK 0x00000400UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_RETUNETMR_SHIFT 6UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_RETUNETMR_WIDTH 4UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_RETUNETMR_MASK 0x000003c0UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_RETUNETMR_DEFVAL 0x8UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDRIVER_SHIFT 5UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDRIVER_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDRIVER_MASK 0x00000020UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDRIVER_DEFVAL 0x0UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_CDRIVER_SHIFT 4UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_CDRIVER_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_CDRIVER_MASK 0x00000010UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_CDRIVER_DEFVAL 0x0UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_ADRIVER_SHIFT 3UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_ADRIVER_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_ADRIVER_MASK 0x00000008UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_ADRIVER_DEFVAL 0x0UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDR50_SHIFT 2UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDR50_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDR50_MASK 0x00000004UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDR50_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR104_SHIFT 1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR104_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR104_MASK 0x00000002UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR104_DEFVAL 0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR50_SHIFT 0UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR50_WIDTH 1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR50_MASK 0x00000001UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR50_DEFVAL 0x1UL
/**
* Register: XiouSlcrSdInitpreset
@@ -3207,15 +3207,15 @@ extern "C" {
#define XIOU_SLCR_SD_INITPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000328UL )
#define XIOU_SLCR_SD_INITPRESET_RSTVAL 0x01000100UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT 16UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH 13UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK 0x1fff0000UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL 0x100UL
+#define XIOU_SLCR_SD1_INITPRESET_XSDPS_SHIFT 16UL
+#define XIOU_SLCR_SD1_INITPRESET_XSDPS_WIDTH 13UL
+#define XIOU_SLCR_SD1_INITPRESET_XSDPS_MASK 0x1fff0000UL
+#define XIOU_SLCR_SD1_INITPRESET_XSDPS_DEFVAL 0x100UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT 0UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH 13UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK 0x00001fffUL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL 0x100UL
+#define XIOU_SLCR_SD0_INITPRESET_XSDPS_SHIFT 0UL
+#define XIOU_SLCR_SD0_INITPRESET_XSDPS_WIDTH 13UL
+#define XIOU_SLCR_SD0_INITPRESET_XSDPS_MASK 0x00001fffUL
+#define XIOU_SLCR_SD0_INITPRESET_XSDPS_DEFVAL 0x100UL
/**
* Register: XiouSlcrSdDsppreset
@@ -3223,15 +3223,15 @@ extern "C" {
#define XIOU_SLCR_SD_DSPPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x0000032CUL )
#define XIOU_SLCR_SD_DSPPRESET_RSTVAL 0x00040004UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT 16UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH 13UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK 0x1fff0000UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL 0x4UL
+#define XIOU_SLCR_SD1_DSPPRESET_XSDPS_SHIFT 16UL
+#define XIOU_SLCR_SD1_DSPPRESET_XSDPS_WIDTH 13UL
+#define XIOU_SLCR_SD1_DSPPRESET_XSDPS_MASK 0x1fff0000UL
+#define XIOU_SLCR_SD1_DSPPRESET_XSDPS_DEFVAL 0x4UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT 0UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH 13UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK 0x00001fffUL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL 0x4UL
+#define XIOU_SLCR_SD0_DSPPRESET_XSDPS_SHIFT 0UL
+#define XIOU_SLCR_SD0_DSPPRESET_XSDPS_WIDTH 13UL
+#define XIOU_SLCR_SD0_DSPPRESET_XSDPS_MASK 0x00001fffUL
+#define XIOU_SLCR_SD0_DSPPRESET_XSDPS_DEFVAL 0x4UL
/**
* Register: XiouSlcrSdHspdpreset
@@ -3239,15 +3239,15 @@ extern "C" {
#define XIOU_SLCR_SD_HSPDPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000330UL )
#define XIOU_SLCR_SD_HSPDPRESET_RSTVAL 0x00020002UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT 16UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH 13UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK 0x1fff0000UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL 0x2UL
+#define XIOU_SLCR_SD1_HSPDPRESET_XSDPS_SHIFT 16UL
+#define XIOU_SLCR_SD1_HSPDPRESET_XSDPS_WIDTH 13UL
+#define XIOU_SLCR_SD1_HSPDPRESET_XSDPS_MASK 0x1fff0000UL
+#define XIOU_SLCR_SD1_HSPDPRESET_XSDPS_DEFVAL 0x2UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT 0UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH 13UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK 0x00001fffUL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL 0x2UL
+#define XIOU_SLCR_SD0_HSPDPRESET_XSDPS_SHIFT 0UL
+#define XIOU_SLCR_SD0_HSPDPRESET_XSDPS_WIDTH 13UL
+#define XIOU_SLCR_SD0_HSPDPRESET_XSDPS_MASK 0x00001fffUL
+#define XIOU_SLCR_SD0_HSPDPRESET_XSDPS_DEFVAL 0x2UL
/**
* Register: XiouSlcrSdSdr12preset
@@ -3255,15 +3255,15 @@ extern "C" {
#define XIOU_SLCR_SD_SDR12PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000334UL )
#define XIOU_SLCR_SD_SDR12PRESET_RSTVAL 0x00040004UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT 16UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH 13UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK 0x1fff0000UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL 0x4UL
+#define XIOU_SLCR_SD1_SDR12PRESET_XSDPS_SHIFT 16UL
+#define XIOU_SLCR_SD1_SDR12PRESET_XSDPS_WIDTH 13UL
+#define XIOU_SLCR_SD1_SDR12PRESET_XSDPS_MASK 0x1fff0000UL
+#define XIOU_SLCR_SD1_SDR12PRESET_XSDPS_DEFVAL 0x4UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT 0UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH 13UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK 0x00001fffUL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL 0x4UL
+#define XIOU_SLCR_SD0_SDR12PRESET_XSDPS_SHIFT 0UL
+#define XIOU_SLCR_SD0_SDR12PRESET_XSDPS_WIDTH 13UL
+#define XIOU_SLCR_SD0_SDR12PRESET_XSDPS_MASK 0x00001fffUL
+#define XIOU_SLCR_SD0_SDR12PRESET_XSDPS_DEFVAL 0x4UL
/**
* Register: XiouSlcrSdSdr25preset
@@ -3271,15 +3271,15 @@ extern "C" {
#define XIOU_SLCR_SD_SDR25PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000338UL )
#define XIOU_SLCR_SD_SDR25PRESET_RSTVAL 0x00020002UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT 16UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH 13UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK 0x1fff0000UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL 0x2UL
+#define XIOU_SLCR_SD1_SDR25PRESET_XSDPS_SHIFT 16UL
+#define XIOU_SLCR_SD1_SDR25PRESET_XSDPS_WIDTH 13UL
+#define XIOU_SLCR_SD1_SDR25PRESET_XSDPS_MASK 0x1fff0000UL
+#define XIOU_SLCR_SD1_SDR25PRESET_XSDPS_DEFVAL 0x2UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT 0UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH 13UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK 0x00001fffUL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL 0x2UL
+#define XIOU_SLCR_SD0_SDR25PRESET_XSDPS_SHIFT 0UL
+#define XIOU_SLCR_SD0_SDR25PRESET_XSDPS_WIDTH 13UL
+#define XIOU_SLCR_SD0_SDR25PRESET_XSDPS_MASK 0x00001fffUL
+#define XIOU_SLCR_SD0_SDR25PRESET_XSDPS_DEFVAL 0x2UL
/**
* Register: XiouSlcrSdSdr50prset
@@ -3287,15 +3287,15 @@ extern "C" {
#define XIOU_SLCR_SD_SDR50PRSET ( ( XIOU_SLCR_BASEADDR ) + 0x0000033CUL )
#define XIOU_SLCR_SD_SDR50PRSET_RSTVAL 0x00010001UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT 16UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH 13UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK 0x1fff0000UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL 0x1UL
+#define XIOU_SLCR_SD1_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT 16UL
+#define XIOU_SLCR_SD1_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH 13UL
+#define XIOU_SLCR_SD1_SDR50PRSET_XSDPS_SDR50PRESET_MASK 0x1fff0000UL
+#define XIOU_SLCR_SD1_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL 0x1UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT 0UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH 13UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK 0x00001fffUL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL 0x1UL
+#define XIOU_SLCR_SD0_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT 0UL
+#define XIOU_SLCR_SD0_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH 13UL
+#define XIOU_SLCR_SD0_SDR50PRSET_XSDPS_SDR50PRESET_MASK 0x00001fffUL
+#define XIOU_SLCR_SD0_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL 0x1UL
/**
* Register: XiouSlcrSdSdr104prst
@@ -3303,15 +3303,15 @@ extern "C" {
#define XIOU_SLCR_SD_SDR104PRST ( ( XIOU_SLCR_BASEADDR ) + 0x00000340UL )
#define XIOU_SLCR_SD_SDR104PRST_RSTVAL 0x00000000UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT 16UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH 13UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK 0x1fff0000UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL 0x0UL
+#define XIOU_SLCR_SD1_SDR104PRST_XSDPS_SDR104PRESET_SHIFT 16UL
+#define XIOU_SLCR_SD1_SDR104PRST_XSDPS_SDR104PRESET_WIDTH 13UL
+#define XIOU_SLCR_SD1_SDR104PRST_XSDPS_SDR104PRESET_MASK 0x1fff0000UL
+#define XIOU_SLCR_SD1_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT 0UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH 13UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK 0x00001fffUL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL 0x0UL
+#define XIOU_SLCR_SD0_SDR104PRST_XSDPS_SDR104PRESET_SHIFT 0UL
+#define XIOU_SLCR_SD0_SDR104PRST_XSDPS_SDR104PRESET_WIDTH 13UL
+#define XIOU_SLCR_SD0_SDR104PRST_XSDPS_SDR104PRESET_MASK 0x00001fffUL
+#define XIOU_SLCR_SD0_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL 0x0UL
/**
* Register: XiouSlcrSdDdr50preset
@@ -3319,15 +3319,15 @@ extern "C" {
#define XIOU_SLCR_SD_DDR50PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000344UL )
#define XIOU_SLCR_SD_DDR50PRESET_RSTVAL 0x00020002UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT 16UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH 13UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK 0x1fff0000UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL 0x2UL
+#define XIOU_SLCR_SD1_DDR50PRESET_XSDPS_SHIFT 16UL
+#define XIOU_SLCR_SD1_DDR50PRESET_XSDPS_WIDTH 13UL
+#define XIOU_SLCR_SD1_DDR50PRESET_XSDPS_MASK 0x1fff0000UL
+#define XIOU_SLCR_SD1_DDR50PRESET_XSDPS_DEFVAL 0x2UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT 0UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH 13UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK 0x00001fffUL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL 0x2UL
+#define XIOU_SLCR_SD0_DDR50PRESET_XSDPS_SHIFT 0UL
+#define XIOU_SLCR_SD0_DDR50PRESET_XSDPS_WIDTH 13UL
+#define XIOU_SLCR_SD0_DDR50PRESET_XSDPS_MASK 0x00001fffUL
+#define XIOU_SLCR_SD0_DDR50PRESET_XSDPS_DEFVAL 0x2UL
/**
* Register: XiouSlcrSdMaxcur1p8
@@ -3335,15 +3335,15 @@ extern "C" {
#define XIOU_SLCR_SD_MAXCUR1P8 ( ( XIOU_SLCR_BASEADDR ) + 0x0000034CUL )
#define XIOU_SLCR_SD_MAXCUR1P8_RSTVAL 0x00000000UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT 16UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH 8UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK 0x00ff0000UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL 0x0UL
+#define XIOU_SLCR_SD1_MAXCUR1P8_XSDPS_SHIFT 16UL
+#define XIOU_SLCR_SD1_MAXCUR1P8_XSDPS_WIDTH 8UL
+#define XIOU_SLCR_SD1_MAXCUR1P8_XSDPS_MASK 0x00ff0000UL
+#define XIOU_SLCR_SD1_MAXCUR1P8_XSDPS_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT 0UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH 8UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK 0x000000ffUL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL 0x0UL
+#define XIOU_SLCR_SD0_MAXCUR1P8_XSDPS_SHIFT 0UL
+#define XIOU_SLCR_SD0_MAXCUR1P8_XSDPS_WIDTH 8UL
+#define XIOU_SLCR_SD0_MAXCUR1P8_XSDPS_MASK 0x000000ffUL
+#define XIOU_SLCR_SD0_MAXCUR1P8_XSDPS_DEFVAL 0x0UL
/**
* Register: XiouSlcrSdMaxcur3p0
@@ -3351,15 +3351,15 @@ extern "C" {
#define XIOU_SLCR_SD_MAXCUR3P0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000350UL )
#define XIOU_SLCR_SD_MAXCUR3P0_RSTVAL 0x00000000UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT 16UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH 8UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK 0x00ff0000UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL 0x0UL
+#define XIOU_SLCR_SD1_MAXCUR3P0_XSDPS_SHIFT 16UL
+#define XIOU_SLCR_SD1_MAXCUR3P0_XSDPS_WIDTH 8UL
+#define XIOU_SLCR_SD1_MAXCUR3P0_XSDPS_MASK 0x00ff0000UL
+#define XIOU_SLCR_SD1_MAXCUR3P0_XSDPS_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT 0UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH 8UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK 0x000000ffUL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL 0x0UL
+#define XIOU_SLCR_SD0_MAXCUR3P0_XSDPS_SHIFT 0UL
+#define XIOU_SLCR_SD0_MAXCUR3P0_XSDPS_WIDTH 8UL
+#define XIOU_SLCR_SD0_MAXCUR3P0_XSDPS_MASK 0x000000ffUL
+#define XIOU_SLCR_SD0_MAXCUR3P0_XSDPS_DEFVAL 0x0UL
/**
* Register: XiouSlcrSdMaxcur3p3
@@ -3367,15 +3367,15 @@ extern "C" {
#define XIOU_SLCR_SD_MAXCUR3P3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000354UL )
#define XIOU_SLCR_SD_MAXCUR3P3_RSTVAL 0x00000000UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT 16UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH 8UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK 0x00ff0000UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL 0x0UL
+#define XIOU_SLCR_SD1_MAXCUR3P3_XSDPS_SHIFT 16UL
+#define XIOU_SLCR_SD1_MAXCUR3P3_XSDPS_WIDTH 8UL
+#define XIOU_SLCR_SD1_MAXCUR3P3_XSDPS_MASK 0x00ff0000UL
+#define XIOU_SLCR_SD1_MAXCUR3P3_XSDPS_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT 0UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH 8UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK 0x000000ffUL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL 0x0UL
+#define XIOU_SLCR_SD0_MAXCUR3P3_XSDPS_SHIFT 0UL
+#define XIOU_SLCR_SD0_MAXCUR3P3_XSDPS_WIDTH 8UL
+#define XIOU_SLCR_SD0_MAXCUR3P3_XSDPS_MASK 0x000000ffUL
+#define XIOU_SLCR_SD0_MAXCUR3P3_XSDPS_DEFVAL 0x0UL
/**
* Register: XiouSlcrSdDllCtrl
@@ -3383,35 +3383,35 @@ extern "C" {
#define XIOU_SLCR_SD_DLL_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000358UL )
#define XIOU_SLCR_SD_DLL_CTRL_RSTVAL 0x00000000UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT 18UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH 1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK 0x00040000UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL 0x0UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_RST_SHIFT 18UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_RST_WIDTH 1UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_RST_MASK 0x00040000UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_RST_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT 17UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH 1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK 0x00020000UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL 0x0UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_TESTMODE_SHIFT 17UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_TESTMODE_WIDTH 1UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_TESTMODE_MASK 0x00020000UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_TESTMODE_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT 16UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH 1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK 0x00010000UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL 0x0UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_LOCK_SHIFT 16UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_LOCK_WIDTH 1UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_LOCK_MASK 0x00010000UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_LOCK_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT 2UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH 1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK 0x00000004UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL 0x0UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_RST_SHIFT 2UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_RST_WIDTH 1UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_RST_MASK 0x00000004UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_RST_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT 1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH 1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK 0x00000002UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL 0x0UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_TESTMODE_SHIFT 1UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_TESTMODE_WIDTH 1UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_TESTMODE_MASK 0x00000002UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_TESTMODE_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT 0UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH 1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK 0x00000001UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL 0x0UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_LOCK_SHIFT 0UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_LOCK_WIDTH 1UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_LOCK_MASK 0x00000001UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_LOCK_DEFVAL 0x0UL
/**
* Register: XiouSlcrSdCdnCtrl
@@ -3419,15 +3419,15 @@ extern "C" {
#define XIOU_SLCR_SD_CDN_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x0000035CUL )
#define XIOU_SLCR_SD_CDN_CTRL_RSTVAL 0x00000000UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT 16UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH 1UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK 0x00010000UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL 0x0UL
+#define XIOU_SLCR_SD1_CDN_CTRL_XSDPS_SHIFT 16UL
+#define XIOU_SLCR_SD1_CDN_CTRL_XSDPS_WIDTH 1UL
+#define XIOU_SLCR_SD1_CDN_CTRL_XSDPS_MASK 0x00010000UL
+#define XIOU_SLCR_SD1_CDN_CTRL_XSDPS_DEFVAL 0x0UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT 0UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH 1UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK 0x00000001UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL 0x0UL
+#define XIOU_SLCR_SD0_CDN_CTRL_XSDPS_SHIFT 0UL
+#define XIOU_SLCR_SD0_CDN_CTRL_XSDPS_WIDTH 1UL
+#define XIOU_SLCR_SD0_CDN_CTRL_XSDPS_MASK 0x00000001UL
+#define XIOU_SLCR_SD0_CDN_CTRL_XSDPS_DEFVAL 0x0UL
/**
* Register: XiouSlcrGemCtrl
@@ -3435,25 +3435,25 @@ extern "C" {
#define XIOU_SLCR_GEM_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000360UL )
#define XIOU_SLCR_GEM_CTRL_RSTVAL 0x00000000UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 6UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x000000c0UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL
+#define XIOU_SLCR_GEM3_CTRL_XEMACPS_SGMII_SD_SHIFT 6UL
+#define XIOU_SLCR_GEM3_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL
+#define XIOU_SLCR_GEM3_CTRL_XEMACPS_SGMII_SD_MASK 0x000000c0UL
+#define XIOU_SLCR_GEM3_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 4UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x00000030UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL
+#define XIOU_SLCR_GEM2_CTRL_XEMACPS_SGMII_SD_SHIFT 4UL
+#define XIOU_SLCR_GEM2_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL
+#define XIOU_SLCR_GEM2_CTRL_XEMACPS_SGMII_SD_MASK 0x00000030UL
+#define XIOU_SLCR_GEM2_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 2UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x0000000cUL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL
+#define XIOU_SLCR_GEM1_CTRL_XEMACPS_SGMII_SD_SHIFT 2UL
+#define XIOU_SLCR_GEM1_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL
+#define XIOU_SLCR_GEM1_CTRL_XEMACPS_SGMII_SD_MASK 0x0000000cUL
+#define XIOU_SLCR_GEM1_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 0UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x00000003UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL
+#define XIOU_SLCR_GEM0_CTRL_XEMACPS_SGMII_SD_SHIFT 0UL
+#define XIOU_SLCR_GEM0_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL
+#define XIOU_SLCR_GEM0_CTRL_XEMACPS_SGMII_SD_MASK 0x00000003UL
+#define XIOU_SLCR_GEM0_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL
/**
* Register: XiouSlcrTtcApbClk
@@ -3518,35 +3518,35 @@ extern "C" {
#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_MASK 0x0f000000UL
#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_DEFVAL 0x0UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT 20UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH 4UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK 0x00f00000UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL 0x0UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS1_AXI_COH_SHIFT 20UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS1_AXI_COH_WIDTH 4UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS1_AXI_COH_MASK 0x00f00000UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS1_AXI_COH_DEFVAL 0x0UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT 16UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH 4UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK 0x000f0000UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL 0x0UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS0_AXI_COH_SHIFT 16UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS0_AXI_COH_WIDTH 4UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS0_AXI_COH_MASK 0x000f0000UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS0_AXI_COH_DEFVAL 0x0UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 12UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x0000f000UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM3_AXI_COH_SHIFT 12UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM3_AXI_COH_WIDTH 4UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM3_AXI_COH_MASK 0x0000f000UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM3_AXI_COH_DEFVAL 0x0UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 8UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x00000f00UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM2_AXI_COH_SHIFT 8UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM2_AXI_COH_WIDTH 4UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM2_AXI_COH_MASK 0x00000f00UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM2_AXI_COH_DEFVAL 0x0UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 4UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x000000f0UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM1_AXI_COH_SHIFT 4UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM1_AXI_COH_WIDTH 4UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM1_AXI_COH_MASK 0x000000f0UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM1_AXI_COH_DEFVAL 0x0UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 0UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x0000000fUL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM0_AXI_COH_SHIFT 0UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM0_AXI_COH_WIDTH 4UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM0_AXI_COH_MASK 0x0000000fUL
+#define XIOU_SLCR_COHERENT_CTRL_GEM0_AXI_COH_DEFVAL 0x0UL
/**
* Register: XiouSlcrVideoPssClkSel
@@ -3580,221 +3580,221 @@ extern "C" {
#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_MASK 0x00000040UL
#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_DEFVAL 0x0UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT 5UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH 1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK 0x00000020UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL 0x0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS1_SHIFT 5UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS1_WIDTH 1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS1_MASK 0x00000020UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS1_DEFVAL 0x0UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT 4UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH 1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK 0x00000010UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL 0x0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS0_SHIFT 4UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS0_WIDTH 1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS0_MASK 0x00000010UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS0_DEFVAL 0x0UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 3UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000008UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM3_SHIFT 3UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM3_WIDTH 1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM3_MASK 0x00000008UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM3_DEFVAL 0x0UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 2UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000004UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM2_SHIFT 2UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM2_WIDTH 1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM2_MASK 0x00000004UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM2_DEFVAL 0x0UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000002UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM1_SHIFT 1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM1_WIDTH 1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM1_MASK 0x00000002UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM1_DEFVAL 0x0UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 0UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000001UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM0_SHIFT 0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM0_WIDTH 1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM0_MASK 0x00000001UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM0_DEFVAL 0x0UL
-/**
- * Register: XiouSlcrRamXemacps
+/**
+ * Register: XiouSlcrRamGem0
*/
-#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000500UL )
-#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL
+#define XIOU_SLCR_RAM_GEM0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000500UL )
+#define XIOU_SLCR_RAM_GEM0_RSTVAL 0x00005b5bUL
+
+#define XIOU_SLCR_RAM_GEM0_EMASA1_SHIFT 14UL
+#define XIOU_SLCR_RAM_GEM0_EMASA1_WIDTH 1UL
+#define XIOU_SLCR_RAM_GEM0_EMASA1_MASK 0x00004000UL
+#define XIOU_SLCR_RAM_GEM0_EMASA1_DEFVAL 0x1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_GEM0_EMAB1_SHIFT 11UL
+#define XIOU_SLCR_RAM_GEM0_EMAB1_WIDTH 3UL
+#define XIOU_SLCR_RAM_GEM0_EMAB1_MASK 0x00003800UL
+#define XIOU_SLCR_RAM_GEM0_EMAB1_DEFVAL 0x3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_GEM0_EMAA1_SHIFT 8UL
+#define XIOU_SLCR_RAM_GEM0_EMAA1_WIDTH 3UL
+#define XIOU_SLCR_RAM_GEM0_EMAA1_MASK 0x00000700UL
+#define XIOU_SLCR_RAM_GEM0_EMAA1_DEFVAL 0x3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL
+#define XIOU_SLCR_RAM_GEM0_EMASA0_SHIFT 6UL
+#define XIOU_SLCR_RAM_GEM0_EMASA0_WIDTH 1UL
+#define XIOU_SLCR_RAM_GEM0_EMASA0_MASK 0x00000040UL
+#define XIOU_SLCR_RAM_GEM0_EMASA0_DEFVAL 0x1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_GEM0_EMAB0_SHIFT 3UL
+#define XIOU_SLCR_RAM_GEM0_EMAB0_WIDTH 3UL
+#define XIOU_SLCR_RAM_GEM0_EMAB0_MASK 0x00000038UL
+#define XIOU_SLCR_RAM_GEM0_EMAB0_DEFVAL 0x3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_GEM0_EMAA0_SHIFT 0UL
+#define XIOU_SLCR_RAM_GEM0_EMAA0_WIDTH 3UL
+#define XIOU_SLCR_RAM_GEM0_EMAA0_MASK 0x00000007UL
+#define XIOU_SLCR_RAM_GEM0_EMAA0_DEFVAL 0x3UL
-/**
- * Register: XiouSlcrRamXemacps
+/**
+ * Register: XiouSlcrRamgem1
*/
-#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000504UL )
-#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL
+#define XIOU_SLCR_RAM_GEM1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000504UL )
+#define XIOU_SLCR_RAM_GEM1_RSTVAL 0x00005b5bUL
+
+#define XIOU_SLCR_RAM_GEM1_EMASA1_SHIFT 14UL
+#define XIOU_SLCR_RAM_GEM1_EMASA1_WIDTH 1UL
+#define XIOU_SLCR_RAM_GEM1_EMASA1_MASK 0x00004000UL
+#define XIOU_SLCR_RAM_GEM1_EMASA1_DEFVAL 0x1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_GEM1_EMAB1_SHIFT 11UL
+#define XIOU_SLCR_RAM_GEM1_EMAB1_WIDTH 3UL
+#define XIOU_SLCR_RAM_GEM1_EMAB1_MASK 0x00003800UL
+#define XIOU_SLCR_RAM_GEM1_EMAB1_DEFVAL 0x3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_GEM1_EMAA1_SHIFT 8UL
+#define XIOU_SLCR_RAM_GEM1_EMAA1_WIDTH 3UL
+#define XIOU_SLCR_RAM_GEM1_EMAA1_MASK 0x00000700UL
+#define XIOU_SLCR_RAM_GEM1_EMAA1_DEFVAL 0x3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL
+#define XIOU_SLCR_RAM_GEM1_EMASA0_SHIFT 6UL
+#define XIOU_SLCR_RAM_GEM1_EMASA0_WIDTH 1UL
+#define XIOU_SLCR_RAM_GEM1_EMASA0_MASK 0x00000040UL
+#define XIOU_SLCR_RAM_GEM1_EMASA0_DEFVAL 0x1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_GEM1_EMAB0_SHIFT 3UL
+#define XIOU_SLCR_RAM_GEM1_EMAB0_WIDTH 3UL
+#define XIOU_SLCR_RAM_GEM1_EMAB0_MASK 0x00000038UL
+#define XIOU_SLCR_RAM_GEM1_EMAB0_DEFVAL 0x3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_GEM1_EMAA0_SHIFT 0UL
+#define XIOU_SLCR_RAM_GEM1_EMAA0_WIDTH 3UL
+#define XIOU_SLCR_RAM_GEM1_EMAA0_MASK 0x00000007UL
+#define XIOU_SLCR_RAM_GEM1_EMAA0_DEFVAL 0x3UL
/**
- * Register: XiouSlcrRamXemacps
+ * Register: XiouSlcrRamGem2
*/
-#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000508UL )
-#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL
+#define XIOU_SLCR_RAM_GEM2 ( ( XIOU_SLCR_BASEADDR ) + 0x00000508UL )
+#define XIOU_SLCR_RAM_GEM2_RSTVAL 0x00005b5bUL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL
+#define XIOU_SLCR_RAM_GEM2_EMASA1_SHIFT 14UL
+#define XIOU_SLCR_RAM_GEM2_EMASA1_WIDTH 1UL
+#define XIOU_SLCR_RAM_GEM2_EMASA1_MASK 0x00004000UL
+#define XIOU_SLCR_RAM_GEM2_EMASA1_DEFVAL 0x1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_GEM2_EMAB1_SHIFT 11UL
+#define XIOU_SLCR_RAM_GEM2_EMAB1_WIDTH 3UL
+#define XIOU_SLCR_RAM_GEM2_EMAB1_MASK 0x00003800UL
+#define XIOU_SLCR_RAM_GEM2_EMAB1_DEFVAL 0x3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_GEM2_EMAA1_SHIFT 8UL
+#define XIOU_SLCR_RAM_GEM2_EMAA1_WIDTH 3UL
+#define XIOU_SLCR_RAM_GEM2_EMAA1_MASK 0x00000700UL
+#define XIOU_SLCR_RAM_GEM2_EMAA1_DEFVAL 0x3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL
+#define XIOU_SLCR_RAM_GEM2_EMASA0_SHIFT 6UL
+#define XIOU_SLCR_RAM_GEM2_EMASA0_WIDTH 1UL
+#define XIOU_SLCR_RAM_GEM2_EMASA0_MASK 0x00000040UL
+#define XIOU_SLCR_RAM_GEM2_EMASA0_DEFVAL 0x1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_GEM2_EMAB0_SHIFT 3UL
+#define XIOU_SLCR_RAM_GEM2_EMAB0_WIDTH 3UL
+#define XIOU_SLCR_RAM_GEM2_EMAB0_MASK 0x00000038UL
+#define XIOU_SLCR_RAM_GEM2_EMAB0_DEFVAL 0x3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_GEM2_EMAA0_SHIFT 0UL
+#define XIOU_SLCR_RAM_GEM2_EMAA0_WIDTH 3UL
+#define XIOU_SLCR_RAM_GEM2_EMAA0_MASK 0x00000007UL
+#define XIOU_SLCR_RAM_GEM2_EMAA0_DEFVAL 0x3UL
/**
- * Register: XiouSlcrRamXemacps
+ * Register: XiouSlcrRamGem3
*/
-#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x0000050CUL )
-#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL
+#define XIOU_SLCR_RAM_GEM3 ( ( XIOU_SLCR_BASEADDR ) + 0x0000050CUL )
+#define XIOU_SLCR_RAM_GEM3_RSTVAL 0x00005b5bUL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL
+#define XIOU_SLCR_RAM_GEM3_EMASA1_SHIFT 14UL
+#define XIOU_SLCR_RAM_GEM3_EMASA1_WIDTH 1UL
+#define XIOU_SLCR_RAM_GEM3_EMASA1_MASK 0x00004000UL
+#define XIOU_SLCR_RAM_GEM3_EMASA1_DEFVAL 0x1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_GEM3_EMAB1_SHIFT 11UL
+#define XIOU_SLCR_RAM_GEM3_EMAB1_WIDTH 3UL
+#define XIOU_SLCR_RAM_GEM3_EMAB1_MASK 0x00003800UL
+#define XIOU_SLCR_RAM_GEM3_EMAB1_DEFVAL 0x3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_GEM3_EMAA1_SHIFT 8UL
+#define XIOU_SLCR_RAM_GEM3_EMAA1_WIDTH 3UL
+#define XIOU_SLCR_RAM_GEM3_EMAA1_MASK 0x00000700UL
+#define XIOU_SLCR_RAM_GEM3_EMAA1_DEFVAL 0x3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL
+#define XIOU_SLCR_RAM_GEM3_EMASA0_SHIFT 6UL
+#define XIOU_SLCR_RAM_GEM3_EMASA0_WIDTH 1UL
+#define XIOU_SLCR_RAM_GEM3_EMASA0_MASK 0x00000040UL
+#define XIOU_SLCR_RAM_GEM3_EMASA0_DEFVAL 0x1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_GEM3_EMAB0_SHIFT 3UL
+#define XIOU_SLCR_RAM_GEM3_EMAB0_WIDTH 3UL
+#define XIOU_SLCR_RAM_GEM3_EMAB0_MASK 0x00000038UL
+#define XIOU_SLCR_RAM_GEM3_EMAB0_DEFVAL 0x3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_GEM3_EMAA0_SHIFT 0UL
+#define XIOU_SLCR_RAM_GEM3_EMAA0_WIDTH 3UL
+#define XIOU_SLCR_RAM_GEM3_EMAA0_MASK 0x00000007UL
+#define XIOU_SLCR_RAM_GEM3_EMAA0_DEFVAL 0x3UL
/**
- * Register: XiouSlcrRamXsdps
+ * Register: XiouSlcrRamXsdps0
*/
-#define XIOU_SLCR_RAM_XSDPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000510UL )
-#define XIOU_SLCR_RAM_XSDPS_RSTVAL 0x0000005bUL
+#define XIOU_SLCR_RAM_XSDPS0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000510UL )
+#define XIOU_SLCR_RAM_XSDPS0_RSTVAL 0x0000005bUL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT 6UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH 1UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK 0x00000040UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL 0x1UL
+#define XIOU_SLCR_RAM_XSDPS0_EMASA0_SHIFT 6UL
+#define XIOU_SLCR_RAM_XSDPS0_EMASA0_WIDTH 1UL
+#define XIOU_SLCR_RAM_XSDPS0_EMASA0_MASK 0x00000040UL
+#define XIOU_SLCR_RAM_XSDPS0_EMASA0_DEFVAL 0x1UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT 3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH 3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK 0x00000038UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAB0_SHIFT 3UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAB0_WIDTH 3UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAB0_MASK 0x00000038UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAB0_DEFVAL 0x3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT 0UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH 3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK 0x00000007UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAA0_SHIFT 0UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAA0_WIDTH 3UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAA0_MASK 0x00000007UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAA0_DEFVAL 0x3UL
/**
- * Register: XiouSlcrRamXsdps
+ * Register: XiouSlcrRamXsdps1
*/
-#define XIOU_SLCR_RAM_XSDPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000514UL )
-#define XIOU_SLCR_RAM_XSDPS_RSTVAL 0x0000005bUL
+#define XIOU_SLCR_RAM_XSDPS1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000514UL )
+#define XIOU_SLCR_RAM_XSDPS1_RSTVAL 0x0000005bUL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT 6UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH 1UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK 0x00000040UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL 0x1UL
+#define XIOU_SLCR_RAM_XSDPS1_EMASA0_SHIFT 6UL
+#define XIOU_SLCR_RAM_XSDPS1_EMASA0_WIDTH 1UL
+#define XIOU_SLCR_RAM_XSDPS1_EMASA0_MASK 0x00000040UL
+#define XIOU_SLCR_RAM_XSDPS1_EMASA0_DEFVAL 0x1UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT 3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH 3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK 0x00000038UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAB0_SHIFT 3UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAB0_WIDTH 3UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAB0_MASK 0x00000038UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAB0_DEFVAL 0x3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT 0UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH 3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK 0x00000007UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL 0x3UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAA0_SHIFT 0UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAA0_WIDTH 3UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAA0_MASK 0x00000007UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAA0_DEFVAL 0x3UL
/**
* Register: XiouSlcrRamCan0
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr_secure.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr_secure.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr_secure.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu_sink.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu_sink.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu_sink.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu_sink.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xocm_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xocm_xmpu_cfg.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/includes_ps/xocm_xmpu_cfg.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xocm_xmpu_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/initialise_monitor_handles.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/initialise_monitor_handles.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/initialise_monitor_handles.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/initialise_monitor_handles.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/isatty.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/isatty.c
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/isatty.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/isatty.c
index 242d8faf3..f14251511 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/isatty.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/isatty.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/kill.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/kill.c
similarity index 89%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/kill.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/kill.c
index 1c67ace57..fc2f89d6c 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/kill.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/kill.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -35,7 +35,7 @@
#ifdef __cplusplus
extern "C" {
- __attribute__((weak)) s32 _kill(s32 pid, s32 sig);
+ __attribute__((weak)) int _kill(pid_t pid, int sig);
}
#endif
@@ -43,7 +43,7 @@ extern "C" {
* kill -- go out via exit...
*/
-__attribute__((weak)) s32 kill(s32 pid, s32 sig)
+__attribute__((weak)) int kill(pid_t pid, int sig)
{
if(pid == 1) {
_exit(sig);
@@ -51,7 +51,7 @@ __attribute__((weak)) s32 kill(s32 pid, s32 sig)
return 0;
}
-__attribute__((weak)) s32 _kill(s32 pid, s32 sig)
+__attribute__((weak)) int _kill(pid_t pid, int sig)
{
if(pid == 1) {
_exit(sig);
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/lseek.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/lseek.c
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/lseek.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/lseek.c
index 5cd5a2dd1..106c45c89 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/lseek.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/lseek.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/open.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/open.c
similarity index 89%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/open.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/open.c
index 2bb745ab1..4b51839fd 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/open.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/open.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -29,20 +29,20 @@
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
-
+#ifndef UNDEFINE_FILE_OPS
#include
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
- __attribute__((weak)) s32 open(const char8 *buf, s32 flags, s32 mode);
+ __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode);
}
#endif
/*
* open -- open a file descriptor. We don't have a filesystem, so
* we return an error.
*/
-__attribute__((weak)) s32 open(const char8 *buf, s32 flags, s32 mode)
+__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
{
(void *)buf;
(void)flags;
@@ -50,3 +50,4 @@ __attribute__((weak)) s32 open(const char8 *buf, s32 flags, s32 mode)
errno = EIO;
return (-1);
}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/outbyte.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/outbyte.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/outbyte.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/outbyte.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/print.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/print.c
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/print.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/print.c
index 31d7b1989..74d70ee4a 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/print.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/print.c
@@ -24,7 +24,7 @@ void print(const char8 *ptr)
#ifdef STDOUT_BASEADDRESS
while (*ptr != (char8)0) {
outbyte (*ptr);
- *ptr++;
+ ptr++;
}
#else
(void)ptr;
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/putnum.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/putnum.c
similarity index 93%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/putnum.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/putnum.c
index ec0dc37ee..aaf9edee7 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/putnum.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/putnum.c
@@ -27,7 +27,7 @@ void putnum(u32 num);
void putnum(u32 num)
{
char8 buf[9];
- u32 cnt;
+ s32 cnt;
s32 i;
char8 *ptr;
u32 digit;
@@ -36,8 +36,8 @@ void putnum(u32 num)
}
ptr = buf;
- for (cnt = 7U ; cnt >= 0U ; cnt--) {
- digit = ((num >> (cnt * 4U)) & 0x0000000FU);
+ for (cnt = 7 ; cnt >= 0 ; cnt--) {
+ digit = (num >> (cnt * 4U)) & 0x0000000fU;
if ((digit <= 9U) && (ptr != NULL)) {
digit += (u32)'0';
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/read.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/read.c
similarity index 80%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/read.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/read.c
index 9a67e02d1..7f7b7d261 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/read.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/read.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -32,9 +32,9 @@
/* read.c -- read bytes from a input device.
*/
-
-#include "xparameters.h"
+#ifndef UNDEFINE_FILE_OPS
#include "xil_printf.h"
+#include "xparameters.h"
#ifdef __cplusplus
extern "C" {
@@ -51,25 +51,21 @@ read (s32 fd, char8* buf, s32 nbytes)
{
#ifdef STDIN_BASEADDRESS
s32 i;
+ s32 numbytes = 0;
char8* LocalBuf = buf;
(void)fd;
- for (i = 0; i < nbytes; i++) {
- if(LocalBuf != NULL) {
- LocalBuf += i;
- }
- if(LocalBuf != NULL) {
- *LocalBuf = inbyte();
- if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
- break;
+ if(LocalBuf != NULL) {
+ for (i = 0; i < nbytes; i++) {
+ numbytes++;
+ *(LocalBuf + i) = inbyte();
+ if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+ break;
}
}
- if(LocalBuf != NULL) {
- LocalBuf -= i;
- }
}
- return (i + 1);
+ return numbytes;
#else
(void)fd;
(void)buf;
@@ -83,25 +79,21 @@ _read (s32 fd, char8* buf, s32 nbytes)
{
#ifdef STDIN_BASEADDRESS
s32 i;
+ s32 numbytes = 0;
char8* LocalBuf = buf;
(void)fd;
- for (i = 0; i < nbytes; i++) {
- if(LocalBuf != NULL) {
- LocalBuf += i;
- }
- if(LocalBuf != NULL) {
- *LocalBuf = inbyte();
- if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
- break;
+ if(LocalBuf != NULL) {
+ for (i = 0; i < nbytes; i++) {
+ numbytes++;
+ *(LocalBuf + i) = inbyte();
+ if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+ break;
}
}
- if(LocalBuf != NULL) {
- LocalBuf -= i;
- }
}
- return (i + 1);
+ return numbytes;
#else
(void)fd;
(void)buf;
@@ -109,3 +101,4 @@ _read (s32 fd, char8* buf, s32 nbytes)
return 0;
#endif
}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/sbrk.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sbrk.c
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/sbrk.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sbrk.c
index 7f94fabb4..64d5156af 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/sbrk.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sbrk.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/sleep.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sleep.c
similarity index 68%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/sleep.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sleep.c
index c81e1f381..c1df66bcf 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/sleep.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sleep.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -45,6 +45,11 @@
* 5.04 pkp 28/01/16 Modified the sleep API to configure Time Stamp
* generator only when disable using frequency from
* xparamters.h instead of hardcoding
+* 5.05 pkp 13/04/16 Modified sleep routine to call XTime_StartTimer
+* which enables timer only when it is disabled and
+* read counter value directly from register instead
+* of calling XTime_GetTime for optimization
+* 6.0 asa 08/15/16 Updated the sleep/usleep signature. Fix for CR#956899.
*
*
******************************************************************************/
@@ -54,6 +59,42 @@
#include "xtime_l.h"
#include "xparameters.h"
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_USECOND (COUNTS_PER_SECOND / 1000000 )
+
+static void sleep_common(u32 n, u32 count)
+{
+ XTime tEnd, tCur;
+ /* Start global timer counter, it will only be enabled if it is disabled */
+ XTime_StartTimer();
+
+ tCur = mfcp(CNTPCT_EL0);
+ tEnd = tCur + (((XTime) n) * count);
+ do {
+ tCur = mfcp(CNTPCT_EL0);
+ } while (tCur < tEnd);
+}
+
+/*****************************************************************************/
+/**
+*
+* This API gives a delay in microseconds
+*
+* @param useconds requested
+*
+* @return 0 if the delay can be achieved, -1 if the requested delay
+* is out of range
+*
+* @note None.
+*
+****************************************************************************/
+int usleep(unsigned long useconds)
+{
+ sleep_common((u32)useconds, COUNTS_PER_USECOND);
+
+ return 0;
+}
+
/*****************************************************************************/
/*
*
@@ -66,24 +107,9 @@
* @note None.
*
****************************************************************************/
-s32 sleep(u32 seconds)
+unsigned sleep(unsigned int seconds)
{
- XTime tEnd, tCur;
- /* Enable the counter only if it is disable */
- if(((Xil_In32(XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET)) & XIOU_SCNTRS_CNT_CNTRL_REG_EN_MASK) != XIOU_SCNTRS_CNT_CNTRL_REG_EN){
-
- /*write frequency to System Time Stamp Generator Register*/
- Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_FREQ_REG_OFFSET),XIOU_SCNTRS_FREQ);
-
- /*Enable the counter*/
- Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),XIOU_SCNTRS_CNT_CNTRL_REG_EN);
- }
- XTime_GetTime(&tCur);
- tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
- do
- {
- XTime_GetTime(&tCur);
- } while (tCur < tEnd);
+ sleep_common(seconds, COUNTS_PER_SECOND);
return 0;
}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/sleep.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sleep.h
similarity index 92%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/sleep.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sleep.h
index d2629b6b8..27add6605 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/sleep.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sleep.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -40,8 +40,8 @@
extern "C" {
#endif
-s32 usleep(u32 useconds);
-s32 sleep(u32 seconds);
+int usleep(unsigned long useconds);
+unsigned sleep(unsigned int seconds);
#ifdef __cplusplus
}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/translation_table.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/translation_table.S
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/translation_table.S
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/translation_table.S
index 5087307f2..49b3dcf35 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/translation_table.S
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/translation_table.S
@@ -43,6 +43,7 @@
* ----- ---- -------- ---------------------------------------------------
* 5.00 pkp 05/21/14 Initial version
* 5.04 pkp 12/18/15 Updated the address map according to proper address map
+* 6.0 mus 07/20/16 Added warning for ddrless HW design CR-954977
*
* @note
*
@@ -131,6 +132,7 @@ MMUTableL2:
.endif
#else
.set DDR_REG, 0
+#warning "There's no DDR in the HW design. MMU translation table marks 2 GB DDR address space as undefined"
#endif
.set UNDEF_REG, 0x400 - DDR_REG
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/uart.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/uart.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/uart.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/uart.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/unlink.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/unlink.c
similarity index 91%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/unlink.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/unlink.c
index 3e5690e83..84e44a47c 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/unlink.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/unlink.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -35,14 +35,14 @@
#ifdef __cplusplus
extern "C" {
- __attribute__((weak)) s32 unlink(char8 *path);
+ __attribute__((weak)) sint32 unlink(char8 *path);
}
#endif
/*
* unlink -- since we have no file system,
* we just return an error.
*/
-__attribute__((weak)) s32 unlink(char8 *path)
+__attribute__((weak)) sint32 unlink(char8 *path)
{
(void *)path;
errno = EIO;
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/vectors.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/vectors.c
similarity index 66%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/vectors.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/vectors.c
index d9a1b42ad..0a3616328 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/vectors.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/vectors.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,14 +33,17 @@
/**
* @file vectors.c
*
-* This file contains the C level vectors for the ARM Cortex A53 core.
+* This file contains the C level vectors for the ARM Cortex A9 core.
*
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 05/29/14 First release
+* 1.00a ecm 10/20/09 Initial version, moved over from bsp area
+* 6.0 mus 27/07/16 Consolidated vectors for a53,a9 and r5 processor
+* and added UndefinedException for a53 32 bit and r5
+* processor
*
*
* @note
@@ -71,7 +74,6 @@ extern XExc_VectorTableEntry XExc_VectorTable[];
/************************** Function Prototypes ******************************/
-
/*****************************************************************************/
/**
*
@@ -110,6 +112,84 @@ void IRQInterrupt(void)
XIL_EXCEPTION_ID_IRQ_INT].Data);
}
+#if !defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Undefined exception called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void UndefinedException(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_UNDEFINED_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SW Interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void SWInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_SWI_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the DataAbort Interrupt called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void DataAbortInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler(
+ XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the PrefetchAbort Interrupt called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void PrefetchAbortInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
+ XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
+}
+#else
+
/*****************************************************************************/
/**
*
@@ -147,3 +227,5 @@ void SErrorInterrupt(void)
XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
}
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/vectors.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/vectors.h
similarity index 87%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/vectors.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/vectors.h
index 1ec878563..bb599b560 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/vectors.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/vectors.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,14 +33,15 @@
/**
* @file vectors.h
*
-* This file contains the C level vector prototypes for the ARM Cortex A53 core.
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
*
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 05/29/14 First release
+* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
+* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
*
*
* @note
@@ -67,12 +68,18 @@ extern "C" {
/************************** Constant Definitions *****************************/
/************************** Function Prototypes ******************************/
+
void FIQInterrupt(void);
void IRQInterrupt(void);
+#if !defined (__aarch64__)
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+void UndefinedException(void);
+#else
void SynchronousInterrupt(void);
void SErrorInterrupt(void);
-
-
+#endif
#ifdef __cplusplus
}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/write.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/write.c
similarity index 89%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/write.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/write.c
index 7630914aa..aaa879e73 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/write.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/write.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -32,13 +32,13 @@
/* write.c -- write bytes to an output device.
*/
-
-#include "xparameters.h"
+#ifndef UNDEFINE_FILE_OPS
#include "xil_printf.h"
+#include "xparameters.h"
#ifdef __cplusplus
extern "C" {
- __attribute__((weak)) s32 _write (s32 fd, char8* buf, s32 nbytes);
+ __attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes);
}
#endif
@@ -47,8 +47,8 @@ extern "C" {
* stdout and stderr are the same. Since we have no filesystem,
* open will only return an error.
*/
-__attribute__((weak)) s32
-write (s32 fd, char8* buf, s32 nbytes)
+__attribute__((weak)) sint32
+write (sint32 fd, char8* buf, sint32 nbytes)
{
#ifdef STDOUT_BASEADDRESS
@@ -79,8 +79,8 @@ write (s32 fd, char8* buf, s32 nbytes)
#endif
}
-__attribute__((weak)) s32
-_write (s32 fd, char8* buf, s32 nbytes)
+__attribute__((weak)) sint32
+_write (sint32 fd, char8* buf, sint32 nbytes)
{
#ifdef STDOUT_BASEADDRESS
s32 i;
@@ -109,3 +109,4 @@ _write (s32 fd, char8* buf, s32 nbytes)
return 0;
#endif
}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xbasic_types.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xbasic_types.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xbasic_types.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xbasic_types.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xdebug.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xdebug.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xdebug.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xdebug.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xenv.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xenv.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xenv.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xenv.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xenv_standalone.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xenv_standalone.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xenv_standalone.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xenv_standalone.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil-crt0.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil-crt0.S
similarity index 78%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil-crt0.S
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil-crt0.S
index 227112695..38ca6511c 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil-crt0.S
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil-crt0.S
@@ -56,29 +56,38 @@
.text
.Lsbss_start:
- .long __sbss_start
+ .quad __sbss_start
.Lsbss_end:
- .long __sbss_end
+ .quad __sbss_end
.Lbss_start:
- .long __bss_start__
+ .quad __bss_start__
.Lbss_end:
- .long __bss_end__
+ .quad __bss_end__
+.set APU_PWRCTL, 0xFD5C0090
.globl _startup
_startup:
mov x0, #0
+ /* Check whether the clearing of bss sections shall be skipped */
+ ldr x10, =APU_PWRCTL /* Load PWRCTRL address */
+ ldr w11, [x10] /* Read PWRCTRL register */
+ mrs x2, MPIDR_EL1 /* Read MPIDR_EL1 */
+ ubfx x2, x2, #0, #8 /* Extract CPU ID (affinity level 0) */
+ mov w1, #1
+ lsl w2, w1, w2 /* Shift CPU ID to get one-hot ID */
+ ands w11, w11, w2 /* Get PWRCTRL bit for this core */
+ bne .Lenclbss /* Skip BSS and SBSS clearing */
+
/* clear sbss */
- ldr w1,.Lsbss_start /* calculate beginning of the SBSS */
- ldr w2,.Lsbss_end /* calculate end of the SBSS */
- uxtw x1, w1 /*zero extension to w1 register*/
- uxtw x2, w2 /*zero extension to w2 register*/
+ ldr x1,.Lsbss_start /* calculate beginning of the SBSS */
+ ldr x2,.Lsbss_end /* calculate end of the SBSS */
.Lloop_sbss:
cmp x1,x2
@@ -88,10 +97,8 @@ _startup:
.Lenclsbss:
/* clear bss */
- ldr w1,.Lbss_start /* calculate beginning of the BSS */
- ldr w2,.Lbss_end /* calculate end of the BSS */
- uxtw x1, w1 /*zero extension to w1 register*/
- uxtw x2, w2 /*zero extension to w2 register*/
+ ldr x1,.Lbss_start /* calculate beginning of the BSS */
+ ldr x2,.Lbss_end /* calculate end of the BSS */
.Lloop_bss:
cmp x1,x2
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_assert.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_assert.c
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_assert.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_assert.c
index 42db07deb..3087fe80f 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_assert.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_assert.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -42,6 +42,7 @@
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 Initial release
+* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
*
*
******************************************************************************/
@@ -71,7 +72,7 @@ u32 Xil_AssertStatus;
* such that it does not wait infinitely. Use the debugger to disable the
* waiting during testing of asserts.
*/
-/*s32 Xil_AssertWait = 1*/
+s32 Xil_AssertWait = 1;
/* The callback function to be invoked when an assert is taken */
static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
@@ -95,7 +96,6 @@ static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
******************************************************************************/
void Xil_Assert(const char8 *File, s32 Line)
{
- s32 Xil_AssertWait = 1;
/* if the callback has been set then invoke it */
if (Xil_AssertCallbackRoutine != 0) {
(*Xil_AssertCallbackRoutine)(File, Line);
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_assert.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_assert.h
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_assert.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_assert.h
index 7034bc9ad..1e3c17b50 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_assert.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_assert.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -42,6 +42,7 @@
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
+* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
*
*
******************************************************************************/
@@ -66,6 +67,7 @@ extern "C" {
#define XNULL NULL
extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
extern void Xil_Assert(const char8 *File, s32 Line);
void XNullHandler(void *NullParameter);
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_cache.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_cache.c
similarity index 87%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_cache.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_cache.c
index 7d493f604..8a1f82881 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_cache.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_cache.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -43,6 +43,9 @@
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
+* 5.05 pkp 04/15/16 Updated the Xil_DCacheInvalidate,
+* Xil_DCacheInvalidateLine and Xil_DCacheInvalidateRange
+* functions description for proper explaination
*
*
*
@@ -56,6 +59,7 @@
#include "xparameters.h"
#include "xreg_cortexa53.h"
#include "xil_exception.h"
+#include "bspconfig.h"
/************************** Function Prototypes ******************************/
@@ -77,7 +81,9 @@
void Xil_DCacheEnable(void)
{
u32 CtrlReg;
+
CtrlReg = mfcp(SCTLR_EL3);
+
/* enable caches only if they are disabled */
if((CtrlReg & XREG_CONTROL_DCACHE_BIT) == 0X00000000U){
@@ -86,7 +92,7 @@ void Xil_DCacheEnable(void)
CtrlReg |= XREG_CONTROL_DCACHE_BIT;
- /* enable the Data cache */
+ /* enable the Data cache for el3*/
mtcp(SCTLR_EL3,CtrlReg);
}
}
@@ -107,29 +113,37 @@ void Xil_DCacheDisable(void)
u32 CtrlReg;
/* clean and invalidate the Data cache */
Xil_DCacheFlush();
+
CtrlReg = mfcp(SCTLR_EL3);
CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- /* disable the Data cache */
+
+ /* disable the Data cache for el3*/
mtcp(SCTLR_EL3,CtrlReg);
}
/****************************************************************************
*
-* invalidate the Data cache.
+* Invalidate the Data cache. The contents present in the cache are cleaned and
+* invalidated.
*
* @param None.
*
* @return None.
*
-* @note None.
+* @note In Cortex-A53, functionality to simply invalide the cachelines
+* is not present. Such operations are a problem for an environment
+* that supports virtualisation. It would allow one OS to invalidate
+* a line belonging to another OS which could lead to that OS crashing
+* because of the loss of essential data. Hence, such operations are
+* promoted to clean and invalidate which avoids such corruption.
*
****************************************************************************/
void Xil_DCacheInvalidate(void)
{
register u32 CsidReg, C7Reg;
u32 LineSize, NumWays;
- u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, NumCacheLevel, CacheLevel,CacheLevelIndex;
+ u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, CacheLevel;
u32 currmask;
currmask = mfcpsr();
@@ -137,7 +151,6 @@ void Xil_DCacheInvalidate(void)
/* Number of level of cache*/
- NumCacheLevel = (mfcp(CLIDR_EL1)>>24U) & 0x00000007U;
CacheLevel=0U;
/* Select cache level 0 and D cache in CSSR */
@@ -217,16 +230,18 @@ void Xil_DCacheInvalidate(void)
/****************************************************************************
*
-* Invalidate a Data cache line. If the byte specified by the address (adr)
-* is cached by the Data cache, the cacheline containing that byte is
-* invalidated. If the cacheline is modified (dirty), the modified contents
-* are written to system memory before the line is invalidated.
+* Invalidate a Data cache line. The cacheline is cleaned and invalidated
*
* @param Address to be flushed.
*
* @return None.
*
-* @note The bottom 6 bits are set to 0, forced by architecture.
+* @note In Cortex-A53, functionality to simply invalide the cachelines
+* is not present. Such operations are a problem for an environment
+* that supports virtualisation. It would allow one OS to invalidate
+* a line belonging to another OS which could lead to that OS crashing
+* because of the loss of essential data. Hence, such operations are
+* promoted to clean and invalidate which avoids such corruption.
*
****************************************************************************/
void Xil_DCacheInvalidateLine(INTPTR adr)
@@ -252,17 +267,19 @@ void Xil_DCacheInvalidateLine(INTPTR adr)
/****************************************************************************
*
* Invalidate the Data cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the Data cache,
-* the cacheline containing that byte is invalidated. If the cacheline
-* is modified (dirty), the modified contents are written to system memory
-* before the line is invalidated.
+* The cachelines present in the adderss range are cleaned and invalidated
*
* @param Start address of range to be invalidated.
* @param Length of range to be invalidated in bytes.
*
* @return None.
*
-* @note None.
+* @note In Cortex-A53, functionality to simply invalide the cachelines
+* is not present. Such operations are a problem for an environment
+* that supports virtualisation. It would allow one OS to invalidate
+* a line belonging to another OS which could lead to that OS crashing
+* because of the loss of essential data. Hence, such operations are
+* promoted to clean and invalidate which avoids such corruption.
*
****************************************************************************/
void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len)
@@ -322,7 +339,7 @@ void Xil_DCacheFlush(void)
{
register u32 CsidReg, C7Reg;
u32 LineSize, NumWays;
- u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, NumCacheLevel, CacheLevel,CacheLevelIndex;
+ u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, CacheLevel;
u32 currmask;
currmask = mfcpsr();
@@ -330,7 +347,6 @@ void Xil_DCacheFlush(void)
/* Number of level of cache*/
- NumCacheLevel = (mfcp(CLIDR_EL1)>>24U) & 0x00000007U;
CacheLevel = 0U;
/* Select cache level 0 and D cache in CSSR */
@@ -514,17 +530,19 @@ void Xil_DCacheFlushRange(INTPTR adr, INTPTR len)
void Xil_ICacheEnable(void)
{
-
u32 CtrlReg;
+
CtrlReg = mfcp(SCTLR_EL3);
+
/* enable caches only if they are disabled */
if((CtrlReg & XREG_CONTROL_ICACHE_BIT)==0x00000000U){
- /* invalidate the instruction cache */
- Xil_ICacheInvalidate();
+ /* invalidate the instruction cache */
+ Xil_ICacheInvalidate();
- CtrlReg |= XREG_CONTROL_ICACHE_BIT;
- /* enable the instruction cache */
- mtcp(SCTLR_EL3,CtrlReg);
+ CtrlReg |= XREG_CONTROL_ICACHE_BIT;
+
+ /* enable the instruction cache for el3*/
+ mtcp(SCTLR_EL3,CtrlReg);
}
}
@@ -542,12 +560,15 @@ void Xil_ICacheEnable(void)
void Xil_ICacheDisable(void)
{
u32 CtrlReg;
+
CtrlReg = mfcp(SCTLR_EL3);
+
/* invalidate the instruction cache */
Xil_ICacheInvalidate();
CtrlReg &= ~(XREG_CONTROL_ICACHE_BIT);
/* disable the instruction cache */
mtcp(SCTLR_EL3,CtrlReg);
+
}
/****************************************************************************
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_cache.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_cache.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_cache.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_cache.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_cache_vxworks.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_cache_vxworks.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_exception.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_exception.c
similarity index 62%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_exception.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_exception.c
index 101ba0674..66f722d92 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_exception.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_exception.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -34,7 +34,7 @@
*
* @file xil_exception.c
*
-* This file contains low-level driver functions for the Cortex A53 exception
+* This file contains low-level driver functions for the Cortex A53,A9,R5 exception
* Handler.
*
*
@@ -42,7 +42,10 @@
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
+* 5.2 pkp 28/05/15 First release
+* 6.0 mus 27/07/16 Consolidated exceptions for a53,a9 and r5
+* processors and added Xil_UndefinedExceptionHandler
+* for a53 32 bit and r5 as well.
*
*
*****************************************************************************/
@@ -66,13 +69,12 @@ typedef struct {
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Function Prototypes *****************************/
-
static void Xil_ExceptionNullHandler(void *Data);
-
/************************** Variable Definitions *****************************/
/*
* Exception vector table to store handlers for each exception vector.
*/
+#if defined (__aarch64__)
XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
{
{Xil_ExceptionNullHandler, NULL},
@@ -82,6 +84,27 @@ XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
{Xil_SErrorAbortHandler, NULL},
};
+#else
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_UndefinedExceptionHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_PrefetchAbortHandler, NULL},
+ {Xil_DataAbortHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+};
+#endif
+#if !defined (__aarch64__)
+u32 DataAbortAddr; /* Address of instruction causing data abort */
+u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */
+u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined
+ exception */
+#endif
+
+/*****************************************************************************/
+
/****************************************************************************/
/**
*
@@ -105,11 +128,13 @@ DieLoop: goto DieLoop;
/****************************************************************************/
/**
-*
* The function is a common API used to initialize exception handlers across all
-* processors supported. For ARM CortexA53, the exception handlers are being
+* processors supported. For ARM CortexA53,R5,A9, the exception handlers are being
* initialized statically and hence this function does not do anything.
-*
+* However, it is still present to avoid any compilation issues in case an
+* application uses this API and also to take care of backward compatibility
+* issues (in earlier versions of BSPs, this API was being used to initialize
+* exception handlers).
*
* @param None.
*
@@ -172,6 +197,8 @@ void Xil_ExceptionRemoveHandler(u32 Exception_id)
Xil_ExceptionNullHandler,
NULL);
}
+
+#if defined (__aarch64__)
/*****************************************************************************/
/**
*
@@ -212,3 +239,93 @@ void Xil_SErrorAbortHandler(void *CallBackRef){
;
}
}
+#else
+/*****************************************************************************/
+/**
+*
+* Default Data abort handler which prints data fault status register through
+* which information about data fault can be acquired
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+
+void Xil_DataAbortHandler(void *CallBackRef){
+#ifdef DEBUG
+ u32 FaultStatus;
+
+ xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
+ #ifdef __GNUC__
+ FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
+ #elif defined (__ICCARM__)
+ mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus);
+ #else
+ { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
+ FaultStatus = Reg; }
+ #endif
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %x\n",FaultStatus);
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Data abort %x\n",DataAbortAddr);
+#endif
+ while(1) {
+ ;
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* Default Prefetch abort handler which prints prefetch fault status register through
+* which information about instruction prefetch fault can be acquired
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_PrefetchAbortHandler(void *CallBackRef){
+#ifdef DEBUG
+ u32 FaultStatus;
+
+ xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
+ #ifdef __GNUC__
+ FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
+ #elif defined (__ICCARM__)
+ mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus);
+ #else
+ { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
+ FaultStatus = Reg; }
+ #endif
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %x\n",FaultStatus);
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Prefetch abort %x\n",PrefetchAbortAddr);
+#endif
+ while(1) {
+ ;
+ }
+}
+/*****************************************************************************/
+/**
+*
+* Default undefined exception handler which prints address of the undefined
+* instruction if debug prints are enabled
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_UndefinedExceptionHandler(void *CallBackRef){
+
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %x\n",UndefinedExceptionAddr);
+ while(1) {
+ ;
+ }
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_exception.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_exception.h
similarity index 59%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_exception.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_exception.h
index 288a60475..434ef2a6a 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_exception.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_exception.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -34,7 +34,7 @@
*
* @file xil_exception.h
*
-* This header file contains ARM Cortex A53 specific exception related APIs.
+* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
* For exception related functions that can be used across all Xilinx supported
* processors, please use xil_exception.h.
*
@@ -43,7 +43,8 @@
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
+* 5.2 pkp 28/05/15 First release
+* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
*
*
******************************************************************************/
@@ -67,11 +68,22 @@ extern "C" {
#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
#define XIL_EXCEPTION_ID_FIRST 0U
+#if defined (__aarch64__)
#define XIL_EXCEPTION_ID_SYNC_INT 1U
#define XIL_EXCEPTION_ID_IRQ_INT 2U
#define XIL_EXCEPTION_ID_FIQ_INT 3U
#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
#define XIL_EXCEPTION_ID_LAST 5U
+#else
+#define XIL_EXCEPTION_ID_RESET 0U
+#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
+#define XIL_EXCEPTION_ID_SWI_INT 2U
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_IRQ_INT 5U
+#define XIL_EXCEPTION_ID_FIQ_INT 6U
+#define XIL_EXCEPTION_ID_LAST 6U
+#endif
/*
* XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
@@ -100,10 +112,16 @@ typedef void (*Xil_InterruptHandler)(void *data);
* C-Style signature: void Xil_ExceptionEnableMask(Mask)
*
******************************************************************************/
-
+#if defined (__GNUC__) || defined (__ICCARM__)
#define Xil_ExceptionEnableMask(Mask) \
mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
-
+#else
+#define Xil_ExceptionEnableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+ }
+#endif
/****************************************************************************/
/**
* Enable the IRQ exception.
@@ -128,10 +146,16 @@ typedef void (*Xil_InterruptHandler)(void *data);
* C-Style signature: Xil_ExceptionDisableMask(Mask)
*
******************************************************************************/
-
+#if defined (__GNUC__) || defined (__ICCARM__)
#define Xil_ExceptionDisableMask(Mask) \
mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
-
+#else
+#define Xil_ExceptionDisableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+ }
+#endif
/****************************************************************************/
/**
* Disable the IRQ exception.
@@ -144,7 +168,56 @@ typedef void (*Xil_InterruptHandler)(void *data);
#define Xil_ExceptionDisable() \
Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+#if !defined (__aarch64__) && !defined (ARMA53_32)
+/****************************************************************************/
+/**
+* Enable nested interrupts by clearing the I and F bits it CPSR
+*
+* @return None.
+*
+* @note This macro is supposed to be used from interrupt handlers. In the
+* interrupt handler the interrupts are disabled by default (I and F
+* are 1). To allow nesting of interrupts, this macro should be
+* used. It clears the I and F bits by changing the ARM mode to
+* system mode. Once these bits are cleared and provided the
+* preemption of interrupt conditions are met in the GIC, nesting of
+* interrupts will start happening.
+* Caution: This macro must be used with caution. Before calling this
+* macro, the user must ensure that the source of the current IRQ
+* is appropriately cleared. Otherwise, as soon as we clear the I and
+* F bits, there can be an infinite loop of interrupts with an
+* eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("mrs lr, spsr"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}");
+
+/****************************************************************************/
+/**
+* Disable the nested interrupts by setting the I and F bits.
+*
+* @return None.
+*
+* @note This macro is meant to be called in the interrupt service routines.
+* This macro cannot be used independently. It can only be used when
+* nesting of interrupts have been enabled by using the macro
+* Xil_EnableNestedInterrupts(). In a typical flow, the user first
+* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+* point. The user then must call this macro before exiting the interrupt
+* service routine. This macro puts the ARM back in IRQ/FIQ mode and
+* hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+#endif
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
@@ -156,10 +229,14 @@ extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
extern void Xil_ExceptionInit(void);
-
+#if defined (__aarch64__)
void Xil_SyncAbortHandler(void *CallBackRef);
-
void Xil_SErrorAbortHandler(void *CallBackRef);
+#else
+extern void Xil_DataAbortHandler(void *CallBackRef);
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
+#endif
#ifdef __cplusplus
}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_hal.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_hal.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_hal.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_hal.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/usleep.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_io.c
similarity index 60%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/usleep.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_io.c
index e512e3ea2..31de05581 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/usleep.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_io.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -32,10 +32,15 @@
/*****************************************************************************/
/**
*
-* @file usleep.c
+* @file xil_io.c
*
-* This function provides a microsecond delay using the Global Timer register in
-* the ARM Cortex A53 MP core.
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures. These functions encapsulate Cortex A53 architecture-specific
+* I/O requirements.
+*
+* @note
+*
+* This file contains architecture-dependent code.
*
*
* MODIFICATION HISTORY:
@@ -43,54 +48,60 @@
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
-* 5.04 pkp 01/28/16 Modified the usleep API to configure Time Stamp
-* generator only when disable using frequency from
-* xparamters.h instead of hardcoding
*
-*
******************************************************************************/
-/***************************** Include Files *********************************/
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-#include "xpseudo_asm.h"
-#include "xreg_cortexa53.h"
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_USECOND (COUNTS_PER_SECOND/1000000 )
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xil_assert.h"
/*****************************************************************************/
/**
*
-* This API gives a delay in microseconds
+* Perform a 16-bit endian converion.
*
-* @param useconds requested
+* @param Data contains the value to be converted.
*
-* @return 0 if the delay can be achieved, -1 if the requested delay
-* is out of range
+* @return converted value.
*
* @note None.
*
-****************************************************************************/
-s32 usleep(u32 useconds)
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
{
- XTime tEnd, tCur;
- /* Enable the counter only if it is disable */
- if(((Xil_In32(XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET)) & XIOU_SCNTRS_CNT_CNTRL_REG_EN_MASK) != XIOU_SCNTRS_CNT_CNTRL_REG_EN){
- /*write frequency to System Time Stamp Generator Register*/
- Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_FREQ_REG_OFFSET),XIOU_SCNTRS_FREQ);
+ return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 32-bit endian converion.
+*
+* @param Data contains the value to be converted.
+*
+* @return converted value.
+*
+* @note None.
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+ u16 LoWord;
+ u16 HiWord;
+
+ /* get each of the half words from the 32 bit word */
+
+ LoWord = (u16) (Data & 0x0000FFFFU);
+ HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+ /* byte swap each of the 16 bit half words */
- /*Enable the counter*/
- Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),XIOU_SCNTRS_CNT_CNTRL_REG_EN);
- }
+ LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+ HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
- XTime_GetTime(&tCur);
- tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
- do
- {
- XTime_GetTime(&tCur);
- } while (tCur < tEnd);
+ /* swap the half words before returning the value */
- return 0;
+ return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_io.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_io.h
similarity index 57%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_io.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_io.h
index b7eea5feb..06d89dcc3 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_io.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_io.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -32,15 +32,12 @@
/*****************************************************************************/
/**
*
-* @file xil_io.c
+* @file xil_io.h
*
-* Contains I/O functions for memory-mapped or non-memory-mapped I/O
-* architectures. These functions encapsulate Cortex A53 architecture-specific
-* I/O requirements.
+* This file contains the interface for the general IO component, which
+* encapsulates the Input/Output functions for processors that do not
+* require any special I/O handling.
*
-* @note
-*
-* This file contains architecture-dependent code.
*
*
* MODIFICATION HISTORY:
@@ -48,24 +45,56 @@
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
+* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+* ARM processors
*
******************************************************************************/
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
/***************************** Include Files *********************************/
-#include "xil_io.h"
+
#include "xil_types.h"
-#include "xil_assert.h"
-#include "xpseudo_asm.h"
-#include "xreg_cortexa53.h"
+#include "xil_printf.h"
-/************************** Constant Definitions *****************************/
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
+#include "xpseudo_asm.h"
+#endif
-/**************************** Type Definitions *******************************/
+/************************** Function Prototypes ******************************/
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+# define INST_SYNC mbar(0)
+# define DATA_SYNC mbar(1)
+# else
+# define SYNCHRONIZE_IO dmb()
+# define INST_SYNC isb()
+# define DATA_SYNC dsb()
+# endif
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+# define INST_SYNC
+# define DATA_SYNC
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline
+#else
+#define INLINE __inline
+#endif
/*****************************************************************************/
/**
@@ -81,7 +110,7 @@
* @note None.
*
******************************************************************************/
-u8 Xil_In8(INTPTR Addr)
+static INLINE u8 Xil_In8(UINTPTR Addr)
{
return *(volatile u8 *) Addr;
}
@@ -100,7 +129,7 @@ u8 Xil_In8(INTPTR Addr)
* @note None.
*
******************************************************************************/
-u16 Xil_In16(INTPTR Addr)
+static INLINE u16 Xil_In16(UINTPTR Addr)
{
return *(volatile u16 *) Addr;
}
@@ -119,7 +148,7 @@ u16 Xil_In16(INTPTR Addr)
* @note None.
*
******************************************************************************/
-u32 Xil_In32(INTPTR Addr)
+static INLINE u32 Xil_In32(UINTPTR Addr)
{
return *(volatile u32 *) Addr;
}
@@ -127,10 +156,10 @@ u32 Xil_In32(INTPTR Addr)
/*****************************************************************************/
/**
*
-* Performs an output operation for an 8-bit memory location by writing the
+* Performs an input operation for a 64-bit memory location by reading the
* specified Value to the the specified address.
*
-* @param Addr contains the address to perform the output operation
+* @param OutAddress contains the address to perform the output operation
* at.
* @param Value contains the Value to be output at the specified address.
*
@@ -139,16 +168,15 @@ u32 Xil_In32(INTPTR Addr)
* @note None.
*
******************************************************************************/
-void Xil_Out8(INTPTR Addr, u8 Value)
+static INLINE u64 Xil_In64(UINTPTR Addr)
{
- volatile u8 *LocalAddr = (u8 *)Addr;
- *LocalAddr = Value;
+ return *(volatile u64 *) Addr;
}
/*****************************************************************************/
/**
*
-* Performs an output operation for a 16-bit memory location by writing the
+* Performs an output operation for an 8-bit memory location by writing the
* specified Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
@@ -160,16 +188,16 @@ void Xil_Out8(INTPTR Addr, u8 Value)
* @note None.
*
******************************************************************************/
-void Xil_Out16(INTPTR Addr, u16 Value)
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
{
- volatile u16 *LocalAddr = (u16 *)Addr;
+ volatile u8 *LocalAddr = (volatile u8 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
-* Performs an output operation for a 32-bit memory location by writing the
+* Performs an output operation for a 16-bit memory location by writing the
* specified Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
@@ -181,16 +209,16 @@ void Xil_Out16(INTPTR Addr, u16 Value)
* @note None.
*
******************************************************************************/
-void Xil_Out32(INTPTR Addr, u32 Value)
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
{
- volatile u32 *LocalAddr = (u32 *)Addr;
+ volatile u16 *LocalAddr = (volatile u16 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
-* Performs an output operation for a 64-bit memory location by writing the
+* Performs an output operation for a 32-bit memory location by writing the
* specified Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
@@ -202,19 +230,19 @@ void Xil_Out32(INTPTR Addr, u32 Value)
* @note None.
*
******************************************************************************/
-void Xil_Out64(INTPTR Addr, u64 Value)
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
{
- volatile u64 *LocalAddr = (u64 *)Addr;
+ volatile u32 *LocalAddr = (volatile u32 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
-* Performs an input operation for a 64-bit memory location by reading the
+* Performs an output operation for a 64-bit memory location by writing the
* specified Value to the the specified address.
*
-* @param OutAddress contains the address to perform the output operation
+* @param Addr contains the address to perform the output operation
* at.
* @param Value contains the Value to be output at the specified address.
*
@@ -223,159 +251,101 @@ void Xil_Out64(INTPTR Addr, u64 Value)
* @note None.
*
******************************************************************************/
-u64 Xil_In64(INTPTR Addr)
-{
- return *(volatile u64 *) Addr;
-}
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for a 16-bit memory location by reading from the
-* specified address and returning the byte-swapped Value read from that
-* address.
-*
-* @param Addr contains the address to perform the input operation
-* at.
-*
-* @return The byte-swapped Value read from the specified input address.
-*
-* @note None.
-*
-******************************************************************************/
-u16 Xil_In16BE(INTPTR Addr)
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
{
- u16 temp;
- u16 result;
-
- temp = Xil_In16(Addr);
-
- result = Xil_EndianSwap16(temp);
-
- return result;
+ volatile u64 *LocalAddr = (volatile u64 *)Addr;
+ *LocalAddr = Value;
}
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for a 32-bit memory location by reading from the
-* specified address and returning the byte-swapped Value read from that
-* address.
-*
-* @param Addr contains the address to perform the input operation
-* at.
-*
-* @return The byte-swapped Value read from the specified input address.
-*
-* @note None.
-*
-******************************************************************************/
-u32 Xil_In32BE(INTPTR Addr)
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+# else
+# define Xil_In16BE Xil_In16
+# define Xil_In32BE Xil_In32
+# define Xil_Out16BE Xil_Out16
+# define Xil_Out32BE Xil_Out32
+# define Xil_Htons(Data) (Data)
+# define Xil_Htonl(Data) (Data)
+# define Xil_Ntohs(Data) (Data)
+# define Xil_Ntohl(Data) (Data)
+#endif
+#else
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
{
- u32 temp;
- u32 result;
-
- temp = Xil_In32(Addr);
-
- result = Xil_EndianSwap32(temp);
-
- return result;
+ u16 value = Xil_In16(Addr);
+ return Xil_EndianSwap16(value);
}
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for a 16-bit memory location by writing the
-* specified Value to the the specified address. The Value is byte-swapped
-* before being written.
-*
-* @param Addr contains the address to perform the output operation
-* at.
-* @param Value contains the Value to be output at the specified address.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void Xil_Out16BE(INTPTR Addr, u16 Value)
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
{
- u16 temp;
-
- temp = Xil_EndianSwap16(Value);
-
- Xil_Out16(Addr, temp);
+ u16 value = Xil_In32(Addr);
+ return Xil_EndianSwap32(value);
}
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for a 32-bit memory location by writing the
-* specified Value to the the specified address. The Value is byte-swapped
-* before being written.
-*
-* @param Addr contains the address to perform the output operation
-* at.
-* @param Value contains the Value to be output at the specified address.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void Xil_Out32BE(INTPTR Addr, u32 Value)
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#endif
+#else
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
{
- u32 temp;
-
- temp = Xil_EndianSwap32(Value);
-
- Xil_Out32(Addr, temp);
+ Value = Xil_EndianSwap16(Value);
+ Xil_Out16(Addr, Value);
}
-/*****************************************************************************/
-/**
-*
-* Perform a 16-bit endian converion.
-*
-* @param Data contains the value to be converted.
-*
-* @return converted value.
-*
-* @note None.
-*
-******************************************************************************/
-u16 Xil_EndianSwap16(u16 Data)
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#endif
+#else
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
{
- return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+ Value = Xil_EndianSwap32(Value);
+ Xil_Out32(Addr, Value);
}
-/*****************************************************************************/
-/**
-*
-* Perform a 32-bit endian converion.
-*
-* @param Data contains the value to be converted.
-*
-* @return converted value.
-*
-* @note None.
-*
-******************************************************************************/
-u32 Xil_EndianSwap32(u32 Data)
-{
- u16 LoWord;
- u16 HiWord;
-
- /* get each of the half words from the 32 bit word */
-
- LoWord = (u16) (Data & 0x0000FFFFU);
- HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
-
- /* byte swap each of the 16 bit half words */
-
- LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
- HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
-
- /* swap the half words before returning the value */
-
- return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+#ifdef __cplusplus
}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_macroback.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_macroback.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_macroback.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_macroback.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_mmu.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_mmu.c
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_mmu.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_mmu.c
index b16a77e4a..1e28b699c 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_mmu.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_mmu.c
@@ -58,7 +58,7 @@
#include "xpseudo_asm.h"
#include "xil_types.h"
#include "xil_mmu.h"
-
+#include "bspconfig.h"
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
@@ -111,6 +111,7 @@ void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib)
*ptr = (Addr & (~(block_size-1))) | attrib;
Xil_DCacheFlush();
+
mtcptlbi(ALLE3);
dsb(); /* ensure completion of the BP and TLB invalidation */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_mmu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_mmu.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_mmu.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_mmu.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_printf.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_printf.c
similarity index 87%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_printf.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_printf.c
index 964dc14db..9dffed148 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_printf.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_printf.c
@@ -12,6 +12,10 @@
#include
#include
+static void padding( const s32 l_flag,const struct params_s *par);
+static void outs(const charptr lp, struct params_s *par);
+static s32 getnum( charptr* linep);
+
typedef struct params_s {
s32 len;
s32 num1;
@@ -22,9 +26,6 @@ typedef struct params_s {
s32 unsigned_flag;
} params_t;
-static void padding( const s32 l_flag,const params_t *par);
-static void outs(const charptr lp, params_t *par);
-static s32 getnum( charptr* linep);
/*---------------------------------------------------*/
/* The purpose of this routine is to output data the */
@@ -40,14 +41,16 @@ static s32 getnum( charptr* linep);
/* This routine puts pad characters into the output */
/* buffer. */
/* */
-static void padding( const s32 l_flag, const params_t *par)
+static void padding( const s32 l_flag, const struct params_s *par)
{
s32 i;
if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
i=(par->len);
for (; i<(par->num1); i++) {
+#ifdef STDOUT_BASEADDRESS
outbyte( par->pad_character);
+#endif
}
}
}
@@ -57,7 +60,7 @@ static void padding( const s32 l_flag, const params_t *par)
/* This routine moves a string to the output buffer */
/* as directed by the padding and positioning flags. */
/* */
-static void outs(const charptr lp, params_t *par)
+static void outs(const charptr lp, struct params_s *par)
{
charptr LocalPtr;
LocalPtr = lp;
@@ -70,8 +73,10 @@ static void outs(const charptr lp, params_t *par)
/* Move string to the buffer */
while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
(par->num2)--;
+#ifdef STDOUT_BASEADDRESS
outbyte(*LocalPtr);
LocalPtr += 1;
+#endif
}
/* Pad on right if needed */
@@ -86,9 +91,8 @@ static void outs(const charptr lp, params_t *par)
/* as directed by the padding and positioning flags. */
/* */
-static void outnum( const s32 n, const s32 base, params_t *par)
+static void outnum( const s32 n, const s32 base, struct params_s *par)
{
- charptr cp;
s32 negative;
s32 i;
char8 outbuf[32];
@@ -104,7 +108,7 @@ static void outnum( const s32 n, const s32 base, params_t *par)
num =(-(n));
}
else{
- num = (n);
+ num = n;
negative = 0;
}
@@ -129,22 +133,22 @@ static void outnum( const s32 n, const s32 base, params_t *par)
par->len = (s32)strlen(outbuf);
padding( !(par->left_flag), par);
while (&outbuf[i] >= outbuf) {
+#ifdef STDOUT_BASEADDRESS
outbyte( outbuf[i] );
i--;
+#endif
}
padding( par->left_flag, par);
}
-
/*---------------------------------------------------*/
/* */
/* This routine moves a 64-bit number to the output */
/* buffer as directed by the padding and positioning */
/* flags. */
/* */
-
+#if defined (__aarch64__)
static void outnum1( const s64 n, const s32 base, params_t *par)
{
- charptr cp;
s32 negative;
s32 i;
char8 outbuf[64];
@@ -190,6 +194,7 @@ static void outnum1( const s64 n, const s32 base, params_t *par)
}
padding( par->left_flag, par);
}
+#endif
/*---------------------------------------------------*/
/* */
/* This routine gets a number from the format */
@@ -237,7 +242,9 @@ static s32 getnum( charptr* linep)
void xil_printf( const char8 *ctrl1, ...)
{
s32 Check;
+#if defined (__aarch64__)
s32 long_flag;
+#endif
s32 dot_flag;
params_t par;
@@ -253,14 +260,18 @@ void xil_printf( const char8 *ctrl1, ...)
/* move format string chars to buffer until a */
/* format control is found. */
if (*ctrl != '%') {
+#ifdef STDOUT_BASEADDRESS
outbyte(*ctrl);
ctrl += 1;
+#endif
continue;
}
/* initialize all the flags for this format. */
dot_flag = 0;
+#if defined (__aarch64__)
long_flag = 0;
+#endif
par.unsigned_flag = 0;
par.left_flag = 0;
par.do_padding = 0;
@@ -301,7 +312,9 @@ void xil_printf( const char8 *ctrl1, ...)
switch (tolower((s32)ch)) {
case '%':
+#ifdef STDOUT_BASEADDRESS
outbyte( '%');
+#endif
Check = 1;
break;
@@ -316,7 +329,9 @@ void xil_printf( const char8 *ctrl1, ...)
break;
case 'l':
+ #if defined (__aarch64__)
long_flag = 1;
+ #endif
Check = 0;
break;
@@ -325,27 +340,38 @@ void xil_printf( const char8 *ctrl1, ...)
/* fall through */
case 'i':
case 'd':
+ #if defined (__aarch64__)
if (long_flag != 0){
- outnum1((s64)va_arg(argp, s64), 10L, &par);
+ outnum1((s64)va_arg(argp, s64), 10L, &par);
}
else {
outnum( va_arg(argp, s32), 10L, &par);
}
+ #else
+ outnum( va_arg(argp, s32), 10L, &par);
+ #endif
Check = 1;
break;
case 'p':
+ #if defined (__aarch64__)
par.unsigned_flag = 1;
- outnum1((s64)va_arg(argp, s64), 16L, &par);
- Check = 1;
+ outnum1((s64)va_arg(argp, s64), 16L, &par);
+ Check = 1;
break;
+ #endif
+ case 'X':
case 'x':
par.unsigned_flag = 1;
+ #if defined (__aarch64__)
if (long_flag != 0) {
- outnum1((s64)va_arg(argp, s64), 16L, &par);
- }
- else {
- outnum((s32)va_arg(argp, s32), 16L, &par);
+ outnum1((s64)va_arg(argp, s64), 16L, &par);
+ }
+ else {
+ outnum((s32)va_arg(argp, s32), 16L, &par);
}
+ #else
+ outnum((s32)va_arg(argp, s32), 16L, &par);
+ #endif
Check = 1;
break;
@@ -355,27 +381,39 @@ void xil_printf( const char8 *ctrl1, ...)
break;
case 'c':
+#ifdef STDOUT_BASEADDRESS
outbyte( va_arg( argp, s32));
+#endif
Check = 1;
break;
case '\\':
switch (*ctrl) {
case 'a':
+#ifdef STDOUT_BASEADDRESS
outbyte( ((char8)0x07));
+#endif
break;
case 'h':
+#ifdef STDOUT_BASEADDRESS
outbyte( ((char8)0x08));
+#endif
break;
case 'r':
+#ifdef STDOUT_BASEADDRESS
outbyte( ((char8)0x0D));
+#endif
break;
case 'n':
+#ifdef STDOUT_BASEADDRESS
outbyte( ((char8)0x0D));
outbyte( ((char8)0x0A));
+#endif
break;
default:
+#ifdef STDOUT_BASEADDRESS
outbyte( *ctrl);
+#endif
break;
}
ctrl += 1;
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_printf.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_printf.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_printf.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_printf.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_testcache.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testcache.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_testcache.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testcache.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_testcache.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testcache.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_testcache.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testcache.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_testio.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testio.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_testio.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testio.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_testio.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testio.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_testio.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testio.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_testmem.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testmem.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_testmem.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testmem.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_testmem.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testmem.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_testmem.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testmem.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_types.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_types.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xil_types.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_types.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xparameters_ps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xparameters_ps.h
similarity index 82%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xparameters_ps.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xparameters_ps.h
index 601056206..708160962 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xparameters_ps.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xparameters_ps.h
@@ -89,10 +89,9 @@ extern "C" {
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
-#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
+#define XPAR_XWDTPS_0_INTR XPS_LPD_SWDT_INT_ID
+#define XPAR_XWDTPS_1_INTR XPS_FPD_SWDT_INT_ID
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
-#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
-#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
@@ -105,15 +104,6 @@ extern "C" {
#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID
#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID
#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID
-#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID
#define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID
#define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID
@@ -168,28 +158,22 @@ extern "C" {
/* Shared Peripheral Interrupts (SPI) */
-
-/* FIXME */
-/*#define XPS_FPGA0_INT_ID 100U */
-#define XPS_FPGA1_INT_ID 62U
-#define XPS_FPGA2_INT_ID 63U
-#define XPS_FPGA3_INT_ID 64U
-#define XPS_FPGA4_INT_ID 65U
-#define XPS_FPGA5_INT_ID 66U
-#define XPS_FPGA6_INT_ID 67U
-#define XPS_FPGA7_INT_ID 68U
-#define XPS_DMA4_INT_ID 72U
-#define XPS_DMA5_INT_ID 73U
-#define XPS_DMA6_INT_ID 74U
-#define XPS_DMA7_INT_ID 75U
-#define XPS_FPGA8_INT_ID 84U
-#define XPS_FPGA9_INT_ID 85U
-#define XPS_FPGA10_INT_ID 86U
-#define XPS_FPGA11_INT_ID 87U
-#define XPS_FPGA12_INT_ID 88U
-#define XPS_FPGA13_INT_ID 89U
-#define XPS_FPGA14_INT_ID 90U
-#define XPS_FPGA15_INT_ID 91U
+#define XPS_FPGA0_INT_ID 121U
+#define XPS_FPGA1_INT_ID 122U
+#define XPS_FPGA2_INT_ID 123U
+#define XPS_FPGA3_INT_ID 124U
+#define XPS_FPGA4_INT_ID 125U
+#define XPS_FPGA5_INT_ID 126U
+#define XPS_FPGA6_INT_ID 127U
+#define XPS_FPGA7_INT_ID 128U
+#define XPS_FPGA8_INT_ID 136U
+#define XPS_FPGA9_INT_ID 137U
+#define XPS_FPGA10_INT_ID 138U
+#define XPS_FPGA11_INT_ID 139U
+#define XPS_FPGA12_INT_ID 140U
+#define XPS_FPGA13_INT_ID 141U
+#define XPS_FPGA14_INT_ID 142U
+#define XPS_FPGA15_INT_ID 143U
/* Updated Interrupt-IDs */
#define XPS_OCMINTR_INT_ID (10U + 32U)
@@ -206,7 +190,8 @@ extern "C" {
#define XPS_CAN1_INT_ID (24U + 32U)
#define XPS_RTC_ALARM_INT_ID (26U + 32U)
#define XPS_RTC_SEC_INT_ID (27U + 32U)
-#define XPS_WDT_INT_ID (52U + 32U)
+#define XPS_LPD_SWDT_INT_ID (52U + 32U)
+#define XPS_FPD_SWDT_INT_ID (113U + 32U)
#define XPS_TTC0_0_INT_ID (36U + 32U)
#define XPS_TTC0_1_INT_ID (37U + 32U)
#define XPS_TTC0_2_INT_ID (38U + 32U)
@@ -259,33 +244,6 @@ extern "C" {
#define XPS_APM5_INT_ID (123U + 32U)
/* REDEFINES for TEST APP */
-/* Definitions for UART */
-#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
-#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
-#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
-#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
-#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
-#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
-#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
-#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
-#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
-#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
-#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
-#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
-#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
-#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
-#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
-#define XPAR_PS7_ETHERNET_2_INTR XPS_GEM2_INT_ID
-#define XPAR_PS7_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
-#define XPAR_PS7_ETHERNET_3_INTR XPS_GEM3_INT_ID
-#define XPAR_PS7_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
-
-#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
-#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
-#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
-#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
-#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
-
#define XPAR_PSU_UART_0_INTR XPS_UART0_INT_ID
#define XPAR_PSU_UART_1_INTR XPS_UART1_INT_ID
#define XPAR_PSU_USB_0_INTR XPS_USB0_INT_ID
@@ -306,9 +264,8 @@ extern "C" {
#define XPAR_PSU_ETHERNET_3_INTR XPS_GEM3_INT_ID
#define XPAR_PSU_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
#define XPAR_PSU_QSPI_0_INTR XPS_QSPI_INT_ID
-#define XPAR_PSU_WDT_0_INTR XPS_WDT_INT_ID
-#define XPAR_PSU_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
-#define XPAR_PSU_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_PSU_WDT_0_INTR XPS_LPD_SWDT_INT_ID
+#define XPAR_PSU_WDT_1_INTR XPS_FPD_SWDT_INT_ID
#define XPAR_PSU_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_PSU_TTC_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_PSU_TTC_1_INTR XPS_TTC0_1_INT_ID
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xplatform_info.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xplatform_info.c
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xplatform_info.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xplatform_info.c
index fea992e40..9d4560a98 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xplatform_info.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xplatform_info.c
@@ -44,6 +44,7 @@
* 5.00 pkp 12/15/14 Initial release
* 5.04 pkp 01/12/16 Added platform information support for Cortex-A53 32bit
* mode
+* 6.00 mus 17/08/16 Removed unused variable from XGetPlatform_Info
*
*
******************************************************************************/
@@ -51,6 +52,7 @@
/***************************** Include Files *********************************/
#include "xil_types.h"
+#include "xil_io.h"
#include "xplatform_info.h"
/************************** Constant Definitions *****************************/
@@ -78,7 +80,7 @@
******************************************************************************/
u32 XGetPlatform_Info()
{
- u32 reg;
+
#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
return XPLAT_ZYNQ_ULTRA_MP;
#elif (__microblaze__)
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xplatform_info.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xplatform_info.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xplatform_info.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xplatform_info.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xpseudo_asm.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xpseudo_asm.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xpseudo_asm.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xpseudo_asm.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h
similarity index 65%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h
index 58dd8abcc..b475c90e7 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -43,6 +43,7 @@
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/21/14 First release
+* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
*
*
******************************************************************************/
@@ -68,13 +69,14 @@ extern "C" {
#define stringify(s) tostring(s)
#define tostring(s) #s
+#if defined (__aarch64__)
/* pseudo assembler instructions */
#define mfcpsr() ({u32 rval; \
asm volatile("mrs %0, DAIF" : "=r" (rval));\
rval;\
})
-#define mtcpsr(v) asm ("msr DAIF, %0" : : "r" (v))
+#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
#define cpsiei() //__asm__ __volatile__("cpsie i\n")
#define cpsidi() //__asm__ __volatile__("cpsid i\n")
@@ -100,13 +102,13 @@ extern "C" {
/* memory synchronization operations */
/* Instruction Synchronization Barrier */
-#define isb() asm ("isb sy")
+#define isb() __asm__ __volatile__ ("isb sy")
/* Data Synchronization Barrier */
-#define dsb() asm("dsb sy")
+#define dsb() __asm__ __volatile__("dsb sy")
/* Data Memory Barrier */
-#define dmb() asm("dmb sy")
+#define dmb() __asm__ __volatile__("dmb sy")
/* Memory Operations */
@@ -118,6 +120,66 @@ extern "C" {
rval;\
})
+#else
+
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval; \
+ __asm__ __volatile__(\
+ "mrs %0, cpsr\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__(\
+ "msr cpsr,%0\n"\
+ : : "r" (v)\
+ )
+
+#define cpsiei() __asm__ __volatile__("cpsie i\n")
+#define cpsidi() __asm__ __volatile__("cpsid i\n")
+
+#define cpsief() __asm__ __volatile__("cpsie f\n")
+#define cpsidf() __asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) __asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )
+
+#define mfgpr(rn) ({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u32 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#endif
+
#define ldrb(adr) ({u8 rval; \
__asm__ __volatile__(\
"ldrb %0,[%1]"\
@@ -144,19 +206,37 @@ extern "C" {
);\
rval;\
})
-#define mtcpdc(reg,val) asm("dc " #reg ",%0" : : "r" (val))
-#define mtcpic(reg,val) asm("ic " #reg ",%0" : : "r" (val))
-#define mtcpicall(reg) asm("ic " #reg)
-#define mtcptlbi(reg) asm("tlbi " #reg)
-#define mtcpat(reg,val) asm("at " #reg ",%0" : : "r" (val))
+#if defined (__aarch64__)
+#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val))
+#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val))
+
+#define mtcpicall(reg) __asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val))
/* CP15 operations */
#define mfcp(reg) ({u64 rval;\
- asm("mrs %0, " #reg : "=r" (rval));\
+ __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
rval;\
})
-#define mtcp(reg,val) asm("msr " #reg ",%0" : : "r" (val))
+#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val))
+
+#else
+/* CP15 operations */
+#define mtcp(rn, v) __asm__ __volatile__(\
+ "mcr " rn "\n"\
+ : : "r" (v)\
+ );
+
+#define mfcp(rn) ({u32 rval; \
+ __asm__ __volatile__(\
+ "mrc " rn "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+#endif
/************************** Variable Definitions ****************************/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xreg_cortexa53.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xreg_cortexa53.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xreg_cortexa53.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xreg_cortexa53.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xstatus.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xstatus.h
similarity index 98%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xstatus.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xstatus.h
index ba5f96b20..4873e85eb 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xstatus.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xstatus.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -303,6 +303,8 @@ extern "C" {
#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */
#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE 1163 /* controller completed polling the
+ device for status */
/********************** OPB Arbiter statuses 1176 - 1200 *********************/
@@ -416,7 +418,7 @@ extern "C" {
/**************************** Type Definitions *******************************/
-typedef int XStatus;
+typedef s32 XStatus;
/***************** Macros (Inline Functions) Definitions *********************/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xtime_l.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xtime_l.c
similarity index 75%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xtime_l.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xtime_l.c
index 162b3ff74..e9998969c 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xtime_l.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xtime_l.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -41,7 +41,10 @@
*
* Ver Who Date Changes
* ----- ------ -------- ---------------------------------------------------
-* 5.00 pkp 05/29/14 First release
+* 5.00 pkp 05/29/14 First release
+* 5.05 pkp 04/13/16 Added XTime_StartTimer API to start the global timer
+* counter if it is disabled. Also XTime_GetTime calls
+* this API to ensure the global timer counter is enabled
*
*
* @note None.
@@ -54,6 +57,7 @@
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
+#include "bspconfig.h"
/***************** Macros (Inline Functions) Definitions *********************/
@@ -65,6 +69,31 @@
/************************** Function Prototypes ******************************/
+/****************************************************************************
+*
+* Start the Global Timer Counter.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XTime_StartTimer(void)
+{
+ /* Enable the global timer counter only if it is disabled */
+ if(((Xil_In32(XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET))
+ & XIOU_SCNTRS_CNT_CNTRL_REG_EN_MASK) !=
+ XIOU_SCNTRS_CNT_CNTRL_REG_EN){
+ /*write frequency to System Time Stamp Generator Register*/
+ Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_FREQ_REG_OFFSET),
+ XIOU_SCNTRS_FREQ);
+ /*Enable the timer/counter*/
+ Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),
+ XIOU_SCNTRS_CNT_CNTRL_REG_EN);
+ }
+}
/****************************************************************************
*
* Set the time in the Global Timer Counter Register.
@@ -96,5 +125,8 @@ so the API is left unimplemented*/
****************************************************************************/
void XTime_GetTime(XTime *Xtime_Global)
{
+ /* Start global timer counter, it will only be enabled if it is disabled */
+ XTime_StartTimer();
+
*Xtime_Global = mfcp(CNTPCT_EL0);
}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xtime_l.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xtime_l.h
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xtime_l.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xtime_l.h
index e03cbb50d..489be3559 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/xtime_l.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xtime_l.h
@@ -66,7 +66,6 @@ typedef u64 XTime;
/************************** Constant Definitions *****************************/
#define COUNTS_PER_SECOND XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
-
#define XIOU_SCNTRS_BASEADDR 0xFF260000U
#define XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET 0x00000000U
#define XIOU_SCNTRS_FREQ_REG_OFFSET 0x00000020U
@@ -77,6 +76,7 @@ typedef u64 XTime;
/************************** Function Prototypes ******************************/
+void XTime_StartTimer(void);
void XTime_SetTime(XTime Xtime_Global);
void XTime_GetTime(XTime *Xtime_Global);
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/Makefile
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/Makefile
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c
similarity index 93%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c
index a30a257fb..b047a4599 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c
@@ -51,6 +51,16 @@
* 03/03/16 Added Temperature remote channel for Setsingle
* channel API. Also corrected external mux channel
* numbers.
+* 1.1 kvn 05/05/16 Modified code for MISRA-C:2012 Compliance.
+* 2.0 vns 08/14/16 Fixed CR #956780, added support for enabling/disabling
+* SEQ_CH2 and SEQ_AVG2 registers, modified function
+* prototypes of XSysMonPsu_GetSeqAvgEnables,
+* XSysMonPsu_SetSeqAvgEnables, XSysMonPsu_SetSeqChEnables,
+* XSysMonPsu_GetSeqChEnables,
+* XSysMonPsu_SetSeqInputMode, XSysMonPsu_GetSeqInputMode,
+* XSysMonPsu_SetSeqAcqTime
+* and XSysMonPsu_GetSeqAcqTime to provide support for
+* set/get 64 bit value.
*
*
*
@@ -148,7 +158,6 @@ s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigP
* function will be called.
*
* @param CallBackRef is unused by this function.
-* @param Event is unused by this function.
*
* @return None.
*
@@ -575,11 +584,6 @@ s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel,
(IsDifferentialMode == FALSE));
Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
- /* Calculate the effective baseaddress based on the Sysmon instance. */
- EffectiveBaseAddress =
- XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
- SysmonBlk);
-
/* Check if the device is in single channel mode else return failure */
if ((XSysMonPsu_GetSequencerMode(InstancePtr, SysmonBlk)
!= XSM_SEQ_MODE_SINGCHAN)) {
@@ -587,6 +591,11 @@ s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel,
goto End;
}
+ /* Calculate the effective baseaddress based on the Sysmon instance. */
+ EffectiveBaseAddress =
+ XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+ SysmonBlk);
+
/* Read the Configuration Register 0 and extract out Averaging value. */
RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
XSYSMONPSU_CFG_REG0_OFFSET) & XSYSMONPSU_CFG_REG0_AVRGNG_MASK;
@@ -653,10 +662,11 @@ End:
*
* @param InstancePtr is a pointer to the XSysMonPsu instance.
* @param AlmEnableMask is the bit-mask of the alarm outputs to be enabled
-* in the Configuration Register 1.
+* in the Configuration Registers 1 and 3.
* Bit positions of 1 will be enabled. Bit positions of 0 will be
* disabled. This mask is formed by OR'ing XSYSMONPSU_CFR_REG1_ALRM_*_MASK
-* masks defined in xsysmonpsu.h.
+* masks defined in xsysmonpsu.h, but XSM_CFR_ALM_SUPPLY8_MASK to
+* XSM_CFR_ALM_SUPPLY13_MASK are applicable only for PS.
* @param SysmonBlk is the value that tells whether it is for PS Sysmon
* block or PL Sysmon block register region.
*
@@ -668,6 +678,7 @@ End:
* The alarm outputs specified by the AlmEnableMask are negated
* before writing to the Configuration Register 1 because it
* was Disable register bits.
+* Upper 16 bits of AlmEnableMask are applicable only for PS.
*
*****************************************************************************/
void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
@@ -679,7 +690,9 @@ void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
/* Assert the arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(AlmEnableMask <= XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
+ Xil_AssertVoid(AlmEnableMask <=
+ (XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK |
+ (XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK << XSM_CFG_ALARM_SHIFT)));
Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
/* Calculate the effective baseaddress based on the Sysmon instance. */
@@ -698,6 +711,16 @@ void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
*/
XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG1_OFFSET,
RegValue);
+ /* Upper 16 bits of AlmEnableMask are valid only for PS */
+ if (SysmonBlk == XSYSMON_PS) {
+ RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+ XSYSMONPSU_CFG_REG3_OFFSET);
+ RegValue &= (u32)(~XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
+ RegValue |= (~(AlmEnableMask >> XSM_CFG_ALARM_SHIFT) &
+ (u32)XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
+ XSysmonPsu_WriteReg(EffectiveBaseAddress +
+ XSYSMONPSU_CFG_REG3_OFFSET, RegValue);
+ }
}
/****************************************************************************/
@@ -723,13 +746,15 @@ void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
* be disabled and alarms for bit positions of 0 will be enabled.
* The enabled alarm outputs returned by this function is the
* negated value of the the data read from the Configuration
-* Register 1.
+* Register 1. Upper 16 bits of return value are valid only if the
+* channel selected is PS.
*
*****************************************************************************/
u32 XSysMonPsu_GetAlarmEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
{
u32 RegValue;
u32 EffectiveBaseAddress;
+ u32 ReadReg;
/* Assert the arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
@@ -749,6 +774,13 @@ u32 XSysMonPsu_GetAlarmEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
XSYSMONPSU_CFG_REG1_OFFSET) & XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK;
RegValue = (~RegValue & XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
+ if (SysmonBlk == XSYSMON_PS) {
+ ReadReg = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+ XSYSMONPSU_CFG_REG3_OFFSET) & XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK;
+ ReadReg = (~ReadReg & XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
+ RegValue |= ReadReg << XSM_CFG_ALARM_SHIFT;
+ }
+
return RegValue;
}
@@ -1143,7 +1175,7 @@ u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk)
* Use XSYSMONPSU_SEQ_CH* defined in xsysmon_hw.h to specify the Channel
* numbers. Bit masks of 1 will be enabled and bit mask of 0 will
* be disabled.
-* The ChEnableMask is a 32 bit mask that is written to the two
+* The ChEnableMask is a 64 bit mask that is written to the three
* 16 bit ADC Channel Selection Sequencer Registers.
* @param SysmonBlk is the value that tells whether it is for PS Sysmon
* block or PL Sysmon block register region.
@@ -1156,7 +1188,7 @@ u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk)
* @note None.
*
*****************************************************************************/
-s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u32 ChEnableMask,
+s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u64 ChEnableMask,
u32 SysmonBlk)
{
s32 Status;
@@ -1193,6 +1225,10 @@ s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u32 ChEnableMask,
(ChEnableMask >> XSM_SEQ_CH_SHIFT) &
XSYSMONPSU_SEQ_CH1_VALID_MASK);
+ XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH2_OFFSET,
+ (ChEnableMask >> XSM_SEQ_CH2_SHIFT) &
+ XSYSMONPSU_SEQ_CH2_VALID_MASK);
+
Status = (s32)XST_SUCCESS;
End:
@@ -1219,9 +1255,9 @@ End:
* @note None.
*
*****************************************************************************/
-u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+u64 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
{
- u32 RegVal;
+ u64 RegVal;
u32 EffectiveBaseAddress;
/* Assert the arguments. */
@@ -1243,6 +1279,9 @@ u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
RegVal |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
XSYSMONPSU_SEQ_CH1_OFFSET) & XSYSMONPSU_SEQ_CH1_VALID_MASK) <<
XSM_SEQ_CH_SHIFT;
+ RegVal |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
+ XSYSMONPSU_SEQ_CH2_OFFSET) &
+ XSYSMONPSU_SEQ_CH2_VALID_MASK) << XSM_SEQ_CH2_SHIFT;
return RegVal;
}
@@ -1259,8 +1298,8 @@ u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
* averaging is to be enabled. Use XSYSMONPSU_SEQ_AVERAGE* defined in
* xsysmonpsu_hw.h to specify the Channel numbers. Averaging will be
* enabled for bit masks of 1 and disabled for bit mask of 0.
-* The AvgEnableChMask is a 32 bit mask that is written to the
-* two 16 bit ADC Channel Averaging Enable Sequencer Registers.
+* The AvgEnableChMask is a 64 bit mask that is written to the
+* three 16 bit ADC Channel Averaging Enable Sequencer Registers.
* @param SysmonBlk is the value that tells whether it is for PS Sysmon
* block or PL Sysmon block register region.
*
@@ -1272,7 +1311,7 @@ u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
* @note None.
*
*****************************************************************************/
-s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 AvgEnableChMask,
+s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u64 AvgEnableChMask,
u32 SysmonBlk)
{
s32 Status;
@@ -1283,11 +1322,6 @@ s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 AvgEnableChMask,
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
- /* Calculate the effective baseaddress based on the Sysmon instance. */
- EffectiveBaseAddress =
- XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
- SysmonBlk);
-
/*
* The sequencer must be disabled for writing any of these registers.
* Return XST_FAILURE if the channel sequencer is enabled.
@@ -1295,24 +1329,32 @@ s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 AvgEnableChMask,
if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
!= XSM_SEQ_MODE_SAFE)) {
Status = (s32)XST_FAILURE;
- goto End;
+ } else {
+ /* Calculate the effective baseaddress based on the Sysmon instance. */
+ EffectiveBaseAddress =
+ XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+ SysmonBlk);
+ /*
+ * Enable/disable the averaging for the specified channels in the
+ * ADC Channel Averaging Enables Sequencer Registers.
+ */
+ XSysmonPsu_WriteReg(EffectiveBaseAddress +
+ XSYSMONPSU_SEQ_AVERAGE0_OFFSET,
+ (AvgEnableChMask & XSYSMONPSU_SEQ_AVERAGE0_MASK));
+
+ XSysmonPsu_WriteReg(EffectiveBaseAddress +
+ XSYSMONPSU_SEQ_AVERAGE1_OFFSET,
+ (AvgEnableChMask >> XSM_SEQ_CH_SHIFT) &
+ XSYSMONPSU_SEQ_AVERAGE1_MASK);
+
+ XSysmonPsu_WriteReg(EffectiveBaseAddress +
+ XSYSMONPSU_SEQ_AVERAGE2_OFFSET,
+ (AvgEnableChMask >> XSM_SEQ_CH2_SHIFT) &
+ XSYSMONPSU_SEQ_AVERAGE2_MASK);
+
+ Status = (s32)XST_SUCCESS;
}
- /*
- * Enable/disable the averaging for the specified channels in the
- * ADC Channel Averaging Enables Sequencer Registers.
- */
- XSysmonPsu_WriteReg(EffectiveBaseAddress +
- XSYSMONPSU_SEQ_AVERAGE0_OFFSET,
- (AvgEnableChMask & XSYSMONPSU_SEQ_AVERAGE0_MASK));
-
- XSysmonPsu_WriteReg(EffectiveBaseAddress +
- XSYSMONPSU_SEQ_AVERAGE1_OFFSET,
- (AvgEnableChMask >> XSM_SEQ_CH_SHIFT) &
- XSYSMONPSU_SEQ_AVERAGE1_MASK);
-
- Status = (s32)XST_SUCCESS;
-End:
return Status;
}
@@ -1335,9 +1377,9 @@ End:
* @note None.
*
*****************************************************************************/
-u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+u64 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
{
- u32 RegVal;
+ u64 RegVal;
u32 EffectiveBaseAddress;
/* Assert the arguments. */
@@ -1359,6 +1401,9 @@ u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
RegVal |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
XSYSMONPSU_SEQ_AVERAGE1_OFFSET) & XSYSMONPSU_SEQ_AVERAGE1_MASK) <<
XSM_SEQ_CH_SHIFT;
+ RegVal |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
+ XSYSMONPSU_SEQ_AVERAGE2_OFFSET) &
+ XSYSMONPSU_SEQ_AVERAGE2_MASK) << XSM_SEQ_CH2_SHIFT;
return RegVal;
}
@@ -1376,7 +1421,7 @@ u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
* defined in xsysmonpsu_hw.h to specify the channel numbers. Differential
* or Bipolar input mode will be set for bit masks of 1 and unipolar input
* mode for bit masks of 0.
-* The InputModeChMask is a 32 bit mask that is written to the two
+* The InputModeChMask is a 64 bit mask that is written to the three
* 16 bit ADC Channel Analog-Input Mode Sequencer Registers.
* @param SysmonBlk is the value that tells whether it is for PS Sysmon
* block or PL Sysmon block register region.
@@ -1389,7 +1434,7 @@ u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
* @note None.
*
*****************************************************************************/
-s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u32 InputModeChMask,
+s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u64 InputModeChMask,
u32 SysmonBlk)
{
s32 Status;
@@ -1429,6 +1474,11 @@ s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u32 InputModeChMask,
(InputModeChMask >> XSM_SEQ_CH_SHIFT) &
XSYSMONPSU_SEQ_INPUT_MDE1_MASK);
+ XSysmonPsu_WriteReg(EffectiveBaseAddress +
+ XSYSMONPSU_SEQ_INPUT_MDE2_OFFSET,
+ (InputModeChMask >> XSM_SEQ_CH2_SHIFT) &
+ XSYSMONPSU_SEQ_INPUT_MDE2_MASK);
+
Status = (s32)XST_SUCCESS;
End:
@@ -1454,9 +1504,9 @@ End:
* @note None.
*
*****************************************************************************/
-u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+u64 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
{
- u32 InputMode;
+ u64 InputMode;
u32 EffectiveBaseAddress;
/* Assert the arguments. */
@@ -1478,6 +1528,9 @@ u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
InputMode |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
XSYSMONPSU_SEQ_INPUT_MDE1_OFFSET) & XSYSMONPSU_SEQ_INPUT_MDE1_MASK) <<
XSM_SEQ_CH_SHIFT;
+ InputMode |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
+ XSYSMONPSU_SEQ_INPUT_MDE2_OFFSET) &
+ XSYSMONPSU_SEQ_INPUT_MDE2_MASK) << XSM_SEQ_CH2_SHIFT;
return InputMode;
}
@@ -1496,7 +1549,7 @@ u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
* numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
* for bit masks of 1 and will be the default 4 ADCCLK cycles for
* bit masks of 0.
-* The AcqCyclesChMask is a 32 bit mask that is written to the two
+* The AcqCyclesChMask is a 64 bit mask that is written to the three
* 16 bit ADC Channel Acquisition Time Sequencer Registers.
* @param SysmonBlk is the value that tells whether it is for PS Sysmon
* block or PL Sysmon block register region.
@@ -1509,7 +1562,7 @@ u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
* @note None.
*
*****************************************************************************/
-s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u32 AcqCyclesChMask,
+s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u64 AcqCyclesChMask,
u32 SysmonBlk)
{
s32 Status;
@@ -1546,6 +1599,10 @@ s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u32 AcqCyclesChMask,
XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ1_OFFSET,
(AcqCyclesChMask >> XSM_SEQ_CH_SHIFT) & XSYSMONPSU_SEQ_ACQ1_MASK);
+ XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ2_OFFSET,
+ (AcqCyclesChMask >> XSM_SEQ_CH2_SHIFT) &
+ XSYSMONPSU_SEQ_ACQ2_MASK);
+
Status = (s32)XST_SUCCESS;
End:
@@ -1571,9 +1628,9 @@ End:
* @note None.
*
*****************************************************************************/
-u32 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+u64 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk)
{
- u32 RegValAcq;
+ u64 RegValAcq;
u32 EffectiveBaseAddress;
/* Assert the arguments. */
@@ -1595,6 +1652,9 @@ u32 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk)
RegValAcq |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
XSYSMONPSU_SEQ_ACQ1_OFFSET) & XSYSMONPSU_SEQ_ACQ1_MASK) <<
XSM_SEQ_CH_SHIFT;
+ RegValAcq |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
+ XSYSMONPSU_SEQ_ACQ2_OFFSET) &
+ XSYSMONPSU_SEQ_ACQ2_MASK) << XSM_SEQ_CH2_SHIFT;
return RegValAcq;
}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h
similarity index 92%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h
index ae55db9ce..ba090c5aa 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h
@@ -151,6 +151,18 @@
* 03/03/16 Added Temperature remote channel for Setsingle
* channel API. Also corrected external mux channel
* numbers.
+* 1.1 kvn 05/05/16 Modified code for MISRA-C:2012 Compliance.
+* 2.0 vns 08/14/16 Fixed CR #956780, added support for enabling/disabling
+* SEQ_CH2 and SEQ_AVG2 registers, modified function
+* prototypes of XSysMonPsu_GetSeqAvgEnables,
+* XSysMonPsu_SetSeqAvgEnables, XSysMonPsu_SetSeqChEnables,
+* XSysMonPsu_GetSeqChEnables,
+* XSysMonPsu_SetSeqInputMode, XSysMonPsu_GetSeqInputMode,
+* XSysMonPsu_SetSeqAcqTime
+* and XSysMonPsu_GetSeqAcqTime to provide support for
+* set/get 64 bit value.
+* Added constants XSM_CFR_ALM_SUPPLY*(8-31)_MASKs to
+* provide support for enabling extra PS alarams.
*
*
*
@@ -332,6 +344,12 @@ extern "C" {
* @name Alarm masks for channels in Configuration registers 1
* @{
*/
+#define XSM_CFR_ALM_SUPPLY13_MASK 0x200000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY12_MASK 0x100000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY11_MASK 0x080000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY10_MASK 0x040000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY9_MASK 0x020000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY8_MASK 0x010000 /**< Alarm 6 - SUPPLY6 */
#define XSM_CFR_ALM_SUPPLY6_MASK 0x0800 /**< Alarm 6 - SUPPLY6 */
#define XSM_CFR_ALM_SUPPLY5_MASK 0x0400 /**< Alarm 5 - SUPPLY5 */
#define XSM_CFR_ALM_SUPPLY4_MASK 0x0200 /**< Alarm 4 - SUPPLY4 */
@@ -458,7 +476,7 @@ typedef struct {
*
*****************************************************************************/
#define XSysMonPsu_TemperatureToRaw_OnChip(Temperature) \
- ((int)(((Temperature) + 273.6777f)*65536.0f*0.00199451786f))
+ ((s32)(((Temperature) + 273.6777f)*65536.0f*0.00199451786f))
/****************************************************************************/
/**
@@ -476,7 +494,7 @@ typedef struct {
*
*****************************************************************************/
#define XSysMonPsu_TemperatureToRaw_ExternalRef(Temperature) \
- ((int)(((Temperature) + 273.8195f)*65536.0f*0.00198842814f))
+ ((s32)(((Temperature) + 273.8195f)*65536.0f*0.00198842814f))
/****************************************************************************/
/**
@@ -534,7 +552,7 @@ void XSysMonPsu_Reset(XSysMonPsu *InstancePtr);
void XSysMonPsu_Reset_FromLPD(XSysMonPsu *InstancePtr);
u32 XSysMonPsu_GetStatus(XSysMonPsu *InstancePtr, u32 SysmonBlk);
void XSysMonPsu_StartAdcConversion(XSysMonPsu *InstancePtr);
-u16 XSysMonPsu_GetAdcData(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk);
+u16 XSysMonPsu_GetAdcData(XSysMonPsu *InstancePtr, u8 Channel, u32 Block);
u16 XSysMonPsu_GetCalibCoefficient(XSysMonPsu *InstancePtr, u8 CoeffType, u32 SysmonBlk);
u16 XSysMonPsu_GetMinMaxMeasurement(XSysMonPsu *InstancePtr, u8 MeasurementType,
u32 SysmonBlk);
@@ -556,18 +574,18 @@ void XSysMonPsu_SetExtenalMux(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk
u32 XSysMonPsu_GetExtenalMux(XSysMonPsu *InstancePtr, u32 SysmonBlk);
void XSysMonPsu_SetAdcClkDivisor(XSysMonPsu *InstancePtr, u8 Divisor, u32 SysmonBlk);
u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u32 ChEnableMask,
+s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u64 ChEnableMask,
u32 SysmonBlk);
-u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 AvgEnableChMask,
+u64 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+u64 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u64 AvgEnableChMask,
u32 SysmonBlk);
-s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u32 InputModeChMask,
+s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u64 InputModeChMask,
u32 SysmonBlk);
-u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u32 AcqCyclesChMask,
+u64 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u64 AcqCyclesChMask,
u32 SysmonBlk);
-u32 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+u64 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk);
void XSysMonPsu_SetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
u16 Value, u32 SysmonBlk);
u16 XSysMonPsu_GetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_hw.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h
index 3012bf327..80266ebf9 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_hw.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h
@@ -44,6 +44,8 @@
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.0 kvn 12/15/15 First release
+* 2.0 vns 08/14/16 Added CFG_REG3, SEQ_INPUT_MODE2, SEQ_ACQ2,
+* SEQ_CH2 and SEQ_AVG2 offsets and bit masks
*
*
*
@@ -1563,6 +1565,40 @@ extern "C" {
#define XSYSMONPSU_CFG_REG2_TST_MDE_WIDTH 2U
#define XSYSMONPSU_CFG_REG2_TST_MDE_MASK 0x00000003U
+/* Register: XSysmonPsuCfgReg3 */
+#define XSYSMONPSU_CFG_REG3_OFFSET 0x0000010CU
+#define XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK 0x0000003FU
+
+#define XSM_CFG_ALARM_SHIFT 16U
+
+/* Register: XSysmonPsuSeqCh2 */
+#define XSYSMONPSU_SEQ_CH2_OFFSET 0x00000118U
+
+#define XSYSMONPSU_SEQ_CH2_TEMP_RMT_SHIFT 5U
+#define XSYSMONPSU_SEQ_CH2_TEMP_RMT_MASK 0x00000020U
+
+#define XSYSMONPSU_SEQ_CH2_VCCAMS_SHIFT 4U
+#define XSYSMONPSU_SEQ_CH2_VCCAMS_MASK 0x00000010U
+
+#define XSYSMONPSU_SEQ_CH2_SUP10_SHIFT 3U
+#define XSYSMONPSU_SEQ_CH2_SUP10_MASK 0x00000008U
+
+#define XSYSMONPSU_SEQ_CH2_SUP9_SHIFT 2U
+#define XSYSMONPSU_SEQ_CH2_SUP9_MASK 0x00000004U
+
+#define XSYSMONPSU_SEQ_CH2_SUP8_SHIFT 1U
+#define XSYSMONPSU_SEQ_CH2_SUP8_MASK 0x00000002U
+
+#define XSYSMONPSU_SEQ_CH2_SUP7_SHIFT 0U
+#define XSYSMONPSU_SEQ_CH2_SUP7_MASK 0x00000001U
+
+#define XSYSMONPSU_SEQ_CH2_VALID_MASK 0x0000003FU
+
+/* Register: XSysmonPsuSeqAverage0 */
+#define XSYSMONPSU_SEQ_AVERAGE2_OFFSET 0x0000011CU
+#define XSYSMONPSU_SEQ_AVERAGE1_RSTVAL 0x00000000U
+#define XSYSMONPSU_SEQ_AVERAGE2_MASK 0x0000003FU
+
/**
* Register: XSysmonPsuSeqCh0
*/
@@ -1695,6 +1731,7 @@ extern "C" {
#define XSYSMONPSU_SEQ_CH1_VAUX00_MASK 0x00000001U
#define XSM_SEQ_CH_SHIFT 16U
+#define XSM_SEQ_CH2_SHIFT 32U
/**
* Register: XSysmonPsuSeqAverage0
@@ -2048,6 +2085,22 @@ extern "C" {
#define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_WIDTH 1U
#define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_MASK 0x00000001U
+/* Register: XSysmonPsuSeqInputMde2 */
+#define XSYSMONPSU_SEQ_INPUT_MDE2_OFFSET 0x000001E0U
+#define XSYSMONPSU_SEQ_INPUT_MDE2_RSTVAL 0x00000000U
+
+#define XSYSMONPSU_SEQ_INPUT_MDE2_SHIFT 0U
+#define XSYSMONPSU_SEQ_INPUT_MDE2_MASK 0x0000003FU
+
+/**
+ * Register: XSysmonPsuSeqAcq2
+ */
+#define XSYSMONPSU_SEQ_ACQ2_OFFSET 0x000001E4U
+#define XSYSMONPSU_SEQ_ACQ2_RSTVAL 0x00000000U
+
+#define XSYSMONPSU_SEQ_ACQ2_SHIFT 0U
+#define XSYSMONPSU_SEQ_ACQ2_MASK 0x0000003FU
+
/**
* Register: XSysmonPsuSup7
*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_intr.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_selftest.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_sinit.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/Makefile
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/Makefile
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps.c
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps.c
index 4534553f6..394262868 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps.c
@@ -50,6 +50,8 @@
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.01 pkp 01/30/16 Modified XTtcPs_CfgInitialize to add XTtcps_Stop
* to stop the timer before configuring
+* 3.2 mus 10/28/16 Modified XTtcPs_CalcIntervalFromFreq to calculate
+* 32 bit interval count for zynq ultrascale+mpsoc
*
*
*
@@ -377,7 +379,7 @@ u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
*
****************************************************************************/
void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
- u16 *Interval, u8 *Prescaler)
+ XInterval *Interval, u8 *Prescaler)
{
u8 TmpPrescaler;
u32 TempValue;
@@ -396,7 +398,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
* The frequency is too high, it is too close to the input
* clock value. Use maximum values to signal caller.
*/
- *Interval = 0xFFFFU;
+ *Interval = XTTCPS_MAX_INTERVAL_COUNT;
*Prescaler = 0xFFU;
return;
}
@@ -408,7 +410,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
/*
* We do not need a prescaler, so set the values appropriately
*/
- *Interval = (u16)TempValue;
+ *Interval = (XInterval)TempValue;
*Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE;
return;
}
@@ -425,7 +427,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
/*
* Set the values appropriately
*/
- *Interval = (u16)TempValue;
+ *Interval = (XInterval)TempValue;
*Prescaler = TmpPrescaler;
return;
}
@@ -434,7 +436,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
/* Can not find interval values that work for the given frequency.
* Return maximum values to signal caller.
*/
- *Interval = 0XFFFFU;
+ *Interval = XTTCPS_MAX_INTERVAL_COUNT;
*Prescaler = 0XFFU;
return;
}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps.h
similarity index 89%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps.h
index 646d24db5..be266d9b3 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps.h
@@ -91,6 +91,8 @@
* 2.0 adk 12/10/13 Updated as per the New Tcl API's
* 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp.Also code
* modified for MISRA-C:2012 compliance.
+* 3.2 mus 10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
+* macros to return 32 bit values for zynq ultrascale+mpsoc
*
*
******************************************************************************/
@@ -108,6 +110,21 @@ extern "C" {
#include "xstatus.h"
/************************** Constant Definitions *****************************/
+/*
+ * Flag for a9 processor
+ */
+ #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+ #define ARMA9
+ #endif
+
+/*
+ * Maximum Value for interval counter
+ */
+ #if defined(ARMA9)
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU
+ #else
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
+ #endif
/** @name Configuration options
*
@@ -125,7 +142,6 @@ extern "C" {
#define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */
#define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */
/*@}*/
-
/**************************** Type Definitions *******************************/
/**
@@ -148,7 +164,14 @@ typedef struct {
u32 IsReady; /**< Device is initialized and ready */
} XTtcPs;
-
+/**
+ * This typedef contains interval count
+ */
+#if defined(ARMA9)
+typedef u16 XInterval;
+#else
+typedef u32 XInterval;
+#endif
/***************** Macros (Inline Functions) Definitions *********************/
/*
@@ -223,14 +246,27 @@ typedef struct {
*
* @param InstancePtr is a pointer to the XTtcPs instance.
*
-* @return 16-bit counter value.
+* @return zynq:16 bit counter value.
+* zynq ultrascale+mpsoc:32 bit counter value.
*
* @note C-style signature:
-* u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+* zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+* zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
*
****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit counter for zynq
+ */
#define XTtcPs_GetCounterValue(InstancePtr) \
(u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#else
+/*
+ * ttc supports 32 bit counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+ InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#endif
/*****************************************************************************/
/**
@@ -256,15 +292,27 @@ typedef struct {
*
* @param InstancePtr is a pointer to the XTtcPs instance.
*
-* @return 16-bit interval value
+* @return zynq:16 bit interval value.
+* zynq ultrascale+mpsoc:32 bit interval value.
*
* @note C-style signature:
-* u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+* zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+* zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)
*
****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit interval counter for zynq
+ */
#define XTtcPs_GetInterval(InstancePtr) \
(u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
-
+#else
+/*
+ * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+ InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#endif
/*****************************************************************************/
/**
*
@@ -391,7 +439,7 @@ void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
- u16 *Interval, u8 *Prescaler);
+ XInterval *Interval, u8 *Prescaler);
/*
* Functions for options, in file xttcps_options.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_g.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_g.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_g.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_hw.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_hw.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_hw.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_options.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_options.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_options.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_options.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_selftest.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_sinit.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/Makefile
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/Makefile
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps.h
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps.h
index 6bd42b21c..d915917bb 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps.h
@@ -161,6 +161,7 @@
* platform variable in driver instance structure.
* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when
* uart is connected to a valid interrupt controller CR#946803.
+* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
*
*
*
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_g.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_g.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_g.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_hw.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_hw.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_hw.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_hw.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_hw.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_hw.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_hw.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_intr.c
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_intr.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_intr.c
index 849cb48db..3068ee795 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_intr.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_intr.c
@@ -249,7 +249,7 @@ void XUartPs_InterruptHandler(XUartPs *InstancePtr)
*****************************************************************************/
static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus)
{
- u32 ByteStatusValue, EventData;
+ u32 EventData;
u32 Event;
InstancePtr->is_rxbs_error = 0;
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_options.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_options.c
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_options.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_options.c
index 7051d07ec..9a699afa1 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_options.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_options.c
@@ -47,6 +47,7 @@
* 1.00 sdm 09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
* value was not being written to the register.
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
*
*
*
@@ -199,6 +200,8 @@ void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
* the register.
*/
if ((Options & OptionsTable[Index].Option) != (u16)0) {
+ if(OptionsTable[Index].Option == XUARTPS_OPTION_SET_BREAK)
+ Register &= ~XUARTPS_CR_STOPBRK;
Register |= OptionsTable[Index].Mask;
}
else {
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_selftest.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_selftest.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_selftest.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_sinit.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_sinit.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_sinit.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/Makefile
new file mode 100644
index 000000000..d30648814
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xusbps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling usbpsu"
+
+xusbps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xusbps_includes
+
+xusbps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu.c
new file mode 100644
index 000000000..c39d11a2f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu.c
@@ -0,0 +1,906 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu.c
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.0 sg 06/16/16 First release
+* 1.1 sg 10/24/16 Added new function XUsbPsu_IsSuperSpeed
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* Waits until a bit in a register is cleared or timeout occurs
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param Offset is register offset.
+* @param BitMask is bit mask of required bit to be checked.
+* @param Timeout is the time to wait specified in micro seconds.
+*
+* @return
+* - XST_SUCCESS when bit is cleared.
+* - XST_FAILURE when timed out.
+*
+******************************************************************************/
+s32 XUsbPsu_Wait_Clear_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+ u32 BitMask, u32 Timeout)
+{
+ u32 RegVal;
+ u32 LocalTimeout = Timeout;
+
+ do {
+ RegVal = XUsbPsu_ReadReg(InstancePtr, Offset);
+ if ((RegVal & BitMask) == 0U) {
+ break;
+ }
+ LocalTimeout--;
+ if (LocalTimeout == 0U) {
+ return XST_FAILURE;
+ }
+ XUsbSleep(1U);
+ } while (1);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Waits until a bit in a register is set or timeout occurs
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param Offset is register offset.
+* @param BitMask is bit mask of required bit to be checked.
+* @param Timeout is the time to wait specified in micro seconds.
+*
+* @return
+* - XST_SUCCESS when bit is set.
+* - XST_FAILURE when timed out.
+*
+******************************************************************************/
+s32 XUsbPsu_Wait_Set_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+ u32 BitMask, u32 Timeout)
+{
+ u32 RegVal;
+ u32 LocalTimeout = Timeout;
+
+ do {
+ RegVal = XUsbPsu_ReadReg(InstancePtr, Offset);
+ if ((RegVal & BitMask) != 0U) {
+ break;
+ }
+ LocalTimeout--;
+ if (LocalTimeout == 0U) {
+ return XST_FAILURE;
+ }
+ XUsbSleep(1U);
+ } while (1);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Sets mode of Core to USB Device/Host/OTG.
+*
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param Mode is mode to set
+* - XUSBPSU_GCTL_PRTCAP_OTG
+* - XUSBPSU_GCTL_PRTCAP_HOST
+* - XUSBPSU_GCTL_PRTCAP_DEVICE
+*
+* @return None
+*
+******************************************************************************/
+void XUsbPsu_SetMode(struct XUsbPsu *InstancePtr, u32 Mode)
+{
+ u32 RegVal;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid((Mode <= XUSBPSU_GCTL_PRTCAP_OTG) &&
+ (Mode >= XUSBPSU_GCTL_PRTCAP_HOST));
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+ RegVal &= ~(XUSBPSU_GCTL_PRTCAPDIR(XUSBPSU_GCTL_PRTCAP_OTG));
+ RegVal |= XUSBPSU_GCTL_PRTCAPDIR(Mode);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* Issues core PHY reset.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return None
+*
+******************************************************************************/
+void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /* Before Resetting PHY, put Core in Reset */
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+ RegVal |= XUSBPSU_GCTL_CORESOFTRESET;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+
+ /* Assert USB3 PHY reset */
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0));
+ RegVal |= XUSBPSU_GUSB3PIPECTL_PHYSOFTRST;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal);
+
+ /* Assert USB2 PHY reset */
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0));
+ RegVal |= XUSBPSU_GUSB2PHYCFG_PHYSOFTRST;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal);
+
+ XUsbSleep(XUSBPSU_PHY_TIMEOUT);
+
+ /* Clear USB3 PHY reset */
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0));
+ RegVal &= ~XUSBPSU_GUSB3PIPECTL_PHYSOFTRST;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal);
+
+ /* Clear USB2 PHY reset */
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0));
+ RegVal &= ~XUSBPSU_GUSB2PHYCFG_PHYSOFTRST;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal);
+
+ XUsbSleep(XUSBPSU_PHY_TIMEOUT);
+
+ /* Take Core out of reset state after PHYS are stable*/
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+ RegVal &= ~XUSBPSU_GCTL_CORESOFTRESET;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* Sets up Event buffers so that events are written by Core.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return None
+*
+******************************************************************************/
+void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr)
+{
+ struct XUsbPsu_EvtBuffer *Evt;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ Evt = &InstancePtr->Evt;
+ Evt->BuffAddr = (void *)InstancePtr->EventBuffer;
+
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0),
+ (UINTPTR)InstancePtr->EventBuffer);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0),
+ ((UINTPTR)(InstancePtr->EventBuffer) >> 16U) >> 16U);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0),
+ XUSBPSU_GEVNTSIZ_SIZE(sizeof(InstancePtr->EventBuffer)));
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 0);
+}
+
+/*****************************************************************************/
+/**
+* Resets Event buffer Registers to zero so that events are not written by Core.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return None
+*
+******************************************************************************/
+void XUsbPsu_EventBuffersReset(struct XUsbPsu *InstancePtr)
+{
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0U), 0U);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0U), 0U);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0U),
+ (u32)XUSBPSU_GEVNTSIZ_INTMASK | XUSBPSU_GEVNTSIZ_SIZE(0U));
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0U), 0U);
+}
+
+/*****************************************************************************/
+/**
+* Reads data from Hardware Params Registers of Core.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param RegIndex is Register number to read
+* - XUSBPSU_GHWPARAMS0
+* - XUSBPSU_GHWPARAMS1
+* - XUSBPSU_GHWPARAMS2
+* - XUSBPSU_GHWPARAMS3
+* - XUSBPSU_GHWPARAMS4
+* - XUSBPSU_GHWPARAMS5
+* - XUSBPSU_GHWPARAMS6
+* - XUSBPSU_GHWPARAMS7
+*
+* @return One of the GHWPARAMS RegValister contents.
+*
+******************************************************************************/
+u32 XUsbPsu_ReadHwParams(struct XUsbPsu *InstancePtr, u8 RegIndex)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(RegIndex <= (u8)XUSBPSU_GHWPARAMS7);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, ((u32)XUSBPSU_GHWPARAMS0_OFFSET +
+ ((u32)RegIndex * (u32)4)));
+ return RegVal;
+}
+
+/*****************************************************************************/
+/**
+* Initializes Core.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if initialization was not successful
+*
+******************************************************************************/
+s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+ u32 Hwparams1;
+
+ /* issue device SoftReset too */
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, XUSBPSU_DCTL_CSFTRST);
+
+ if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DCTL,
+ XUSBPSU_DCTL_CSFTRST, 500U) == XST_FAILURE) {
+ /* timed out return failure */
+ return XST_FAILURE;
+ }
+
+ XUsbPsu_PhyReset(InstancePtr);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+ RegVal &= ~XUSBPSU_GCTL_SCALEDOWN_MASK;
+ RegVal &= ~XUSBPSU_GCTL_DISSCRAMBLE;
+ RegVal |= XUSBPSU_GCTL_U2EXIT_LFPS;
+
+ Hwparams1 = XUsbPsu_ReadHwParams(InstancePtr, 1U);
+
+ switch (XUSBPSU_GHWPARAMS1_EN_PWROPT(Hwparams1)) {
+ case XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK:
+ RegVal &= ~XUSBPSU_GCTL_DSBLCLKGTNG;
+ break;
+
+ case XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB:
+ /* enable hibernation here */
+ break;
+
+ default:
+ /* Made for Misra-C Compliance. */
+ break;
+ }
+
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Enables an interrupt in Event Enable RegValister.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on
+* @param Mask is the OR of any Interrupt Enable Masks:
+* - XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN
+* - XUSBPSU_DEVTEN_EVNTOVERFLOWEN
+* - XUSBPSU_DEVTEN_CMDCMPLTEN
+* - XUSBPSU_DEVTEN_ERRTICERREN
+* - XUSBPSU_DEVTEN_SOFEN
+* - XUSBPSU_DEVTEN_EOPFEN
+* - XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN
+* - XUSBPSU_DEVTEN_WKUPEVTEN
+* - XUSBPSU_DEVTEN_ULSTCNGEN
+* - XUSBPSU_DEVTEN_CONNECTDONEEN
+* - XUSBPSU_DEVTEN_USBRSTEN
+* - XUSBPSU_DEVTEN_DISCONNEVTEN
+*
+* @return None
+*
+******************************************************************************/
+void XUsbPsu_EnableIntr(struct XUsbPsu *InstancePtr, u32 Mask)
+{
+ u32 RegVal;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEVTEN);
+ RegVal |= Mask;
+
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEVTEN, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* Disables an interrupt in Event Enable RegValister.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param Mask is the OR of Interrupt Enable Masks
+* - XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN
+* - XUSBPSU_DEVTEN_EVNTOVERFLOWEN
+* - XUSBPSU_DEVTEN_CMDCMPLTEN
+* - XUSBPSU_DEVTEN_ERRTICERREN
+* - XUSBPSU_DEVTEN_SOFEN
+* - XUSBPSU_DEVTEN_EOPFEN
+* - XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN
+* - XUSBPSU_DEVTEN_WKUPEVTEN
+* - XUSBPSU_DEVTEN_ULSTCNGEN
+* - XUSBPSU_DEVTEN_CONNECTDONEEN
+* - XUSBPSU_DEVTEN_USBRSTEN
+* - XUSBPSU_DEVTEN_DISCONNEVTEN
+*
+* @return None
+*
+******************************************************************************/
+void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask)
+{
+ u32 RegVal;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEVTEN);
+ RegVal &= ~Mask;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEVTEN, RegVal);
+}
+
+/****************************************************************************/
+/**
+*
+* This function does the following:
+* - initializes a specific XUsbPsu instance.
+* - sets up Event Buffer for Core to write events.
+* - Core Reset and PHY Reset.
+* - Sets core in Device Mode.
+* - Sets default speed as HIGH_SPEED.
+* - Sets Device Address to 0.
+* - Enables interrupts.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param ConfigPtr points to the XUsbPsu device configuration structure.
+* @param BaseAddress is the device base address in the virtual memory
+* address space. If the address translation is not used then the
+* physical address is passed.
+* Unexpected errors may occur if the address mapping is changed
+* after this function is invoked.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr,
+ XUsbPsu_Config *ConfigPtr, u32 BaseAddress)
+{
+ int Status;
+ u32 RegVal;
+
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+ Xil_AssertNonvoid(BaseAddress != 0U)
+
+ InstancePtr->ConfigPtr = ConfigPtr;
+
+ Status = XUsbPsu_CoreInit(InstancePtr);
+ if (Status != XST_SUCCESS) {
+#ifdef XUSBPSU_DEBUG
+ xil_printf("Core initialization failed\r\n");
+#endif
+ return XST_FAILURE;
+ }
+
+ RegVal = XUsbPsu_ReadHwParams(InstancePtr, 3U);
+ InstancePtr->NumInEps = (u8)XUSBPSU_NUM_IN_EPS(RegVal);
+ InstancePtr->NumOutEps = (u8)(XUSBPSU_NUM_EPS(RegVal) -
+ InstancePtr->NumInEps);
+
+ /* Map USB and Physical Endpoints */
+ XUsbPsu_InitializeEps(InstancePtr);
+
+ XUsbPsu_EventBuffersSetup(InstancePtr);
+
+ XUsbPsu_SetMode(InstancePtr, XUSBPSU_GCTL_PRTCAP_DEVICE);
+
+ /*
+ * Setting to max speed to support SS and HS
+ */
+ XUsbPsu_SetSpeed(InstancePtr, XUSBPSU_DCFG_SUPERSPEED);
+
+ (void)XUsbPsu_SetDeviceAddress(InstancePtr, 0U);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* Starts the controller so that Host can detect this device.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Start(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+
+ RegVal |= XUSBPSU_DCTL_RUN_STOP;
+
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS,
+ XUSBPSU_DSTS_DEVCTRLHLT, 500U) == XST_FAILURE) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* Stops the controller so that Device disconnects from Host.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Stop(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal &= ~XUSBPSU_DCTL_RUN_STOP;
+
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ if (XUsbPsu_Wait_Set_Timeout(InstancePtr, XUSBPSU_DSTS,
+ XUSBPSU_DSTS_DEVCTRLHLT, 500U) == XST_FAILURE) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+ * Enables USB2 Test Modes
+ *
+ * @param InstancePtr is a pointer to the XUsbPsu instance.
+ * @param Mode is Test mode to set.
+ *
+ * @return XST_SUCCESS else XST_FAILURE
+ *
+ * @note None.
+ *
+ ****************************************************************************/
+s32 XUsbPsu_SetTestMode(struct XUsbPsu *InstancePtr, u32 Mode)
+{
+ u32 RegVal;
+ s32 Status = XST_SUCCESS;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid((Mode >= XUSBPSU_TEST_J)
+ && (Mode <= XUSBPSU_TEST_FORCE_ENABLE));
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK;
+
+ switch (Mode) {
+ case XUSBPSU_TEST_J:
+ case XUSBPSU_TEST_K:
+ case XUSBPSU_TEST_SE0_NAK:
+ case XUSBPSU_TEST_PACKET:
+ case XUSBPSU_TEST_FORCE_ENABLE:
+ RegVal |= (u32)Mode << 1;
+ break;
+
+ default:
+ Status = (s32)XST_FAILURE;
+ break;
+ }
+
+ if (Status != (s32)XST_FAILURE) {
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+ Status = XST_SUCCESS;
+ }
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+ * Gets current State of USB Link
+ *
+ * @param InstancePtr is a pointer to the XUsbPsu instance.
+ *
+ * @return Link State
+ *
+ * @note None.
+ *
+ ****************************************************************************/
+XusbPsuLinkState XUsbPsu_GetLinkState(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS);
+
+ return XUSBPSU_DSTS_USBLNKST(RegVal);
+}
+
+/****************************************************************************/
+/**
+ * Sets USB Link to a particular State
+ *
+ * @param InstancePtr is a pointer to the XUsbPsu instance.
+ * @param State is State of Link to set.
+ *
+ * @return XST_SUCCESS else XST_FAILURE
+ *
+ * @note None.
+ *
+ ****************************************************************************/
+s32 XUsbPsu_SetLinkState(struct XUsbPsu *InstancePtr,
+ XusbPsuLinkStateChange State)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Wait until device controller is ready. */
+ if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS,
+ XUSBPSU_DSTS_DCNRD, 500U) == XST_FAILURE) {
+ return XST_FAILURE;
+ }
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal &= ~XUSBPSU_DCTL_ULSTCHNGREQ_MASK;
+
+ RegVal |= XUSBPSU_DCTL_ULSTCHNGREQ(State);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sets speed of the Core for connecting to Host
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Speed is required speed
+* - XUSBPSU_DCFG_HIGHSPEED
+* - XUSBPSU_DCFG_FULLSPEED2
+* - XUSBPSU_DCFG_LOWSPEED
+* - XUSBPSU_DCFG_FULLSPEED1
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed)
+{
+ u32 RegVal;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Speed <= (u32)XUSBPSU_DCFG_SUPERSPEED);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
+ RegVal &= ~(XUSBPSU_DCFG_SPEED_MASK);
+ RegVal |= Speed;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
+}
+
+/****************************************************************************/
+/**
+* Sets Device Address of the Core
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Addr is address to set.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Addr <= 127U);
+
+ if (InstancePtr->State == XUSBPSU_STATE_CONFIGURED) {
+ return XST_FAILURE;
+ }
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
+ RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK);
+ RegVal |= XUSBPSU_DCFG_DEVADDR(Addr);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
+
+ if (Addr) {
+ InstancePtr->State = XUSBPSU_STATE_ADDRESS;
+ }
+ else {
+ InstancePtr->State = XUSBPSU_STATE_DEFAULT;
+ }
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sets speed of the Core for connecting to Host
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_IsSuperSpeed(struct XUsbPsu *InstancePtr)
+{
+ if (InstancePtr->Speed != XUSBPSU_SPEED_SUPER) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Set U1 sleep timeout
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Sleep is time in microseconds
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetU1SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_PORTMSC_30);
+ RegVal &= ~XUSBPSU_PORTMSC_30_U1_TIMEOUT_MASK;
+ RegVal |= (Sleep << XUSBPSU_PORTMSC_30_U1_TIMEOUT_SHIFT);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_PORTMSC_30, RegVal);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Set U2 sleep timeout
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Sleep is time in microseconds
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetU2SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_PORTMSC_30);
+ RegVal &= ~XUSBPSU_PORTMSC_30_U2_TIMEOUT_MASK;
+ RegVal |= (Sleep << XUSBPSU_PORTMSC_30_U2_TIMEOUT_SHIFT);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_PORTMSC_30, RegVal);
+
+ return XST_SUCCESS;
+}
+/****************************************************************************/
+/**
+* Enable Accept U1 and U2 sleep enable
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_AcceptU1U2Sleep(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal |= XUSBPSU_DCTL_ACCEPTU2ENA | XUSBPSU_DCTL_ACCEPTU1ENA;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enable U1 enable sleep
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_U1SleepEnable(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal |= XUSBPSU_DCTL_INITU1ENA;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enable U2 enable sleep
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_U2SleepEnable(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal |= XUSBPSU_DCTL_INITU2ENA;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enable U1 disable sleep
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_U1SleepDisable(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal &= ~XUSBPSU_DCTL_INITU1ENA;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enable U2 disable sleep
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_U2SleepDisable(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal &= ~XUSBPSU_DCTL_INITU2ENA;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ return XST_SUCCESS;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu.h
new file mode 100644
index 000000000..a1366487b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu.h
@@ -0,0 +1,608 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu.h
+* @addtogroup usbpsu_v1_0
+* @{
+* @details
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.0 sg 06/06/16 First release
+* 1.1 sg 10/24/16 Update for backward compatability
+* Added XUsbPsu_IsSuperSpeed function in xusbpsu.c
+*
+*
+*
+*****************************************************************************/
+#ifndef XUSBPSU_H /* Prevent circular inclusions */
+#define XUSBPSU_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xusbpsu_hw.h"
+#include "xil_io.h"
+/*
+ * The header sleep.h and API usleep() can only be used with an arm design.
+ * MB_Sleep() is used for microblaze design.
+ */
+#if defined (__arm__) || defined (__aarch64__)
+#include "sleep.h"
+#endif
+
+#ifdef __MICROBLAZE__
+#include "microblaze_sleep.h"
+#endif
+#include "xil_cache.h"
+
+/************************** Constant Definitions ****************************/
+
+#define ALIGNMENT_CACHELINE __attribute__ ((aligned(64)))
+
+#define XUSBPSU_PHY_TIMEOUT 5000U /* in micro seconds */
+
+#define XUSBPSU_EP_DIR_IN 1U
+#define XUSBPSU_EP_DIR_OUT 0U
+
+#define XUSBPSU_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */
+#define XUSBPSU_ENDPOINT_DIR_MASK 0x80
+
+#define XUSBPSU_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */
+#define XUSBPSU_ENDPOINT_XFER_CONTROL 0U
+#define XUSBPSU_ENDPOINT_XFER_ISOC 1U
+#define XUSBPSU_ENDPOINT_XFER_BULK 2U
+#define XUSBPSU_ENDPOINT_XFER_INT 3U
+#define XUSBPSU_ENDPOINT_MAX_ADJUSTABLE 0x80
+
+#define XUSBPSU_TEST_J 1U
+#define XUSBPSU_TEST_K 2U
+#define XUSBPSU_TEST_SE0_NAK 3U
+#define XUSBPSU_TEST_PACKET 4U
+#define XUSBPSU_TEST_FORCE_ENABLE 5U
+
+#define XUSBPSU_NUM_TRBS 8
+
+#define XUSBPSU_EVENT_PENDING (0x00000001U << 0)
+
+#define XUSBPSU_EP_ENABLED (0x00000001U << 0)
+#define XUSBPSU_EP_STALL (0x00000001U << 1)
+#define XUSBPSU_EP_WEDGE (0x00000001U << 2)
+#define XUSBPSU_EP_BUSY ((u32)0x00000001U << 4)
+#define XUSBPSU_EP_PENDING_REQUEST (0x00000001U << 5)
+#define XUSBPSU_EP_MISSED_ISOC (0x00000001U << 6)
+
+#define XUSBPSU_GHWPARAMS0 0U
+#define XUSBPSU_GHWPARAMS1 1U
+#define XUSBPSU_GHWPARAMS2 2U
+#define XUSBPSU_GHWPARAMS3 3U
+#define XUSBPSU_GHWPARAMS4 4U
+#define XUSBPSU_GHWPARAMS5 5U
+#define XUSBPSU_GHWPARAMS6 6U
+#define XUSBPSU_GHWPARAMS7 7U
+
+/* HWPARAMS0 */
+#define XUSBPSU_MODE(n) ((n) & 0x7)
+#define XUSBPSU_MDWIDTH(n) (((n) & 0xff00) >> 8)
+
+/* HWPARAMS1 */
+#define XUSBPSU_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
+
+/* HWPARAMS3 */
+#define XUSBPSU_NUM_IN_EPS_MASK ((u32)0x0000001fU << (u32)18)
+#define XUSBPSU_NUM_EPS_MASK ((u32)0x0000003fU << (u32)12)
+#define XUSBPSU_NUM_EPS(p) (((u32)(p) & \
+ (XUSBPSU_NUM_EPS_MASK)) >> (u32)12)
+#define XUSBPSU_NUM_IN_EPS(p) (((u32)(p) & \
+ (XUSBPSU_NUM_IN_EPS_MASK)) >> (u32)18)
+
+/* HWPARAMS7 */
+#define XUSBPSU_RAM1_DEPTH(n) ((n) & 0xffff)
+
+#define XUSBPSU_DEPEVT_XFERCOMPLETE 0x01U
+#define XUSBPSU_DEPEVT_XFERINPROGRESS 0x02U
+#define XUSBPSU_DEPEVT_XFERNOTREADY 0x03U
+#define XUSBPSU_DEPEVT_STREAMEVT 0x06U
+#define XUSBPSU_DEPEVT_EPCMDCMPLT 0x07U
+
+/* Within XferNotReady */
+#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
+
+/* Within XferComplete */
+#define DEPEVT_STATUS_BUSERR (1 << 0)
+#define DEPEVT_STATUS_SHORT (1 << 1)
+#define DEPEVT_STATUS_IOC (1 << 2)
+#define DEPEVT_STATUS_LST (1 << 3)
+
+/* Stream event only */
+#define DEPEVT_STREAMEVT_FOUND 1U
+#define DEPEVT_STREAMEVT_NOTFOUND 2U
+
+/* Control-only Status */
+#define DEPEVT_STATUS_CONTROL_DATA 1U
+#define DEPEVT_STATUS_CONTROL_STATUS 2U
+#define DEPEVT_STATUS_CONTROL_DATA_INVALTRB 9
+#define DEPEVT_STATUS_CONTROL_STATUS_INVALTRB 0xA
+
+#define XUSBPSU_ENDPOINTS_NUM 12U
+
+#define XUSBPSU_EVENT_SIZE 4U /* bytes */
+#define XUSBPSU_EVENT_MAX_NUM 64U /* 2 events/endpoint */
+#define XUSBPSU_EVENT_BUFFERS_SIZE (XUSBPSU_EVENT_SIZE * \
+ XUSBPSU_EVENT_MAX_NUM)
+
+#define XUSBPSU_EVENT_TYPE_MASK 0x000000feU
+
+#define XUSBPSU_EVENT_TYPE_DEV 0U
+#define XUSBPSU_EVENT_TYPE_CARKIT 3U
+#define XUSBPSU_EVENT_TYPE_I2C 4U
+
+#define XUSBPSU_DEVICE_EVENT_DISCONNECT 0U
+#define XUSBPSU_DEVICE_EVENT_RESET 1U
+#define XUSBPSU_DEVICE_EVENT_CONNECT_DONE 2U
+#define XUSBPSU_DEVICE_EVENT_LINK_STATUS_CHANGE 3U
+#define XUSBPSU_DEVICE_EVENT_WAKEUP 4U
+#define XUSBPSU_DEVICE_EVENT_HIBER_REQ 5U
+#define XUSBPSU_DEVICE_EVENT_EOPF 6U
+#define XUSBPSU_DEVICE_EVENT_SOF 7U
+#define XUSBPSU_DEVICE_EVENT_ERRATIC_ERROR 9U
+#define XUSBPSU_DEVICE_EVENT_CMD_CMPL 10U
+#define XUSBPSU_DEVICE_EVENT_OVERFLOW 11U
+
+#define XUSBPSU_GEVNTCOUNT_MASK 0x0000fffcU
+
+/*
+ * Control Endpoint state
+ */
+#define XUSBPSU_EP0_SETUP_PHASE 1U /**< Setup Phase */
+#define XUSBPSU_EP0_DATA_PHASE 2U /**< Data Phase */
+#define XUSBPSU_EP0_STATUS_PHASE 3U /**< Status Pahse */
+
+/*
+ * Link State
+ */
+#define XUSBPSU_LINK_STATE_MASK 0x0FU
+
+typedef enum {
+ XUSBPSU_LINK_STATE_U0 = 0x00U, /**< in HS - ON */
+ XUSBPSU_LINK_STATE_U1 = 0x01U,
+ XUSBPSU_LINK_STATE_U2 = 0x02U, /**< in HS - SLEEP */
+ XUSBPSU_LINK_STATE_U3 = 0x03U, /**< in HS - SUSPEND */
+ XUSBPSU_LINK_STATE_SS_DIS = 0x04U,
+ XUSBPSU_LINK_STATE_RX_DET = 0x05U,
+ XUSBPSU_LINK_STATE_SS_INACT = 0x06U,
+ XUSBPSU_LINK_STATE_POLL = 0x07U,
+ XUSBPSU_LINK_STATE_RECOV = 0x08U,
+ XUSBPSU_LINK_STATE_HRESET = 0x09U,
+ XUSBPSU_LINK_STATE_CMPLY = 0x0AU,
+ XUSBPSU_LINK_STATE_LPBK = 0x0BU,
+ XUSBPSU_LINK_STATE_RESET = 0x0EU,
+ XUSBPSU_LINK_STATE_RESUME = 0x0FU,
+}XusbPsuLinkState;
+
+typedef enum {
+ XUSBPSU_LINK_STATE_CHANGE_U0 = 0x00U, /**< in HS - ON */
+ XUSBPSU_LINK_STATE_CHANGE_SS_DIS = 0x04U,
+ XUSBPSU_LINK_STATE_CHANGE_RX_DET = 0x05U,
+ XUSBPSU_LINK_STATE_CHANGE_SS_INACT = 0x06U,
+ XUSBPSU_LINK_STATE_CHANGE_RECOV = 0x08U,
+ XUSBPSU_LINK_STATE_CHANGE_CMPLY = 0x0AU,
+}XusbPsuLinkStateChange;
+
+/*
+ * Device States
+ */
+#define XUSBPSU_STATE_ATTACHED 0U
+#define XUSBPSU_STATE_POWERED 1U
+#define XUSBPSU_STATE_DEFAULT 2U
+#define XUSBPSU_STATE_ADDRESS 3U
+#define XUSBPSU_STATE_CONFIGURED 4U
+#define XUSBPSU_STATE_SUSPENDED 5U
+
+/*
+ * Device Speeds
+ */
+#define XUSBPSU_SPEED_UNKNOWN 0U
+#define XUSBPSU_SPEED_LOW 1U
+#define XUSBPSU_SPEED_FULL 2U
+#define XUSBPSU_SPEED_HIGH 3U
+#define XUSBPSU_SPEED_SUPER 4U
+
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XUSBPSU
+ * device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of controller */
+ u32 BaseAddress; /**< Core register base address */
+} XUsbPsu_Config;
+
+/**
+ * Software Event buffer representation
+ */
+struct XUsbPsu_EvtBuffer {
+ void *BuffAddr;
+ u32 Offset;
+ u32 Count;
+ u32 Flags;
+};
+
+/**
+ * Transfer Request Block - Hardware format
+ */
+struct XUsbPsu_Trb {
+ u32 BufferPtrLow;
+ u32 BufferPtrHigh;
+ u32 Size;
+ u32 Ctrl;
+} __attribute__((packed));
+
+
+/*
+ * Endpoint Parameters
+ */
+struct XUsbPsu_EpParams {
+ u32 Param2; /**< Parameter 2 */
+ u32 Param1; /**< Parameter 1 */
+ u32 Param0; /**< Parameter 0 */
+};
+
+/**
+ * USB Standard Control Request
+ */
+typedef struct {
+ u8 bRequestType;
+ u8 bRequest;
+ u16 wValue;
+ u16 wIndex;
+ u16 wLength;
+} __attribute__ ((packed)) SetupPacket;
+
+/**
+ * Endpoint representation
+ */
+struct XUsbPsu_Ep {
+ void (*Handler)(void *, u32, u32);
+ /** < User handler called
+ * when data is sent for IN Ep
+ * and received for OUT Ep
+ */
+ struct XUsbPsu_Trb EpTrb ALIGNMENT_CACHELINE;/**< TRB used by endpoint */
+ u32 EpStatus; /**< Flags to represent Endpoint status */
+ u32 RequestedBytes; /**< RequestedBytes for transfer */
+ u32 BytesTxed; /**< Actual Bytes transferred */
+ u16 MaxSize; /**< Size of endpoint */
+ u8 *BufferPtr; /**< Buffer location */
+ u8 ResourceIndex; /**< Resource Index assigned to
+ * Endpoint by core
+ */
+ u8 PhyEpNum; /**< Physical Endpoint Number in core */
+ u8 UsbEpNum; /**< USB Endpoint Number */
+ u8 Type; /**< Type of Endpoint -
+ * Control/BULK/INTERRUPT/ISOC
+ */
+ u8 Direction; /**< Direction - EP_DIR_OUT/EP_DIR_IN */
+ u8 UnalignedTx;
+};
+
+/**
+ * USB Device Controller representation
+ */
+struct XUsbPsu {
+ SetupPacket SetupData ALIGNMENT_CACHELINE;
+ /**< Setup Packet buffer */
+ struct XUsbPsu_Trb Ep0_Trb ALIGNMENT_CACHELINE;
+ /**< TRB for control transfers */
+ XUsbPsu_Config *ConfigPtr; /**< Configuration info pointer */
+ struct XUsbPsu_Ep eps[XUSBPSU_ENDPOINTS_NUM]; /**< Endpoints */
+ struct XUsbPsu_EvtBuffer Evt;
+ struct XUsbPsu_EpParams EpParams;
+ u32 BaseAddress; /**< Core register base address */
+ u32 DevDescSize;
+ u32 ConfigDescSize;
+ void (*Chapter9)(struct XUsbPsu *, SetupPacket *);
+ void (*ClassHandler)(struct XUsbPsu *, SetupPacket *);
+ void *DevDesc;
+ void *ConfigDesc;
+ u8 EventBuffer[XUSBPSU_EVENT_BUFFERS_SIZE]
+ __attribute__((aligned(XUSBPSU_EVENT_BUFFERS_SIZE)));
+ u8 NumOutEps;
+ u8 NumInEps;
+ u8 ControlDir;
+ u8 IsInTestMode;
+ u8 TestMode;
+ u8 Speed;
+ u8 State;
+ u8 Ep0State;
+ u8 LinkState;
+ u8 UnalignedTx;
+ u8 IsConfigDone;
+ u8 IsThreeStage;
+};
+
+struct XUsbPsu_Event_Type {
+ u32 Is_DevEvt:1;
+ u32 Type:7;
+ u32 Reserved8_31:24;
+} __attribute__((packed));
+
+/**
+ * struct XUsbPsu_event_depvt - Device Endpoint Events
+ * @Is_EpEvt: indicates this is an endpoint event
+ * @endpoint_number: number of the endpoint
+ * @endpoint_event: The event we have:
+ * 0x00 - Reserved
+ * 0x01 - XferComplete
+ * 0x02 - XferInProgress
+ * 0x03 - XferNotReady
+ * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
+ * 0x05 - Reserved
+ * 0x06 - StreamEvt
+ * 0x07 - EPCmdCmplt
+ * @Reserved11_10: Reserved, don't use.
+ * @Status: Indicates the status of the event. Refer to databook for
+ * more information.
+ * @Parameters: Parameters of the current event. Refer to databook for
+ * more information.
+ */
+struct XUsbPsu_Event_Epevt {
+ u32 Is_EpEvt:1;
+ u32 Epnumber:5;
+ u32 Endpoint_Event:4;
+ u32 Reserved11_10:2;
+ u32 Status:4;
+ u32 Parameters:16;
+} __attribute__((packed));
+
+/**
+ * struct XUsbPsu_event_devt - Device Events
+ * @Is_DevEvt: indicates this is a non-endpoint event
+ * @Device_Event: indicates it's a device event. Should read as 0x00
+ * @Type: indicates the type of device event.
+ * 0 - DisconnEvt
+ * 1 - USBRst
+ * 2 - ConnectDone
+ * 3 - ULStChng
+ * 4 - WkUpEvt
+ * 5 - Reserved
+ * 6 - EOPF
+ * 7 - SOF
+ * 8 - Reserved
+ * 9 - ErrticErr
+ * 10 - CmdCmplt
+ * 11 - EvntOverflow
+ * 12 - VndrDevTstRcved
+ * @Reserved15_12: Reserved, not used
+ * @Event_Info: Information about this event
+ * @Reserved31_25: Reserved, not used
+ */
+struct XUsbPsu_Event_Devt {
+ u32 Is_DevEvt:1;
+ u32 Device_Event:7;
+ u32 Type:4;
+ u32 Reserved15_12:4;
+ u32 Event_Info:9;
+ u32 Reserved31_25:7;
+} __attribute__((packed));
+
+/**
+ * struct XUsbPsu_event_gevt - Other Core Events
+ * @one_bit: indicates this is a non-endpoint event (not used)
+ * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
+ * @phy_port_number: self-explanatory
+ * @reserved31_12: Reserved, not used.
+ */
+struct XUsbPsu_Event_Gevt {
+ u32 Is_GlobalEvt:1;
+ u32 Device_Event:7;
+ u32 Phy_Port_Number:4;
+ u32 Reserved31_12:20;
+} __attribute__((packed));
+
+/**
+ * union XUsbPsu_event - representation of Event Buffer contents
+ * @raw: raw 32-bit event
+ * @type: the type of the event
+ * @depevt: Device Endpoint Event
+ * @devt: Device Event
+ * @gevt: Global Event
+ */
+union XUsbPsu_Event {
+ u32 Raw;
+ struct XUsbPsu_Event_Type Type;
+ struct XUsbPsu_Event_Epevt Epevt;
+ struct XUsbPsu_Event_Devt Devt;
+ struct XUsbPsu_Event_Gevt Gevt;
+};
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0U)
+
+#define roundup(x, y) ( \
+{ \
+ const typeof(y) y__ = (y); \
+ (((x) + (u32)(y__ - 1)) / (u32)y__) * (u32)y__; \
+} \
+)
+
+#define DECLARE_DEV_DESC(Instance, desc) \
+ (Instance).DevDesc = &(desc); \
+ (Instance).DevDescSize = sizeof((desc))
+
+#define DECLARE_CONFIG_DESC(Instance, desc) \
+ (Instance).ConfigDesc = &(desc); \
+ (Instance).ConfigDescSize = sizeof((desc))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions in xusbpsu.c
+ */
+s32 XUsbPsu_Wait_Clear_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+ u32 BitMask, u32 Timeout);
+s32 XUsbPsu_Wait_Set_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+ u32 BitMask, u32 Timeout);
+void XUsbPsu_SetMode(struct XUsbPsu *InstancePtr, u32 Mode);
+void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr);
+void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr);
+void XUsbPsu_EventBuffersReset(struct XUsbPsu *InstancePtr);
+void XUsbPsu_CoreNumEps(struct XUsbPsu *InstancePtr);
+void XUsbPsu_cache_hwparams(struct XUsbPsu *InstancePtr);
+u32 XUsbPsu_ReadHwParams(struct XUsbPsu *InstancePtr, u8 RegIndex);
+s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr);
+void XUsbPsu_EnableIntr(struct XUsbPsu *InstancePtr, u32 Mask);
+void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask);
+s32 XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr,
+ XUsbPsu_Config *ConfigPtr, u32 BaseAddress);
+s32 XUsbPsu_Start(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_Stop(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_SetTestMode(struct XUsbPsu *InstancePtr, u32 Mode);
+XusbPsuLinkState XUsbPsu_GetLinkState(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_SetLinkState(struct XUsbPsu *InstancePtr,
+ XusbPsuLinkStateChange State);
+s32 XUsbPsu_SendGenericCmd(struct XUsbPsu *InstancePtr,
+ s32 Cmd, u32 Param);
+void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed);
+s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr);
+s32 XUsbPsu_IsSuperSpeed(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_SetU1SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep);
+s32 XUsbPsu_SetU2SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep);
+s32 XUsbPsu_AcceptU1U2Sleep(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_U1SleepEnable(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_U2SleepEnable(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_U1SleepDisable(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_U2SleepDisable(struct XUsbPsu *InstancePtr);
+
+/*
+ * Functions in xusbpsu_endpoint.c
+ */
+struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr);
+u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum,
+ u8 Dir);
+const char *XUsbPsu_EpCmdString(u8 Cmd);
+s32 XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+ u32 Cmd, struct XUsbPsu_EpParams *Params);
+s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum,
+ u8 Dir);
+s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+ u16 Size, u8 Type);
+s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir);
+s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+ u16 Maxsize, u8 Type);
+s32 XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir);
+s32 XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 Size);
+void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr);
+void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir);
+void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp,
+ u8 *BufferPtr, u32 BufferLen);
+s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp,
+ u8 *BufferPtr, u32 Length);
+void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir);
+void XUsbPsu_EpClearStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir);
+void XUsbPsu_SetEpHandler(struct XUsbPsu *InstancePtr, u8 Epnum,
+ u8 Dir, void (*Handler)(void *, u32, u32));
+s32 XUsbPsu_IsEpStalled(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir);
+void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event);
+
+/*
+ * Functions in xusbpsu_controltransfers.c
+ */
+s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr);
+void XUsbPsu_Ep0StallRestart(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_SetConfiguration(struct XUsbPsu *InstancePtr,
+ SetupPacket *Ctrl);
+void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event);
+s32 XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_Ep0_EndControlData(struct XUsbPsu *InstancePtr,
+ struct XUsbPsu_Ep *Ept);
+void XUsbPsu_Ep0XferNotReady(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_Ep0Intr(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event);
+s32 XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr,
+ u32 BufferLen);
+s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length);
+void XUsbSleep(u32 USeconds);
+
+/*
+ * Functions in xusbpsu_intr.c
+ */
+void XUsbPsu_EpInterrupt(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_DisconnectIntr(struct XUsbPsu *InstancePtr);
+void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr);
+void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr);
+void XUsbPsu_LinkStsChangeIntr(struct XUsbPsu *InstancePtr,
+ u32 EvtInfo);
+void XUsbPsu_DevInterrupt(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Devt *Event);
+void XUsbPsu_EventHandler(struct XUsbPsu *InstancePtr,
+ const union XUsbPsu_Event *Event);
+void XUsbPsu_EventBufferHandler(struct XUsbPsu *InstancePtr);
+void XUsbPsu_IntrHandler(void *XUsbPsuInstancePtr);
+
+/*
+ * Functions in xusbpsu_sinit.c
+ */
+XUsbPsu_Config *XUsbPsu_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro. */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c
new file mode 100644
index 000000000..b3a93dc63
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c
@@ -0,0 +1,681 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_controltransfers.c
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0 sg 06/06/16 First release
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xusbpsu.h"
+#include "xusbpsu_endpoint.h"
+/************************** Constant Definitions *****************************/
+
+#define USB_DIR_OUT 0U /* to device */
+#define USB_DIR_IN 0x80U /* to host */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+* Initiates DMA on Control Endpoint 0 to receive Setup packet.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE.
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr)
+{
+ struct XUsbPsu_EpParams *Params;
+ struct XUsbPsu_Trb *TrbPtr;
+ struct XUsbPsu_Ep *Ept;
+ s32 Ret;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+
+ /* Setup packet always on EP0 */
+ Ept = &InstancePtr->eps[0];
+ if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
+ return XST_FAILURE;
+ }
+
+ TrbPtr = &InstancePtr->Ep0_Trb;
+
+ TrbPtr->BufferPtrLow = (UINTPTR)&InstancePtr->SetupData;
+ TrbPtr->BufferPtrHigh = ((UINTPTR)&InstancePtr->SetupData >> 16) >> 16;
+ TrbPtr->Size = 8U;
+ TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_SETUP;
+
+ TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+ | XUSBPSU_TRB_CTRL_LST
+ | XUSBPSU_TRB_CTRL_IOC
+ | XUSBPSU_TRB_CTRL_ISP_IMI);
+
+ Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+ Params->Param0 = 0U;
+ Params->Param1 = (UINTPTR)TrbPtr;
+
+ InstancePtr->Ep0State = XUSBPSU_EP0_SETUP_PHASE;
+
+ Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT,
+ XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+ if (Ret != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ Ept->EpStatus |= XUSBPSU_EP_BUSY;
+ Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+ Ept->UsbEpNum, Ept->Direction);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Stalls Control Endpoint and restarts to receive Setup packet.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0StallRestart(struct XUsbPsu *InstancePtr)
+{
+ struct XUsbPsu_Ep *Ept;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /* reinitialize physical ep1 */
+ Ept = &InstancePtr->eps[1];
+ Ept->EpStatus = XUSBPSU_EP_ENABLED;
+
+ /* stall is always issued on EP0 */
+ XUsbPsu_EpSetStall(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT);
+
+ Ept = &InstancePtr->eps[0];
+ Ept->EpStatus = XUSBPSU_EP_ENABLED;
+ InstancePtr->Ep0State = XUSBPSU_EP0_SETUP_PHASE;
+ (void)XUsbPsu_RecvSetup(InstancePtr);
+}
+
+/****************************************************************************/
+/**
+* Checks the Data Phase and calls user Endpoint handler.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is a pointer to the Endpoint event occured in core.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event)
+{
+ struct XUsbPsu_Ep *Ept;
+ struct XUsbPsu_Trb *TrbPtr;
+ u32 Status;
+ u32 Length;
+ u32 Epnum;
+ u8 Dir;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Event != NULL);
+
+ Epnum = Event->Epnumber;
+ Dir = (u8)(!!Epnum);
+ Ept = &InstancePtr->eps[Epnum];
+ TrbPtr = &InstancePtr->Ep0_Trb;
+
+ Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+ Status = XUSBPSU_TRB_SIZE_TRBSTS(TrbPtr->Size);
+ if (Status == XUSBPSU_TRBSTS_SETUP_PENDING) {
+ return;
+ }
+
+ Length = TrbPtr->Size & XUSBPSU_TRB_SIZE_MASK;
+
+ if (Length == 0U) {
+ Ept->BytesTxed = Ept->RequestedBytes;
+ } else {
+ if (Dir == XUSBPSU_EP_DIR_IN) {
+ Ept->BytesTxed = Ept->RequestedBytes - Length;
+ } else if (Dir == XUSBPSU_EP_DIR_OUT) {
+ if (Ept->UnalignedTx == 1U) {
+ Ept->BytesTxed = Ept->RequestedBytes;
+ Ept->UnalignedTx = 0U;
+ }
+ }
+ }
+
+ if (Dir == XUSBPSU_EP_DIR_OUT) {
+ /* Invalidate Cache */
+ Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed);
+ }
+
+ if (Ept->Handler != NULL) {
+ Ept->Handler(InstancePtr, Ept->RequestedBytes, Ept->BytesTxed);
+ }
+}
+
+/****************************************************************************/
+/**
+* Checks the Status Phase and starts next Control transfer.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is a pointer to the Endpoint event occured in core.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event)
+{
+ struct XUsbPsu_Trb *TrbPtr;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Event != NULL);
+
+ TrbPtr = &InstancePtr->Ep0_Trb;
+
+ if (InstancePtr->IsInTestMode != 0U) {
+ s32 Ret;
+
+ Ret = XUsbPsu_SetTestMode(InstancePtr,
+ InstancePtr->TestMode);
+ if (Ret < 0) {
+ XUsbPsu_Ep0StallRestart(InstancePtr);
+ return;
+ }
+ }
+ Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+ (void)XUsbPsu_RecvSetup(InstancePtr);
+}
+
+/****************************************************************************/
+/**
+* Handles Transfer complete event of Control Endpoints EP0 OUT and EP0 IN.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is a pointer to the Endpoint event occured in core.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event)
+{
+ struct XUsbPsu_Ep *Ept;
+ SetupPacket *Ctrl;
+ u16 Length;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Event != NULL);
+
+ Ept = &InstancePtr->eps[Event->Epnumber];
+ Ctrl = &InstancePtr->SetupData;
+
+ Ept->EpStatus &= ~XUSBPSU_EP_BUSY;
+ Ept->ResourceIndex = 0U;
+
+ switch (InstancePtr->Ep0State) {
+ case XUSBPSU_EP0_SETUP_PHASE:
+ Xil_DCacheInvalidateRange((INTPTR)&InstancePtr->SetupData,
+ sizeof(InstancePtr->SetupData));
+ Length = Ctrl->wLength;
+ if (Length == 0U) {
+ InstancePtr->IsThreeStage = 0U;
+ InstancePtr->ControlDir = XUSBPSU_EP_DIR_OUT;
+ } else {
+ InstancePtr->IsThreeStage = 1U;
+ InstancePtr->ControlDir = !!(Ctrl->bRequestType &
+ USB_DIR_IN);
+ }
+
+ Xil_AssertVoid(InstancePtr->Chapter9 != NULL);
+
+ InstancePtr->Chapter9(InstancePtr,
+ &InstancePtr->SetupData);
+ break;
+
+ case XUSBPSU_EP0_DATA_PHASE:
+ XUsbPsu_Ep0DataDone(InstancePtr, Event);
+ break;
+
+ case XUSBPSU_EP0_STATUS_PHASE:
+ XUsbPsu_Ep0StatusDone(InstancePtr, Event);
+ break;
+
+ default:
+ /* Default case is a required MISRA-C guideline. */
+ break;
+ }
+}
+
+/****************************************************************************/
+/**
+* Starts Status Phase of Control Transfer
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is a pointer to the Endpoint event occured in core.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event)
+{
+ struct XUsbPsu_Ep *Ept;
+ struct XUsbPsu_EpParams *Params;
+ struct XUsbPsu_Trb *TrbPtr;
+ u32 Type;
+ s32 Ret;
+ u8 Dir;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Event != NULL);
+
+ Ept = &InstancePtr->eps[Event->Epnumber];
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+ if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
+ return XST_FAILURE;
+ }
+
+ Type = (InstancePtr->IsThreeStage != 0U) ? XUSBPSU_TRBCTL_CONTROL_STATUS3
+ : XUSBPSU_TRBCTL_CONTROL_STATUS2;
+ TrbPtr = &InstancePtr->Ep0_Trb;
+ /* we use same TrbPtr for setup packet */
+ TrbPtr->BufferPtrLow = (UINTPTR)&InstancePtr->SetupData;
+ TrbPtr->BufferPtrHigh = ((UINTPTR)&InstancePtr->SetupData >> 16) >> 16;
+ TrbPtr->Size = 0U;
+ TrbPtr->Ctrl = Type;
+
+ TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+ | XUSBPSU_TRB_CTRL_LST
+ | XUSBPSU_TRB_CTRL_IOC
+ | XUSBPSU_TRB_CTRL_ISP_IMI);
+
+ Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+ Params->Param0 = 0U;
+ Params->Param1 = (UINTPTR)TrbPtr;
+
+ InstancePtr->Ep0State = XUSBPSU_EP0_STATUS_PHASE;
+
+ /*
+ * Control OUT transfer - Status stage happens on EP0 IN - EP1
+ * Control IN transfer - Status stage happens on EP0 OUT - EP0
+ */
+ Dir = !InstancePtr->ControlDir;
+
+ Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, Dir,
+ XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+ if (Ret != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ Ept->EpStatus |= XUSBPSU_EP_BUSY;
+ Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+ Ept->UsbEpNum, Ept->Direction);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Ends Data Phase - used incase of error.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Dep is a pointer to the Endpoint structure.
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0_EndControlData(struct XUsbPsu *InstancePtr,
+ struct XUsbPsu_Ep *Ept)
+{
+ struct XUsbPsu_EpParams *Params;
+ u32 Cmd;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Ept != NULL);
+
+ if (Ept->ResourceIndex == 0U) {
+ return;
+ }
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertVoid(Params != NULL);
+
+ Cmd = XUSBPSU_DEPCMD_ENDTRANSFER;
+ Cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex);
+ (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction,
+ Cmd, Params);
+ Ept->ResourceIndex = 0U;
+ XUsbSleep(200U);
+}
+
+/****************************************************************************/
+/**
+* Handles Transfer Not Ready event of Control Endpoints EP0 OUT and EP0 IN.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is a pointer to the Endpoint event occured in core.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0XferNotReady(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event)
+{
+ struct XUsbPsu_Ep *Ept;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Event != NULL);
+
+ Ept = &InstancePtr->eps[Event->Epnumber];
+
+ switch (Event->Status) {
+ case DEPEVT_STATUS_CONTROL_DATA:
+ /*
+ * We already have a DATA transfer in the controller's cache,
+ * if we receive a XferNotReady(DATA) we will ignore it, unless
+ * it's for the wrong direction.
+ *
+ * In that case, we must issue END_TRANSFER command to the Data
+ * Phase we already have started and issue SetStall on the
+ * control endpoint.
+ */
+ if (Event->Epnumber != InstancePtr->ControlDir) {
+ XUsbPsu_Ep0_EndControlData(InstancePtr, Ept);
+ XUsbPsu_Ep0StallRestart(InstancePtr);
+ }
+ break;
+
+ case DEPEVT_STATUS_CONTROL_STATUS:
+ (void)XUsbPsu_Ep0StartStatus(InstancePtr, Event);
+ break;
+
+ default:
+ /* Default case is a required MIRSA-C guideline. */
+ break;
+ }
+}
+
+/****************************************************************************/
+/**
+* Handles Interrupts of Control Endpoints EP0 OUT and EP0 IN.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is a pointer to the Endpoint event occured in core.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0Intr(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event)
+{
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Event != NULL);
+
+ switch (Event->Endpoint_Event) {
+ case XUSBPSU_DEPEVT_XFERCOMPLETE:
+ XUsbPsu_Ep0XferComplete(InstancePtr, Event);
+ break;
+
+ case XUSBPSU_DEPEVT_XFERNOTREADY:
+ XUsbPsu_Ep0XferNotReady(InstancePtr, Event);
+ break;
+
+ case XUSBPSU_DEPEVT_XFERINPROGRESS:
+ case XUSBPSU_DEPEVT_STREAMEVT:
+ case XUSBPSU_DEPEVT_EPCMDCMPLT:
+ break;
+
+ default:
+ /* Default case is a required MIRSA-C guideline. */
+ break;
+ }
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to send data on Control Endpoint EP0 IN to Host.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param BufferPtr is pointer to data.
+* @param BufferLen is Length of data buffer.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 BufferLen)
+{
+ /* Control IN - EP1 */
+ struct XUsbPsu_EpParams *Params;
+ struct XUsbPsu_Ep *Ept;
+ struct XUsbPsu_Trb *TrbPtr;
+ s32 Ret;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(BufferPtr != NULL);
+
+ Ept = &InstancePtr->eps[1];
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+
+ if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
+ return XST_FAILURE;
+ }
+
+ Ept->RequestedBytes = BufferLen;
+ Ept->BytesTxed = 0U;
+ Ept->BufferPtr = BufferPtr;
+
+ TrbPtr = &InstancePtr->Ep0_Trb;
+
+ TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr;
+ TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16;
+ TrbPtr->Size = BufferLen;
+ TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_DATA;
+
+ TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+ | XUSBPSU_TRB_CTRL_LST
+ | XUSBPSU_TRB_CTRL_IOC
+ | XUSBPSU_TRB_CTRL_ISP_IMI);
+
+ Params->Param0 = 0U;
+ Params->Param1 = (UINTPTR)TrbPtr;
+
+ Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+ Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen);
+
+ InstancePtr->Ep0State = XUSBPSU_EP0_DATA_PHASE;
+
+ Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_IN,
+ XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+ if (Ret != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ Ept->EpStatus |= XUSBPSU_EP_BUSY;
+ Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+ Ept->UsbEpNum, Ept->Direction);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to receive data on Control Endpoint EP0 OUT from Host.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param BufferPtr is pointer to data.
+* @param Length is Length of data to be received.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length)
+{
+ struct XUsbPsu_EpParams *Params;
+ struct XUsbPsu_Ep *Ept;
+ struct XUsbPsu_Trb *TrbPtr;
+ u32 Size;
+ s32 Ret;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(BufferPtr != NULL);
+
+ Ept = &InstancePtr->eps[0];
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+
+ if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
+ return XST_FAILURE;
+ }
+
+ Ept->RequestedBytes = Length;
+ Size = Length;
+ Ept->BytesTxed = 0U;
+ Ept->BufferPtr = BufferPtr;
+
+ /*
+ * 8.2.5 - An OUT transfer size (Total TRB buffer allocation)
+ * must be a multiple of MaxPacketSize even if software is expecting a
+ * fixed non-multiple of MaxPacketSize transfer from the Host.
+ */
+ if (!IS_ALIGNED(Length, Ept->MaxSize)) {
+ Size = (u32)roundup(Length, Ept->MaxSize);
+ InstancePtr->UnalignedTx = 1U;
+ }
+
+ TrbPtr = &InstancePtr->Ep0_Trb;
+
+ TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr;
+ TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16;
+ TrbPtr->Size = Size;
+ TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_DATA;
+
+ TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+ | XUSBPSU_TRB_CTRL_LST
+ | XUSBPSU_TRB_CTRL_IOC
+ | XUSBPSU_TRB_CTRL_ISP_IMI);
+
+ Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+ Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length);
+
+ Params->Param0 = 0U;
+ Params->Param1 = (UINTPTR)TrbPtr;
+
+ InstancePtr->Ep0State = XUSBPSU_EP0_DATA_PHASE;
+
+ Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT,
+ XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+ if (Ret != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ Ept->EpStatus |= XUSBPSU_EP_BUSY;
+ Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+ Ept->UsbEpNum, Ept->Direction);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* API for Sleep routine.
+*
+* @param USeconds is time in MicroSeconds.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XUsbSleep(u32 USeconds) {
+ (void)usleep(USeconds);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c
new file mode 100644
index 000000000..41368e526
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c
@@ -0,0 +1,927 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_endpoint.c
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0 sg 06/06/16 First release
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xusbpsu.h"
+#include "xusbpsu_endpoint.h"
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* return Physical EP number as dwc3 mapping */
+#define PhysicalEp(epnum, direction) (((epnum) << 1 ) | (direction))
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+* Returns zeroed parameters to be used by Endpoint commands
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return Zeroed Params structure pointer.
+*
+* @note None.
+*
+*****************************************************************************/
+struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr)
+{
+ if (InstancePtr == NULL) {
+ return NULL;
+ }
+
+ InstancePtr->EpParams.Param0 = 0x00U;
+ InstancePtr->EpParams.Param1 = 0x00U;
+ InstancePtr->EpParams.Param2 = 0x00U;
+
+ return &InstancePtr->EpParams;
+}
+
+/****************************************************************************/
+/**
+* Returns Transfer Index assigned by Core for an Endpoint transfer.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEpNum is USB endpoint number.
+* @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT
+*
+* @return Transfer Resource Index.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum,
+ u8 Dir)
+{
+ u8 PhyEpNum;
+ u32 ResourceIndex;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+ Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+ (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = (u8)PhysicalEp(UsbEpNum, Dir);
+ ResourceIndex = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEPCMD(PhyEpNum));
+
+ return (u32)XUSBPSU_DEPCMD_GET_RSC_IDX(ResourceIndex);
+}
+
+/****************************************************************************/
+/**
+* Sends Endpoint command to Endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEpNum is USB endpoint number.
+* @param Dir is direction of endpoint
+* - XUSBPSU_EP_DIR_IN/ XUSBPSU_EP_DIR_OUT.
+* @param Cmd is Endpoint command.
+* @param Params is Endpoint command parameters.
+*
+* @return XST_SUCCESS else XST_FAILURE.
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+ u32 Cmd, struct XUsbPsu_EpParams *Params)
+{
+ u32 PhyEpNum;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+ Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+ (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = PhysicalEp(UsbEpNum, Dir);
+
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR0(PhyEpNum),
+ Params->Param0);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR1(PhyEpNum),
+ Params->Param1);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR2(PhyEpNum),
+ Params->Param2);
+
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMD(PhyEpNum),
+ Cmd | XUSBPSU_DEPCMD_CMDACT);
+
+ if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DEPCMD(PhyEpNum),
+ XUSBPSU_DEPCMD_CMDACT, 500U) == (s32)XST_FAILURE) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sends Start New Configuration command to Endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEpNum is USB endpoint number.
+* @param Dir is direction of endpoint
+* - XUSBPSU_EP_DIR_IN/ XUSBPSU_EP_DIR_OUT.
+*
+* @return XST_SUCCESS else XST_FAILURE.
+*
+* @note
+* As per data book this command should be issued by software
+* under these conditions:
+* 1. After power-on-reset with XferRscIdx=0 before starting
+* to configure Physical Endpoints 0 and 1.
+* 2. With XferRscIdx=2 before starting to configure
+* Physical Endpoints > 1
+* 3. This command should always be issued to
+* Endpoint 0 (DEPCMD0).
+*
+*****************************************************************************/
+s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum, u8 Dir)
+{
+ struct XUsbPsu_EpParams *Params;
+ u32 Cmd;
+ u8 PhyEpNum;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEpNum <= (u32)16U);
+ Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+ (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = (u8)PhysicalEp(UsbEpNum, (u32)Dir);
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+
+ if (PhyEpNum != 1U) {
+ Cmd = XUSBPSU_DEPCMD_DEPSTARTCFG;
+ /* XferRscIdx == 0 for EP0 and 2 for the remaining */
+ if (PhyEpNum > 1U) {
+ if (InstancePtr->IsConfigDone != 0U) {
+ return XST_SUCCESS;
+ }
+ InstancePtr->IsConfigDone = 1U;
+ Cmd |= XUSBPSU_DEPCMD_PARAM(2);
+ }
+
+ return XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT,
+ Cmd, Params);
+ }
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sends Set Endpoint Configuration command to Endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEpNum is USB endpoint number.
+* @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+* @param Size is size of Endpoint size.
+* @param Type is Endpoint type Control/Bulk/Interrupt/Isoc.
+*
+* @return XST_SUCCESS else XST_FAILURE.
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+ u16 Size, u8 Type)
+{
+ struct XUsbPsu_EpParams *Params;
+ u8 PhyEpNum;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+ Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+ (Dir == XUSBPSU_EP_DIR_OUT));
+ Xil_AssertNonvoid((Size >= 64U) && (Size <= 1024U));
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+
+ PhyEpNum = PhysicalEp(UsbEpNum , Dir);
+
+ Params->Param0 = XUSBPSU_DEPCFG_EP_TYPE(Type)
+ | XUSBPSU_DEPCFG_MAX_PACKET_SIZE(Size);
+
+ /*
+ * Set burst size to 1 as recommended
+ */
+ Params->Param0 |= XUSBPSU_DEPCFG_BURST_SIZE(1);
+
+ Params->Param1 = XUSBPSU_DEPCFG_XFER_COMPLETE_EN
+ | XUSBPSU_DEPCFG_XFER_NOT_READY_EN;
+
+ /*
+ * We are doing 1:1 mapping for endpoints, meaning
+ * Physical Endpoints 2 maps to Logical Endpoint 2 and
+ * so on. We consider the direction bit as part of the physical
+ * endpoint number. So USB endpoint 0x81 is 0x03.
+ */
+ Params->Param1 |= XUSBPSU_DEPCFG_EP_NUMBER(PhyEpNum);
+
+ if (Dir != XUSBPSU_EP_DIR_OUT) {
+ Params->Param0 |= XUSBPSU_DEPCFG_FIFO_NUMBER((u32)PhyEpNum >> 1);
+ }
+
+ return XUsbPsu_SendEpCmd(InstancePtr, UsbEpNum, Dir,
+ XUSBPSU_DEPCMD_SETEPCONFIG, Params);
+}
+
+/****************************************************************************/
+/**
+* Sends Set Transfer Resource command to Endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEpNum is USB endpoint number.
+* @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/
+* XUSBPSU_EP_DIR_OUT.
+*
+* @return XST_SUCCESS else XST_FAILURE.
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
+{
+ struct XUsbPsu_EpParams *Params;
+
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+ Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+ (Dir == XUSBPSU_EP_DIR_OUT));
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+
+ Params->Param0 = XUSBPSU_DEPXFERCFG_NUM_XFER_RES(1);
+
+ return XUsbPsu_SendEpCmd(InstancePtr, UsbEpNum, Dir,
+ XUSBPSU_DEPCMD_SETTRANSFRESOURCE, Params);
+}
+
+/****************************************************************************/
+/**
+* Enables Endpoint for sending/receiving data.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEpNum is USB endpoint number.
+* @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+* @param Maxsize is size of Endpoint size.
+* @param Type is Endpoint type Control/Bulk/Interrupt/Isoc.
+*
+* @return XST_SUCCESS else XST_FAILURE.
+*
+* @note None.
+*
+****************************************************************************/
+s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+ u16 Maxsize, u8 Type)
+{
+ struct XUsbPsu_Ep *Ept;
+ u32 RegVal;
+ s32 Ret = (s32)XST_FAILURE;
+ u32 PhyEpNum;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+ Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+ (Dir == XUSBPSU_EP_DIR_OUT));
+ Xil_AssertNonvoid((Maxsize >= 64U) && (Maxsize <= 1024U));
+
+ PhyEpNum = PhysicalEp(UsbEpNum , Dir);
+ Ept = &InstancePtr->eps[PhyEpNum];
+
+ Ept->UsbEpNum = UsbEpNum;
+ Ept->Direction = Dir;
+ Ept->Type = Type;
+ Ept->MaxSize = Maxsize;
+ Ept->PhyEpNum = (u8)PhyEpNum;
+
+ if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) {
+ Ret = XUsbPsu_StartEpConfig(InstancePtr, UsbEpNum, Dir);
+ if (Ret != 0) {
+ return Ret;
+ }
+ }
+
+ Ret = XUsbPsu_SetEpConfig(InstancePtr, UsbEpNum, Dir, Maxsize, Type);
+ if (Ret != 0) {
+ return Ret;
+ }
+
+ if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) {
+ Ret = XUsbPsu_SetXferResource(InstancePtr, UsbEpNum, Dir);
+ if (Ret != 0) {
+ return Ret;
+ }
+
+ Ept->EpStatus |= XUSBPSU_EP_ENABLED;
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA);
+ RegVal |= XUSBPSU_DALEPENA_EP(Ept->PhyEpNum);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal);
+ }
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Disables Endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEpNum is USB endpoint number.
+* @param Dir is direction of endpoint
+* - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+*
+* @return XST_SUCCESS else XST_FAILURE.
+*
+* @note None.
+*
+****************************************************************************/
+s32 XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
+{
+ u32 RegVal;
+ u8 PhyEpNum;
+ struct XUsbPsu_Ep *Ept;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+ Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+ (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = PhysicalEp(UsbEpNum , Dir);
+ Ept = &InstancePtr->eps[PhyEpNum];
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA);
+ RegVal &= ~XUSBPSU_DALEPENA_EP(PhyEpNum);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal);
+
+ Ept->Type = 0U;
+ Ept->EpStatus = 0U;
+ Ept->MaxSize = 0U;
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enables USB Control Endpoint i.e., EP0OUT and EP0IN of Core.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Size is control endpoint size.
+*
+* @return XST_SUCCESS else XST_FAILURE.
+*
+* @note None.
+*
+****************************************************************************/
+s32 XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 Size)
+{
+ s32 RetVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid((Size >= 64U) && (Size <= 512U));
+
+ RetVal = XUsbPsu_EpEnable(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT, Size,
+ XUSBPSU_ENDPOINT_XFER_CONTROL);
+ if (RetVal != 0) {
+ return XST_FAILURE;
+ }
+
+ RetVal = XUsbPsu_EpEnable(InstancePtr, 0U, XUSBPSU_EP_DIR_IN, Size,
+ XUSBPSU_ENDPOINT_XFER_CONTROL);
+ if (RetVal != 0) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Initializes Endpoints. All OUT endpoints are even numbered and all IN
+* endpoints are odd numbered. EP0 is for Control OUT and EP1 is for
+* Control IN.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr)
+{
+ u8 i;
+ u8 Epnum;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ for (i = 0U; i < InstancePtr->NumOutEps; i++) {
+ Epnum = (i << 1U) | XUSBPSU_EP_DIR_OUT;
+ InstancePtr->eps[Epnum].PhyEpNum = Epnum;
+ InstancePtr->eps[Epnum].Direction = XUSBPSU_EP_DIR_OUT;
+ }
+ for (i = 0U; i < InstancePtr->NumInEps; i++) {
+ Epnum = (i << 1U) | XUSBPSU_EP_DIR_IN;
+ InstancePtr->eps[Epnum].PhyEpNum = Epnum;
+ InstancePtr->eps[Epnum].Direction = XUSBPSU_EP_DIR_IN;
+ }
+}
+
+/****************************************************************************/
+/**
+* Stops transfer on Endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEpNum is USB endpoint number.
+* @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
+{
+ struct XUsbPsu_Ep *Ept;
+ struct XUsbPsu_EpParams *Params;
+ u8 PhyEpNum;
+ u32 Cmd;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(UsbEpNum <= (u8)16U);
+ Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = PhysicalEp(UsbEpNum, Dir);
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertVoid(Params != NULL);
+
+ Ept = &InstancePtr->eps[PhyEpNum];
+
+ if (Ept->ResourceIndex == 0U) {
+ return;
+ }
+
+ /*
+ * - Issue EndTransfer WITH CMDIOC bit set
+ * - Wait 100us
+ */
+ Cmd = XUSBPSU_DEPCMD_ENDTRANSFER;
+ Cmd |= XUSBPSU_DEPCMD_CMDIOC;
+ Cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex);
+ (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction,
+ Cmd, Params);
+ Ept->ResourceIndex = 0U;
+ Ept->EpStatus &= ~XUSBPSU_EP_BUSY;
+ XUsbSleep(100U);
+}
+
+/****************************************************************************/
+/**
+* Clears Stall on all endpoints.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr)
+{
+ struct XUsbPsu_EpParams *Params;
+ u32 Epnum;
+ struct XUsbPsu_Ep *Ept;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertVoid(Params != NULL);
+
+ for (Epnum = 1U; Epnum < XUSBPSU_ENDPOINTS_NUM; Epnum++) {
+
+ Ept = &InstancePtr->eps[Epnum];
+ if (Ept == NULL) {
+ continue;
+ }
+
+ if ((Ept->EpStatus & XUSBPSU_EP_STALL) == 0U) {
+ continue;
+ }
+
+ Ept->EpStatus &= ~XUSBPSU_EP_STALL;
+
+ (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum,
+ Ept->Direction, XUSBPSU_DEPCMD_CLEARSTALL,
+ Params);
+ }
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to send data on endpoint to Host.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEp is USB endpoint number.
+* @param BufferPtr is pointer to data.
+* @param BufferLen is length of data buffer.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp,
+ u8 *BufferPtr, u32 BufferLen)
+{
+ u8 PhyEpNum;
+ s32 RetVal;
+ struct XUsbPsu_Trb *TrbPtr;
+ struct XUsbPsu_Ep *Ept;
+ struct XUsbPsu_EpParams *Params;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEp <= (u8)16U);
+ Xil_AssertNonvoid(BufferPtr != NULL);
+
+ PhyEpNum = PhysicalEp(UsbEp, XUSBPSU_EP_DIR_IN);
+ if (PhyEpNum == 1U) {
+ RetVal = XUsbPsu_Ep0Send(InstancePtr, BufferPtr, BufferLen);
+ return RetVal;
+ }
+
+ Ept = &InstancePtr->eps[PhyEpNum];
+
+ if (Ept->Direction != XUSBPSU_EP_DIR_IN) {
+ return XST_FAILURE;
+ }
+
+ Ept->RequestedBytes = BufferLen;
+ Ept->BytesTxed = 0U;
+ Ept->BufferPtr = BufferPtr;
+
+ TrbPtr = &Ept->EpTrb;
+ Xil_AssertNonvoid(TrbPtr != NULL);
+
+ TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr;
+ TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16;
+ TrbPtr->Size = BufferLen & XUSBPSU_TRB_SIZE_MASK;
+ TrbPtr->Ctrl = XUSBPSU_TRBCTL_NORMAL;
+
+ TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+ | XUSBPSU_TRB_CTRL_LST
+ | XUSBPSU_TRB_CTRL_IOC
+ | XUSBPSU_TRB_CTRL_ISP_IMI);
+
+ Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+ Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen);
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+ Params->Param0 = 0U;
+ Params->Param1 = (UINTPTR)TrbPtr;
+
+ RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction,
+ XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+ if (RetVal != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+ Ept->UsbEpNum,
+ Ept->Direction);
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to receive data on Endpoint from Host.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param EpNum is USB endpoint number.
+* @param BufferPtr is pointer to data.
+* @param Length is length of data to be received.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp,
+ u8 *BufferPtr, u32 Length)
+{
+ u8 PhyEpNum;
+ u32 Size;
+ s32 RetVal;
+ struct XUsbPsu_Trb *TrbPtr;
+ struct XUsbPsu_Ep *Ept;
+ struct XUsbPsu_EpParams *Params;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEp <= (u8)16U);
+ Xil_AssertNonvoid(BufferPtr != NULL);
+
+ PhyEpNum = PhysicalEp(UsbEp, XUSBPSU_EP_DIR_OUT);
+ if (PhyEpNum == 0U) {
+ RetVal = XUsbPsu_Ep0Recv(InstancePtr, BufferPtr, Length);
+ return RetVal;
+ }
+
+ Ept = &InstancePtr->eps[PhyEpNum];
+
+ if (Ept->Direction != XUSBPSU_EP_DIR_OUT) {
+ return XST_FAILURE;
+ }
+
+ Ept->RequestedBytes = Length;
+ Size = Length;
+ Ept->BytesTxed = 0U;
+ Ept->BufferPtr = BufferPtr;
+
+ /*
+ * 8.2.5 - An OUT transfer size (Total TRB buffer allocation)
+ * must be a multiple of MaxPacketSize even if software is expecting a
+ * fixed non-multiple of MaxPacketSize transfer from the Host.
+ */
+ if (!IS_ALIGNED(Length, Ept->MaxSize)) {
+ Size = (u32)roundup(Length, Ept->MaxSize);
+ Ept->UnalignedTx = 1U;
+ }
+
+ TrbPtr = &Ept->EpTrb;
+ Xil_AssertNonvoid(TrbPtr != NULL);
+
+ TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr;
+ TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16;
+ TrbPtr->Size = Size;
+ TrbPtr->Ctrl = XUSBPSU_TRBCTL_NORMAL;
+
+ TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+ | XUSBPSU_TRB_CTRL_LST
+ | XUSBPSU_TRB_CTRL_IOC
+ | XUSBPSU_TRB_CTRL_ISP_IMI);
+
+
+ Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+ Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length);
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+ Params->Param0 = 0U;
+ Params->Param1 = (UINTPTR)TrbPtr;
+
+ RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction,
+ XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+ if (RetVal != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+ Ept->UsbEpNum,
+ Ept->Direction);
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Stalls an Endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param EpNum is USB endpoint number.
+* @param Dir is direction.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
+{
+ u8 PhyEpNum;
+ struct XUsbPsu_Ep *Ept = NULL;
+ struct XUsbPsu_EpParams *Params;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Epnum <= (u8)16U);
+ Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = PhysicalEp(Epnum, Dir);
+ Ept = &InstancePtr->eps[PhyEpNum];
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertVoid(Params != NULL);
+
+ (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction,
+ XUSBPSU_DEPCMD_SETSTALL, Params);
+
+ Ept->EpStatus |= XUSBPSU_EP_STALL;
+}
+
+/****************************************************************************/
+/**
+* Clears Stall on an Endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param EpNum is USB endpoint number.
+* @param Dir is direction.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_EpClearStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
+{
+ u8 PhyEpNum;
+ struct XUsbPsu_Ep *Ept = NULL;
+ struct XUsbPsu_EpParams *Params;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Epnum <= (u8)16U);
+ Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = PhysicalEp(Epnum, Dir);
+ Ept = &InstancePtr->eps[PhyEpNum];
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertVoid(Params != NULL);
+
+ (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction,
+ XUSBPSU_DEPCMD_CLEARSTALL, Params);
+
+ Ept->EpStatus &= ~XUSBPSU_EP_STALL;
+}
+
+/****************************************************************************/
+/**
+* Sets an user handler to be called after data is sent/received by an Endpoint
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param EpNum is USB endpoint number.
+* @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+* @param Handler is user handler to be called.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_SetEpHandler(struct XUsbPsu *InstancePtr, u8 Epnum,
+ u8 Dir, void (*Handler)(void *, u32, u32))
+{
+ u8 PhyEpNum;
+ struct XUsbPsu_Ep *Ept;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Epnum <= (u8)16U);
+ Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = PhysicalEp(Epnum, Dir);
+ Ept = &InstancePtr->eps[PhyEpNum];
+ Ept->Handler = Handler;
+}
+
+/****************************************************************************/
+/**
+* Returns status of endpoint - Stalled or not
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param EpNum is USB endpoint number.
+* @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+*
+* @return
+* 1 - if stalled
+* 0 - if not stalled
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_IsEpStalled(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
+{
+ u8 PhyEpNum;
+ struct XUsbPsu_Ep *Ept;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Epnum <= (u8)16U);
+ Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = PhysicalEp(Epnum, Dir);
+ Ept = &InstancePtr->eps[PhyEpNum];
+
+ return (s32)(!!(Ept->EpStatus & XUSBPSU_EP_STALL));
+}
+
+/****************************************************************************/
+/**
+* Checks the Data Phase and calls user Endpoint handler.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is a pointer to the Endpoint event occured in core.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event)
+{
+ struct XUsbPsu_Ep *Ept;
+ struct XUsbPsu_Trb *TrbPtr;
+ u32 Length;
+ u32 Epnum;
+ u8 Dir;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Event != NULL);
+
+ Epnum = Event->Epnumber;
+ Ept = &InstancePtr->eps[Epnum];
+ Dir = Ept->Direction;
+ TrbPtr = &Ept->EpTrb;
+ Xil_AssertVoid(TrbPtr != NULL);
+
+ Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+ Length = TrbPtr->Size & XUSBPSU_TRB_SIZE_MASK;
+
+ if (Length == 0U) {
+ Ept->BytesTxed = Ept->RequestedBytes;
+ } else {
+ if (Dir == XUSBPSU_EP_DIR_IN) {
+ Ept->BytesTxed = Ept->RequestedBytes - Length;
+ } else if (Dir == XUSBPSU_EP_DIR_OUT) {
+ if (Ept->UnalignedTx == 1U) {
+ Ept->BytesTxed = Ept->RequestedBytes;
+ Ept->UnalignedTx = 0U;
+ }
+ }
+ }
+
+ if (Dir == XUSBPSU_EP_DIR_OUT) {
+ /* Invalidate Cache */
+ Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed);
+ }
+
+ if (Ept->Handler != NULL) {
+ Ept->Handler(InstancePtr, Ept->RequestedBytes, Ept->BytesTxed);
+ }
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h
new file mode 100644
index 000000000..299837862
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h
@@ -0,0 +1,184 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_endpoint.h
+* @addtogroup usbpsu_v1_0
+* @{
+ *
+ * This is an internal file containing the definitions for endpoints. It is
+ * included by the xusbps_endpoint.c which is implementing the endpoint
+ * functions and by xusbps_intr.c.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.0 sg 06/06/16 First release
+ *
+ *
+ ******************************************************************************/
+#ifndef XUSBPSU_ENDPOINT_H
+#define XUSBPSU_ENDPOINT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xusbpsu.h"
+#include "xil_types.h"
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Device Generic Command Register */
+#define XUSBPSU_DGCMD_SET_LMP 0x00000001U
+#define XUSBPSU_DGCMD_SET_PERIODIC_PAR 0x00000002U
+#define XUSBPSU_DGCMD_XMIT_FUNCTION 0x00000003U
+
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x00000004U
+#define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x00000005U
+
+#define XUSBPSU_DGCMD_SELECTED_FIFO_FLUSH 0x00000009U
+#define XUSBPSU_DGCMD_ALL_FIFO_FLUSH 0x0000000aU
+#define XUSBPSU_DGCMD_SET_ENDPOINT_NRDY 0x0000000cU
+#define XUSBPSU_DGCMD_RUN_SOC_BUS_LOOPBACK 0x00000010U
+
+#define XUSBPSU_DGCMD_STATUS(n) (((u32)(n) >> 15) & 1)
+#define XUSBPSU_DGCMD_CMDACT (0x00000001U << 10)
+#define XUSBPSU_DGCMD_CMDIOC (0x00000001U << 8)
+
+/* Device Generic Command Parameter Register */
+#define XUSBPSU_DGCMDPAR_FORCE_LINKPM_ACCEPT (0x00000001U << 0)
+#define XUSBPSU_DGCMDPAR_FIFO_NUM(n) ((u32)(n) << 0)
+#define XUSBPSU_DGCMDPAR_RX_FIFO (0x00000000U << 5)
+#define XUSBPSU_DGCMDPAR_TX_FIFO (0x00000001U << 5)
+#define XUSBPSU_DGCMDPAR_LOOPBACK_DIS (0x00000000U << 0)
+#define XUSBPSU_DGCMDPAR_LOOPBACK_ENA (0x00000001U << 0)
+
+/* Device Endpoint Command Register */
+#define XUSBPSU_DEPCMD_PARAM_SHIFT 16U
+#define XUSBPSU_DEPCMD_PARAM(x) ((u32)(x) << XUSBPSU_DEPCMD_PARAM_SHIFT)
+#define XUSBPSU_DEPCMD_GET_RSC_IDX(x) (((u32)(x) >> XUSBPSU_DEPCMD_PARAM_SHIFT) & \
+ (u32)0x0000007fU)
+#define XUSBPSU_DEPCMD_STATUS(x) (((u32)(x) >> 12) & (u32)0xF)
+#define XUSBPSU_DEPCMD_HIPRI_FORCERM (0x00000001U << 11)
+#define XUSBPSU_DEPCMD_CMDACT (0x00000001U << 10)
+#define XUSBPSU_DEPCMD_CMDIOC (0x00000001U << 8)
+
+#define XUSBPSU_DEPCMD_DEPSTARTCFG 0x00000009U
+#define XUSBPSU_DEPCMD_ENDTRANSFER 0x00000008U
+#define XUSBPSU_DEPCMD_UPDATETRANSFER 0x00000007U
+#define XUSBPSU_DEPCMD_STARTTRANSFER 0x00000006U
+#define XUSBPSU_DEPCMD_CLEARSTALL 0x00000005U
+#define XUSBPSU_DEPCMD_SETSTALL 0x00000004U
+#define XUSBPSU_DEPCMD_GETEPSTATE 0x00000003U
+#define XUSBPSU_DEPCMD_SETTRANSFRESOURCE 0x00000002U
+#define XUSBPSU_DEPCMD_SETEPCONFIG 0x00000001U
+
+/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
+#define XUSBPSU_DALEPENA_EP(n) (0x00000001U << (n))
+
+#define XUSBPSU_DEPCFG_INT_NUM(n) ((u32)(n) << 0)
+#define XUSBPSU_DEPCFG_XFER_COMPLETE_EN (0x00000001U << 8)
+#define XUSBPSU_DEPCFG_XFER_IN_PROGRESS_EN (0x00000001U << 9)
+#define XUSBPSU_DEPCFG_XFER_NOT_READY_EN (0x00000001U << 10)
+#define XUSBPSU_DEPCFG_FIFO_ERROR_EN (0x00000001U << 11)
+#define XUSBPSU_DEPCFG_STREAM_EVENT_EN (0x00000001U << 13)
+#define XUSBPSU_DEPCFG_BINTERVAL_M1(n) ((u32)(n) << 16)
+#define XUSBPSU_DEPCFG_STREAM_CAPABLE (0x00000001U << 24)
+#define XUSBPSU_DEPCFG_EP_NUMBER(n) ((u32)(n) << 25)
+#define XUSBPSU_DEPCFG_BULK_BASED (0x00000001U << 30)
+#define XUSBPSU_DEPCFG_FIFO_BASED (0x00000001U << 31)
+
+/* DEPCFG parameter 0 */
+#define XUSBPSU_DEPCFG_EP_TYPE(n) ((u32)(n) << 1)
+#define XUSBPSU_DEPCFG_MAX_PACKET_SIZE(n) ((u32)(n) << 3)
+#define XUSBPSU_DEPCFG_FIFO_NUMBER(n) ((u32)(n) << 17)
+#define XUSBPSU_DEPCFG_BURST_SIZE(n) ((u32)(n) << 22)
+#define XUSBPSU_DEPCFG_DATA_SEQ_NUM(n) ((u32)(n) << 26)
+/* This applies for core versions earlier than 1.94a */
+#define XUSBPSU_DEPCFG_IGN_SEQ_NUM (0x00000001U << 31)
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DEPCFG_ACTION_INIT (0x00000000U << 30)
+#define XUSBPSU_DEPCFG_ACTION_RESTORE (0x00000001U << 30)
+#define XUSBPSU_DEPCFG_ACTION_MODIFY (0x00000002U << 30)
+
+/* DEPXFERCFG parameter 0 */
+#define XUSBPSU_DEPXFERCFG_NUM_XFER_RES(n) ((u32)(n) & (u32)0xffff)
+
+#define XUSBPSU_DEPCMD_TYPE_BULK 2U
+#define XUSBPSU_DEPCMD_TYPE_INTR 3U
+
+/* TRB Length, PCM and Status */
+#define XUSBPSU_TRB_SIZE_MASK (0x00ffffffU)
+#define XUSBPSU_TRB_SIZE_LENGTH(n) ((u32)(n) & XUSBPSU_TRB_SIZE_MASK)
+#define XUSBPSU_TRB_SIZE_PCM1(n) (((u32)(n) & (u32)0x03) << 24)
+#define XUSBPSU_TRB_SIZE_TRBSTS(n) (((u32)(n) & ((u32)0x0f << 28)) >> 28)
+
+#define XUSBPSU_TRBSTS_OK 0U
+#define XUSBPSU_TRBSTS_MISSED_ISOC 1U
+#define XUSBPSU_TRBSTS_SETUP_PENDING 2U
+#define XUSBPSU_TRB_STS_XFER_IN_PROG 4U
+
+/* TRB Control */
+#define XUSBPSU_TRB_CTRL_HWO ((u32)0x00000001U << 0)
+#define XUSBPSU_TRB_CTRL_LST ((u32)0x00000001U << 1)
+#define XUSBPSU_TRB_CTRL_CHN ((u32)0x00000001U << 2)
+#define XUSBPSU_TRB_CTRL_CSP ((u32)0x00000001U << 3)
+#define XUSBPSU_TRB_CTRL_TRBCTL(n) (((u32)(n) & (u32)0x3f) << 4)
+#define XUSBPSU_TRB_CTRL_ISP_IMI (0x00000001U << 10)
+#define XUSBPSU_TRB_CTRL_IOC (0x00000001U << 11)
+#define XUSBPSU_TRB_CTRL_SID_SOFN(n) (((u32)(n) & (u32)0xffff) << 14)
+
+#define XUSBPSU_TRBCTL_NORMAL XUSBPSU_TRB_CTRL_TRBCTL(1)
+#define XUSBPSU_TRBCTL_CONTROL_SETUP XUSBPSU_TRB_CTRL_TRBCTL(2)
+#define XUSBPSU_TRBCTL_CONTROL_STATUS2 XUSBPSU_TRB_CTRL_TRBCTL(3)
+#define XUSBPSU_TRBCTL_CONTROL_STATUS3 XUSBPSU_TRB_CTRL_TRBCTL(4)
+#define XUSBPSU_TRBCTL_CONTROL_DATA XUSBPSU_TRB_CTRL_TRBCTL(5)
+#define XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST XUSBPSU_TRB_CTRL_TRBCTL(6)
+#define XUSBPSU_TRBCTL_ISOCHRONOUS XUSBPSU_TRB_CTRL_TRBCTL(7)
+#define XUSBPSU_TRBCTL_LINK_TRB XUSBPSU_TRB_CTRL_TRBCTL(8)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPSU_ENDPOINT_H */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c
new file mode 100644
index 000000000..41a9b8c7a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xusbpsu.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUsbPsu_Config XUsbPsu_ConfigTable[] =
+{
+ {
+ XPAR_PSU_USB_0_DEVICE_ID,
+ XPAR_PSU_USB_0_BASEADDR
+ }
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h
new file mode 100644
index 000000000..db612b00f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h
@@ -0,0 +1,363 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_hw.h
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.0 sg 06/06/16 First release
+*
+*
+*
+*****************************************************************************/
+
+#ifndef XUSBPSU_HW_H /* Prevent circular inclusions */
+#define XUSBPSU_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+/************************** Constant Definitions ****************************/
+
+/**@name Register offsets
+ *
+ * The following constants provide access to each of the registers of the
+ * USBPSU device.
+ * @{
+ */
+
+/**/
+#define XUSBPSU_PORTSC_30 0x430
+#define XUSBPSU_PORTMSC_30 0x434
+
+/* XUSBPSU registers memory space boundries */
+#define XUSBPSU_GLOBALS_REGS_START 0xc100
+#define XUSBPSU_GLOBALS_REGS_END 0xc6ff
+#define XUSBPSU_DEVICE_REGS_START 0xc700
+#define XUSBPSU_DEVICE_REGS_END 0xcbff
+#define XUSBPSU_OTG_REGS_START 0xcc00
+#define XUSBPSU_OTG_REGS_END 0xccff
+
+/* Global Registers */
+#define XUSBPSU_GSBUSCFG0 0xc100
+#define XUSBPSU_GSBUSCFG1 0xc104
+#define XUSBPSU_GTXTHRCFG 0xc108
+#define XUSBPSU_GRXTHRCFG 0xc10c
+#define XUSBPSU_GCTL 0xc110
+#define XUSBPSU_GEVTEN 0xc114
+#define XUSBPSU_GSTS 0xc118
+#define XUSBPSU_GSNPSID 0xc120
+#define XUSBPSU_GGPIO 0xc124
+#define XUSBPSU_GUID 0xc128
+#define XUSBPSU_GUCTL 0xc12c
+#define XUSBPSU_GBUSERRADDR0 0xc130
+#define XUSBPSU_GBUSERRADDR1 0xc134
+#define XUSBPSU_GPRTBIMAP0 0xc138
+#define XUSBPSU_GPRTBIMAP1 0xc13c
+#define XUSBPSU_GHWPARAMS0_OFFSET 0xc140U
+#define XUSBPSU_GHWPARAMS1_OFFSET 0xc144U
+#define XUSBPSU_GHWPARAMS2_OFFSET 0xc148U
+#define XUSBPSU_GHWPARAMS3_OFFSET 0xc14cU
+#define XUSBPSU_GHWPARAMS4_OFFSET 0xc150U
+#define XUSBPSU_GHWPARAMS5_OFFSET 0xc154U
+#define XUSBPSU_GHWPARAMS6_OFFSET 0xc158U
+#define XUSBPSU_GHWPARAMS7_OFFSET 0xc15cU
+#define XUSBPSU_GDBGFIFOSPACE 0xc160
+#define XUSBPSU_GDBGLTSSM 0xc164
+#define XUSBPSU_GPRTBIMAP_HS0 0xc180
+#define XUSBPSU_GPRTBIMAP_HS1 0xc184
+#define XUSBPSU_GPRTBIMAP_FS0 0xc188
+#define XUSBPSU_GPRTBIMAP_FS1 0xc18c
+
+#define XUSBPSU_GUSB2PHYCFG(n) ((u32)0xc200 + ((u32)(n) * (u32)0x04))
+#define XUSBPSU_GUSB2I2CCTL(n) ((u32)0xc240 + ((u32)(n) * (u32)0x04))
+
+#define XUSBPSU_GUSB2PHYACC(n) ((u32)0xc280 + ((u32)(n) * (u32)0x04))
+
+#define XUSBPSU_GUSB3PIPECTL(n) ((u32)0xc2c0 + ((u32)(n) * (u32)0x04))
+
+#define XUSBPSU_GTXFIFOSIZ(n) ((u32)0xc300 + ((u32)(n) * (u32)0x04))
+#define XUSBPSU_GRXFIFOSIZ(n) ((u32)0xc380 + ((u32)(n) * (u32)0x04))
+
+#define XUSBPSU_GEVNTADRLO(n) ((u32)0xc400 + ((u32)(n) * (u32)0x10))
+#define XUSBPSU_GEVNTADRHI(n) ((u32)0xc404 + ((u32)(n) * (u32)0x10))
+#define XUSBPSU_GEVNTSIZ(n) ((u32)0xc408 + ((u32)(n) * (u32)0x10))
+#define XUSBPSU_GEVNTCOUNT(n) ((u32)0xc40c + ((u32)(n) * (u32)0x10))
+
+#define XUSBPSU_GHWPARAMS8 0x0000c600U
+
+/* Device Registers */
+#define XUSBPSU_DCFG 0x0000c700U
+#define XUSBPSU_DCTL 0x0000c704U
+#define XUSBPSU_DEVTEN 0x0000c708U
+#define XUSBPSU_DSTS 0x0000c70cU
+#define XUSBPSU_DGCMDPAR 0x0000c710U
+#define XUSBPSU_DGCMD 0x0000c714U
+#define XUSBPSU_DALEPENA 0x0000c720U
+#define XUSBPSU_DEPCMDPAR2(n) ((u32)0xc800 + ((u32)n * (u32)0x10))
+#define XUSBPSU_DEPCMDPAR1(n) ((u32)0xc804 + ((u32)n * (u32)0x10))
+#define XUSBPSU_DEPCMDPAR0(n) ((u32)0xc808 + ((u32)n * (u32)0x10))
+#define XUSBPSU_DEPCMD(n) ((u32)0xc80c + ((u32)n * (u32)0x10))
+
+/* OTG Registers */
+#define XUSBPSU_OCFG 0x0000cc00U
+#define XUSBPSU_OCTL 0x0000cc04U
+#define XUSBPSU_OEVT 0xcc08U
+#define XUSBPSU_OEVTEN 0xcc0CU
+#define XUSBPSU_OSTS 0xcc10U
+
+/* Bit fields */
+
+/* Global Configuration Register */
+#define XUSBPSU_GCTL_PWRDNSCALE(n) ((n) << 19)
+#define XUSBPSU_GCTL_U2RSTECN (1 << 16)
+#define XUSBPSU_GCTL_RAMCLKSEL(x) (((x) & XUSBPSU_GCTL_CLK_MASK) << 6)
+#define XUSBPSU_GCTL_CLK_BUS (0U)
+#define XUSBPSU_GCTL_CLK_PIPE (1U)
+#define XUSBPSU_GCTL_CLK_PIPEHALF (2U)
+#define XUSBPSU_GCTL_CLK_MASK (3U)
+
+#define XUSBPSU_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
+#define XUSBPSU_GCTL_PRTCAPDIR(n) ((n) << 12)
+#define XUSBPSU_GCTL_PRTCAP_HOST 1U
+#define XUSBPSU_GCTL_PRTCAP_DEVICE 2U
+#define XUSBPSU_GCTL_PRTCAP_OTG 3U
+
+#define XUSBPSU_GCTL_CORESOFTRESET (0x00000001U << 11)
+#define XUSBPSU_GCTL_SOFITPSYNC (0x00000001U << 10)
+#define XUSBPSU_GCTL_SCALEDOWN(n) ((u32)(n) << 4)
+#define XUSBPSU_GCTL_SCALEDOWN_MASK XUSBPSU_GCTL_SCALEDOWN(3)
+#define XUSBPSU_GCTL_DISSCRAMBLE (0x00000001U << 3)
+#define XUSBPSU_GCTL_U2EXIT_LFPS (0x00000001U << 2)
+#define XUSBPSU_GCTL_GBLHIBERNATIONEN (0x00000001U << 1)
+#define XUSBPSU_GCTL_DSBLCLKGTNG (0x00000001U << 0)
+
+/* Global Status Register Device Interrupt Mask */
+#define XUSBPSU_GSTS_DEVICE_IP_MASK 0x00000040
+
+/* Global USB2 PHY Configuration Register */
+#define XUSBPSU_GUSB2PHYCFG_PHYSOFTRST (0x00000001U << 31)
+#define XUSBPSU_GUSB2PHYCFG_SUSPHY (0x00000001U << 6)
+
+/* Global USB3 PIPE Control Register */
+#define XUSBPSU_GUSB3PIPECTL_PHYSOFTRST (0x00000001U << 31)
+#define XUSBPSU_GUSB3PIPECTL_SUSPHY (0x00000001U << 17)
+
+/* Global TX Fifo Size Register */
+#define XUSBPSU_GTXFIFOSIZ_TXFDEF(n) ((u32)(n) & (u32)0xffffU)
+#define XUSBPSU_GTXFIFOSIZ_TXFSTADDR(n) ((u32)(n) & 0xffff0000U)
+
+/* Global Event Size Registers */
+#define XUSBPSU_GEVNTSIZ_INTMASK ((u32)0x00000001U << 31U)
+#define XUSBPSU_GEVNTSIZ_SIZE(n) ((u32)(n) & (u32)0xffffU)
+
+/* Global HWPARAMS1 Register */
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT(n) (((u32)(n) & ((u32)3 << 24)) >> 24)
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT_NO 0U
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK 1U
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB 2U
+#define XUSBPSU_GHWPARAMS1_PWROPT(n) ((u32)(n) << 24)
+#define XUSBPSU_GHWPARAMS1_PWROPT_MASK XUSBPSU_GHWPARAMS1_PWROPT(3)
+
+/* Global HWPARAMS4 Register */
+#define XUSBPSU_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((u32)(n) & ((u32)0x0f << 13)) >> 13)
+#define XUSBPSU_MAX_HIBER_SCRATCHBUFS 15U
+
+/* Device Configuration Register */
+#define XUSBPSU_DCFG_DEVADDR(addr) ((u32)(addr) << 3)
+#define XUSBPSU_DCFG_DEVADDR_MASK XUSBPSU_DCFG_DEVADDR(0x7f)
+
+#define XUSBPSU_DCFG_SPEED_MASK 7U
+#define XUSBPSU_DCFG_SUPERSPEED 4U
+#define XUSBPSU_DCFG_HIGHSPEED 0U
+#define XUSBPSU_DCFG_FULLSPEED2 1U
+#define XUSBPSU_DCFG_LOWSPEED 2U
+#define XUSBPSU_DCFG_FULLSPEED1 3U
+
+#define XUSBPSU_DCFG_LPM_CAP (0x00000001U << 22U)
+
+/* Device Control Register */
+#define XUSBPSU_DCTL_RUN_STOP (0x00000001U << 31U)
+#define XUSBPSU_DCTL_CSFTRST ((u32)0x00000001U << 30U)
+#define XUSBPSU_DCTL_LSFTRST (0x00000001U << 29U)
+
+#define XUSBPSU_DCTL_HIRD_THRES_MASK (0x0000001fU << 24U)
+#define XUSBPSU_DCTL_HIRD_THRES(n) ((u32)(n) << 24)
+
+#define XUSBPSU_DCTL_APPL1RES (0x00000001U << 23)
+
+/* These apply for core versions 1.87a and earlier */
+#define XUSBPSU_DCTL_TRGTULST_MASK (0x0000000fU << 17)
+#define XUSBPSU_DCTL_TRGTULST(n) ((u32)(n) << 17)
+#define XUSBPSU_DCTL_TRGTULST_U2 (XUSBPSU_DCTL_TRGTULST(2))
+#define XUSBPSU_DCTL_TRGTULST_U3 (XUSBPSU_DCTL_TRGTULST(3))
+#define XUSBPSU_DCTL_TRGTULST_SS_DIS (XUSBPSU_DCTL_TRGTULST(4))
+#define XUSBPSU_DCTL_TRGTULST_RX_DET (XUSBPSU_DCTL_TRGTULST(5))
+#define XUSBPSU_DCTL_TRGTULST_SS_INACT (XUSBPSU_DCTL_TRGTULST(6))
+
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DCTL_KEEP_CONNECT (0x00000001U << 19)
+#define XUSBPSU_DCTL_L1_HIBER_EN (0x00000001U << 18)
+#define XUSBPSU_DCTL_CRS (0x00000001U << 17)
+#define XUSBPSU_DCTL_CSS (0x00000001U << 16)
+
+#define XUSBPSU_DCTL_INITU2ENA (0x00000001U << 12)
+#define XUSBPSU_DCTL_ACCEPTU2ENA (0x00000001U << 11)
+#define XUSBPSU_DCTL_INITU1ENA (0x00000001U << 10)
+#define XUSBPSU_DCTL_ACCEPTU1ENA (0x00000001U << 9)
+#define XUSBPSU_DCTL_TSTCTRL_MASK (0x0000000fU << 1)
+
+#define XUSBPSU_DCTL_ULSTCHNGREQ_MASK (0x0000000fU << 5)
+#define XUSBPSU_DCTL_ULSTCHNGREQ(n) (((u32)(n) << 5) & XUSBPSU_DCTL_ULSTCHNGREQ_MASK)
+
+#define XUSBPSU_DCTL_ULSTCHNG_NO_ACTION (XUSBPSU_DCTL_ULSTCHNGREQ(0))
+#define XUSBPSU_DCTL_ULSTCHNG_SS_DISABLED (XUSBPSU_DCTL_ULSTCHNGREQ(4))
+#define XUSBPSU_DCTL_ULSTCHNG_RX_DETECT (XUSBPSU_DCTL_ULSTCHNGREQ(5))
+#define XUSBPSU_DCTL_ULSTCHNG_SS_INACTIVE (XUSBPSU_DCTL_ULSTCHNGREQ(6))
+#define XUSBPSU_DCTL_ULSTCHNG_RECOVERY (XUSBPSU_DCTL_ULSTCHNGREQ(8))
+#define XUSBPSU_DCTL_ULSTCHNG_COMPLIANCE (XUSBPSU_DCTL_ULSTCHNGREQ(10))
+#define XUSBPSU_DCTL_ULSTCHNG_LOOPBACK (XUSBPSU_DCTL_ULSTCHNGREQ(11))
+
+/* Device Event Enable Register */
+#define XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN ((u32)0x00000001 << 12)
+#define XUSBPSU_DEVTEN_EVNTOVERFLOWEN ((u32)0x00000001 << 11)
+#define XUSBPSU_DEVTEN_CMDCMPLTEN ((u32)0x00000001 << 10)
+#define XUSBPSU_DEVTEN_ERRTICERREN ((u32)0x00000001 << 9)
+#define XUSBPSU_DEVTEN_SOFEN ((u32)0x00000001 << 7)
+#define XUSBPSU_DEVTEN_EOPFEN ((u32)0x00000001 << 6)
+#define XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN ((u32)0x00000001 << 5)
+#define XUSBPSU_DEVTEN_WKUPEVTEN ((u32)0x00000001 << 4)
+#define XUSBPSU_DEVTEN_ULSTCNGEN ((u32)0x00000001 << 3)
+#define XUSBPSU_DEVTEN_CONNECTDONEEN ((u32)0x00000001 << 2)
+#define XUSBPSU_DEVTEN_USBRSTEN ((u32)0x00000001 << 1)
+#define XUSBPSU_DEVTEN_DISCONNEVTEN ((u32)0x00000001 << 0)
+
+/* Device Status Register */
+#define XUSBPSU_DSTS_DCNRD (0x00000001U << 29)
+
+/* This applies for core versions 1.87a and earlier */
+#define XUSBPSU_DSTS_PWRUPREQ (0x00000001U << 24)
+
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DSTS_RSS (0x00000001U << 25)
+#define XUSBPSU_DSTS_SSS (0x00000001U << 24)
+
+#define XUSBPSU_DSTS_COREIDLE (0x00000001U << 23)
+#define XUSBPSU_DSTS_DEVCTRLHLT (0x00000001U << 22)
+
+#define XUSBPSU_DSTS_USBLNKST_MASK (0x0000000fU << 18)
+#define XUSBPSU_DSTS_USBLNKST(n) (((u32)(n) & XUSBPSU_DSTS_USBLNKST_MASK) >> 18)
+
+#define XUSBPSU_DSTS_RXFIFOEMPTY (0x00000001U << 17)
+
+#define XUSBPSU_DSTS_SOFFN_MASK (0x00003fffU << 3)
+#define XUSBPSU_DSTS_SOFFN(n) (((u32)(n) & XUSBPSU_DSTS_SOFFN_MASK) >> 3)
+
+#define XUSBPSU_DSTS_CONNECTSPD (0x00000007U << 0)
+
+#define XUSBPSU_DSTS_SUPERSPEED (4U << 0)
+#define XUSBPSU_DSTS_HIGHSPEED (0U << 0)
+#define XUSBPSU_DSTS_FULLSPEED2 (1U << 0)
+#define XUSBPSU_DSTS_LOWSPEED (2U << 0)
+#define XUSBPSU_DSTS_FULLSPEED1 (3U << 0)
+
+/*Portpmsc 3.0 bit field*/
+#define XUSBPSU_PORTMSC_30_FLA_MASK (1U << 16)
+#define XUSBPSU_PORTMSC_30_U2_TIMEOUT_MASK (0xffU << 8)
+#define XUSBPSU_PORTMSC_30_U2_TIMEOUT_SHIFT (8U)
+#define XUSBPSU_PORTMSC_30_U1_TIMEOUT_MASK (0xffU << 0)
+#define XUSBPSU_PORTMSC_30_U1_TIMEOUT_SHIFT (0U)
+
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* Read a register of the USBPS8 device. This macro provides register
+* access to all registers using the register offsets defined above.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Offset is the offset of the register to read.
+*
+* @return The contents of the register.
+*
+* @note C-style Signature:
+* u32 XUsbPsu_ReadReg(struct XUsbPsu *InstancePtr, u32 Offset);
+*
+******************************************************************************/
+#define XUsbPsu_ReadReg(InstancePtr, Offset) \
+ Xil_In32((InstancePtr)->ConfigPtr->BaseAddress + (u32)(Offset))
+
+/*****************************************************************************/
+/**
+*
+* Write a register of the USBPS8 device. This macro provides
+* register access to all registers using the register offsets defined above.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param RegOffset is the offset of the register to write.
+* @param Data is the value to write to the register.
+*
+* @return None.
+*
+* @note C-style Signature:
+* void XUsbPsu_WriteReg(struct XUsbPsu *InstancePtr,
+* u32 Offset,u32 Data)
+*
+******************************************************************************/
+#define XUsbPsu_WriteReg(InstancePtr, Offset, Data) \
+ Xil_Out32((InstancePtr)->ConfigPtr->BaseAddress + (u32)(Offset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro. */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c
new file mode 100644
index 000000000..85baab0f8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c
@@ -0,0 +1,434 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_intr.c
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0 sg 06/06/16 First release
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+* Endpoint interrupt handler.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is endpoint Event occured in the core.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_EpInterrupt(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event)
+{
+ struct XUsbPsu_Ep *Ept;
+ u32 Epnum;
+
+ Epnum = Event->Epnumber;
+ Ept = &InstancePtr->eps[Epnum];
+
+ if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == (u32)0U) {
+ return;
+ }
+
+ if ((Epnum == (u32)0) || (Epnum == (u32)1)) {
+ XUsbPsu_Ep0Intr(InstancePtr, Event);
+ return;
+ }
+
+ /* Handle other end point events */
+ switch (Event->Endpoint_Event) {
+ case XUSBPSU_DEPEVT_XFERCOMPLETE:
+ XUsbPsu_EpXferComplete(InstancePtr, Event);
+ break;
+
+ case XUSBPSU_DEPEVT_XFERNOTREADY:
+ break;
+
+ default:
+ /* Made for Misra-C Compliance. */
+ break;
+ }
+}
+
+/****************************************************************************/
+/**
+* Disconnect Interrupt handler.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_DisconnectIntr(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal &= ~XUSBPSU_DCTL_INITU1ENA;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ RegVal &= ~XUSBPSU_DCTL_INITU2ENA;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ InstancePtr->IsConfigDone = 0U;
+ InstancePtr->Speed = XUSBPSU_SPEED_UNKNOWN;
+}
+
+/****************************************************************************/
+/**
+* Reset Interrupt handler.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+ u32 Index;
+
+ InstancePtr->State = XUSBPSU_STATE_DEFAULT;
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+ InstancePtr->TestMode = 0U;
+
+ for (Index = 0U; Index < (InstancePtr->NumInEps + InstancePtr->NumOutEps);
+ Index++)
+ {
+ InstancePtr->eps[Index].EpStatus = 0U;
+ }
+
+ InstancePtr->IsConfigDone = 0U;
+
+ /* Reset device address to zero */
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
+ RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
+}
+
+/****************************************************************************/
+/**
+* Connection Done Interrupt handler.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+ u16 Size;
+ u8 Speed;
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS);
+ Speed = (u8)(RegVal & XUSBPSU_DSTS_CONNECTSPD);
+ InstancePtr->Speed = Speed;
+
+ switch (Speed) {
+ case XUSBPSU_DCFG_SUPERSPEED:
+#ifdef XUSBPSU_DEBUG
+ xil_printf("Super Speed\r\n");
+#endif
+ Size = 512U;
+ InstancePtr->Speed = XUSBPSU_SPEED_SUPER;
+ break;
+
+ case XUSBPSU_DCFG_HIGHSPEED:
+#ifdef XUSBPSU_DEBUG
+ xil_printf("High Speed\r\n");
+#endif
+ Size = 64U;
+ InstancePtr->Speed = XUSBPSU_SPEED_HIGH;
+ break;
+
+ case XUSBPSU_DCFG_FULLSPEED2:
+ case XUSBPSU_DCFG_FULLSPEED1:
+#ifdef XUSBPSU_DEBUG
+ xil_printf("Full Speed\r\n");
+#endif
+ Size = 64U;
+ InstancePtr->Speed = XUSBPSU_SPEED_FULL;
+ break;
+
+ case XUSBPSU_DCFG_LOWSPEED:
+#ifdef XUSBPSU_DEBUG
+ xil_printf("Low Speed\r\n");
+#endif
+ Size = 64U;
+ InstancePtr->Speed = XUSBPSU_SPEED_LOW;
+ break;
+ default :
+ Size = 64U;
+ break;
+ }
+
+ (void)XUsbPsu_EnableControlEp(InstancePtr, Size);
+ (void)XUsbPsu_RecvSetup(InstancePtr);
+}
+
+/****************************************************************************/
+/**
+* Link Status Change Interrupt handler.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param EvtInfo is Event information.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_LinkStsChangeIntr(struct XUsbPsu *InstancePtr, u32 EvtInfo)
+{
+ u32 State = EvtInfo & (u32)XUSBPSU_LINK_STATE_MASK;
+ InstancePtr->LinkState = (u8)State;
+}
+
+/****************************************************************************/
+/**
+* Interrupt handler for device specific events.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is the Device Event occured in core.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_DevInterrupt(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Devt *Event)
+{
+
+ switch (Event->Type) {
+ case XUSBPSU_DEVICE_EVENT_DISCONNECT:
+ XUsbPsu_DisconnectIntr(InstancePtr);
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_RESET:
+ XUsbPsu_ResetIntr(InstancePtr);
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_CONNECT_DONE:
+ XUsbPsu_ConnDoneIntr(InstancePtr);
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_WAKEUP:
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_HIBER_REQ:
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_LINK_STATUS_CHANGE:
+ XUsbPsu_LinkStsChangeIntr(InstancePtr,
+ Event->Event_Info);
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_EOPF:
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_SOF:
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_ERRATIC_ERROR:
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_CMD_CMPL:
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_OVERFLOW:
+ break;
+
+ default:
+ /* Made for Misra-C Compliance. */
+ break;
+ }
+}
+
+/****************************************************************************/
+/**
+* Processes an Event entry in Event Buffer.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is the Event entry.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_EventHandler(struct XUsbPsu *InstancePtr,
+ const union XUsbPsu_Event *Event)
+{
+
+ if (Event->Type.Is_DevEvt == 0U) {
+ /* End point Specific Event */
+ XUsbPsu_EpInterrupt(InstancePtr, &Event->Epevt);
+ return;
+ }
+
+ switch (Event->Type.Type) {
+ case XUSBPSU_EVENT_TYPE_DEV:
+ /* Device Specific Event */
+ XUsbPsu_DevInterrupt(InstancePtr, &Event->Devt);
+ break;
+ /* Carkit and I2C events not supported now */
+ default:
+ /* Made for Misra-C Compliance. */
+ break;
+ }
+}
+
+/****************************************************************************/
+/**
+* Processes events in an Event Buffer.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @bus Event buffer number.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_EventBufferHandler(struct XUsbPsu *InstancePtr)
+{
+ struct XUsbPsu_EvtBuffer *Evt;
+ union XUsbPsu_Event Event = {0};
+
+ Evt = &InstancePtr->Evt;
+
+ Xil_DCacheInvalidateRange((INTPTR)Evt->BuffAddr,
+ (u32)XUSBPSU_EVENT_BUFFERS_SIZE);
+
+ while (Evt->Count > 0) {
+ Event.Raw = *(UINTPTR *)(Evt->BuffAddr + Evt->Offset);
+
+ /*
+ * Process the event received
+ */
+ XUsbPsu_EventHandler(InstancePtr, &Event);
+
+ Evt->Offset = (Evt->Offset + 4U) % XUSBPSU_EVENT_BUFFERS_SIZE;
+ Evt->Count -= 4;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 4U);
+ }
+
+ Evt->Flags &= ~XUSBPSU_EVENT_PENDING;
+}
+
+/****************************************************************************/
+/**
+* Main Interrupt Handler.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_IntrHandler(void *XUsbPsuInstancePtr)
+{
+ struct XUsbPsu *InstancePtr;
+ struct XUsbPsu_EvtBuffer *Evt;
+ u32 Count;
+ u32 RegVal;
+
+ InstancePtr = XUsbPsuInstancePtr;
+
+ Evt = &InstancePtr->Evt;
+
+ Count = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0));
+ Count &= XUSBPSU_GEVNTCOUNT_MASK;
+ /*
+ * As per data book software should only process Events if Event count
+ * is greater than zero.
+ */
+ if (Count == 0U) {
+ return;
+ }
+
+ Evt->Count = Count;
+ Evt->Flags |= XUSBPSU_EVENT_PENDING;
+
+ /* Mask event interrupt */
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0));
+ RegVal |= XUSBPSU_GEVNTSIZ_INTMASK;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), RegVal);
+
+ /* Processes events in an Event Buffer */
+ XUsbPsu_EventBufferHandler(InstancePtr);
+
+ /* Unmask event interrupt */
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0));
+ RegVal &= ~XUSBPSU_GEVNTSIZ_INTMASK;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), RegVal);
+}
+
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c
new file mode 100644
index 000000000..c172c5d69
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_sinit.h
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0 sg 06/06/16 First release
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+extern XUsbPsu_Config XUsbPsu_ConfigTable[];
+
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+******************************************************************************/
+XUsbPsu_Config *XUsbPsu_LookupConfig(u16 DeviceId)
+{
+ XUsbPsu_Config *CfgPtr = NULL;
+ u32 i;
+
+ for (i = 0U; i < (u32)XPAR_XUSBPSU_NUM_INSTANCES; i++) {
+ if (XUsbPsu_ConfigTable[i].DeviceId == DeviceId) {
+ CfgPtr = &XUsbPsu_ConfigTable[i];
+ break;
+ }
+ }
+
+ return (XUsbPsu_Config *)(CfgPtr);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/system.mss b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/system.mss
index 37c19f84d..664a10efe 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/system.mss
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/system.mss
@@ -4,7 +4,7 @@
BEGIN OS
PARAMETER OS_NAME = standalone
- PARAMETER OS_VER = 5.4
+ PARAMETER OS_VER = 6.1
PARAMETER PROC_INSTANCE = psu_cortexa53_0
PARAMETER stdin = psu_uart_0
PARAMETER stdout = psu_uart_0
@@ -13,14 +13,14 @@ END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu_cortexa53
- PARAMETER DRIVER_VER = 1.1
+ PARAMETER DRIVER_VER = 1.2
PARAMETER HW_INSTANCE = psu_cortexa53_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = scugic
- PARAMETER DRIVER_VER = 3.2
+ PARAMETER DRIVER_VER = 3.5
PARAMETER HW_INSTANCE = psu_acpu_gic
END
@@ -116,31 +116,31 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = sysmonpsu
- PARAMETER DRIVER_VER = 1.0
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = psu_ams
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = axipmon
- PARAMETER DRIVER_VER = 6.4
+ PARAMETER DRIVER_VER = 6.5
PARAMETER HW_INSTANCE = psu_apm_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = axipmon
- PARAMETER DRIVER_VER = 6.4
+ PARAMETER DRIVER_VER = 6.5
PARAMETER HW_INSTANCE = psu_apm_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = axipmon
- PARAMETER DRIVER_VER = 6.4
+ PARAMETER DRIVER_VER = 6.5
PARAMETER HW_INSTANCE = psu_apm_2
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = axipmon
- PARAMETER DRIVER_VER = 6.4
+ PARAMETER DRIVER_VER = 6.5
PARAMETER HW_INSTANCE = psu_apm_5
END
@@ -150,15 +150,9 @@ BEGIN DRIVER
PARAMETER HW_INSTANCE = psu_apu
END
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_bbram_0
-END
-
BEGIN DRIVER
PARAMETER DRIVER_NAME = canps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
PARAMETER HW_INSTANCE = psu_can_1
END
@@ -176,7 +170,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = coresightps_dcc
- PARAMETER DRIVER_VER = 1.2
+ PARAMETER DRIVER_VER = 1.3
PARAMETER HW_INSTANCE = psu_coresight_0
END
@@ -192,15 +186,9 @@ BEGIN DRIVER
PARAMETER HW_INSTANCE = psu_crl_apb
END
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_csu_0
-END
-
BEGIN DRIVER
PARAMETER DRIVER_NAME = csudma
- PARAMETER DRIVER_VER = 1.0
+ PARAMETER DRIVER_VER = 1.1
PARAMETER HW_INSTANCE = psu_csudma
END
@@ -210,6 +198,12 @@ BEGIN DRIVER
PARAMETER HW_INSTANCE = psu_ddr_0
END
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_1
+END
+
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
@@ -259,8 +253,8 @@ BEGIN DRIVER
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
+ PARAMETER DRIVER_NAME = ddrcpsu
+ PARAMETER DRIVER_VER = 1.1
PARAMETER HW_INSTANCE = psu_ddrc_0
END
@@ -284,7 +278,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = emacps
- PARAMETER DRIVER_VER = 3.2
+ PARAMETER DRIVER_VER = 3.3
PARAMETER HW_INSTANCE = psu_ethernet_3
END
@@ -380,22 +374,16 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.4
PARAMETER HW_INSTANCE = psu_i2c_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.4
PARAMETER HW_INSTANCE = psu_i2c_1
END
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_iou_s
-END
-
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
@@ -422,7 +410,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ipipsu
- PARAMETER DRIVER_VER = 2.0
+ PARAMETER DRIVER_VER = 2.1
PARAMETER HW_INSTANCE = psu_ipi_0
END
@@ -471,54 +459,54 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_ocm_ram_1
+ PARAMETER HW_INSTANCE = psu_ocm_xmpu_cfg
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_ocm_xmpu_cfg
+ PARAMETER HW_INSTANCE = psu_pcie
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_pcie
+ PARAMETER HW_INSTANCE = psu_pcie_attrib_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_pcie_attrib_0
+ PARAMETER HW_INSTANCE = psu_pcie_dma
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_pcie_dma
+ PARAMETER HW_INSTANCE = psu_pcie_high
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_pmu_global_0
+ PARAMETER HW_INSTANCE = psu_pcie_low
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_pmu_iomodule
+ PARAMETER HW_INSTANCE = psu_pmu_global_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_pmu_ram
+ PARAMETER HW_INSTANCE = psu_pmu_iomodule
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = qspipsu
- PARAMETER DRIVER_VER = 1.0
+ PARAMETER DRIVER_VER = 1.3
PARAMETER HW_INSTANCE = psu_qspi_0
END
@@ -528,9 +516,39 @@ BEGIN DRIVER
PARAMETER HW_INSTANCE = psu_qspi_linear_0
END
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_0_atcm_global
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_0_btcm_global
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_1_atcm_global
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_1_btcm_global
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_tcm_ram_global
+END
+
BEGIN DRIVER
PARAMETER DRIVER_NAME = scugic
- PARAMETER DRIVER_VER = 3.2
+ PARAMETER DRIVER_VER = 3.5
PARAMETER HW_INSTANCE = psu_rcpu_gic
END
@@ -548,7 +566,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = rtcpsu
- PARAMETER DRIVER_VER = 1.2
+ PARAMETER DRIVER_VER = 1.3
PARAMETER HW_INSTANCE = psu_rtc
END
@@ -560,7 +578,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = sdps
- PARAMETER DRIVER_VER = 2.7
+ PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_sd_1
END
@@ -590,43 +608,43 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
PARAMETER HW_INSTANCE = psu_ttc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
PARAMETER HW_INSTANCE = psu_ttc_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
PARAMETER HW_INSTANCE = psu_ttc_2
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
PARAMETER HW_INSTANCE = psu_ttc_3
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.3
PARAMETER HW_INSTANCE = psu_uart_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.3
PARAMETER HW_INSTANCE = psu_uart_1
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
+ PARAMETER DRIVER_NAME = usbpsu
+ PARAMETER DRIVER_VER = 1.1
PARAMETER HW_INSTANCE = psu_usb_0
END
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/.project b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/.project
index aab343b6e..97855f6fd 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/.project
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/.project
@@ -1,7 +1,7 @@
ZynqMP_ZCU102_hw_platform
- Created by SDK v2016.1
+ Created by SDK v2016.4
@@ -11,7 +11,7 @@
- 1461845622212
+ 1484841836970
6
@@ -20,7 +20,7 @@
- 1461845622222
+ 1484841836972
6
@@ -29,7 +29,7 @@
- 1461845622222
+ 1484841836978
6
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c
index ec9441e4c..f206bc7bf 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c
@@ -878,99 +878,6 @@ unsigned long psu_pll_init_data() {
}
unsigned long psu_clock_init_data() {
// : CLOCK CONTROL SLCR REGISTER
- /*Register : GEM0_REF_CTRL @ 0XFF5E0050
-
- Clock active for the RX channel
- PSU_CRL_APB_GEM0_REF_CTRL_RX_CLKACT 0x1
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_GEM0_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR0 0x8
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_GEM0_REF_CTRL_SRCSEL 0x0
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E0050, 0x063F3F07U ,0x06010800U)
- RegMask = (CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM0_REF_CTRL_CLKACT_MASK | CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT
- | 0x00000008U << CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000000U << CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_GEM0_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010800U);
- /*############################################################################################################################ */
-
- /*Register : GEM1_REF_CTRL @ 0XFF5E0054
-
- Clock active for the RX channel
- PSU_CRL_APB_GEM1_REF_CTRL_RX_CLKACT 0x1
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_GEM1_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR0 0x8
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_GEM1_REF_CTRL_SRCSEL 0x0
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E0054, 0x063F3F07U ,0x06010800U)
- RegMask = (CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM1_REF_CTRL_CLKACT_MASK | CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT
- | 0x00000008U << CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000000U << CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_GEM1_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010800U);
- /*############################################################################################################################ */
-
- /*Register : GEM2_REF_CTRL @ 0XFF5E0058
-
- Clock active for the RX channel
- PSU_CRL_APB_GEM2_REF_CTRL_RX_CLKACT 0x1
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_GEM2_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR0 0x8
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_GEM2_REF_CTRL_SRCSEL 0x0
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E0058, 0x063F3F07U ,0x06010800U)
- RegMask = (CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM2_REF_CTRL_CLKACT_MASK | CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT
- | 0x00000008U << CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000000U << CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_GEM2_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010800U);
- /*############################################################################################################################ */
-
/*Register : GEM3_REF_CTRL @ 0XFF5E005C
Clock active for the RX channel
@@ -1002,33 +909,6 @@ unsigned long psu_clock_init_data() {
PSU_Mask_Write (CRL_APB_GEM3_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010C00U);
/*############################################################################################################################ */
- /*Register : GEM_TSU_REF_CTRL @ 0XFF5E0100
-
- 6 bit divider
- PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x2
-
- 6 bit divider
- PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010602U)
- RegMask = (CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK | CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK | 0 );
-
- RegVal = ((0x00000006U << CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000002U << CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT
- | 0x00000001U << CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT
- | 0x00000001U << CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_GEM_TSU_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010602U);
- /*############################################################################################################################ */
-
/*Register : USB0_BUS_REF_CTRL @ 0XFF5E0060
Clock active signal. Switch to 0 to disable the clock
@@ -1056,33 +936,6 @@ unsigned long psu_clock_init_data() {
PSU_Mask_Write (CRL_APB_USB0_BUS_REF_CTRL_OFFSET ,0x023F3F07U ,0x02010600U);
/*############################################################################################################################ */
- /*Register : USB1_BUS_REF_CTRL @ 0XFF5E0064
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_USB1_BUS_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0 0x4
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_USB1_BUS_REF_CTRL_SRCSEL 0x0
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E0064, 0x023F3F07U ,0x02010400U)
- RegMask = (CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT
- | 0x00000004U << CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000000U << CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_USB1_BUS_REF_CTRL_OFFSET ,0x023F3F07U ,0x02010400U);
- /*############################################################################################################################ */
-
/*Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C
Clock active signal. Switch to 0 to disable the clock
@@ -1137,33 +990,6 @@ unsigned long psu_clock_init_data() {
PSU_Mask_Write (CRL_APB_QSPI_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010C00U);
/*############################################################################################################################ */
- /*Register : SDIO0_REF_CTRL @ 0XFF5E006C
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_SDIO0_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR0 0x7
-
- 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_SDIO0_REF_CTRL_SRCSEL 0x2
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E006C, 0x013F3F07U ,0x01010702U)
- RegMask = (CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT
- | 0x00000007U << CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000002U << CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_SDIO0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010702U);
- /*############################################################################################################################ */
-
/*Register : SDIO1_REF_CTRL @ 0XFF5E0070
Clock active signal. Switch to 0 to disable the clock
@@ -1313,87 +1139,6 @@ unsigned long psu_clock_init_data() {
PSU_Mask_Write (CRL_APB_I2C1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
/*############################################################################################################################ */
- /*Register : SPI0_REF_CTRL @ 0XFF5E007C
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_SPI0_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0 0x7
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL 0x2
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E007C, 0x013F3F07U ,0x01010702U)
- RegMask = (CRL_APB_SPI0_REF_CTRL_CLKACT_MASK | CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK | CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK | CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT
- | 0x00000007U << CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000002U << CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_SPI0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010702U);
- /*############################################################################################################################ */
-
- /*Register : SPI1_REF_CTRL @ 0XFF5E0080
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_SPI1_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0 0x7
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL 0x2
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E0080, 0x013F3F07U ,0x01010702U)
- RegMask = (CRL_APB_SPI1_REF_CTRL_CLKACT_MASK | CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT
- | 0x00000007U << CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000002U << CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_SPI1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010702U);
- /*############################################################################################################################ */
-
- /*Register : CAN0_REF_CTRL @ 0XFF5E0084
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_CAN0_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR0 0xa
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_CAN0_REF_CTRL_SRCSEL 0x0
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E0084, 0x013F3F07U ,0x01010A00U)
- RegMask = (CRL_APB_CAN0_REF_CTRL_CLKACT_MASK | CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT
- | 0x0000000AU << CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000000U << CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_CAN0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010A00U);
- /*############################################################################################################################ */
-
/*Register : CAN1_REF_CTRL @ 0XFF5E0088
Clock active signal. Switch to 0 to disable the clock
@@ -1468,29 +1213,6 @@ unsigned long psu_clock_init_data() {
PSU_Mask_Write (CRL_APB_IOU_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
/*############################################################################################################################ */
- /*Register : CSU_PLL_CTRL @ 0XFF5E00A0
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_CSU_PLL_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_CSU_PLL_CTRL_DIVISOR0 0x3
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_CSU_PLL_CTRL_SRCSEL 0x2
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E00A0, 0x01003F07U ,0x01000302U)
- RegMask = (CRL_APB_CSU_PLL_CTRL_CLKACT_MASK | CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK | CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT
- | 0x00000003U << CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT
- | 0x00000002U << CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_CSU_PLL_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
- /*############################################################################################################################ */
-
/*Register : PCAP_CTRL @ 0XFF5E00A4
Clock active signal. Switch to 0 to disable the clock
@@ -1583,33 +1305,6 @@ unsigned long psu_clock_init_data() {
PSU_Mask_Write (CRL_APB_DBG_LPD_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
/*############################################################################################################################ */
- /*Register : NAND_REF_CTRL @ 0XFF5E00B4
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_NAND_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_NAND_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_NAND_REF_CTRL_DIVISOR0 0xa
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_NAND_REF_CTRL_SRCSEL 0x0
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E00B4, 0x013F3F07U ,0x01010A00U)
- RegMask = (CRL_APB_NAND_REF_CTRL_CLKACT_MASK | CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK | CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK | CRL_APB_NAND_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT
- | 0x0000000AU << CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000000U << CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_NAND_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010A00U);
- /*############################################################################################################################ */
-
/*Register : ADMA_REF_CTRL @ 0XFF5E00B8
Clock active signal. Switch to 0 to disable the clock
@@ -2149,29 +1844,6 @@ unsigned long psu_clock_init_data() {
PSU_Mask_Write (CRF_APB_TOPSW_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000502U);
/*############################################################################################################################ */
- /*Register : GTGREF0_REF_CTRL @ 0XFD1A00C8
-
- 6 bit divider
- PSU_CRF_APB_GTGREF0_REF_CTRL_DIVISOR0 0x4
-
- 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
- he new clock. This is not usually an issue, but designers must be aware.)
- PSU_CRF_APB_GTGREF0_REF_CTRL_SRCSEL 0x0
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRF_APB_GTGREF0_REF_CTRL_CLKACT 0x1
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFD1A00C8, 0x01003F07U ,0x01000400U)
- RegMask = (CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK | CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK | CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK | 0 );
-
- RegVal = ((0x00000004U << CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000000U << CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT
- | 0x00000001U << CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRF_APB_GTGREF0_REF_CTRL_OFFSET ,0x01003F07U ,0x01000400U);
- /*############################################################################################################################ */
-
/*Register : DBG_TSTMP_CTRL @ 0XFD1A00F8
6 bit divider
@@ -3342,22 +3014,22 @@ unsigned long psu_ddr_init_data() {
ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t
is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L
DDR2/LPDDR3/LPDDR4 devices.
- PSU_DDRC_DRAMTMG7_T_CKPDE 0x1
+ PSU_DDRC_DRAMTMG7_T_CKPDE 0x6
This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable
time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO=
, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti
g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
- PSU_DDRC_DRAMTMG7_T_CKPDX 0x1
+ PSU_DDRC_DRAMTMG7_T_CKPDX 0x6
SDRAM Timing Register 7
- (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000101U)
+ (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U)
RegMask = (DDRC_DRAMTMG7_T_CKPDE_MASK | DDRC_DRAMTMG7_T_CKPDX_MASK | 0 );
- RegVal = ((0x00000001U << DDRC_DRAMTMG7_T_CKPDE_SHIFT
- | 0x00000001U << DDRC_DRAMTMG7_T_CKPDX_SHIFT
+ RegVal = ((0x00000006U << DDRC_DRAMTMG7_T_CKPDE_SHIFT
+ | 0x00000006U << DDRC_DRAMTMG7_T_CKPDX_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDRC_DRAMTMG7_OFFSET ,0x00000F0FU ,0x00000101U);
+ PSU_Mask_Write (DDRC_DRAMTMG7_OFFSET ,0x00000F0FU ,0x00000606U);
/*############################################################################################################################ */
/*Register : DRAMTMG8 @ 0XFD070120
@@ -3680,13 +3352,13 @@ unsigned long psu_ddr_init_data() {
s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20
8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107
cycles - 0xE - 262144 cycles - 0xF - Unlimited
- PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x4
+ PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0
Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled
PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1
DFI Low Power Configuration Register 0
- (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000141U)
+ (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U)
RegMask = (DDRC_DFILPCFG0_DFI_TLP_RESP_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK | DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK | 0 );
RegVal = ((0x00000007U << DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT
@@ -3694,10 +3366,10 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT
| 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT
| 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT
- | 0x00000004U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT
+ | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT
| 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDRC_DFILPCFG0_OFFSET ,0x0FF1F1F1U ,0x07000141U);
+ PSU_Mask_Write (DDRC_DFILPCFG0_OFFSET ,0x0FF1F1F1U ,0x07000101U);
/*############################################################################################################################ */
/*Register : DFILPCFG1 @ 0XFD07019C
@@ -5644,10 +5316,10 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0
Refresh Period
- PSU_DDR_PHY_PGCR2_TREFPRD 0x12302
+ PSU_DDR_PHY_PGCR2_TREFPRD 0x10028
PHY General Configuration Register 2
- (OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F12302U)
+ (OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10028U)
RegMask = (DDR_PHY_PGCR2_CLRTSTAT_MASK | DDR_PHY_PGCR2_CLRZCAL_MASK | DDR_PHY_PGCR2_CLRPERR_MASK | DDR_PHY_PGCR2_ICPC_MASK | DDR_PHY_PGCR2_DTPMXTMR_MASK | DDR_PHY_PGCR2_INITFSMBYP_MASK | DDR_PHY_PGCR2_PLLFSMBYP_MASK | DDR_PHY_PGCR2_TREFPRD_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_PGCR2_CLRTSTAT_SHIFT
@@ -5657,9 +5329,67 @@ unsigned long psu_ddr_init_data() {
| 0x0000000FU << DDR_PHY_PGCR2_DTPMXTMR_SHIFT
| 0x00000000U << DDR_PHY_PGCR2_INITFSMBYP_SHIFT
| 0x00000000U << DDR_PHY_PGCR2_PLLFSMBYP_SHIFT
- | 0x00012302U << DDR_PHY_PGCR2_TREFPRD_SHIFT
+ | 0x00010028U << DDR_PHY_PGCR2_TREFPRD_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_PGCR2_OFFSET ,0xFFFFFFFFU ,0x00F10028U);
+ /*############################################################################################################################ */
+
+ /*Register : PGCR3 @ 0XFD08001C
+
+ CKN Enable
+ PSU_DDR_PHY_PGCR3_CKNEN 0x55
+
+ CK Enable
+ PSU_DDR_PHY_PGCR3_CKEN 0xaa
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_PGCR3_RESERVED_15 0x0
+
+ Enable Clock Gating for AC [0] ctl_rd_clk
+ PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2
+
+ Enable Clock Gating for AC [0] ddr_clk
+ PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2
+
+ Enable Clock Gating for AC [0] ctl_clk
+ PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_PGCR3_RESERVED_8 0x0
+
+ Controls DDL Bypass Modes
+ PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2
+
+ IO Loop-Back Select
+ PSU_DDR_PHY_PGCR3_IOLB 0x0
+
+ AC Receive FIFO Read Mode
+ PSU_DDR_PHY_PGCR3_RDMODE 0x0
+
+ Read FIFO Reset Disable
+ PSU_DDR_PHY_PGCR3_DISRST 0x0
+
+ Clock Level when Clock Gating
+ PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0
+
+ PHY General Configuration Register 3
+ (OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U)
+ RegMask = (DDR_PHY_PGCR3_CKNEN_MASK | DDR_PHY_PGCR3_CKEN_MASK | DDR_PHY_PGCR3_RESERVED_15_MASK | DDR_PHY_PGCR3_GATEACRDCLK_MASK | DDR_PHY_PGCR3_GATEACDDRCLK_MASK | DDR_PHY_PGCR3_GATEACCTLCLK_MASK | DDR_PHY_PGCR3_RESERVED_8_MASK | DDR_PHY_PGCR3_DDLBYPMODE_MASK | DDR_PHY_PGCR3_IOLB_MASK | DDR_PHY_PGCR3_RDMODE_MASK | DDR_PHY_PGCR3_DISRST_MASK | DDR_PHY_PGCR3_CLKLEVEL_MASK | 0 );
+
+ RegVal = ((0x00000055U << DDR_PHY_PGCR3_CKNEN_SHIFT
+ | 0x000000AAU << DDR_PHY_PGCR3_CKEN_SHIFT
+ | 0x00000000U << DDR_PHY_PGCR3_RESERVED_15_SHIFT
+ | 0x00000002U << DDR_PHY_PGCR3_GATEACRDCLK_SHIFT
+ | 0x00000002U << DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT
+ | 0x00000002U << DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT
+ | 0x00000000U << DDR_PHY_PGCR3_RESERVED_8_SHIFT
+ | 0x00000002U << DDR_PHY_PGCR3_DDLBYPMODE_SHIFT
+ | 0x00000000U << DDR_PHY_PGCR3_IOLB_SHIFT
+ | 0x00000000U << DDR_PHY_PGCR3_RDMODE_SHIFT
+ | 0x00000000U << DDR_PHY_PGCR3_DISRST_SHIFT
+ | 0x00000000U << DDR_PHY_PGCR3_CLKLEVEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_PGCR2_OFFSET ,0xFFFFFFFFU ,0x00F12302U);
+ PSU_Mask_Write (DDR_PHY_PGCR3_OFFSET ,0xFFFFFFFFU ,0x55AA5480U);
/*############################################################################################################################ */
/*Register : PGCR5 @ 0XFD080024
@@ -5915,16 +5645,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DTPR0_RESERVED_15 0x0
Precharge command period
- PSU_DDR_PHY_DTPR0_TRP 0x12
+ PSU_DDR_PHY_DTPR0_TRP 0xf
Reserved. Return zeroes on reads.
PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0
Internal read to precharge command delay
- PSU_DDR_PHY_DTPR0_TRTP 0x8
+ PSU_DDR_PHY_DTPR0_TRTP 0x9
DRAM Timing Parameters Register 0
- (OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06241208U)
+ (OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F09U)
RegMask = (DDR_PHY_DTPR0_RESERVED_31_29_MASK | DDR_PHY_DTPR0_TRRD_MASK | DDR_PHY_DTPR0_RESERVED_23_MASK | DDR_PHY_DTPR0_TRAS_MASK | DDR_PHY_DTPR0_RESERVED_15_MASK | DDR_PHY_DTPR0_TRP_MASK | DDR_PHY_DTPR0_RESERVED_7_5_MASK | DDR_PHY_DTPR0_TRTP_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DTPR0_RESERVED_31_29_SHIFT
@@ -5932,11 +5662,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DTPR0_RESERVED_23_SHIFT
| 0x00000024U << DDR_PHY_DTPR0_TRAS_SHIFT
| 0x00000000U << DDR_PHY_DTPR0_RESERVED_15_SHIFT
- | 0x00000012U << DDR_PHY_DTPR0_TRP_SHIFT
+ | 0x0000000FU << DDR_PHY_DTPR0_TRP_SHIFT
| 0x00000000U << DDR_PHY_DTPR0_RESERVED_7_5_SHIFT
- | 0x00000008U << DDR_PHY_DTPR0_TRTP_SHIFT
+ | 0x00000009U << DDR_PHY_DTPR0_TRTP_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DTPR0_OFFSET ,0xFFFFFFFFU ,0x06241208U);
+ PSU_Mask_Write (DDR_PHY_DTPR0_OFFSET ,0xFFFFFFFFU ,0x06240F09U);
/*############################################################################################################################ */
/*Register : DTPR1 @ 0XFD080114
@@ -6044,10 +5774,10 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0
DQS output access time from CK/CK# (LPDDR2/3 only)
- PSU_DDR_PHY_DTPR3_TDQSCK 0x4
+ PSU_DDR_PHY_DTPR3_TDQSCK 0x0
DRAM Timing Parameters Register 3
- (OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000804U)
+ (OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U)
RegMask = (DDR_PHY_DTPR3_TOFDX_MASK | DDR_PHY_DTPR3_TCCD_MASK | DDR_PHY_DTPR3_TDLLK_MASK | DDR_PHY_DTPR3_RESERVED_15_12_MASK | DDR_PHY_DTPR3_TDQSCKMAX_MASK | DDR_PHY_DTPR3_RESERVED_7_3_MASK | DDR_PHY_DTPR3_TDQSCK_MASK | 0 );
RegVal = ((0x00000004U << DDR_PHY_DTPR3_TOFDX_SHIFT
@@ -6056,9 +5786,9 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DTPR3_RESERVED_15_12_SHIFT
| 0x00000008U << DDR_PHY_DTPR3_TDQSCKMAX_SHIFT
| 0x00000000U << DDR_PHY_DTPR3_RESERVED_7_3_SHIFT
- | 0x00000004U << DDR_PHY_DTPR3_TDQSCK_SHIFT
+ | 0x00000000U << DDR_PHY_DTPR3_TDQSCK_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DTPR3_OFFSET ,0xFFFFFFFFU ,0x83000804U);
+ PSU_Mask_Write (DDR_PHY_DTPR3_OFFSET ,0xFFFFFFFFU ,0x83000800U);
/*############################################################################################################################ */
/*Register : DTPR4 @ 0XFD080120
@@ -6307,6 +6037,50 @@ unsigned long psu_ddr_init_data() {
PSU_Mask_Write (DDR_PHY_RDIMMGCR1_OFFSET ,0xFFFFFFFFU ,0x00000C80U);
/*############################################################################################################################ */
+ /*Register : RDIMMCR0 @ 0XFD080150
+
+ DDR4/DDR3 Control Word 7
+ PSU_DDR_PHY_RDIMMCR0_RC7 0x0
+
+ DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved
+ PSU_DDR_PHY_RDIMMCR0_RC6 0x0
+
+ DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)
+ PSU_DDR_PHY_RDIMMCR0_RC5 0x0
+
+ DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C
+ aracteristics Control Word)
+ PSU_DDR_PHY_RDIMMCR0_RC4 0x0
+
+ DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr
+ ver Characteristrics Control Word)
+ PSU_DDR_PHY_RDIMMCR0_RC3 0x0
+
+ DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)
+ PSU_DDR_PHY_RDIMMCR0_RC2 0x0
+
+ DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)
+ PSU_DDR_PHY_RDIMMCR0_RC1 0x0
+
+ DDR4/DDR3 Control Word 0 (Global Features Control Word)
+ PSU_DDR_PHY_RDIMMCR0_RC0 0x0
+
+ RDIMM Control Register 0
+ (OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U)
+ RegMask = (DDR_PHY_RDIMMCR0_RC7_MASK | DDR_PHY_RDIMMCR0_RC6_MASK | DDR_PHY_RDIMMCR0_RC5_MASK | DDR_PHY_RDIMMCR0_RC4_MASK | DDR_PHY_RDIMMCR0_RC3_MASK | DDR_PHY_RDIMMCR0_RC2_MASK | DDR_PHY_RDIMMCR0_RC1_MASK | DDR_PHY_RDIMMCR0_RC0_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_RDIMMCR0_RC7_SHIFT
+ | 0x00000000U << DDR_PHY_RDIMMCR0_RC6_SHIFT
+ | 0x00000000U << DDR_PHY_RDIMMCR0_RC5_SHIFT
+ | 0x00000000U << DDR_PHY_RDIMMCR0_RC4_SHIFT
+ | 0x00000000U << DDR_PHY_RDIMMCR0_RC3_SHIFT
+ | 0x00000000U << DDR_PHY_RDIMMCR0_RC2_SHIFT
+ | 0x00000000U << DDR_PHY_RDIMMCR0_RC1_SHIFT
+ | 0x00000000U << DDR_PHY_RDIMMCR0_RC0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_RDIMMCR0_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+ /*############################################################################################################################ */
+
/*Register : RDIMMCR1 @ 0XFD080154
Control Word 15
@@ -6804,7 +6578,7 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0
Data Training Debug Rank Select
- PSU_DDR_PHY_DTCR0_DTDRS 0x1
+ PSU_DDR_PHY_DTCR0_DTDRS 0x0
Data Training with Early/Extended Gate
PSU_DDR_PHY_DTCR0_DTEXG 0x0
@@ -6822,7 +6596,7 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DTCR0_DTDBS 0x0
Data Training read DBI deskewing configuration
- PSU_DDR_PHY_DTCR0_DTRDBITR 0x0
+ PSU_DDR_PHY_DTCR0_DTRDBITR 0x2
Reserved. Return zeroes on reads.
PSU_DDR_PHY_DTCR0_RESERVED_13 0x0
@@ -6846,18 +6620,18 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DTCR0_DTRPTN 0x7
Data Training Configuration Register 0
- (OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x810011C7U)
+ (OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U)
RegMask = (DDR_PHY_DTCR0_RFSHDT_MASK | DDR_PHY_DTCR0_RESERVED_27_26_MASK | DDR_PHY_DTCR0_DTDRS_MASK | DDR_PHY_DTCR0_DTEXG_MASK | DDR_PHY_DTCR0_DTEXD_MASK | DDR_PHY_DTCR0_DTDSTP_MASK | DDR_PHY_DTCR0_DTDEN_MASK | DDR_PHY_DTCR0_DTDBS_MASK | DDR_PHY_DTCR0_DTRDBITR_MASK | DDR_PHY_DTCR0_RESERVED_13_MASK | DDR_PHY_DTCR0_DTWBDDM_MASK | DDR_PHY_DTCR0_RFSHEN_MASK | DDR_PHY_DTCR0_DTCMPD_MASK | DDR_PHY_DTCR0_DTMPR_MASK | DDR_PHY_DTCR0_RESERVED_5_4_MASK | DDR_PHY_DTCR0_DTRPTN_MASK | 0 );
RegVal = ((0x00000008U << DDR_PHY_DTCR0_RFSHDT_SHIFT
| 0x00000000U << DDR_PHY_DTCR0_RESERVED_27_26_SHIFT
- | 0x00000001U << DDR_PHY_DTCR0_DTDRS_SHIFT
+ | 0x00000000U << DDR_PHY_DTCR0_DTDRS_SHIFT
| 0x00000000U << DDR_PHY_DTCR0_DTEXG_SHIFT
| 0x00000000U << DDR_PHY_DTCR0_DTEXD_SHIFT
| 0x00000000U << DDR_PHY_DTCR0_DTDSTP_SHIFT
| 0x00000000U << DDR_PHY_DTCR0_DTDEN_SHIFT
| 0x00000000U << DDR_PHY_DTCR0_DTDBS_SHIFT
- | 0x00000000U << DDR_PHY_DTCR0_DTRDBITR_SHIFT
+ | 0x00000002U << DDR_PHY_DTCR0_DTRDBITR_SHIFT
| 0x00000000U << DDR_PHY_DTCR0_RESERVED_13_SHIFT
| 0x00000001U << DDR_PHY_DTCR0_DTWBDDM_SHIFT
| 0x00000001U << DDR_PHY_DTCR0_RFSHEN_SHIFT
@@ -6866,7 +6640,7 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DTCR0_RESERVED_5_4_SHIFT
| 0x00000007U << DDR_PHY_DTCR0_DTRPTN_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DTCR0_OFFSET ,0xFFFFFFFFU ,0x810011C7U);
+ PSU_Mask_Write (DDR_PHY_DTCR0_OFFSET ,0xFFFFFFFFU ,0x800091C7U);
/*############################################################################################################################ */
/*Register : DTCR1 @ 0XFD080204
@@ -6962,6 +6736,20 @@ unsigned long psu_ddr_init_data() {
PSU_Mask_Write (DDR_PHY_CATR0_OFFSET ,0xFFFFFFFFU ,0x00141054U);
/*############################################################################################################################ */
+ /*Register : BISTLSR @ 0XFD080414
+
+ LFSR seed for pseudo-random BIST patterns
+ PSU_DDR_PHY_BISTLSR_SEED 0x12341000
+
+ BIST LFSR Seed Register
+ (OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U)
+ RegMask = (DDR_PHY_BISTLSR_SEED_MASK | 0 );
+
+ RegVal = ((0x12341000U << DDR_PHY_BISTLSR_SEED_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_BISTLSR_OFFSET ,0xFFFFFFFFU ,0x12341000U);
+ /*############################################################################################################################ */
+
/*Register : RIOCR5 @ 0XFD0804F4
Reserved. Return zeroes on reads.
@@ -7287,13 +7075,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_VTCR1_SHREN 0x1
Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training
- PSU_DDR_PHY_VTCR1_TVREFIO 0x4
+ PSU_DDR_PHY_VTCR1_TVREFIO 0x7
Eye LCDL Offset value for VREF training
- PSU_DDR_PHY_VTCR1_EOFF 0x1
+ PSU_DDR_PHY_VTCR1_EOFF 0x0
Number of LCDL Eye points for which VREF training is repeated
- PSU_DDR_PHY_VTCR1_ENUM 0x1
+ PSU_DDR_PHY_VTCR1_ENUM 0x0
HOST (IO) internal VREF training Enable
PSU_DDR_PHY_VTCR1_HVEN 0x1
@@ -7302,7 +7090,7 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_VTCR1_HVIO 0x1
VREF Training Control Register 1
- (OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F0018FU)
+ (OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U)
RegMask = (DDR_PHY_VTCR1_HVSS_MASK | DDR_PHY_VTCR1_RESERVED_27_MASK | DDR_PHY_VTCR1_HVMAX_MASK | DDR_PHY_VTCR1_RESERVED_19_MASK | DDR_PHY_VTCR1_HVMIN_MASK | DDR_PHY_VTCR1_RESERVED_11_MASK | DDR_PHY_VTCR1_SHRNK_MASK | DDR_PHY_VTCR1_SHREN_MASK | DDR_PHY_VTCR1_TVREFIO_MASK | DDR_PHY_VTCR1_EOFF_MASK | DDR_PHY_VTCR1_ENUM_MASK | DDR_PHY_VTCR1_HVEN_MASK | DDR_PHY_VTCR1_HVIO_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_VTCR1_HVSS_SHIFT
@@ -7313,13 +7101,97 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_VTCR1_RESERVED_11_SHIFT
| 0x00000000U << DDR_PHY_VTCR1_SHRNK_SHIFT
| 0x00000001U << DDR_PHY_VTCR1_SHREN_SHIFT
- | 0x00000004U << DDR_PHY_VTCR1_TVREFIO_SHIFT
- | 0x00000001U << DDR_PHY_VTCR1_EOFF_SHIFT
- | 0x00000001U << DDR_PHY_VTCR1_ENUM_SHIFT
+ | 0x00000007U << DDR_PHY_VTCR1_TVREFIO_SHIFT
+ | 0x00000000U << DDR_PHY_VTCR1_EOFF_SHIFT
+ | 0x00000000U << DDR_PHY_VTCR1_ENUM_SHIFT
| 0x00000001U << DDR_PHY_VTCR1_HVEN_SHIFT
| 0x00000001U << DDR_PHY_VTCR1_HVIO_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_VTCR1_OFFSET ,0xFFFFFFFFU ,0x07F0018FU);
+ PSU_Mask_Write (DDR_PHY_VTCR1_OFFSET ,0xFFFFFFFFU ,0x07F001E3U);
+ /*############################################################################################################################ */
+
+ /*Register : ACBDLR1 @ 0XFD080544
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0
+
+ Delay select for the BDL on Parity.
+ PSU_DDR_PHY_ACBDLR1_PARBD 0x0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0
+
+ Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE.
+ PSU_DDR_PHY_ACBDLR1_A16BD 0x0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0
+
+ Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS.
+ PSU_DDR_PHY_ACBDLR1_A17BD 0x0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0
+
+ Delay select for the BDL on ACTN.
+ PSU_DDR_PHY_ACBDLR1_ACTBD 0x0
+
+ AC Bit Delay Line Register 1
+ (OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U)
+ RegMask = (DDR_PHY_ACBDLR1_RESERVED_31_30_MASK | DDR_PHY_ACBDLR1_PARBD_MASK | DDR_PHY_ACBDLR1_RESERVED_23_22_MASK | DDR_PHY_ACBDLR1_A16BD_MASK | DDR_PHY_ACBDLR1_RESERVED_15_14_MASK | DDR_PHY_ACBDLR1_A17BD_MASK | DDR_PHY_ACBDLR1_RESERVED_7_6_MASK | DDR_PHY_ACBDLR1_ACTBD_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR1_PARBD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR1_A16BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR1_A17BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR1_ACTBD_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_ACBDLR1_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : ACBDLR2 @ 0XFD080548
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0
+
+ Delay select for the BDL on BG[1].
+ PSU_DDR_PHY_ACBDLR2_BG1BD 0x0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0
+
+ Delay select for the BDL on BG[0].
+ PSU_DDR_PHY_ACBDLR2_BG0BD 0x0
+
+ Reser.ved Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0
+
+ Delay select for the BDL on BA[1].
+ PSU_DDR_PHY_ACBDLR2_BA1BD 0x0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0
+
+ Delay select for the BDL on BA[0].
+ PSU_DDR_PHY_ACBDLR2_BA0BD 0x0
+
+ AC Bit Delay Line Register 2
+ (OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U)
+ RegMask = (DDR_PHY_ACBDLR2_RESERVED_31_30_MASK | DDR_PHY_ACBDLR2_BG1BD_MASK | DDR_PHY_ACBDLR2_RESERVED_23_22_MASK | DDR_PHY_ACBDLR2_BG0BD_MASK | DDR_PHY_ACBDLR2_RESERVED_15_14_MASK | DDR_PHY_ACBDLR2_BA1BD_MASK | DDR_PHY_ACBDLR2_RESERVED_7_6_MASK | DDR_PHY_ACBDLR2_BA0BD_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR2_BG1BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR2_BG0BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR2_BA1BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR2_BA0BD_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_ACBDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
/*############################################################################################################################ */
/*Register : ACBDLR6 @ 0XFD080558
@@ -7448,12 +7320,54 @@ unsigned long psu_ddr_init_data() {
PSU_Mask_Write (DDR_PHY_ACBDLR8_OFFSET ,0xFFFFFFFFU ,0x00000000U);
/*############################################################################################################################ */
- /*Register : ZQCR @ 0XFD080680
+ /*Register : ACBDLR9 @ 0XFD080564
Reserved. Return zeroes on reads.
- PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0
+ PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0
- ZQ VREF Range
+ Delay select for the BDL on Address A[15].
+ PSU_DDR_PHY_ACBDLR9_A15BD 0x0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0
+
+ Delay select for the BDL on Address A[14].
+ PSU_DDR_PHY_ACBDLR9_A14BD 0x0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0
+
+ Delay select for the BDL on Address A[13].
+ PSU_DDR_PHY_ACBDLR9_A13BD 0x0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0
+
+ Delay select for the BDL on Address A[12].
+ PSU_DDR_PHY_ACBDLR9_A12BD 0x0
+
+ AC Bit Delay Line Register 9
+ (OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U)
+ RegMask = (DDR_PHY_ACBDLR9_RESERVED_31_30_MASK | DDR_PHY_ACBDLR9_A15BD_MASK | DDR_PHY_ACBDLR9_RESERVED_23_22_MASK | DDR_PHY_ACBDLR9_A14BD_MASK | DDR_PHY_ACBDLR9_RESERVED_15_14_MASK | DDR_PHY_ACBDLR9_A13BD_MASK | DDR_PHY_ACBDLR9_RESERVED_7_6_MASK | DDR_PHY_ACBDLR9_A12BD_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR9_A15BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR9_A14BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR9_A13BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR9_A12BD_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_ACBDLR9_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : ZQCR @ 0XFD080680
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0
+
+ ZQ VREF Range
PSU_DDR_PHY_ZQCR_ZQREFISELRANGE 0x0
Programmable Wait for Frequency B
@@ -7840,16 +7754,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX0GCR5_RESERVED_31_MASK | DDR_PHY_DX0GCR5_DXREFISELR3_MASK | DDR_PHY_DX0GCR5_RESERVED_23_MASK | DDR_PHY_DX0GCR5_DXREFISELR2_MASK | DDR_PHY_DX0GCR5_RESERVED_15_MASK | DDR_PHY_DX0GCR5_DXREFISELR1_MASK | DDR_PHY_DX0GCR5_RESERVED_7_MASK | DDR_PHY_DX0GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX0GCR5_RESERVED_31_SHIFT
@@ -7857,11 +7771,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX0GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX0GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX0GCR6 @ 0XFD080718
@@ -8128,16 +8042,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX1GCR5_RESERVED_31_MASK | DDR_PHY_DX1GCR5_DXREFISELR3_MASK | DDR_PHY_DX1GCR5_RESERVED_23_MASK | DDR_PHY_DX1GCR5_DXREFISELR2_MASK | DDR_PHY_DX1GCR5_RESERVED_15_MASK | DDR_PHY_DX1GCR5_DXREFISELR1_MASK | DDR_PHY_DX1GCR5_RESERVED_7_MASK | DDR_PHY_DX1GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX1GCR5_RESERVED_31_SHIFT
@@ -8145,11 +8059,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX1GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX1GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX1GCR6 @ 0XFD080818
@@ -8466,16 +8380,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX2GCR5_RESERVED_31_MASK | DDR_PHY_DX2GCR5_DXREFISELR3_MASK | DDR_PHY_DX2GCR5_RESERVED_23_MASK | DDR_PHY_DX2GCR5_DXREFISELR2_MASK | DDR_PHY_DX2GCR5_RESERVED_15_MASK | DDR_PHY_DX2GCR5_DXREFISELR1_MASK | DDR_PHY_DX2GCR5_RESERVED_7_MASK | DDR_PHY_DX2GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX2GCR5_RESERVED_31_SHIFT
@@ -8483,11 +8397,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX2GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX2GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX2GCR6 @ 0XFD080918
@@ -8804,16 +8718,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX3GCR5_RESERVED_31_MASK | DDR_PHY_DX3GCR5_DXREFISELR3_MASK | DDR_PHY_DX3GCR5_RESERVED_23_MASK | DDR_PHY_DX3GCR5_DXREFISELR2_MASK | DDR_PHY_DX3GCR5_RESERVED_15_MASK | DDR_PHY_DX3GCR5_DXREFISELR1_MASK | DDR_PHY_DX3GCR5_RESERVED_7_MASK | DDR_PHY_DX3GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX3GCR5_RESERVED_31_SHIFT
@@ -8821,11 +8735,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX3GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX3GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX3GCR6 @ 0XFD080A18
@@ -9142,16 +9056,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX4GCR5_RESERVED_31_MASK | DDR_PHY_DX4GCR5_DXREFISELR3_MASK | DDR_PHY_DX4GCR5_RESERVED_23_MASK | DDR_PHY_DX4GCR5_DXREFISELR2_MASK | DDR_PHY_DX4GCR5_RESERVED_15_MASK | DDR_PHY_DX4GCR5_DXREFISELR1_MASK | DDR_PHY_DX4GCR5_RESERVED_7_MASK | DDR_PHY_DX4GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX4GCR5_RESERVED_31_SHIFT
@@ -9159,11 +9073,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX4GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX4GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX4GCR6 @ 0XFD080B18
@@ -9480,16 +9394,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX5GCR5_RESERVED_31_MASK | DDR_PHY_DX5GCR5_DXREFISELR3_MASK | DDR_PHY_DX5GCR5_RESERVED_23_MASK | DDR_PHY_DX5GCR5_DXREFISELR2_MASK | DDR_PHY_DX5GCR5_RESERVED_15_MASK | DDR_PHY_DX5GCR5_DXREFISELR1_MASK | DDR_PHY_DX5GCR5_RESERVED_7_MASK | DDR_PHY_DX5GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX5GCR5_RESERVED_31_SHIFT
@@ -9497,11 +9411,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX5GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX5GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX5GCR6 @ 0XFD080C18
@@ -9818,16 +9732,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX6GCR5_RESERVED_31_MASK | DDR_PHY_DX6GCR5_DXREFISELR3_MASK | DDR_PHY_DX6GCR5_RESERVED_23_MASK | DDR_PHY_DX6GCR5_DXREFISELR2_MASK | DDR_PHY_DX6GCR5_RESERVED_15_MASK | DDR_PHY_DX6GCR5_DXREFISELR1_MASK | DDR_PHY_DX6GCR5_RESERVED_7_MASK | DDR_PHY_DX6GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX6GCR5_RESERVED_31_SHIFT
@@ -9835,11 +9749,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX6GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX6GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX6GCR6 @ 0XFD080D18
@@ -10156,16 +10070,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX7GCR5_RESERVED_31_MASK | DDR_PHY_DX7GCR5_DXREFISELR3_MASK | DDR_PHY_DX7GCR5_RESERVED_23_MASK | DDR_PHY_DX7GCR5_DXREFISELR2_MASK | DDR_PHY_DX7GCR5_RESERVED_15_MASK | DDR_PHY_DX7GCR5_DXREFISELR1_MASK | DDR_PHY_DX7GCR5_RESERVED_7_MASK | DDR_PHY_DX7GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX7GCR5_RESERVED_31_SHIFT
@@ -10173,11 +10087,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX7GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX7GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX7GCR6 @ 0XFD080E18
@@ -10494,16 +10408,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX8GCR5_RESERVED_31_MASK | DDR_PHY_DX8GCR5_DXREFISELR3_MASK | DDR_PHY_DX8GCR5_RESERVED_23_MASK | DDR_PHY_DX8GCR5_DXREFISELR2_MASK | DDR_PHY_DX8GCR5_RESERVED_15_MASK | DDR_PHY_DX8GCR5_DXREFISELR1_MASK | DDR_PHY_DX8GCR5_RESERVED_7_MASK | DDR_PHY_DX8GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8GCR5_RESERVED_31_SHIFT
@@ -10511,11 +10425,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX8GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX8GCR6 @ 0XFD080F18
@@ -10628,6 +10542,92 @@ unsigned long psu_ddr_init_data() {
PSU_Mask_Write (DDR_PHY_DX8GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
/*############################################################################################################################ */
+ /*Register : DX8SL0OSC @ 0XFD081400
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0
+
+ Enable Clock Gating for DX ddr_clk
+ PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2
+
+ Enable Clock Gating for DX ctl_rd_clk
+ PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2
+
+ Enable Clock Gating for DX ctl_clk
+ PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2
+
+ Selects the level to which clocks will be stalled when clock gating is enabled.
+ PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0
+
+ Loopback Mode
+ PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0
+
+ Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
+ PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0
+
+ Loopback DQS Gating
+ PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0
+
+ Loopback DQS Shift
+ PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0
+
+ PHY High-Speed Reset
+ PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1
+
+ PHY FIFO Reset
+ PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1
+
+ Delay Line Test Start
+ PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0
+
+ Delay Line Test Mode
+ PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3
+
+ Oscillator Mode Write-Data Delay Line Select
+ PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3
+
+ Oscillator Mode Write-Leveling Delay Line Select
+ PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3
+
+ Oscillator Mode Division
+ PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf
+
+ Oscillator Enable
+ PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0
+
+ DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
+ (OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU)
+ RegMask = (DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL0OSC_LBMODE_MASK | DDR_PHY_DX8SL0OSC_LBGSDQS_MASK | DDR_PHY_DX8SL0OSC_LBGDQS_MASK | DDR_PHY_DX8SL0OSC_LBDQSS_MASK | DDR_PHY_DX8SL0OSC_PHYHRST_MASK | DDR_PHY_DX8SL0OSC_PHYFRST_MASK | DDR_PHY_DX8SL0OSC_DLTST_MASK | DDR_PHY_DX8SL0OSC_DLTMODE_MASK | DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL0OSC_OSCWDDL_MASK | DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL0OSC_OSCWDL_MASK | DDR_PHY_DX8SL0OSC_OSCDIV_MASK | DDR_PHY_DX8SL0OSC_OSCEN_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0OSC_LBMODE_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0OSC_DLTST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT
+ | 0x0000000FU << DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0OSC_OSCEN_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_DX8SL0OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
+ /*############################################################################################################################ */
+
/*Register : DX8SL0DQSCTL @ 0XFD08141C
Reserved. Return zeroes on reads.
@@ -10667,13 +10667,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3
DQS_N Resistor
- PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0xc
+ PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0
DQS Resistor
- PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x4
+ PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0
DATX8 0-1 DQS Control Register
- (OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x012643C4U)
+ (OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U)
RegMask = (DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL0DQSCTL_DXSR_MASK | DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT
@@ -10688,10 +10688,10 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT
| 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT
| 0x00000003U << DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT
- | 0x0000000CU << DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT
- | 0x00000004U << DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL0DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+ PSU_Mask_Write (DDR_PHY_DX8SL0DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
/*############################################################################################################################ */
/*Register : DX8SL0DXCTL2 @ 0XFD08142C
@@ -10706,7 +10706,7 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0
OE Extension during Pre-amble
- PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x0
+ PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1
Reserved. Return zeroes on reads.
PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0
@@ -10745,13 +10745,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0
DATX8 0-1 DX Control Register 2
- (OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00001800U)
+ (OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U)
RegMask = (DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL0DXCTL2_IOAG_MASK | DDR_PHY_DX8SL0DXCTL2_IOLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL0DXCTL2_RDBI_MASK | DDR_PHY_DX8SL0DXCTL2_WDBI_MASK | DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL0DXCTL2_DISRST_MASK | DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT
| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT
| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT
- | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT
| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT
| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT
| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT
@@ -10765,7 +10765,7 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT
| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL0DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+ PSU_Mask_Write (DDR_PHY_DX8SL0DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
/*############################################################################################################################ */
/*Register : DX8SL0IOCR @ 0XFD081430
@@ -10802,6 +10802,92 @@ unsigned long psu_ddr_init_data() {
PSU_Mask_Write (DDR_PHY_DX8SL0IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
/*############################################################################################################################ */
+ /*Register : DX8SL1OSC @ 0XFD081440
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0
+
+ Enable Clock Gating for DX ddr_clk
+ PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2
+
+ Enable Clock Gating for DX ctl_rd_clk
+ PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2
+
+ Enable Clock Gating for DX ctl_clk
+ PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2
+
+ Selects the level to which clocks will be stalled when clock gating is enabled.
+ PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0
+
+ Loopback Mode
+ PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0
+
+ Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
+ PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0
+
+ Loopback DQS Gating
+ PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0
+
+ Loopback DQS Shift
+ PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0
+
+ PHY High-Speed Reset
+ PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1
+
+ PHY FIFO Reset
+ PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1
+
+ Delay Line Test Start
+ PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0
+
+ Delay Line Test Mode
+ PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3
+
+ Oscillator Mode Write-Data Delay Line Select
+ PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3
+
+ Oscillator Mode Write-Leveling Delay Line Select
+ PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3
+
+ Oscillator Mode Division
+ PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf
+
+ Oscillator Enable
+ PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0
+
+ DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
+ (OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU)
+ RegMask = (DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL1OSC_LBMODE_MASK | DDR_PHY_DX8SL1OSC_LBGSDQS_MASK | DDR_PHY_DX8SL1OSC_LBGDQS_MASK | DDR_PHY_DX8SL1OSC_LBDQSS_MASK | DDR_PHY_DX8SL1OSC_PHYHRST_MASK | DDR_PHY_DX8SL1OSC_PHYFRST_MASK | DDR_PHY_DX8SL1OSC_DLTST_MASK | DDR_PHY_DX8SL1OSC_DLTMODE_MASK | DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL1OSC_OSCWDDL_MASK | DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL1OSC_OSCWDL_MASK | DDR_PHY_DX8SL1OSC_OSCDIV_MASK | DDR_PHY_DX8SL1OSC_OSCEN_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1OSC_LBMODE_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1OSC_DLTST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT
+ | 0x0000000FU << DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1OSC_OSCEN_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_DX8SL1OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
+ /*############################################################################################################################ */
+
/*Register : DX8SL1DQSCTL @ 0XFD08145C
Reserved. Return zeroes on reads.
@@ -10841,13 +10927,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3
DQS_N Resistor
- PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0xc
+ PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0
DQS Resistor
- PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x4
+ PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0
DATX8 0-1 DQS Control Register
- (OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x012643C4U)
+ (OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U)
RegMask = (DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL1DQSCTL_DXSR_MASK | DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT
@@ -10862,10 +10948,10 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT
| 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT
| 0x00000003U << DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT
- | 0x0000000CU << DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT
- | 0x00000004U << DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL1DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+ PSU_Mask_Write (DDR_PHY_DX8SL1DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
/*############################################################################################################################ */
/*Register : DX8SL1DXCTL2 @ 0XFD08146C
@@ -10880,7 +10966,7 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0
OE Extension during Pre-amble
- PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x0
+ PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1
Reserved. Return zeroes on reads.
PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0
@@ -10919,13 +11005,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0
DATX8 0-1 DX Control Register 2
- (OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00001800U)
+ (OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U)
RegMask = (DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL1DXCTL2_IOAG_MASK | DDR_PHY_DX8SL1DXCTL2_IOLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL1DXCTL2_RDBI_MASK | DDR_PHY_DX8SL1DXCTL2_WDBI_MASK | DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL1DXCTL2_DISRST_MASK | DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT
| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT
| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT
- | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT
| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT
| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT
| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT
@@ -10939,7 +11025,7 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT
| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL1DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+ PSU_Mask_Write (DDR_PHY_DX8SL1DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
/*############################################################################################################################ */
/*Register : DX8SL1IOCR @ 0XFD081470
@@ -10976,6 +11062,92 @@ unsigned long psu_ddr_init_data() {
PSU_Mask_Write (DDR_PHY_DX8SL1IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
/*############################################################################################################################ */
+ /*Register : DX8SL2OSC @ 0XFD081480
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0
+
+ Enable Clock Gating for DX ddr_clk
+ PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2
+
+ Enable Clock Gating for DX ctl_rd_clk
+ PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2
+
+ Enable Clock Gating for DX ctl_clk
+ PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2
+
+ Selects the level to which clocks will be stalled when clock gating is enabled.
+ PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0
+
+ Loopback Mode
+ PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0
+
+ Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
+ PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0
+
+ Loopback DQS Gating
+ PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0
+
+ Loopback DQS Shift
+ PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0
+
+ PHY High-Speed Reset
+ PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1
+
+ PHY FIFO Reset
+ PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1
+
+ Delay Line Test Start
+ PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0
+
+ Delay Line Test Mode
+ PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3
+
+ Oscillator Mode Write-Data Delay Line Select
+ PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3
+
+ Oscillator Mode Write-Leveling Delay Line Select
+ PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3
+
+ Oscillator Mode Division
+ PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf
+
+ Oscillator Enable
+ PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0
+
+ DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
+ (OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU)
+ RegMask = (DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL2OSC_LBMODE_MASK | DDR_PHY_DX8SL2OSC_LBGSDQS_MASK | DDR_PHY_DX8SL2OSC_LBGDQS_MASK | DDR_PHY_DX8SL2OSC_LBDQSS_MASK | DDR_PHY_DX8SL2OSC_PHYHRST_MASK | DDR_PHY_DX8SL2OSC_PHYFRST_MASK | DDR_PHY_DX8SL2OSC_DLTST_MASK | DDR_PHY_DX8SL2OSC_DLTMODE_MASK | DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL2OSC_OSCWDDL_MASK | DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL2OSC_OSCWDL_MASK | DDR_PHY_DX8SL2OSC_OSCDIV_MASK | DDR_PHY_DX8SL2OSC_OSCEN_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2OSC_LBMODE_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2OSC_DLTST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT
+ | 0x0000000FU << DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2OSC_OSCEN_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_DX8SL2OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
+ /*############################################################################################################################ */
+
/*Register : DX8SL2DQSCTL @ 0XFD08149C
Reserved. Return zeroes on reads.
@@ -11015,13 +11187,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3
DQS_N Resistor
- PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0xc
+ PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0
DQS Resistor
- PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x4
+ PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0
DATX8 0-1 DQS Control Register
- (OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x012643C4U)
+ (OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U)
RegMask = (DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL2DQSCTL_DXSR_MASK | DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT
@@ -11036,10 +11208,10 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT
| 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT
| 0x00000003U << DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT
- | 0x0000000CU << DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT
- | 0x00000004U << DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL2DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+ PSU_Mask_Write (DDR_PHY_DX8SL2DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
/*############################################################################################################################ */
/*Register : DX8SL2DXCTL2 @ 0XFD0814AC
@@ -11054,7 +11226,7 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0
OE Extension during Pre-amble
- PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x0
+ PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1
Reserved. Return zeroes on reads.
PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0
@@ -11093,13 +11265,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0
DATX8 0-1 DX Control Register 2
- (OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00001800U)
+ (OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U)
RegMask = (DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL2DXCTL2_IOAG_MASK | DDR_PHY_DX8SL2DXCTL2_IOLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL2DXCTL2_RDBI_MASK | DDR_PHY_DX8SL2DXCTL2_WDBI_MASK | DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL2DXCTL2_DISRST_MASK | DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT
| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT
| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT
- | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT
| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT
| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT
| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT
@@ -11113,7 +11285,7 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT
| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL2DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+ PSU_Mask_Write (DDR_PHY_DX8SL2DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
/*############################################################################################################################ */
/*Register : DX8SL2IOCR @ 0XFD0814B0
@@ -11150,6 +11322,92 @@ unsigned long psu_ddr_init_data() {
PSU_Mask_Write (DDR_PHY_DX8SL2IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
/*############################################################################################################################ */
+ /*Register : DX8SL3OSC @ 0XFD0814C0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0
+
+ Enable Clock Gating for DX ddr_clk
+ PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2
+
+ Enable Clock Gating for DX ctl_rd_clk
+ PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2
+
+ Enable Clock Gating for DX ctl_clk
+ PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2
+
+ Selects the level to which clocks will be stalled when clock gating is enabled.
+ PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0
+
+ Loopback Mode
+ PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0
+
+ Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
+ PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0
+
+ Loopback DQS Gating
+ PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0
+
+ Loopback DQS Shift
+ PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0
+
+ PHY High-Speed Reset
+ PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1
+
+ PHY FIFO Reset
+ PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1
+
+ Delay Line Test Start
+ PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0
+
+ Delay Line Test Mode
+ PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3
+
+ Oscillator Mode Write-Data Delay Line Select
+ PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3
+
+ Oscillator Mode Write-Leveling Delay Line Select
+ PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3
+
+ Oscillator Mode Division
+ PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf
+
+ Oscillator Enable
+ PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0
+
+ DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
+ (OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU)
+ RegMask = (DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL3OSC_LBMODE_MASK | DDR_PHY_DX8SL3OSC_LBGSDQS_MASK | DDR_PHY_DX8SL3OSC_LBGDQS_MASK | DDR_PHY_DX8SL3OSC_LBDQSS_MASK | DDR_PHY_DX8SL3OSC_PHYHRST_MASK | DDR_PHY_DX8SL3OSC_PHYFRST_MASK | DDR_PHY_DX8SL3OSC_DLTST_MASK | DDR_PHY_DX8SL3OSC_DLTMODE_MASK | DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL3OSC_OSCWDDL_MASK | DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL3OSC_OSCWDL_MASK | DDR_PHY_DX8SL3OSC_OSCDIV_MASK | DDR_PHY_DX8SL3OSC_OSCEN_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3OSC_LBMODE_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3OSC_DLTST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT
+ | 0x0000000FU << DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3OSC_OSCEN_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_DX8SL3OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
+ /*############################################################################################################################ */
+
/*Register : DX8SL3DQSCTL @ 0XFD0814DC
Reserved. Return zeroes on reads.
@@ -11189,13 +11447,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3
DQS_N Resistor
- PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0xc
+ PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0
DQS Resistor
- PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x4
+ PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0
DATX8 0-1 DQS Control Register
- (OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x012643C4U)
+ (OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U)
RegMask = (DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL3DQSCTL_DXSR_MASK | DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT
@@ -11210,10 +11468,10 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT
| 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT
| 0x00000003U << DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT
- | 0x0000000CU << DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT
- | 0x00000004U << DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL3DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+ PSU_Mask_Write (DDR_PHY_DX8SL3DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
/*############################################################################################################################ */
/*Register : DX8SL3DXCTL2 @ 0XFD0814EC
@@ -11228,7 +11486,7 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0
OE Extension during Pre-amble
- PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x0
+ PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1
Reserved. Return zeroes on reads.
PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0
@@ -11267,13 +11525,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0
DATX8 0-1 DX Control Register 2
- (OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00001800U)
+ (OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U)
RegMask = (DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL3DXCTL2_IOAG_MASK | DDR_PHY_DX8SL3DXCTL2_IOLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL3DXCTL2_RDBI_MASK | DDR_PHY_DX8SL3DXCTL2_WDBI_MASK | DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL3DXCTL2_DISRST_MASK | DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT
| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT
| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT
- | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT
| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT
| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT
| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT
@@ -11287,7 +11545,7 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT
| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL3DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+ PSU_Mask_Write (DDR_PHY_DX8SL3DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
/*############################################################################################################################ */
/*Register : DX8SL3IOCR @ 0XFD0814F0
@@ -11324,6 +11582,92 @@ unsigned long psu_ddr_init_data() {
PSU_Mask_Write (DDR_PHY_DX8SL3IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
/*############################################################################################################################ */
+ /*Register : DX8SL4OSC @ 0XFD081500
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0
+
+ Enable Clock Gating for DX ddr_clk
+ PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x2
+
+ Enable Clock Gating for DX ctl_rd_clk
+ PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x2
+
+ Enable Clock Gating for DX ctl_clk
+ PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x2
+
+ Selects the level to which clocks will be stalled when clock gating is enabled.
+ PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0
+
+ Loopback Mode
+ PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0
+
+ Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
+ PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0
+
+ Loopback DQS Gating
+ PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0
+
+ Loopback DQS Shift
+ PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0
+
+ PHY High-Speed Reset
+ PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1
+
+ PHY FIFO Reset
+ PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1
+
+ Delay Line Test Start
+ PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0
+
+ Delay Line Test Mode
+ PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3
+
+ Oscillator Mode Write-Data Delay Line Select
+ PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3
+
+ Oscillator Mode Write-Leveling Delay Line Select
+ PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3
+
+ Oscillator Mode Division
+ PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf
+
+ Oscillator Enable
+ PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0
+
+ DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
+ (OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU)
+ RegMask = (DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL4OSC_LBMODE_MASK | DDR_PHY_DX8SL4OSC_LBGSDQS_MASK | DDR_PHY_DX8SL4OSC_LBGDQS_MASK | DDR_PHY_DX8SL4OSC_LBDQSS_MASK | DDR_PHY_DX8SL4OSC_PHYHRST_MASK | DDR_PHY_DX8SL4OSC_PHYFRST_MASK | DDR_PHY_DX8SL4OSC_DLTST_MASK | DDR_PHY_DX8SL4OSC_DLTMODE_MASK | DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL4OSC_OSCWDDL_MASK | DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL4OSC_OSCWDL_MASK | DDR_PHY_DX8SL4OSC_OSCDIV_MASK | DDR_PHY_DX8SL4OSC_OSCEN_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4OSC_LBMODE_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4OSC_DLTST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT
+ | 0x0000000FU << DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4OSC_OSCEN_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_DX8SL4OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
+ /*############################################################################################################################ */
+
/*Register : DX8SL4DQSCTL @ 0XFD08151C
Reserved. Return zeroes on reads.
@@ -11363,13 +11707,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3
DQS_N Resistor
- PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0xc
+ PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0
DQS Resistor
- PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x4
+ PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0
DATX8 0-1 DQS Control Register
- (OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x012643C4U)
+ (OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01264300U)
RegMask = (DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL4DQSCTL_DXSR_MASK | DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT
@@ -11384,10 +11728,10 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT
| 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT
| 0x00000003U << DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT
- | 0x0000000CU << DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT
- | 0x00000004U << DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL4DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+ PSU_Mask_Write (DDR_PHY_DX8SL4DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
/*############################################################################################################################ */
/*Register : DX8SL4DXCTL2 @ 0XFD08152C
@@ -11402,7 +11746,7 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0
OE Extension during Pre-amble
- PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x0
+ PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1
Reserved. Return zeroes on reads.
PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0
@@ -11441,13 +11785,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0
DATX8 0-1 DX Control Register 2
- (OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00001800U)
+ (OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U)
RegMask = (DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL4DXCTL2_IOAG_MASK | DDR_PHY_DX8SL4DXCTL2_IOLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL4DXCTL2_RDBI_MASK | DDR_PHY_DX8SL4DXCTL2_WDBI_MASK | DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL4DXCTL2_DISRST_MASK | DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT
| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT
| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT
- | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT
| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT
| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT
| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT
@@ -11461,7 +11805,7 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT
| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL4DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+ PSU_Mask_Write (DDR_PHY_DX8SL4DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
/*############################################################################################################################ */
/*Register : DX8SL4IOCR @ 0XFD081530
@@ -12515,7 +12859,7 @@ unsigned long psu_mio_init_data() {
Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
- PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 1
+ PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0
Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
@@ -12525,15 +12869,15 @@ unsigned long psu_mio_init_data() {
PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0
Configures MIO Pin 26 peripheral interface mapping
- (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000008U)
+ (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U)
RegMask = (IOU_SLCR_MIO_PIN_26_L0_SEL_MASK | IOU_SLCR_MIO_PIN_26_L1_SEL_MASK | IOU_SLCR_MIO_PIN_26_L2_SEL_MASK | IOU_SLCR_MIO_PIN_26_L3_SEL_MASK | 0 );
RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT
- | 0x00000001U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
+ | 0x00000000U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (IOU_SLCR_MIO_PIN_26_OFFSET ,0x000000FEU ,0x00000008U);
+ PSU_Mask_Write (IOU_SLCR_MIO_PIN_26_OFFSET ,0x000000FEU ,0x00000000U);
/*############################################################################################################################ */
/*Register : MIO_PIN_27 @ 0XFF18006C
@@ -12547,7 +12891,7 @@ unsigned long psu_mio_init_data() {
Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
t, dp_aux_data_out- (Dp Aux Data)
- PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 0
+ PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3
Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
@@ -12557,15 +12901,15 @@ unsigned long psu_mio_init_data() {
PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0
Configures MIO Pin 27 peripheral interface mapping
- (OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U)
RegMask = (IOU_SLCR_MIO_PIN_27_L0_SEL_MASK | IOU_SLCR_MIO_PIN_27_L1_SEL_MASK | IOU_SLCR_MIO_PIN_27_L2_SEL_MASK | IOU_SLCR_MIO_PIN_27_L3_SEL_MASK | 0 );
RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT
- | 0x00000000U << IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
+ | 0x00000003U << IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (IOU_SLCR_MIO_PIN_27_OFFSET ,0x000000FEU ,0x00000000U);
+ PSU_Mask_Write (IOU_SLCR_MIO_PIN_27_OFFSET ,0x000000FEU ,0x00000018U);
/*############################################################################################################################ */
/*Register : MIO_PIN_28 @ 0XFF180070
@@ -12578,7 +12922,7 @@ unsigned long psu_mio_init_data() {
Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
- PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 0
+ PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3
Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
@@ -12587,15 +12931,15 @@ unsigned long psu_mio_init_data() {
PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0
Configures MIO Pin 28 peripheral interface mapping
- (OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U)
RegMask = (IOU_SLCR_MIO_PIN_28_L0_SEL_MASK | IOU_SLCR_MIO_PIN_28_L1_SEL_MASK | IOU_SLCR_MIO_PIN_28_L2_SEL_MASK | IOU_SLCR_MIO_PIN_28_L3_SEL_MASK | 0 );
RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT
- | 0x00000000U << IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
+ | 0x00000003U << IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (IOU_SLCR_MIO_PIN_28_OFFSET ,0x000000FEU ,0x00000000U);
+ PSU_Mask_Write (IOU_SLCR_MIO_PIN_28_OFFSET ,0x000000FEU ,0x00000018U);
/*############################################################################################################################ */
/*Register : MIO_PIN_29 @ 0XFF180074
@@ -12609,7 +12953,7 @@ unsigned long psu_mio_init_data() {
Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
t, dp_aux_data_out- (Dp Aux Data)
- PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 0
+ PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3
Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
@@ -12619,15 +12963,15 @@ unsigned long psu_mio_init_data() {
PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0
Configures MIO Pin 29 peripheral interface mapping
- (OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U)
RegMask = (IOU_SLCR_MIO_PIN_29_L0_SEL_MASK | IOU_SLCR_MIO_PIN_29_L1_SEL_MASK | IOU_SLCR_MIO_PIN_29_L2_SEL_MASK | IOU_SLCR_MIO_PIN_29_L3_SEL_MASK | 0 );
RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT
- | 0x00000000U << IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
+ | 0x00000003U << IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (IOU_SLCR_MIO_PIN_29_OFFSET ,0x000000FEU ,0x00000000U);
+ PSU_Mask_Write (IOU_SLCR_MIO_PIN_29_OFFSET ,0x000000FEU ,0x00000018U);
/*############################################################################################################################ */
/*Register : MIO_PIN_30 @ 0XFF180078
@@ -12640,7 +12984,7 @@ unsigned long psu_mio_init_data() {
Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
- PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 0
+ PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3
Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
@@ -12650,15 +12994,15 @@ unsigned long psu_mio_init_data() {
PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0
Configures MIO Pin 30 peripheral interface mapping
- (OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U)
RegMask = (IOU_SLCR_MIO_PIN_30_L0_SEL_MASK | IOU_SLCR_MIO_PIN_30_L1_SEL_MASK | IOU_SLCR_MIO_PIN_30_L2_SEL_MASK | IOU_SLCR_MIO_PIN_30_L3_SEL_MASK | 0 );
RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT
- | 0x00000000U << IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
+ | 0x00000003U << IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (IOU_SLCR_MIO_PIN_30_OFFSET ,0x000000FEU ,0x00000000U);
+ PSU_Mask_Write (IOU_SLCR_MIO_PIN_30_OFFSET ,0x000000FEU ,0x00000018U);
/*############################################################################################################################ */
/*Register : MIO_PIN_31 @ 0XFF18007C
@@ -14189,25 +14533,25 @@ unsigned long psu_mio_init_data() {
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1
Master Tri-state Enable for pin 26, active high
- PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 1
+ PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0
Master Tri-state Enable for pin 27, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0
Master Tri-state Enable for pin 28, active high
- PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 0
+ PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1
Master Tri-state Enable for pin 29, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0
Master Tri-state Enable for pin 30, active high
- PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 0
+ PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1
Master Tri-state Enable for pin 31, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0
MIO pin Tri-state Enables, 31:0
- (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x06240000U)
+ (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U)
RegMask = (IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK | 0 );
RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT
@@ -14236,14 +14580,14 @@ unsigned long psu_mio_init_data() {
| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT
| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT
| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT
- | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
+ | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT
- | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
+ | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT
- | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
+ | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI0_OFFSET ,0xFFFFFFFFU ,0x06240000U);
+ PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI0_OFFSET ,0xFFFFFFFFU ,0x52240000U);
/*############################################################################################################################ */
/*Register : MIO_MST_TRI1 @ 0XFF180208
@@ -16538,6 +16882,21 @@ unsigned long psu_mio_init_data() {
}
unsigned long psu_peripherals_init_data() {
// : RESET BLOCKS
+ // : TIMESTAMP
+ /*Register : RST_LPD_IOU2 @ 0XFF5E0238
+
+ Block level reset
+ PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0
+
+ Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+ (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00100000U ,0x00000000U)
+ RegMask = (CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK | 0 );
+
+ RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00100000U ,0x00000000U);
+ /*############################################################################################################################ */
+
// : ENET
/*Register : RST_LPD_IOU0 @ 0XFF5E0230
@@ -16568,6 +16927,21 @@ unsigned long psu_peripherals_init_data() {
PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000001U ,0x00000000U);
/*############################################################################################################################ */
+ // : QSPI TAP DELAY
+ /*Register : IOU_TAPDLY_BYPASS @ 0XFF180390
+
+ 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI
+ PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1
+
+ IOU tap delay bypass for the LQSPI and NAND controllers
+ (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U)
+ RegMask = (IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK | 0 );
+
+ RegVal = ((0x00000001U << IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET ,0x00000004U ,0x00000004U);
+ /*############################################################################################################################ */
+
// : NAND
// : USB
/*Register : RST_LPD_TOP @ 0XFF5E023C
@@ -16718,6 +17092,23 @@ unsigned long psu_peripherals_init_data() {
PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG1_OFFSET ,0x7F800000U ,0x63800000U);
/*############################################################################################################################ */
+ // : SD1 RETUNER
+ /*Register : SD_CONFIG_REG3 @ 0XFF180324
+
+ This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf
+ rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon
+ s Fh - Ch = Reserved
+ PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0
+
+ SD Config Register 3
+ (OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U)
+ RegMask = (IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK | 0 );
+
+ RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG3_OFFSET ,0x03C00000U ,0x00000000U);
+ /*############################################################################################################################ */
+
// : CAN
/*Register : RST_LPD_IOU2 @ 0XFF5E0238
@@ -17158,6 +17549,37 @@ unsigned long psu_peripherals_init_data() {
PSU_Mask_Write (RTC_CONTROL_OFFSET ,0x80000000U ,0x80000000U);
/*############################################################################################################################ */
+ // : TIMESTAMP COUNTER
+ /*Register : base_frequency_ID_register @ 0XFF260020
+
+ Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz.
+ PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5e100
+
+ Program this register to match the clock frequency of the timestamp generator, in ticks per second. For example, for a 50 MHz
+ clock, program 0x02FAF080. This register is not accessible to the read-only programming interface.
+ (OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5E100U)
+ RegMask = (IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK | 0 );
+
+ RegVal = ((0x05F5E100U << IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET ,0xFFFFFFFFU ,0x05F5E100U);
+ /*############################################################################################################################ */
+
+ /*Register : counter_control_register @ 0XFF260000
+
+ Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing.
+ PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1
+
+ Controls the counter increments. This register is not accessible to the read-only programming interface.
+ (OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U)
+ RegMask = (IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK | 0 );
+
+ RegVal = ((0x00000001U << IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ // : TTC SRC SELECT
return 1;
}
@@ -17172,6 +17594,98 @@ unsigned long psu_peripherals_powerdwn_data() {
return 1;
}
+unsigned long psu_lpd_xppu_data() {
+ // : XPPU INTERRUPT ENABLE
+ /*Register : IEN @ 0XFF980018
+
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_APER_PARITY 0X1
+
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_APER_TZ 0X1
+
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_APER_PERM 0X1
+
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_MID_PARITY 0X1
+
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_MID_RO 0X1
+
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_MID_MISS 0X1
+
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_INV_APB 0X1
+
+ Interrupt Enable Register
+ (OFFSET, MASK, VALUE) (0XFF980018, 0x000000EFU ,0x000000EFU)
+ RegMask = (LPD_XPPU_CFG_IEN_APER_PARITY_MASK | LPD_XPPU_CFG_IEN_APER_TZ_MASK | LPD_XPPU_CFG_IEN_APER_PERM_MASK | LPD_XPPU_CFG_IEN_MID_PARITY_MASK | LPD_XPPU_CFG_IEN_MID_RO_MASK | LPD_XPPU_CFG_IEN_MID_MISS_MASK | LPD_XPPU_CFG_IEN_INV_APB_MASK | 0 );
+
+ RegVal = ((0x00000001U << LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_APER_TZ_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_APER_PERM_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_MID_RO_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_MID_MISS_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_INV_APB_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (LPD_XPPU_CFG_IEN_OFFSET ,0x000000EFU ,0x000000EFU);
+ /*############################################################################################################################ */
+
+
+ return 1;
+}
+unsigned long psu_ddr_xmpu0_data() {
+
+ return 1;
+}
+unsigned long psu_ddr_xmpu1_data() {
+
+ return 1;
+}
+unsigned long psu_ddr_xmpu2_data() {
+
+ return 1;
+}
+unsigned long psu_ddr_xmpu3_data() {
+
+ return 1;
+}
+unsigned long psu_ddr_xmpu4_data() {
+
+ return 1;
+}
+unsigned long psu_ddr_xmpu5_data() {
+
+ return 1;
+}
+unsigned long psu_ocm_xmpu_data() {
+
+ return 1;
+}
+unsigned long psu_fpd_xmpu_data() {
+
+ return 1;
+}
+unsigned long psu_protection_lock_data() {
+
+ return 1;
+}
+unsigned long psu_apply_master_tz() {
+ // : RPU
+ // : DP TZ
+ // : SATA TZ
+ // : PCIE TZ
+ // : USB TZ
+ // : SD TZ
+ // : GEM TZ
+ // : QSPI TZ
+ // : NAND TZ
+
+ return 1;
+}
unsigned long psu_serdes_init_data() {
// : SERDES INITIALIZATION
// : GT REFERENCE CLOCK SOURCE SELECTION
@@ -17350,99 +17864,99 @@ unsigned long psu_serdes_init_data() {
/*Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368
Spread Spectrum No of Steps [7:0]
- PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x0
+ PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0
Spread Spectrum No of Steps bits 7:0
- (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U)
RegMask = (SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+ RegVal = ((0x000000E0U << SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x000000E0U);
/*############################################################################################################################ */
/*Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C
Spread Spectrum No of Steps [10:8]
- PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x0
+ PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
Spread Spectrum No of Steps bits 10:8
- (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U)
RegMask = (SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+ RegVal = ((0x00000003U << SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
/*############################################################################################################################ */
/*Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368
Spread Spectrum No of Steps [7:0]
- PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x0
+ PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58
Spread Spectrum No of Steps bits 7:0
- (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U)
RegMask = (SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+ RegVal = ((0x00000058U << SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000058U);
/*############################################################################################################################ */
/*Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C
Spread Spectrum No of Steps [10:8]
- PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x0
+ PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
Spread Spectrum No of Steps bits 10:8
- (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U)
RegMask = (SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+ RegVal = ((0x00000003U << SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000000U);
+ PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
/*############################################################################################################################ */
/*Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370
Step Size for Spread Spectrum [7:0]
- PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x0
+ PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C
Step Size for Spread Spectrum LSB
- (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU)
RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+ RegVal = ((0x0000007CU << SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x0000007CU);
/*############################################################################################################################ */
/*Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374
Step Size for Spread Spectrum [15:8]
- PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x0
+ PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33
Step Size for Spread Spectrum 1
- (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U)
RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+ RegVal = ((0x00000033U << SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000033U);
/*############################################################################################################################ */
/*Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378
Step Size for Spread Spectrum [23:16]
- PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x0
+ PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2
Step Size for Spread Spectrum 2
- (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U)
RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+ RegVal = ((0x00000002U << SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U);
/*############################################################################################################################ */
/*Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C
@@ -17534,43 +18048,43 @@ unsigned long psu_serdes_init_data() {
/*Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370
Step Size for Spread Spectrum [7:0]
- PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x0
+ PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9
Step Size for Spread Spectrum LSB
- (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U)
RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+ RegVal = ((0x000000C9U << SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000C9U);
/*############################################################################################################################ */
/*Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374
Step Size for Spread Spectrum [15:8]
- PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x0
+ PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2
Step Size for Spread Spectrum 1
- (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U)
RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+ RegVal = ((0x000000D2U << SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x000000D2U);
/*############################################################################################################################ */
/*Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378
Step Size for Spread Spectrum [23:16]
- PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x0
+ PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1
Step Size for Spread Spectrum 2
- (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U)
RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000001U);
/*############################################################################################################################ */
/*Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C
@@ -17711,38 +18225,883 @@ unsigned long psu_serdes_init_data() {
PSU_Mask_Write (SERDES_L3_TXPMA_ST_0_OFFSET ,0x000000F0U ,0x000000F0U);
/*############################################################################################################################ */
- // : GT LANE SETTINGS
- /*Register : ICM_CFG0 @ 0XFD410010
-
- Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
- , 7 - Unused
- PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1
+ // : ENABLE CHICKEN BIT FOR PCIE AND USB
+ /*Register : L0_TM_AUX_0 @ 0XFD4010CC
- Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused
- 7 - Unused
- PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4
+ Spare- not used
+ PSU_SERDES_L0_TM_AUX_0_BIT_2 1
- ICM Configuration Register 0
- (OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U)
- RegMask = (SERDES_ICM_CFG0_L0_ICM_CFG_MASK | SERDES_ICM_CFG0_L1_ICM_CFG_MASK | 0 );
+ Spare registers
+ (OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U)
+ RegMask = (SERDES_L0_TM_AUX_0_BIT_2_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT
- | 0x00000004U << SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT
+ RegVal = ((0x00000001U << SERDES_L0_TM_AUX_0_BIT_2_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_ICM_CFG0_OFFSET ,0x00000077U ,0x00000041U);
+ PSU_Mask_Write (SERDES_L0_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U);
/*############################################################################################################################ */
- /*Register : ICM_CFG1 @ 0XFD410014
+ /*Register : L2_TM_AUX_0 @ 0XFD4090CC
- Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused
- 7 - Unused
- PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3
+ Spare- not used
+ PSU_SERDES_L2_TM_AUX_0_BIT_2 1
- Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused
- 7 - Unused
- PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2
+ Spare registers
+ (OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U)
+ RegMask = (SERDES_L2_TM_AUX_0_BIT_2_MASK | 0 );
- ICM Configuration Register 1
+ RegVal = ((0x00000001U << SERDES_L2_TM_AUX_0_BIT_2_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U);
+ /*############################################################################################################################ */
+
+ // : ENABLING EYE SURF
+ /*Register : L0_TM_DIG_8 @ 0XFD401074
+
+ Enable Eye Surf
+ PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1
+
+ Test modes for Elastic buffer and enabling Eye Surf
+ (OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U)
+ RegMask = (SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
+ /*############################################################################################################################ */
+
+ /*Register : L1_TM_DIG_8 @ 0XFD405074
+
+ Enable Eye Surf
+ PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1
+
+ Test modes for Elastic buffer and enabling Eye Surf
+ (OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U)
+ RegMask = (SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L1_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_DIG_8 @ 0XFD409074
+
+ Enable Eye Surf
+ PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1
+
+ Test modes for Elastic buffer and enabling Eye Surf
+ (OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U)
+ RegMask = (SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_DIG_8 @ 0XFD40D074
+
+ Enable Eye Surf
+ PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1
+
+ Test modes for Elastic buffer and enabling Eye Surf
+ (OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U)
+ RegMask = (SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
+ /*############################################################################################################################ */
+
+ // : ILL SETTINGS FOR GAIN AND LOCK SETTINGS
+ /*Register : L0_TM_MISC2 @ 0XFD40189C
+
+ ILL calib counts BYPASSED with calcode bits
+ PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
+
+ sampler cal
+ (OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U)
+ RegMask = (SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_IQ_ILL1 @ 0XFD4018F8
+
+ IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U)
+ RegMask = (SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 );
+
+ RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x00000064U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_IQ_ILL2 @ 0XFD4018FC
+
+ IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U)
+ RegMask = (SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 );
+
+ RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x00000064U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_ILL12 @ 0XFD401990
+
+ G1A pll ctr bypass value
+ PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11
+
+ ill pll counter values
+ (OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U)
+ RegMask = (SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 );
+
+ RegVal = ((0x00000011U << SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_ILL12_OFFSET ,0x000000FFU ,0x00000011U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_E_ILL1 @ 0XFD401924
+
+ E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U)
+ RegMask = (SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 );
+
+ RegVal = ((0x00000004U << SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_E_ILL1_OFFSET ,0x000000FFU ,0x00000004U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_E_ILL2 @ 0XFD401928
+
+ E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU)
+ RegMask = (SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 );
+
+ RegVal = ((0x000000FEU << SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_E_ILL2_OFFSET ,0x000000FFU ,0x000000FEU);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_IQ_ILL3 @ 0XFD401900
+
+ IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U)
+ RegMask = (SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 );
+
+ RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x00000064U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_E_ILL3 @ 0XFD40192C
+
+ E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U)
+ RegMask = (SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 );
+
+ RegVal = ((0x00000000U << SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_ILL8 @ 0XFD401980
+
+ ILL calibration code change wait time
+ PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
+
+ ILL cal routine control
+ (OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 );
+
+ RegVal = ((0x000000FFU << SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_IQ_ILL8 @ 0XFD401914
+
+ IQ ILL polytrim bypass value
+ PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
+
+ iqpi polytrim
+ (OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U)
+ RegMask = (SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 );
+
+ RegVal = ((0x000000F7U << SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_IQ_ILL9 @ 0XFD401918
+
+ bypass IQ polytrim
+ PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
+
+ enables for lf,constant gm trim and polytirm
+ (OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_E_ILL8 @ 0XFD401940
+
+ E ILL polytrim bypass value
+ PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
+
+ epi polytrim
+ (OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U)
+ RegMask = (SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 );
+
+ RegVal = ((0x000000F7U << SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_E_ILL9 @ 0XFD401944
+
+ bypass E polytrim
+ PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
+
+ enables for lf,constant gm trim and polytirm
+ (OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_MISC2 @ 0XFD40989C
+
+ ILL calib counts BYPASSED with calcode bits
+ PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
+
+ sampler cal
+ (OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U)
+ RegMask = (SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_IQ_ILL1 @ 0XFD4098F8
+
+ IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU)
+ RegMask = (SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 );
+
+ RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000001AU);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_IQ_ILL2 @ 0XFD4098FC
+
+ IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU)
+ RegMask = (SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 );
+
+ RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000001AU);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_ILL12 @ 0XFD409990
+
+ G1A pll ctr bypass value
+ PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10
+
+ ill pll counter values
+ (OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U)
+ RegMask = (SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 );
+
+ RegVal = ((0x00000010U << SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_ILL12_OFFSET ,0x000000FFU ,0x00000010U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_E_ILL1 @ 0XFD409924
+
+ E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU)
+ RegMask = (SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 );
+
+ RegVal = ((0x000000FEU << SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_E_ILL1_OFFSET ,0x000000FFU ,0x000000FEU);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_E_ILL2 @ 0XFD409928
+
+ E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U)
+ RegMask = (SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 );
+
+ RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_IQ_ILL3 @ 0XFD409900
+
+ IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU)
+ RegMask = (SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 );
+
+ RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000001AU);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_E_ILL3 @ 0XFD40992C
+
+ E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U)
+ RegMask = (SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 );
+
+ RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_ILL8 @ 0XFD409980
+
+ ILL calibration code change wait time
+ PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
+
+ ILL cal routine control
+ (OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 );
+
+ RegVal = ((0x000000FFU << SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_IQ_ILL8 @ 0XFD409914
+
+ IQ ILL polytrim bypass value
+ PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
+
+ iqpi polytrim
+ (OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U)
+ RegMask = (SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 );
+
+ RegVal = ((0x000000F7U << SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_IQ_ILL9 @ 0XFD409918
+
+ bypass IQ polytrim
+ PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
+
+ enables for lf,constant gm trim and polytirm
+ (OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_E_ILL8 @ 0XFD409940
+
+ E ILL polytrim bypass value
+ PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
+
+ epi polytrim
+ (OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U)
+ RegMask = (SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 );
+
+ RegVal = ((0x000000F7U << SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_E_ILL9 @ 0XFD409944
+
+ bypass E polytrim
+ PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
+
+ enables for lf,constant gm trim and polytirm
+ (OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_MISC2 @ 0XFD40D89C
+
+ ILL calib counts BYPASSED with calcode bits
+ PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
+
+ sampler cal
+ (OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U)
+ RegMask = (SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8
+
+ IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU)
+ RegMask = (SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 );
+
+ RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000007DU);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC
+
+ IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU)
+ RegMask = (SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 );
+
+ RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000007DU);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_ILL12 @ 0XFD40D990
+
+ G1A pll ctr bypass value
+ PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1
+
+ ill pll counter values
+ (OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U)
+ RegMask = (SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_ILL12_OFFSET ,0x000000FFU ,0x00000001U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_E_ILL1 @ 0XFD40D924
+
+ E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU)
+ RegMask = (SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 );
+
+ RegVal = ((0x0000009CU << SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_E_ILL1_OFFSET ,0x000000FFU ,0x0000009CU);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_E_ILL2 @ 0XFD40D928
+
+ E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U)
+ RegMask = (SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 );
+
+ RegVal = ((0x00000039U << SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000039U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_ILL11 @ 0XFD40D98C
+
+ G2A_PCIe1 PLL ctr bypass value
+ PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2
+
+ ill pll counter values
+ (OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U)
+ RegMask = (SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK | 0 );
+
+ RegVal = ((0x00000002U << SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_ILL11_OFFSET ,0x000000F0U ,0x00000020U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_IQ_ILL3 @ 0XFD40D900
+
+ IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU)
+ RegMask = (SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 );
+
+ RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000007DU);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_E_ILL3 @ 0XFD40D92C
+
+ E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U)
+ RegMask = (SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 );
+
+ RegVal = ((0x00000064U << SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000064U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_ILL8 @ 0XFD40D980
+
+ ILL calibration code change wait time
+ PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
+
+ ILL cal routine control
+ (OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 );
+
+ RegVal = ((0x000000FFU << SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_IQ_ILL8 @ 0XFD40D914
+
+ IQ ILL polytrim bypass value
+ PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
+
+ iqpi polytrim
+ (OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U)
+ RegMask = (SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 );
+
+ RegVal = ((0x000000F7U << SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_IQ_ILL9 @ 0XFD40D918
+
+ bypass IQ polytrim
+ PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
+
+ enables for lf,constant gm trim and polytirm
+ (OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_E_ILL8 @ 0XFD40D940
+
+ E ILL polytrim bypass value
+ PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
+
+ epi polytrim
+ (OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U)
+ RegMask = (SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 );
+
+ RegVal = ((0x000000F7U << SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_E_ILL9 @ 0XFD40D944
+
+ bypass E polytrim
+ PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
+
+ enables for lf,constant gm trim and polytirm
+ (OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ // : SYMBOL LOCK AND WAIT
+ /*Register : L0_TM_DIG_21 @ 0XFD4010A8
+
+ pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20
+ PSU_SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH 0x11
+
+ Control symbol alignment locking - wait counts
+ (OFFSET, MASK, VALUE) (0XFD4010A8, 0x00000003U ,0x00000003U)
+ RegMask = (SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK | 0 );
+
+ RegVal = ((0x00000011U << SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_DIG_21_OFFSET ,0x00000003U ,0x00000003U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_DIG_10 @ 0XFD40107C
+
+ CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
+ PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0xF
+
+ test control for changing cdr lock wait time
+ (OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x0000000FU)
+ RegMask = (SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK | 0 );
+
+ RegVal = ((0x0000000FU << SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_DIG_10_OFFSET ,0x0000000FU ,0x0000000FU);
+ /*############################################################################################################################ */
+
+ // : SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG
+ /*Register : L0_TM_RST_DLY @ 0XFD4019A4
+
+ Delay apb reset by specified amount
+ PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF
+
+ reset delay for apb reset w.r.t pso of hsrx
+ (OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK | 0 );
+
+ RegVal = ((0x000000FFU << SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_ANA_BYP_15 @ 0XFD401038
+
+ Enable Bypass for <7> of TM_ANA_BYPS_15
+ PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
+
+ Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
+ (OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_ANA_BYP_12 @ 0XFD40102C
+
+ Enable Bypass for <7> of TM_ANA_BYPS_12
+ PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
+
+ Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
+ (OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
+ /*############################################################################################################################ */
+
+ /*Register : L1_TM_RST_DLY @ 0XFD4059A4
+
+ Delay apb reset by specified amount
+ PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF
+
+ reset delay for apb reset w.r.t pso of hsrx
+ (OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK | 0 );
+
+ RegVal = ((0x000000FFU << SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L1_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
+ /*############################################################################################################################ */
+
+ /*Register : L1_TM_ANA_BYP_15 @ 0XFD405038
+
+ Enable Bypass for <7> of TM_ANA_BYPS_15
+ PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
+
+ Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
+ (OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
+ /*############################################################################################################################ */
+
+ /*Register : L1_TM_ANA_BYP_12 @ 0XFD40502C
+
+ Enable Bypass for <7> of TM_ANA_BYPS_12
+ PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
+
+ Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
+ (OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_RST_DLY @ 0XFD4099A4
+
+ Delay apb reset by specified amount
+ PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF
+
+ reset delay for apb reset w.r.t pso of hsrx
+ (OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK | 0 );
+
+ RegVal = ((0x000000FFU << SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_ANA_BYP_15 @ 0XFD409038
+
+ Enable Bypass for <7> of TM_ANA_BYPS_15
+ PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
+
+ Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
+ (OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_ANA_BYP_12 @ 0XFD40902C
+
+ Enable Bypass for <7> of TM_ANA_BYPS_12
+ PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
+
+ Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
+ (OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_RST_DLY @ 0XFD40D9A4
+
+ Delay apb reset by specified amount
+ PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF
+
+ reset delay for apb reset w.r.t pso of hsrx
+ (OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK | 0 );
+
+ RegVal = ((0x000000FFU << SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_ANA_BYP_15 @ 0XFD40D038
+
+ Enable Bypass for <7> of TM_ANA_BYPS_15
+ PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
+
+ Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
+ (OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C
+
+ Enable Bypass for <7> of TM_ANA_BYPS_12
+ PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
+
+ Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
+ (OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
+ /*############################################################################################################################ */
+
+ // : GT LANE SETTINGS
+ /*Register : ICM_CFG0 @ 0XFD410010
+
+ Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
+ , 7 - Unused
+ PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1
+
+ Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused
+ 7 - Unused
+ PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4
+
+ ICM Configuration Register 0
+ (OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U)
+ RegMask = (SERDES_ICM_CFG0_L0_ICM_CFG_MASK | SERDES_ICM_CFG0_L1_ICM_CFG_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT
+ | 0x00000004U << SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_ICM_CFG0_OFFSET ,0x00000077U ,0x00000041U);
+ /*############################################################################################################################ */
+
+ /*Register : ICM_CFG1 @ 0XFD410014
+
+ Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused
+ 7 - Unused
+ PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3
+
+ Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused
+ 7 - Unused
+ PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2
+
+ ICM Configuration Register 1
(OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U)
RegMask = (SERDES_ICM_CFG1_L2_ICM_CFG_MASK | SERDES_ICM_CFG1_L3_ICM_CFG_MASK | 0 );
@@ -17756,48 +19115,128 @@ unsigned long psu_serdes_init_data() {
// : ENABLE SERIAL DATA MUX DEEMPH
/*Register : L1_TXPMD_TM_45 @ 0XFD404CB4
- Enable/disable DP post2 path
- PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1
+ Enable/disable DP post2 path
+ PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1
+
+ Override enable/disable of DP post2 path
+ PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1
+
+ Override enable/disable of DP post1 path
+ PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1
+
+ Enable/disable DP main path
+ PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1
+
+ Override enable/disable of DP main path
+ PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1
+
+ Post or pre or main DP path selection
+ (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U)
+ RegMask = (SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
+ | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
+ | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
+ | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
+ | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L1_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U);
+ /*############################################################################################################################ */
+
+ /*Register : L1_TX_ANA_TM_118 @ 0XFD4041D8
+
+ Test register force for enabling/disablign TX deemphasis bits <17:0>
+ PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
+
+ Enable Override of TX deemphasis
+ (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L1_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8
+
+ Test register force for enabling/disablign TX deemphasis bits <17:0>
+ PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
+
+ Enable Override of TX deemphasis
+ (OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ // : CDR AND RX EQUALIZATION SETTINGS
+ /*Register : L3_TM_CDR5 @ 0XFD40DC14
+
+ FPHL FSM accumulate cycles
+ PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7
+
+ FFL Phase0 int gain aka 2ol SD update rate
+ PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6
+
+ Fast phase lock controls -- FSM accumulator cycle control and phase 0 int gain control.
+ (OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U)
+ RegMask = (SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK | SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK | 0 );
+
+ RegVal = ((0x00000007U << SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT
+ | 0x00000006U << SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_CDR5_OFFSET ,0x000000FFU ,0x000000E6U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_CDR16 @ 0XFD40DC40
+
+ FFL Phase0 prop gain aka 1ol SD update rate
+ PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC
- Override enable/disable of DP post2 path
- PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1
+ Fast phase lock controls -- phase 0 prop gain
+ (OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU)
+ RegMask = (SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK | 0 );
- Override enable/disable of DP post1 path
- PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1
+ RegVal = ((0x0000000CU << SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_CDR16_OFFSET ,0x0000001FU ,0x0000000CU);
+ /*############################################################################################################################ */
- Enable/disable DP main path
- PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1
+ /*Register : L3_TM_EQ0 @ 0XFD40D94C
- Override enable/disable of DP main path
- PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1
+ EQ stg 2 controls BYPASSED
+ PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1
- Post or pre or main DP path selection
- (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U)
- RegMask = (SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK | 0 );
+ eq stg1 and stg2 controls
+ (OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U)
+ RegMask = (SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
- | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
- | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
- | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
- | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U);
+ PSU_Mask_Write (SERDES_L3_TM_EQ0_OFFSET ,0x00000020U ,0x00000020U);
/*############################################################################################################################ */
- /*Register : L1_TX_ANA_TM_118 @ 0XFD4041D8
+ /*Register : L3_TM_EQ1 @ 0XFD40D950
- Test register force for enabling/disablign TX deemphasis bits <17:0>
- PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
+ EQ STG2 RL PROG
+ PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2
- Enable Override of TX deemphasis
- (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U)
- RegMask = (SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 );
+ EQ stg 2 preamp mode val
+ PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1
- RegVal = ((0x00000001U << SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
+ eq stg1 and stg2 controls
+ (OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U)
+ RegMask = (SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK | SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK | 0 );
+
+ RegVal = ((0x00000002U << SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT
+ | 0x00000001U << SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
+ PSU_Mask_Write (SERDES_L3_TM_EQ1_OFFSET ,0x00000007U ,0x00000006U);
/*############################################################################################################################ */
+ // : GEM SERDES SETTINGS
// : ENABLE PRE EMPHAIS AND VOLTAGE SWING
/*Register : L1_TXPMD_TM_48 @ 0XFD404CC0
@@ -17827,6 +19266,20 @@ unsigned long psu_serdes_init_data() {
PSU_Mask_Write (SERDES_L1_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000000U);
/*############################################################################################################################ */
+ /*Register : L3_TX_ANA_TM_18 @ 0XFD40C048
+
+ pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
+ PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1
+
+ Override for PIPE TX de-emphasis
+ (OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U)
+ RegMask = (SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000001U);
+ /*############################################################################################################################ */
+
return 1;
}
@@ -17862,6 +19315,20 @@ unsigned long psu_resetout_init_data() {
PSU_Mask_Write (USB3_0_FPD_POWER_PRSNT_OFFSET ,0x00000001U ,0x00000001U);
/*############################################################################################################################ */
+ /*Register : fpd_pipe_clk @ 0XFF9D007C
+
+ This bit is used to choose between PIPE clock coming from SerDes and the suspend clk
+ PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0
+
+ fpd_pipe_clk
+ (OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U)
+ RegMask = (USB3_0_FPD_PIPE_CLK_OPTION_MASK | 0 );
+
+ RegVal = ((0x00000000U << USB3_0_FPD_PIPE_CLK_OPTION_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (USB3_0_FPD_PIPE_CLK_OFFSET ,0x00000001U ,0x00000000U);
+ /*############################################################################################################################ */
+
// :
/*Register : RST_LPD_TOP @ 0XFF5E023C
@@ -17925,27 +19392,23 @@ unsigned long psu_resetout_init_data() {
PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000000U);
/*############################################################################################################################ */
- // : PUTTING PCIE IN RESET
+ // : PUTTING PCIE CFG AND BRIDGE IN RESET
/*Register : RST_FPD_TOP @ 0XFD1A0100
PCIE config reset
PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0
- PCIE control block level reset
- PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0
-
PCIE bridge block level reset (AXI interface)
PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0
FPD Block level software controlled reset
- (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x00000000U)
- RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | 0 );
+ (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U)
+ RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | 0 );
RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
- | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
| 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000E0000U ,0x00000000U);
+ PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000C0000U ,0x00000000U);
/*############################################################################################################################ */
// : PUTTING DP IN RESET
@@ -18001,7 +19464,7 @@ unsigned long psu_resetout_init_data() {
. The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger
alue. Note: This field is valid only in device mode.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0X9
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9
Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
@@ -18009,7 +19472,7 @@ unsigned long psu_resetout_init_data() {
ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
ng hibernation. - This bit is valid only in device mode.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0X0
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0
Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
_n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
@@ -18018,42 +19481,33 @@ unsigned long psu_resetout_init_data() {
n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
d.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0X0
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0
USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. -
'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0X0
-
- Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
- figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
- ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
- r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
- t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
- g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
- when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0X1
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0
Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0X0
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0
ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
lected through DWC_USB3_HSPHY_INTERFACE.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0X1
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1
PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same
lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0X0
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0
HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for
@@ -18063,25 +19517,24 @@ unsigned long psu_resetout_init_data() {
ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times
- PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0X7
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7
Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either
he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple
ented.
- (OFFSET, MASK, VALUE) (0XFE20C200, 0x00003FFFU ,0x00002457U)
- RegMask = (USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK | USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK | USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK | USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK | USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK | USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK | 0 );
+ (OFFSET, MASK, VALUE) (0XFE20C200, 0x00003FBFU ,0x00002417U)
+ RegMask = (USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK | USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK | USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK | USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK | USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK | 0 );
RegVal = ((0x00000009U << USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT
| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT
| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT
| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT
- | 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT
| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT
| 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT
| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT
| 0x00000007U << USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (USB3_0_XHCI_GUSB2PHYCFG_OFFSET ,0x00003FFFU ,0x00002457U);
+ PSU_Mask_Write (USB3_0_XHCI_GUSB2PHYCFG_OFFSET ,0x00003FBFU ,0x00002417U);
/*############################################################################################################################ */
/*Register : GFLADJ @ 0XFE20C630
@@ -18095,7 +19548,7 @@ unsigned long psu_resetout_init_data() {
uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)
- PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0X0
+ PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0
Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res
ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio
@@ -18107,64 +19560,9 @@ unsigned long psu_resetout_init_data() {
RegVal = ((0x00000000U << USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT
| 0 ) & RegMask); */
PSU_Mask_Write (USB3_0_XHCI_GFLADJ_OFFSET ,0x003FFF00U ,0x00000000U);
- /*############################################################################################################################ */
-
- // : CHECK PLL LOCK FOR LANE0
- /*Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4
-
- Status Read value of PLL Lock
- PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
- (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U) */
- mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET,0x00000010U);
-
- /*############################################################################################################################ */
-
- // : CHECK PLL LOCK FOR LANE1
- /*Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4
-
- Status Read value of PLL Lock
- PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
- (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U) */
- mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET,0x00000010U);
-
- /*############################################################################################################################ */
-
- // : CHECK PLL LOCK FOR LANE2
- /*Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4
-
- Status Read value of PLL Lock
- PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
- (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U) */
- mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET,0x00000010U);
-
- /*############################################################################################################################ */
-
- // : CHECK PLL LOCK FOR LANE3
- /*Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4
-
- Status Read value of PLL Lock
- PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
- (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U) */
- mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET,0x00000010U);
-
/*############################################################################################################################ */
// : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON.
- /*Register : ATTR_37 @ 0XFD480094
-
- Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
- gister.; EP=0x0001; RP=0x0001
- PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0X1
-
- ATTR_37
- (OFFSET, MASK, VALUE) (0XFD480094, 0x00004000U ,0x00004000U)
- RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK | 0 );
-
- RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00004000U ,0x00004000U);
- /*############################################################################################################################ */
-
/*Register : ATTR_25 @ 0XFD480064
If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
@@ -18696,13 +20094,18 @@ unsigned long psu_resetout_init_data() {
Required for Root.; EP=0x0000; RP=0x0001
PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1
+ Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
+ gister.; EP=0x0001; RP=0x0001
+ PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1
+
ATTR_37
- (OFFSET, MASK, VALUE) (0XFD480094, 0x00000200U ,0x00000200U)
- RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK | 0 );
+ (OFFSET, MASK, VALUE) (0XFD480094, 0x00004200U ,0x00004200U)
+ RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK | PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK | 0 );
RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT
+ | 0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00000200U ,0x00000200U);
+ PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00004200U ,0x00004200U);
/*############################################################################################################################ */
/*Register : ATTR_93 @ 0XFD480174
@@ -18876,6 +20279,271 @@ unsigned long psu_resetout_init_data() {
PSU_Mask_Write (PCIE_ATTRIB_ATTR_43_OFFSET ,0x00000100U ,0x00000000U);
/*############################################################################################################################ */
+ /*Register : ATTR_48 @ 0XFD4800C0
+
+ MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note
+ hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000
+ PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0
+
+ ATTR_48
+ (OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U)
+ RegMask = (PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK | 0 );
+
+ RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (PCIE_ATTRIB_ATTR_48_OFFSET ,0x000007FFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : ATTR_46 @ 0XFD4800B8
+
+ MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001;
+ P=0x0000
+ PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0
+
+ ATTR_46
+ (OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U)
+ RegMask = (PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK | 0 );
+
+ RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (PCIE_ATTRIB_ATTR_46_OFFSET ,0x0000FFFFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : ATTR_47 @ 0XFD4800BC
+
+ MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000;
+ P=0x0000
+ PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0
+
+ ATTR_47
+ (OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U)
+ RegMask = (PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK | 0 );
+
+ RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (PCIE_ATTRIB_ATTR_47_OFFSET ,0x00001FFFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : ATTR_44 @ 0XFD4800B0
+
+ MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
+ 0x0001; RP=0x0000
+ PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0
+
+ ATTR_44
+ (OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U)
+ RegMask = (PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK | 0 );
+
+ RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (PCIE_ATTRIB_ATTR_44_OFFSET ,0x0000FFFFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : ATTR_45 @ 0XFD4800B4
+
+ MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
+ 0x1000; RP=0x0000
+ PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0
+
+ ATTR_45
+ (OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U)
+ RegMask = (PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK | 0 );
+
+ RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (PCIE_ATTRIB_ATTR_45_OFFSET ,0x0000FFF8U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : CB @ 0XFD48031C
+
+ DT837748 Enable
+ PSU_PCIE_ATTRIB_CB_CB1 0x0
+
+ ECO Register 1
+ (OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U)
+ RegMask = (PCIE_ATTRIB_CB_CB1_MASK | 0 );
+
+ RegVal = ((0x00000000U << PCIE_ATTRIB_CB_CB1_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (PCIE_ATTRIB_CB_OFFSET ,0x00000002U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : ATTR_35 @ 0XFD48008C
+
+ Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc
+ ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001
+ PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0
+
+ ATTR_35
+ (OFFSET, MASK, VALUE) (0XFD48008C, 0x00003000U ,0x00000000U)
+ RegMask = (PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK | 0 );
+
+ RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (PCIE_ATTRIB_ATTR_35_OFFSET ,0x00003000U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ // : PUTTING PCIE CONTROL IN RESET
+ /*Register : RST_FPD_TOP @ 0XFD1A0100
+
+ PCIE control block level reset
+ PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0
+
+ FPD Block level software controlled reset
+ (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U)
+ RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | 0 );
+
+ RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00020000U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ // : CHECK PLL LOCK FOR LANE0
+ /*Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4
+
+ Status Read value of PLL Lock
+ PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
+ (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U) */
+ mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+
+ /*############################################################################################################################ */
+
+ // : CHECK PLL LOCK FOR LANE1
+ /*Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4
+
+ Status Read value of PLL Lock
+ PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
+ (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U) */
+ mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+
+ /*############################################################################################################################ */
+
+ // : CHECK PLL LOCK FOR LANE2
+ /*Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4
+
+ Status Read value of PLL Lock
+ PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
+ (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U) */
+ mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+
+ /*############################################################################################################################ */
+
+ // : CHECK PLL LOCK FOR LANE3
+ /*Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4
+
+ Status Read value of PLL Lock
+ PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
+ (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U) */
+ mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+
+ /*############################################################################################################################ */
+
+ // : SATA AHCI VENDOR SETTING
+ /*Register : PP2C @ 0XFD0C00AC
+
+ CIBGMN: COMINIT Burst Gap Minimum.
+ PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18
+
+ CIBGMX: COMINIT Burst Gap Maximum.
+ PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40
+
+ CIBGN: COMINIT Burst Gap Nominal.
+ PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18
+
+ CINMP: COMINIT Negate Minimum Period.
+ PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28
+
+ PP2C - Port Phy2Cfg Register. This register controls the configuration of the Phy Control OOB timing for the COMINIT paramete
+ s for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
+ (OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U)
+ RegMask = (SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK | SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK | SATA_AHCI_VENDOR_PP2C_CIBGN_MASK | SATA_AHCI_VENDOR_PP2C_CINMP_MASK | 0 );
+
+ RegVal = ((0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT
+ | 0x00000040U << SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT
+ | 0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT
+ | 0x00000028U << SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SATA_AHCI_VENDOR_PP2C_OFFSET ,0xFFFFFFFFU ,0x28184018U);
+ /*############################################################################################################################ */
+
+ /*Register : PP3C @ 0XFD0C00B0
+
+ CWBGMN: COMWAKE Burst Gap Minimum.
+ PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06
+
+ CWBGMX: COMWAKE Burst Gap Maximum.
+ PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14
+
+ CWBGN: COMWAKE Burst Gap Nominal.
+ PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08
+
+ CWNMP: COMWAKE Negate Minimum Period.
+ PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E
+
+ PP3C - Port Phy3CfgRegister. This register controls the configuration of the Phy Control OOB timing for the COMWAKE parameter
+ for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
+ (OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U)
+ RegMask = (SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK | SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK | SATA_AHCI_VENDOR_PP3C_CWBGN_MASK | SATA_AHCI_VENDOR_PP3C_CWNMP_MASK | 0 );
+
+ RegVal = ((0x00000006U << SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT
+ | 0x00000014U << SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT
+ | 0x00000008U << SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT
+ | 0x0000000EU << SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SATA_AHCI_VENDOR_PP3C_OFFSET ,0xFFFFFFFFU ,0x0E081406U);
+ /*############################################################################################################################ */
+
+ /*Register : PP4C @ 0XFD0C00B4
+
+ BMX: COM Burst Maximum.
+ PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13
+
+ BNM: COM Burst Nominal.
+ PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08
+
+ SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det
+ rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa
+ Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of
+ 500ns based on a 150MHz PMCLK.
+ PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A
+
+ PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th
+ value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128
+ PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06
+
+ PP4C - Port Phy4Cfg Register. This register controls the configuration of the Phy Control Burst timing for the COM parameters
+ for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
+ (OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U)
+ RegMask = (SATA_AHCI_VENDOR_PP4C_BMX_MASK | SATA_AHCI_VENDOR_PP4C_BNM_MASK | SATA_AHCI_VENDOR_PP4C_SFD_MASK | SATA_AHCI_VENDOR_PP4C_PTST_MASK | 0 );
+
+ RegVal = ((0x00000013U << SATA_AHCI_VENDOR_PP4C_BMX_SHIFT
+ | 0x00000008U << SATA_AHCI_VENDOR_PP4C_BNM_SHIFT
+ | 0x0000004AU << SATA_AHCI_VENDOR_PP4C_SFD_SHIFT
+ | 0x00000006U << SATA_AHCI_VENDOR_PP4C_PTST_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SATA_AHCI_VENDOR_PP4C_OFFSET ,0xFFFFFFFFU ,0x064A0813U);
+ /*############################################################################################################################ */
+
+ /*Register : PP5C @ 0XFD0C00B8
+
+ RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed.
+ PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4
+
+ RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha
+ completed, for a fast SERDES it is suggested that this value be 54.2us / 4
+ PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF
+
+ PP5C - Port Phy5Cfg Register. This register controls the configuration of the Phy Control Retry Interval timing for either Po
+ t 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
+ (OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U)
+ RegMask = (SATA_AHCI_VENDOR_PP5C_RIT_MASK | SATA_AHCI_VENDOR_PP5C_RCT_MASK | 0 );
+
+ RegVal = ((0x000C96A4U << SATA_AHCI_VENDOR_PP5C_RIT_SHIFT
+ | 0x000003FFU << SATA_AHCI_VENDOR_PP5C_RCT_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SATA_AHCI_VENDOR_PP5C_OFFSET ,0xFFFFFFFFU ,0x3FFC96A4U);
+ /*############################################################################################################################ */
+
return 1;
}
@@ -19152,12 +20820,23 @@ unsigned long psu_ddr_phybringup_data() {
unsigned int regval = 0;
- Xil_Out32(0xFD090000U, 0x0000A845U);
- Xil_Out32(0xFD090004U, 0x003FFFFFU);
- Xil_Out32(0xFD09000CU, 0x00000010U);
- Xil_Out32(0xFD090010U, 0x00000010U);
+ int dpll_divisor;
+ dpll_divisor = (Xil_In32(0xFD1A0080U) & 0x00003F00U) >> 0x00000008U;
+ prog_reg (0xFD1A0080U, 0x00003F00U, 0x00000008U, 0x00000005U);
+ prog_reg (0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
+ Xil_Out32(0xFD080004U, 0x00040003U);
+ while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U);
+ prog_reg (0xFD080684U, 0x06000000U, 0x00000019U, 0x00000001U);
+ prog_reg (0xFD0806A4U, 0x06000000U, 0x00000019U, 0x00000001U);
+ prog_reg (0xFD0806C4U, 0x06000000U, 0x00000019U, 0x00000001U);
+ prog_reg (0xFD0806E4U, 0x06000000U, 0x00000019U, 0x00000001U);
+ prog_reg (0xFD1A0080, 0x3F00, 0x8, dpll_divisor);
+ Xil_Out32(0xFD080004U, 0x40040071U);
+ while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U);
+ Xil_Out32(0xFD080004U, 0x40040001U);
+ while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U);
// PHY BRINGUP SEQ
- while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000000FU);
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU);
prog_reg (0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
//poll for PHY initialization to complete
while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU);
@@ -19174,14 +20853,14 @@ unsigned long psu_ddr_phybringup_data() {
// Run Vref training in static read mode
- Xil_Out32(0xFD080200U, 0x110011C7U);
+ Xil_Out32(0xFD080200U, 0x100091C7U);
Xil_Out32(0xFD080018U, 0x00F01EF2U);
- Xil_Out32(0xFD08001CU, 0x55AA0098U);
- Xil_Out32(0xFD08142CU, 0x00001830U);
- Xil_Out32(0xFD08146CU, 0x00001830U);
- Xil_Out32(0xFD0814ACU, 0x00001830U);
- Xil_Out32(0xFD0814ECU, 0x00001830U);
- Xil_Out32(0xFD08152CU, 0x00001830U);
+ Xil_Out32(0xFD08001CU, 0x55AA5498U);
+ Xil_Out32(0xFD08142CU, 0x00041830U);
+ Xil_Out32(0xFD08146CU, 0x00041830U);
+ Xil_Out32(0xFD0814ACU, 0x00041830U);
+ Xil_Out32(0xFD0814ECU, 0x00041830U);
+ Xil_Out32(0xFD08152CU, 0x00041830U);
Xil_Out32(0xFD080004, 0x00060001); //PUB_PIR
@@ -19191,14 +20870,22 @@ unsigned long psu_ddr_phybringup_data() {
}
// Vref training is complete, disabling static read mode
- Xil_Out32(0xFD080200U, 0x810011C7U);
+ Xil_Out32(0xFD080200U, 0x800091C7U);
Xil_Out32(0xFD080018U, 0x00F12302U);
- Xil_Out32(0xFD08001CU, 0x55AA0080U);
- Xil_Out32(0xFD08142CU, 0x00001800U);
- Xil_Out32(0xFD08146CU, 0x00001800U);
- Xil_Out32(0xFD0814ACU, 0x00001800U);
- Xil_Out32(0xFD0814ECU, 0x00001800U);
- Xil_Out32(0xFD08152CU, 0x00001800U);
+ Xil_Out32(0xFD08001CU, 0x55AA5480U);
+ Xil_Out32(0xFD08142CU, 0x00041800U);
+ Xil_Out32(0xFD08146CU, 0x00041800U);
+ Xil_Out32(0xFD0814ACU, 0x00041800U);
+ Xil_Out32(0xFD0814ECU, 0x00041800U);
+ Xil_Out32(0xFD08152CU, 0x00041800U);
+
+
+ Xil_Out32(0xFD080004, 0x0000C001); //PUB_PIR
+ regval = Xil_In32(0xFD080030); //PUB_PGSR0
+ while((regval & 0x80000C01) != 0x80000C01){
+ regval = Xil_In32(0xFD080030); //PUB_PGSR0
+ }
+
Xil_Out32(0xFD070180U, 0x01000040U);
Xil_Out32(0xFD070060U, 0x00000000U);
prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
@@ -19228,7 +20915,7 @@ return 1;
int mask_pollOnValue(u32 add , u32 mask, u32 value ) {
- volatile u32 *addr = (volatile u32*) add;
+ volatile u32 *addr = (volatile u32*)(unsigned long) add;
int i = 0;
while ((*addr & mask)!= value) {
if (i == PSU_MASK_POLL_TIME) {
@@ -19241,7 +20928,7 @@ int mask_pollOnValue(u32 add , u32 mask, u32 value ) {
}
int mask_poll(u32 add , u32 mask) {
- volatile u32 *addr = (volatile u32*) add;
+ volatile u32 *addr = (volatile u32*)(unsigned long) add;
int i = 0;
while (!(*addr & mask)) {
if (i == PSU_MASK_POLL_TIME) {
@@ -19258,7 +20945,7 @@ void mask_delay(u32 delay) {
}
u32 mask_read(u32 add , u32 mask ) {
- volatile u32 *addr = (volatile u32*) add;
+ volatile u32 *addr = (volatile u32*)(unsigned long) add;
u32 val = (*addr & mask);
//xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
return val;
@@ -19370,6 +21057,58 @@ void init_peripheral()
tmp_regval &= ~0x00000001;
Xil_Out32(0xFD690030, tmp_regval);
}
+
+int psu_init_xppu_aper_ram() {
+ unsigned long APER_OFFSET = 0xFF981000;
+ int i = 0;
+ for (; i <= 400; i++) {
+ PSU_Mask_Write (APER_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ APER_OFFSET = APER_OFFSET + 0x4;
+ }
+
+ return 0;
+}
+
+int psu_lpd_protection() {
+ psu_init_xppu_aper_ram();
+ psu_lpd_xppu_data();
+ return 0;
+}
+
+int psu_ddr_protection() {
+ psu_ddr_xmpu0_data();
+ psu_ddr_xmpu1_data();
+ psu_ddr_xmpu2_data();
+ psu_ddr_xmpu3_data();
+ psu_ddr_xmpu4_data();
+ psu_ddr_xmpu5_data();
+ return 0;
+}
+int psu_ocm_protection() {
+ psu_ocm_xmpu_data();
+ return 0;
+}
+
+int psu_fpd_protection() {
+ psu_fpd_xmpu_data();
+ return 0;
+}
+
+int psu_protection_lock() {
+ psu_protection_lock_data();
+ return 0;
+}
+
+int psu_protection() {
+ psu_ddr_protection();
+ psu_ocm_protection();
+ psu_fpd_protection();
+ psu_lpd_protection();
+ return 0;
+}
+
+
+
int
psu_init()
{
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h
index 97a2ae16d..e9741eb2f 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h
@@ -784,26 +784,14 @@
#define CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL 0x00000000
#define CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT 0
#define CRF_APB_VPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU
-#undef CRL_APB_GEM0_REF_CTRL_OFFSET
-#define CRL_APB_GEM0_REF_CTRL_OFFSET 0XFF5E0050
-#undef CRL_APB_GEM1_REF_CTRL_OFFSET
-#define CRL_APB_GEM1_REF_CTRL_OFFSET 0XFF5E0054
-#undef CRL_APB_GEM2_REF_CTRL_OFFSET
-#define CRL_APB_GEM2_REF_CTRL_OFFSET 0XFF5E0058
#undef CRL_APB_GEM3_REF_CTRL_OFFSET
#define CRL_APB_GEM3_REF_CTRL_OFFSET 0XFF5E005C
-#undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET
-#define CRL_APB_GEM_TSU_REF_CTRL_OFFSET 0XFF5E0100
#undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET
#define CRL_APB_USB0_BUS_REF_CTRL_OFFSET 0XFF5E0060
-#undef CRL_APB_USB1_BUS_REF_CTRL_OFFSET
-#define CRL_APB_USB1_BUS_REF_CTRL_OFFSET 0XFF5E0064
#undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET
#define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 0XFF5E004C
#undef CRL_APB_QSPI_REF_CTRL_OFFSET
#define CRL_APB_QSPI_REF_CTRL_OFFSET 0XFF5E0068
-#undef CRL_APB_SDIO0_REF_CTRL_OFFSET
-#define CRL_APB_SDIO0_REF_CTRL_OFFSET 0XFF5E006C
#undef CRL_APB_SDIO1_REF_CTRL_OFFSET
#define CRL_APB_SDIO1_REF_CTRL_OFFSET 0XFF5E0070
#undef IOU_SLCR_SDIO_CLK_CTRL_OFFSET
@@ -816,20 +804,12 @@
#define CRL_APB_I2C0_REF_CTRL_OFFSET 0XFF5E0120
#undef CRL_APB_I2C1_REF_CTRL_OFFSET
#define CRL_APB_I2C1_REF_CTRL_OFFSET 0XFF5E0124
-#undef CRL_APB_SPI0_REF_CTRL_OFFSET
-#define CRL_APB_SPI0_REF_CTRL_OFFSET 0XFF5E007C
-#undef CRL_APB_SPI1_REF_CTRL_OFFSET
-#define CRL_APB_SPI1_REF_CTRL_OFFSET 0XFF5E0080
-#undef CRL_APB_CAN0_REF_CTRL_OFFSET
-#define CRL_APB_CAN0_REF_CTRL_OFFSET 0XFF5E0084
#undef CRL_APB_CAN1_REF_CTRL_OFFSET
#define CRL_APB_CAN1_REF_CTRL_OFFSET 0XFF5E0088
#undef CRL_APB_CPU_R5_CTRL_OFFSET
#define CRL_APB_CPU_R5_CTRL_OFFSET 0XFF5E0090
#undef CRL_APB_IOU_SWITCH_CTRL_OFFSET
#define CRL_APB_IOU_SWITCH_CTRL_OFFSET 0XFF5E009C
-#undef CRL_APB_CSU_PLL_CTRL_OFFSET
-#define CRL_APB_CSU_PLL_CTRL_OFFSET 0XFF5E00A0
#undef CRL_APB_PCAP_CTRL_OFFSET
#define CRL_APB_PCAP_CTRL_OFFSET 0XFF5E00A4
#undef CRL_APB_LPD_SWITCH_CTRL_OFFSET
@@ -838,8 +818,6 @@
#define CRL_APB_LPD_LSBUS_CTRL_OFFSET 0XFF5E00AC
#undef CRL_APB_DBG_LPD_CTRL_OFFSET
#define CRL_APB_DBG_LPD_CTRL_OFFSET 0XFF5E00B0
-#undef CRL_APB_NAND_REF_CTRL_OFFSET
-#define CRL_APB_NAND_REF_CTRL_OFFSET 0XFF5E00B4
#undef CRL_APB_ADMA_REF_CTRL_OFFSET
#define CRL_APB_ADMA_REF_CTRL_OFFSET 0XFF5E00B8
#undef CRL_APB_PL0_REF_CTRL_OFFSET
@@ -884,8 +862,6 @@
#define CRF_APB_TOPSW_MAIN_CTRL_OFFSET 0XFD1A00C0
#undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET
#define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 0XFD1A00C4
-#undef CRF_APB_GTGREF0_REF_CTRL_OFFSET
-#define CRF_APB_GTGREF0_REF_CTRL_OFFSET 0XFD1A00C8
#undef CRF_APB_DBG_TSTMP_CTRL_OFFSET
#define CRF_APB_DBG_TSTMP_CTRL_OFFSET 0XFD1A00F8
#undef IOU_SLCR_IOU_TTC_APB_CLK_OFFSET
@@ -897,129 +873,6 @@
#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET
#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 0XFF410050
-/*Clock active for the RX channel*/
-#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL
-#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT
-#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK
-#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500
-#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT 26
-#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK 0x04000000U
-
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_GEM0_REF_CTRL_CLKACT_MASK
-#define CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL 0x00002500
-#define CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT 25
-#define CRL_APB_GEM0_REF_CTRL_CLKACT_MASK 0x02000000U
-
-/*6 bit divider*/
-#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL 0x00002500
-#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL 0x00002500
-#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL 0x00002500
-#define CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK 0x00000007U
-
-/*Clock active for the RX channel*/
-#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL
-#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT
-#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK
-#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500
-#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT 26
-#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK 0x04000000U
-
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_GEM1_REF_CTRL_CLKACT_MASK
-#define CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL 0x00002500
-#define CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT 25
-#define CRL_APB_GEM1_REF_CTRL_CLKACT_MASK 0x02000000U
-
-/*6 bit divider*/
-#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL 0x00002500
-#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL 0x00002500
-#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL 0x00002500
-#define CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK 0x00000007U
-
-/*Clock active for the RX channel*/
-#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL
-#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT
-#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK
-#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500
-#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT 26
-#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK 0x04000000U
-
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_GEM2_REF_CTRL_CLKACT_MASK
-#define CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL 0x00002500
-#define CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT 25
-#define CRL_APB_GEM2_REF_CTRL_CLKACT_MASK 0x02000000U
-
-/*6 bit divider*/
-#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL 0x00002500
-#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL 0x00002500
-#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL 0x00002500
-#define CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK 0x00000007U
-
/*Clock active for the RX channel*/
#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL
#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT
@@ -1061,39 +914,6 @@
#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U
-/*6 bit divider*/
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 0x00051000
-#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 0x00051000
-#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 0x00000007U
-
-/*6 bit divider*/
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 0x00051000
-#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK
-#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 0x00051000
-#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 24
-#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 0x01000000U
-
/*Clock active signal. Switch to 0 to disable the clock*/
#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL
#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT
@@ -1127,39 +947,6 @@
#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK
-#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000
-#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT 25
-#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK 0x02000000U
-
-/*6 bit divider*/
-#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
-#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
-#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000
-#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U
-
/*Clock active signal. Switch to 0 to disable the clock*/
#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL
#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT
@@ -1226,39 +1013,6 @@
#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK
-#define CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL 0x01000F00
-#define CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT 24
-#define CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK 0x01000000U
-
-/*6 bit divider*/
-#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00
-#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00
-#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL 0x01000F00
-#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK 0x00000007U
-
/*Clock active signal. Switch to 0 to disable the clock*/
#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL
#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT
@@ -1432,105 +1186,6 @@
#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_SPI0_REF_CTRL_CLKACT_MASK
-#define CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL 0x01001800
-#define CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT 24
-#define CRL_APB_SPI0_REF_CTRL_CLKACT_MASK 0x01000000U
-
-/*6 bit divider*/
-#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
-#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
-#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL 0x01001800
-#define CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK 0x00000007U
-
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_SPI1_REF_CTRL_CLKACT_MASK
-#define CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL 0x01001800
-#define CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT 24
-#define CRL_APB_SPI1_REF_CTRL_CLKACT_MASK 0x01000000U
-
-/*6 bit divider*/
-#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
-#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
-#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL 0x01001800
-#define CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK 0x00000007U
-
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_CAN0_REF_CTRL_CLKACT_MASK
-#define CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL 0x01001800
-#define CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT 24
-#define CRL_APB_CAN0_REF_CTRL_CLKACT_MASK 0x01000000U
-
-/*6 bit divider*/
-#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
-#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
-#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL 0x01001800
-#define CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK 0x00000007U
-
/*Clock active signal. Switch to 0 to disable the clock*/
#undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL
#undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT
@@ -1615,31 +1270,6 @@
#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_CSU_PLL_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT
-#undef CRL_APB_CSU_PLL_CTRL_CLKACT_MASK
-#define CRL_APB_CSU_PLL_CTRL_CLKACT_DEFVAL 0x01001500
-#define CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT 24
-#define CRL_APB_CSU_PLL_CTRL_CLKACT_MASK 0x01000000U
-
-/*6 bit divider*/
-#undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK
-#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_DEFVAL 0x01001500
-#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_CSU_PLL_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK
-#define CRL_APB_CSU_PLL_CTRL_SRCSEL_DEFVAL 0x01001500
-#define CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK 0x00000007U
-
/*Clock active signal. Switch to 0 to disable the clock*/
#undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL
#undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT
@@ -1740,39 +1370,6 @@
#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_NAND_REF_CTRL_CLKACT_MASK
-#define CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL 0x00052000
-#define CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT 24
-#define CRL_APB_NAND_REF_CTRL_CLKACT_MASK 0x01000000U
-
-/*6 bit divider*/
-#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
-#define CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
-#define CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_NAND_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL 0x00052000
-#define CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_NAND_REF_CTRL_SRCSEL_MASK 0x00000007U
-
/*Clock active signal. Switch to 0 to disable the clock*/
#undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL
#undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT
@@ -2388,31 +1985,6 @@
#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24
#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U
-/*6 bit divider*/
-#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT
-#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK
-#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL 0x00000800
-#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
- he new clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL
-#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT
-#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK
-#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL 0x00000800
-#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT 0
-#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK 0x00000007U
-
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL
-#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT
-#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK
-#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL 0x00000800
-#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT 24
-#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK 0x01000000U
-
/*6 bit divider*/
#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL
#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT
@@ -2714,6 +2286,8 @@
#define DDR_PHY_PGCR0_OFFSET 0XFD080010
#undef DDR_PHY_PGCR2_OFFSET
#define DDR_PHY_PGCR2_OFFSET 0XFD080018
+#undef DDR_PHY_PGCR3_OFFSET
+#define DDR_PHY_PGCR3_OFFSET 0XFD08001C
#undef DDR_PHY_PGCR5_OFFSET
#define DDR_PHY_PGCR5_OFFSET 0XFD080024
#undef DDR_PHY_PTR0_OFFSET
@@ -2742,6 +2316,8 @@
#define DDR_PHY_RDIMMGCR0_OFFSET 0XFD080140
#undef DDR_PHY_RDIMMGCR1_OFFSET
#define DDR_PHY_RDIMMGCR1_OFFSET 0XFD080144
+#undef DDR_PHY_RDIMMCR0_OFFSET
+#define DDR_PHY_RDIMMCR0_OFFSET 0XFD080150
#undef DDR_PHY_RDIMMCR1_OFFSET
#define DDR_PHY_RDIMMCR1_OFFSET 0XFD080154
#undef DDR_PHY_MR0_OFFSET
@@ -2774,6 +2350,8 @@
#define DDR_PHY_DTCR1_OFFSET 0XFD080204
#undef DDR_PHY_CATR0_OFFSET
#define DDR_PHY_CATR0_OFFSET 0XFD080240
+#undef DDR_PHY_BISTLSR_OFFSET
+#define DDR_PHY_BISTLSR_OFFSET 0XFD080414
#undef DDR_PHY_RIOCR5_OFFSET
#define DDR_PHY_RIOCR5_OFFSET 0XFD0804F4
#undef DDR_PHY_ACIOCR0_OFFSET
@@ -2790,12 +2368,18 @@
#define DDR_PHY_VTCR0_OFFSET 0XFD080528
#undef DDR_PHY_VTCR1_OFFSET
#define DDR_PHY_VTCR1_OFFSET 0XFD08052C
+#undef DDR_PHY_ACBDLR1_OFFSET
+#define DDR_PHY_ACBDLR1_OFFSET 0XFD080544
+#undef DDR_PHY_ACBDLR2_OFFSET
+#define DDR_PHY_ACBDLR2_OFFSET 0XFD080548
#undef DDR_PHY_ACBDLR6_OFFSET
#define DDR_PHY_ACBDLR6_OFFSET 0XFD080558
#undef DDR_PHY_ACBDLR7_OFFSET
#define DDR_PHY_ACBDLR7_OFFSET 0XFD08055C
#undef DDR_PHY_ACBDLR8_OFFSET
#define DDR_PHY_ACBDLR8_OFFSET 0XFD080560
+#undef DDR_PHY_ACBDLR9_OFFSET
+#define DDR_PHY_ACBDLR9_OFFSET 0XFD080564
#undef DDR_PHY_ZQCR_OFFSET
#define DDR_PHY_ZQCR_OFFSET 0XFD080680
#undef DDR_PHY_ZQ0PR0_OFFSET
@@ -2928,30 +2512,40 @@
#define DDR_PHY_DX8LCDLR2_OFFSET 0XFD080F88
#undef DDR_PHY_DX8GTR0_OFFSET
#define DDR_PHY_DX8GTR0_OFFSET 0XFD080FC0
+#undef DDR_PHY_DX8SL0OSC_OFFSET
+#define DDR_PHY_DX8SL0OSC_OFFSET 0XFD081400
#undef DDR_PHY_DX8SL0DQSCTL_OFFSET
#define DDR_PHY_DX8SL0DQSCTL_OFFSET 0XFD08141C
#undef DDR_PHY_DX8SL0DXCTL2_OFFSET
#define DDR_PHY_DX8SL0DXCTL2_OFFSET 0XFD08142C
#undef DDR_PHY_DX8SL0IOCR_OFFSET
#define DDR_PHY_DX8SL0IOCR_OFFSET 0XFD081430
+#undef DDR_PHY_DX8SL1OSC_OFFSET
+#define DDR_PHY_DX8SL1OSC_OFFSET 0XFD081440
#undef DDR_PHY_DX8SL1DQSCTL_OFFSET
#define DDR_PHY_DX8SL1DQSCTL_OFFSET 0XFD08145C
#undef DDR_PHY_DX8SL1DXCTL2_OFFSET
#define DDR_PHY_DX8SL1DXCTL2_OFFSET 0XFD08146C
#undef DDR_PHY_DX8SL1IOCR_OFFSET
#define DDR_PHY_DX8SL1IOCR_OFFSET 0XFD081470
+#undef DDR_PHY_DX8SL2OSC_OFFSET
+#define DDR_PHY_DX8SL2OSC_OFFSET 0XFD081480
#undef DDR_PHY_DX8SL2DQSCTL_OFFSET
#define DDR_PHY_DX8SL2DQSCTL_OFFSET 0XFD08149C
#undef DDR_PHY_DX8SL2DXCTL2_OFFSET
#define DDR_PHY_DX8SL2DXCTL2_OFFSET 0XFD0814AC
#undef DDR_PHY_DX8SL2IOCR_OFFSET
#define DDR_PHY_DX8SL2IOCR_OFFSET 0XFD0814B0
+#undef DDR_PHY_DX8SL3OSC_OFFSET
+#define DDR_PHY_DX8SL3OSC_OFFSET 0XFD0814C0
#undef DDR_PHY_DX8SL3DQSCTL_OFFSET
#define DDR_PHY_DX8SL3DQSCTL_OFFSET 0XFD0814DC
#undef DDR_PHY_DX8SL3DXCTL2_OFFSET
#define DDR_PHY_DX8SL3DXCTL2_OFFSET 0XFD0814EC
#undef DDR_PHY_DX8SL3IOCR_OFFSET
#define DDR_PHY_DX8SL3IOCR_OFFSET 0XFD0814F0
+#undef DDR_PHY_DX8SL4OSC_OFFSET
+#define DDR_PHY_DX8SL4OSC_OFFSET 0XFD081500
#undef DDR_PHY_DX8SL4DQSCTL_OFFSET
#define DDR_PHY_DX8SL4DQSCTL_OFFSET 0XFD08151C
#undef DDR_PHY_DX8SL4DXCTL2_OFFSET
@@ -6676,6 +6270,102 @@
#define DDR_PHY_PGCR2_TREFPRD_SHIFT 0
#define DDR_PHY_PGCR2_TREFPRD_MASK 0x0003FFFFU
+/*CKN Enable*/
+#undef DDR_PHY_PGCR3_CKNEN_DEFVAL
+#undef DDR_PHY_PGCR3_CKNEN_SHIFT
+#undef DDR_PHY_PGCR3_CKNEN_MASK
+#define DDR_PHY_PGCR3_CKNEN_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_CKNEN_SHIFT 24
+#define DDR_PHY_PGCR3_CKNEN_MASK 0xFF000000U
+
+/*CK Enable*/
+#undef DDR_PHY_PGCR3_CKEN_DEFVAL
+#undef DDR_PHY_PGCR3_CKEN_SHIFT
+#undef DDR_PHY_PGCR3_CKEN_MASK
+#define DDR_PHY_PGCR3_CKEN_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_CKEN_SHIFT 16
+#define DDR_PHY_PGCR3_CKEN_MASK 0x00FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_PGCR3_RESERVED_15_DEFVAL
+#undef DDR_PHY_PGCR3_RESERVED_15_SHIFT
+#undef DDR_PHY_PGCR3_RESERVED_15_MASK
+#define DDR_PHY_PGCR3_RESERVED_15_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_RESERVED_15_SHIFT 15
+#define DDR_PHY_PGCR3_RESERVED_15_MASK 0x00008000U
+
+/*Enable Clock Gating for AC [0] ctl_rd_clk*/
+#undef DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL
+#undef DDR_PHY_PGCR3_GATEACRDCLK_SHIFT
+#undef DDR_PHY_PGCR3_GATEACRDCLK_MASK
+#define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 13
+#define DDR_PHY_PGCR3_GATEACRDCLK_MASK 0x00006000U
+
+/*Enable Clock Gating for AC [0] ddr_clk*/
+#undef DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL
+#undef DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT
+#undef DDR_PHY_PGCR3_GATEACDDRCLK_MASK
+#define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 11
+#define DDR_PHY_PGCR3_GATEACDDRCLK_MASK 0x00001800U
+
+/*Enable Clock Gating for AC [0] ctl_clk*/
+#undef DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL
+#undef DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT
+#undef DDR_PHY_PGCR3_GATEACCTLCLK_MASK
+#define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 9
+#define DDR_PHY_PGCR3_GATEACCTLCLK_MASK 0x00000600U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_PGCR3_RESERVED_8_DEFVAL
+#undef DDR_PHY_PGCR3_RESERVED_8_SHIFT
+#undef DDR_PHY_PGCR3_RESERVED_8_MASK
+#define DDR_PHY_PGCR3_RESERVED_8_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_RESERVED_8_SHIFT 8
+#define DDR_PHY_PGCR3_RESERVED_8_MASK 0x00000100U
+
+/*Controls DDL Bypass Modes*/
+#undef DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL
+#undef DDR_PHY_PGCR3_DDLBYPMODE_SHIFT
+#undef DDR_PHY_PGCR3_DDLBYPMODE_MASK
+#define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 6
+#define DDR_PHY_PGCR3_DDLBYPMODE_MASK 0x000000C0U
+
+/*IO Loop-Back Select*/
+#undef DDR_PHY_PGCR3_IOLB_DEFVAL
+#undef DDR_PHY_PGCR3_IOLB_SHIFT
+#undef DDR_PHY_PGCR3_IOLB_MASK
+#define DDR_PHY_PGCR3_IOLB_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_IOLB_SHIFT 5
+#define DDR_PHY_PGCR3_IOLB_MASK 0x00000020U
+
+/*AC Receive FIFO Read Mode*/
+#undef DDR_PHY_PGCR3_RDMODE_DEFVAL
+#undef DDR_PHY_PGCR3_RDMODE_SHIFT
+#undef DDR_PHY_PGCR3_RDMODE_MASK
+#define DDR_PHY_PGCR3_RDMODE_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_RDMODE_SHIFT 3
+#define DDR_PHY_PGCR3_RDMODE_MASK 0x00000018U
+
+/*Read FIFO Reset Disable*/
+#undef DDR_PHY_PGCR3_DISRST_DEFVAL
+#undef DDR_PHY_PGCR3_DISRST_SHIFT
+#undef DDR_PHY_PGCR3_DISRST_MASK
+#define DDR_PHY_PGCR3_DISRST_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_DISRST_SHIFT 2
+#define DDR_PHY_PGCR3_DISRST_MASK 0x00000004U
+
+/*Clock Level when Clock Gating*/
+#undef DDR_PHY_PGCR3_CLKLEVEL_DEFVAL
+#undef DDR_PHY_PGCR3_CLKLEVEL_SHIFT
+#undef DDR_PHY_PGCR3_CLKLEVEL_MASK
+#define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_CLKLEVEL_SHIFT 0
+#define DDR_PHY_PGCR3_CLKLEVEL_MASK 0x00000003U
+
/*Frequency B Ratio Term*/
#undef DDR_PHY_PGCR5_FRQBT_DEFVAL
#undef DDR_PHY_PGCR5_FRQBT_SHIFT
@@ -7685,6 +7375,72 @@
#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 0
#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 0x00003FFFU
+/*DDR4/DDR3 Control Word 7*/
+#undef DDR_PHY_RDIMMCR0_RC7_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC7_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC7_MASK
+#define DDR_PHY_RDIMMCR0_RC7_DEFVAL 0x00000000
+#define DDR_PHY_RDIMMCR0_RC7_SHIFT 28
+#define DDR_PHY_RDIMMCR0_RC7_MASK 0xF0000000U
+
+/*DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved*/
+#undef DDR_PHY_RDIMMCR0_RC6_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC6_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC6_MASK
+#define DDR_PHY_RDIMMCR0_RC6_DEFVAL 0x00000000
+#define DDR_PHY_RDIMMCR0_RC6_SHIFT 24
+#define DDR_PHY_RDIMMCR0_RC6_MASK 0x0F000000U
+
+/*DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)*/
+#undef DDR_PHY_RDIMMCR0_RC5_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC5_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC5_MASK
+#define DDR_PHY_RDIMMCR0_RC5_DEFVAL 0x00000000
+#define DDR_PHY_RDIMMCR0_RC5_SHIFT 20
+#define DDR_PHY_RDIMMCR0_RC5_MASK 0x00F00000U
+
+/*DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C
+ aracteristics Control Word)*/
+#undef DDR_PHY_RDIMMCR0_RC4_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC4_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC4_MASK
+#define DDR_PHY_RDIMMCR0_RC4_DEFVAL 0x00000000
+#define DDR_PHY_RDIMMCR0_RC4_SHIFT 16
+#define DDR_PHY_RDIMMCR0_RC4_MASK 0x000F0000U
+
+/*DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr
+ ver Characteristrics Control Word)*/
+#undef DDR_PHY_RDIMMCR0_RC3_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC3_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC3_MASK
+#define DDR_PHY_RDIMMCR0_RC3_DEFVAL 0x00000000
+#define DDR_PHY_RDIMMCR0_RC3_SHIFT 12
+#define DDR_PHY_RDIMMCR0_RC3_MASK 0x0000F000U
+
+/*DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)*/
+#undef DDR_PHY_RDIMMCR0_RC2_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC2_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC2_MASK
+#define DDR_PHY_RDIMMCR0_RC2_DEFVAL 0x00000000
+#define DDR_PHY_RDIMMCR0_RC2_SHIFT 8
+#define DDR_PHY_RDIMMCR0_RC2_MASK 0x00000F00U
+
+/*DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)*/
+#undef DDR_PHY_RDIMMCR0_RC1_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC1_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC1_MASK
+#define DDR_PHY_RDIMMCR0_RC1_DEFVAL 0x00000000
+#define DDR_PHY_RDIMMCR0_RC1_SHIFT 4
+#define DDR_PHY_RDIMMCR0_RC1_MASK 0x000000F0U
+
+/*DDR4/DDR3 Control Word 0 (Global Features Control Word)*/
+#undef DDR_PHY_RDIMMCR0_RC0_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC0_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC0_MASK
+#define DDR_PHY_RDIMMCR0_RC0_DEFVAL 0x00000000
+#define DDR_PHY_RDIMMCR0_RC0_SHIFT 0
+#define DDR_PHY_RDIMMCR0_RC0_MASK 0x0000000FU
+
/*Control Word 15*/
#undef DDR_PHY_RDIMMCR1_RC15_DEFVAL
#undef DDR_PHY_RDIMMCR1_RC15_SHIFT
@@ -8672,6 +8428,14 @@
#define DDR_PHY_CATR0_CA1BYTE0_SHIFT 0
#define DDR_PHY_CATR0_CA1BYTE0_MASK 0x0000000FU
+/*LFSR seed for pseudo-random BIST patterns*/
+#undef DDR_PHY_BISTLSR_SEED_DEFVAL
+#undef DDR_PHY_BISTLSR_SEED_SHIFT
+#undef DDR_PHY_BISTLSR_SEED_MASK
+#define DDR_PHY_BISTLSR_SEED_DEFVAL
+#define DDR_PHY_BISTLSR_SEED_SHIFT 0
+#define DDR_PHY_BISTLSR_SEED_MASK 0xFFFFFFFFU
+
/*Reserved. Return zeroes on reads.*/
#undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL
#undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT
@@ -9232,6 +8996,134 @@
#define DDR_PHY_VTCR1_HVIO_SHIFT 0
#define DDR_PHY_VTCR1_HVIO_MASK 0x00000001U
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT
+#undef DDR_PHY_ACBDLR1_RESERVED_31_30_MASK
+#define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 30
+#define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 0xC0000000U
+
+/*Delay select for the BDL on Parity.*/
+#undef DDR_PHY_ACBDLR1_PARBD_DEFVAL
+#undef DDR_PHY_ACBDLR1_PARBD_SHIFT
+#undef DDR_PHY_ACBDLR1_PARBD_MASK
+#define DDR_PHY_ACBDLR1_PARBD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR1_PARBD_SHIFT 24
+#define DDR_PHY_ACBDLR1_PARBD_MASK 0x3F000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT
+#undef DDR_PHY_ACBDLR1_RESERVED_23_22_MASK
+#define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 22
+#define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 0x00C00000U
+
+/*Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE.*/
+#undef DDR_PHY_ACBDLR1_A16BD_DEFVAL
+#undef DDR_PHY_ACBDLR1_A16BD_SHIFT
+#undef DDR_PHY_ACBDLR1_A16BD_MASK
+#define DDR_PHY_ACBDLR1_A16BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR1_A16BD_SHIFT 16
+#define DDR_PHY_ACBDLR1_A16BD_MASK 0x003F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT
+#undef DDR_PHY_ACBDLR1_RESERVED_15_14_MASK
+#define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 14
+#define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 0x0000C000U
+
+/*Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS.*/
+#undef DDR_PHY_ACBDLR1_A17BD_DEFVAL
+#undef DDR_PHY_ACBDLR1_A17BD_SHIFT
+#undef DDR_PHY_ACBDLR1_A17BD_MASK
+#define DDR_PHY_ACBDLR1_A17BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR1_A17BD_SHIFT 8
+#define DDR_PHY_ACBDLR1_A17BD_MASK 0x00003F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT
+#undef DDR_PHY_ACBDLR1_RESERVED_7_6_MASK
+#define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 6
+#define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 0x000000C0U
+
+/*Delay select for the BDL on ACTN.*/
+#undef DDR_PHY_ACBDLR1_ACTBD_DEFVAL
+#undef DDR_PHY_ACBDLR1_ACTBD_SHIFT
+#undef DDR_PHY_ACBDLR1_ACTBD_MASK
+#define DDR_PHY_ACBDLR1_ACTBD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR1_ACTBD_SHIFT 0
+#define DDR_PHY_ACBDLR1_ACTBD_MASK 0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT
+#undef DDR_PHY_ACBDLR2_RESERVED_31_30_MASK
+#define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 30
+#define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 0xC0000000U
+
+/*Delay select for the BDL on BG[1].*/
+#undef DDR_PHY_ACBDLR2_BG1BD_DEFVAL
+#undef DDR_PHY_ACBDLR2_BG1BD_SHIFT
+#undef DDR_PHY_ACBDLR2_BG1BD_MASK
+#define DDR_PHY_ACBDLR2_BG1BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR2_BG1BD_SHIFT 24
+#define DDR_PHY_ACBDLR2_BG1BD_MASK 0x3F000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT
+#undef DDR_PHY_ACBDLR2_RESERVED_23_22_MASK
+#define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 22
+#define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 0x00C00000U
+
+/*Delay select for the BDL on BG[0].*/
+#undef DDR_PHY_ACBDLR2_BG0BD_DEFVAL
+#undef DDR_PHY_ACBDLR2_BG0BD_SHIFT
+#undef DDR_PHY_ACBDLR2_BG0BD_MASK
+#define DDR_PHY_ACBDLR2_BG0BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR2_BG0BD_SHIFT 16
+#define DDR_PHY_ACBDLR2_BG0BD_MASK 0x003F0000U
+
+/*Reser.ved Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT
+#undef DDR_PHY_ACBDLR2_RESERVED_15_14_MASK
+#define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 14
+#define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 0x0000C000U
+
+/*Delay select for the BDL on BA[1].*/
+#undef DDR_PHY_ACBDLR2_BA1BD_DEFVAL
+#undef DDR_PHY_ACBDLR2_BA1BD_SHIFT
+#undef DDR_PHY_ACBDLR2_BA1BD_MASK
+#define DDR_PHY_ACBDLR2_BA1BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR2_BA1BD_SHIFT 8
+#define DDR_PHY_ACBDLR2_BA1BD_MASK 0x00003F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT
+#undef DDR_PHY_ACBDLR2_RESERVED_7_6_MASK
+#define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 6
+#define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 0x000000C0U
+
+/*Delay select for the BDL on BA[0].*/
+#undef DDR_PHY_ACBDLR2_BA0BD_DEFVAL
+#undef DDR_PHY_ACBDLR2_BA0BD_SHIFT
+#undef DDR_PHY_ACBDLR2_BA0BD_MASK
+#define DDR_PHY_ACBDLR2_BA0BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR2_BA0BD_SHIFT 0
+#define DDR_PHY_ACBDLR2_BA0BD_MASK 0x0000003FU
+
/*Reserved. Return zeroes on reads.*/
#undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL
#undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT
@@ -9424,6 +9316,70 @@
#define DDR_PHY_ACBDLR8_A08BD_SHIFT 0
#define DDR_PHY_ACBDLR8_A08BD_MASK 0x0000003FU
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT
+#undef DDR_PHY_ACBDLR9_RESERVED_31_30_MASK
+#define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 30
+#define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 0xC0000000U
+
+/*Delay select for the BDL on Address A[15].*/
+#undef DDR_PHY_ACBDLR9_A15BD_DEFVAL
+#undef DDR_PHY_ACBDLR9_A15BD_SHIFT
+#undef DDR_PHY_ACBDLR9_A15BD_MASK
+#define DDR_PHY_ACBDLR9_A15BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR9_A15BD_SHIFT 24
+#define DDR_PHY_ACBDLR9_A15BD_MASK 0x3F000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT
+#undef DDR_PHY_ACBDLR9_RESERVED_23_22_MASK
+#define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 22
+#define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 0x00C00000U
+
+/*Delay select for the BDL on Address A[14].*/
+#undef DDR_PHY_ACBDLR9_A14BD_DEFVAL
+#undef DDR_PHY_ACBDLR9_A14BD_SHIFT
+#undef DDR_PHY_ACBDLR9_A14BD_MASK
+#define DDR_PHY_ACBDLR9_A14BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR9_A14BD_SHIFT 16
+#define DDR_PHY_ACBDLR9_A14BD_MASK 0x003F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT
+#undef DDR_PHY_ACBDLR9_RESERVED_15_14_MASK
+#define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 14
+#define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 0x0000C000U
+
+/*Delay select for the BDL on Address A[13].*/
+#undef DDR_PHY_ACBDLR9_A13BD_DEFVAL
+#undef DDR_PHY_ACBDLR9_A13BD_SHIFT
+#undef DDR_PHY_ACBDLR9_A13BD_MASK
+#define DDR_PHY_ACBDLR9_A13BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR9_A13BD_SHIFT 8
+#define DDR_PHY_ACBDLR9_A13BD_MASK 0x00003F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT
+#undef DDR_PHY_ACBDLR9_RESERVED_7_6_MASK
+#define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 6
+#define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 0x000000C0U
+
+/*Delay select for the BDL on Address A[12].*/
+#undef DDR_PHY_ACBDLR9_A12BD_DEFVAL
+#undef DDR_PHY_ACBDLR9_A12BD_SHIFT
+#undef DDR_PHY_ACBDLR9_A12BD_MASK
+#define DDR_PHY_ACBDLR9_A12BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR9_A12BD_SHIFT 0
+#define DDR_PHY_ACBDLR9_A12BD_MASK 0x0000003FU
+
/*Reserved. Return zeroes on reads.*/
#undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL
#undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT
@@ -14464,6 +14420,158 @@
#define DDR_PHY_DX8GTR0_DGSL_SHIFT 0
#define DDR_PHY_DX8GTR0_DGSL_MASK 0x0000001FU
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK
+#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 30
+#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 0xC0000000U
+
+/*Enable Clock Gating for DX ddr_clk*/
+#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT
+#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK
+#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 28
+#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 0x30000000U
+
+/*Enable Clock Gating for DX ctl_rd_clk*/
+#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT
+#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK
+#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 26
+#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 0x0C000000U
+
+/*Enable Clock Gating for DX ctl_clk*/
+#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT
+#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK
+#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 24
+#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 0x03000000U
+
+/*Selects the level to which clocks will be stalled when clock gating is enabled.*/
+#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT
+#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK
+#define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 22
+#define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 0x00C00000U
+
+/*Loopback Mode*/
+#undef DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_LBMODE_SHIFT
+#undef DDR_PHY_DX8SL0OSC_LBMODE_MASK
+#define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 21
+#define DDR_PHY_DX8SL0OSC_LBMODE_MASK 0x00200000U
+
+/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
+#undef DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT
+#undef DDR_PHY_DX8SL0OSC_LBGSDQS_MASK
+#define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 20
+#define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 0x00100000U
+
+/*Loopback DQS Gating*/
+#undef DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT
+#undef DDR_PHY_DX8SL0OSC_LBGDQS_MASK
+#define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 18
+#define DDR_PHY_DX8SL0OSC_LBGDQS_MASK 0x000C0000U
+
+/*Loopback DQS Shift*/
+#undef DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT
+#undef DDR_PHY_DX8SL0OSC_LBDQSS_MASK
+#define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 17
+#define DDR_PHY_DX8SL0OSC_LBDQSS_MASK 0x00020000U
+
+/*PHY High-Speed Reset*/
+#undef DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT
+#undef DDR_PHY_DX8SL0OSC_PHYHRST_MASK
+#define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 16
+#define DDR_PHY_DX8SL0OSC_PHYHRST_MASK 0x00010000U
+
+/*PHY FIFO Reset*/
+#undef DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT
+#undef DDR_PHY_DX8SL0OSC_PHYFRST_MASK
+#define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 15
+#define DDR_PHY_DX8SL0OSC_PHYFRST_MASK 0x00008000U
+
+/*Delay Line Test Start*/
+#undef DDR_PHY_DX8SL0OSC_DLTST_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_DLTST_SHIFT
+#undef DDR_PHY_DX8SL0OSC_DLTST_MASK
+#define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_DLTST_SHIFT 14
+#define DDR_PHY_DX8SL0OSC_DLTST_MASK 0x00004000U
+
+/*Delay Line Test Mode*/
+#undef DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT
+#undef DDR_PHY_DX8SL0OSC_DLTMODE_MASK
+#define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 13
+#define DDR_PHY_DX8SL0OSC_DLTMODE_MASK 0x00002000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT
+#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK
+#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 11
+#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 0x00001800U
+
+/*Oscillator Mode Write-Data Delay Line Select*/
+#undef DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT
+#undef DDR_PHY_DX8SL0OSC_OSCWDDL_MASK
+#define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 9
+#define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 0x00000600U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT
+#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK
+#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 7
+#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 0x00000180U
+
+/*Oscillator Mode Write-Leveling Delay Line Select*/
+#undef DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT
+#undef DDR_PHY_DX8SL0OSC_OSCWDL_MASK
+#define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 5
+#define DDR_PHY_DX8SL0OSC_OSCWDL_MASK 0x00000060U
+
+/*Oscillator Mode Division*/
+#undef DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT
+#undef DDR_PHY_DX8SL0OSC_OSCDIV_MASK
+#define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 1
+#define DDR_PHY_DX8SL0OSC_OSCDIV_MASK 0x0000001EU
+
+/*Oscillator Enable*/
+#undef DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_OSCEN_SHIFT
+#undef DDR_PHY_DX8SL0OSC_OSCEN_MASK
+#define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 0
+#define DDR_PHY_DX8SL0OSC_OSCEN_MASK 0x00000001U
+
/*Reserved. Return zeroes on reads.*/
#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL
#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT
@@ -14752,6 +14860,158 @@
#define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 0
#define DDR_PHY_DX8SL0IOCR_DXRXM_MASK 0x000007FFU
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK
+#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 30
+#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 0xC0000000U
+
+/*Enable Clock Gating for DX ddr_clk*/
+#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT
+#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK
+#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 28
+#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 0x30000000U
+
+/*Enable Clock Gating for DX ctl_rd_clk*/
+#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT
+#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK
+#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 26
+#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 0x0C000000U
+
+/*Enable Clock Gating for DX ctl_clk*/
+#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT
+#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK
+#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 24
+#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 0x03000000U
+
+/*Selects the level to which clocks will be stalled when clock gating is enabled.*/
+#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT
+#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK
+#define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 22
+#define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 0x00C00000U
+
+/*Loopback Mode*/
+#undef DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_LBMODE_SHIFT
+#undef DDR_PHY_DX8SL1OSC_LBMODE_MASK
+#define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 21
+#define DDR_PHY_DX8SL1OSC_LBMODE_MASK 0x00200000U
+
+/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
+#undef DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT
+#undef DDR_PHY_DX8SL1OSC_LBGSDQS_MASK
+#define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 20
+#define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 0x00100000U
+
+/*Loopback DQS Gating*/
+#undef DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT
+#undef DDR_PHY_DX8SL1OSC_LBGDQS_MASK
+#define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 18
+#define DDR_PHY_DX8SL1OSC_LBGDQS_MASK 0x000C0000U
+
+/*Loopback DQS Shift*/
+#undef DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT
+#undef DDR_PHY_DX8SL1OSC_LBDQSS_MASK
+#define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 17
+#define DDR_PHY_DX8SL1OSC_LBDQSS_MASK 0x00020000U
+
+/*PHY High-Speed Reset*/
+#undef DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT
+#undef DDR_PHY_DX8SL1OSC_PHYHRST_MASK
+#define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 16
+#define DDR_PHY_DX8SL1OSC_PHYHRST_MASK 0x00010000U
+
+/*PHY FIFO Reset*/
+#undef DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT
+#undef DDR_PHY_DX8SL1OSC_PHYFRST_MASK
+#define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 15
+#define DDR_PHY_DX8SL1OSC_PHYFRST_MASK 0x00008000U
+
+/*Delay Line Test Start*/
+#undef DDR_PHY_DX8SL1OSC_DLTST_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_DLTST_SHIFT
+#undef DDR_PHY_DX8SL1OSC_DLTST_MASK
+#define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_DLTST_SHIFT 14
+#define DDR_PHY_DX8SL1OSC_DLTST_MASK 0x00004000U
+
+/*Delay Line Test Mode*/
+#undef DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT
+#undef DDR_PHY_DX8SL1OSC_DLTMODE_MASK
+#define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 13
+#define DDR_PHY_DX8SL1OSC_DLTMODE_MASK 0x00002000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT
+#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK
+#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 11
+#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 0x00001800U
+
+/*Oscillator Mode Write-Data Delay Line Select*/
+#undef DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT
+#undef DDR_PHY_DX8SL1OSC_OSCWDDL_MASK
+#define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 9
+#define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 0x00000600U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT
+#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK
+#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 7
+#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 0x00000180U
+
+/*Oscillator Mode Write-Leveling Delay Line Select*/
+#undef DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT
+#undef DDR_PHY_DX8SL1OSC_OSCWDL_MASK
+#define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 5
+#define DDR_PHY_DX8SL1OSC_OSCWDL_MASK 0x00000060U
+
+/*Oscillator Mode Division*/
+#undef DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT
+#undef DDR_PHY_DX8SL1OSC_OSCDIV_MASK
+#define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 1
+#define DDR_PHY_DX8SL1OSC_OSCDIV_MASK 0x0000001EU
+
+/*Oscillator Enable*/
+#undef DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_OSCEN_SHIFT
+#undef DDR_PHY_DX8SL1OSC_OSCEN_MASK
+#define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 0
+#define DDR_PHY_DX8SL1OSC_OSCEN_MASK 0x00000001U
+
/*Reserved. Return zeroes on reads.*/
#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL
#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT
@@ -15040,6 +15300,158 @@
#define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 0
#define DDR_PHY_DX8SL1IOCR_DXRXM_MASK 0x000007FFU
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK
+#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 30
+#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 0xC0000000U
+
+/*Enable Clock Gating for DX ddr_clk*/
+#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT
+#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK
+#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 28
+#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 0x30000000U
+
+/*Enable Clock Gating for DX ctl_rd_clk*/
+#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT
+#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK
+#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 26
+#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 0x0C000000U
+
+/*Enable Clock Gating for DX ctl_clk*/
+#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT
+#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK
+#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 24
+#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 0x03000000U
+
+/*Selects the level to which clocks will be stalled when clock gating is enabled.*/
+#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT
+#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK
+#define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 22
+#define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 0x00C00000U
+
+/*Loopback Mode*/
+#undef DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_LBMODE_SHIFT
+#undef DDR_PHY_DX8SL2OSC_LBMODE_MASK
+#define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 21
+#define DDR_PHY_DX8SL2OSC_LBMODE_MASK 0x00200000U
+
+/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
+#undef DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT
+#undef DDR_PHY_DX8SL2OSC_LBGSDQS_MASK
+#define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 20
+#define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 0x00100000U
+
+/*Loopback DQS Gating*/
+#undef DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT
+#undef DDR_PHY_DX8SL2OSC_LBGDQS_MASK
+#define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 18
+#define DDR_PHY_DX8SL2OSC_LBGDQS_MASK 0x000C0000U
+
+/*Loopback DQS Shift*/
+#undef DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT
+#undef DDR_PHY_DX8SL2OSC_LBDQSS_MASK
+#define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 17
+#define DDR_PHY_DX8SL2OSC_LBDQSS_MASK 0x00020000U
+
+/*PHY High-Speed Reset*/
+#undef DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT
+#undef DDR_PHY_DX8SL2OSC_PHYHRST_MASK
+#define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 16
+#define DDR_PHY_DX8SL2OSC_PHYHRST_MASK 0x00010000U
+
+/*PHY FIFO Reset*/
+#undef DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT
+#undef DDR_PHY_DX8SL2OSC_PHYFRST_MASK
+#define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 15
+#define DDR_PHY_DX8SL2OSC_PHYFRST_MASK 0x00008000U
+
+/*Delay Line Test Start*/
+#undef DDR_PHY_DX8SL2OSC_DLTST_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_DLTST_SHIFT
+#undef DDR_PHY_DX8SL2OSC_DLTST_MASK
+#define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_DLTST_SHIFT 14
+#define DDR_PHY_DX8SL2OSC_DLTST_MASK 0x00004000U
+
+/*Delay Line Test Mode*/
+#undef DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT
+#undef DDR_PHY_DX8SL2OSC_DLTMODE_MASK
+#define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 13
+#define DDR_PHY_DX8SL2OSC_DLTMODE_MASK 0x00002000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT
+#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK
+#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 11
+#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 0x00001800U
+
+/*Oscillator Mode Write-Data Delay Line Select*/
+#undef DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT
+#undef DDR_PHY_DX8SL2OSC_OSCWDDL_MASK
+#define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 9
+#define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 0x00000600U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT
+#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK
+#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 7
+#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 0x00000180U
+
+/*Oscillator Mode Write-Leveling Delay Line Select*/
+#undef DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT
+#undef DDR_PHY_DX8SL2OSC_OSCWDL_MASK
+#define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 5
+#define DDR_PHY_DX8SL2OSC_OSCWDL_MASK 0x00000060U
+
+/*Oscillator Mode Division*/
+#undef DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT
+#undef DDR_PHY_DX8SL2OSC_OSCDIV_MASK
+#define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 1
+#define DDR_PHY_DX8SL2OSC_OSCDIV_MASK 0x0000001EU
+
+/*Oscillator Enable*/
+#undef DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_OSCEN_SHIFT
+#undef DDR_PHY_DX8SL2OSC_OSCEN_MASK
+#define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 0
+#define DDR_PHY_DX8SL2OSC_OSCEN_MASK 0x00000001U
+
/*Reserved. Return zeroes on reads.*/
#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL
#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT
@@ -15328,6 +15740,158 @@
#define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 0
#define DDR_PHY_DX8SL2IOCR_DXRXM_MASK 0x000007FFU
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK
+#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 30
+#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 0xC0000000U
+
+/*Enable Clock Gating for DX ddr_clk*/
+#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT
+#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK
+#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 28
+#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 0x30000000U
+
+/*Enable Clock Gating for DX ctl_rd_clk*/
+#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT
+#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK
+#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 26
+#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 0x0C000000U
+
+/*Enable Clock Gating for DX ctl_clk*/
+#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT
+#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK
+#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 24
+#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 0x03000000U
+
+/*Selects the level to which clocks will be stalled when clock gating is enabled.*/
+#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT
+#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK
+#define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 22
+#define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 0x00C00000U
+
+/*Loopback Mode*/
+#undef DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_LBMODE_SHIFT
+#undef DDR_PHY_DX8SL3OSC_LBMODE_MASK
+#define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 21
+#define DDR_PHY_DX8SL3OSC_LBMODE_MASK 0x00200000U
+
+/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
+#undef DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT
+#undef DDR_PHY_DX8SL3OSC_LBGSDQS_MASK
+#define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 20
+#define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 0x00100000U
+
+/*Loopback DQS Gating*/
+#undef DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT
+#undef DDR_PHY_DX8SL3OSC_LBGDQS_MASK
+#define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 18
+#define DDR_PHY_DX8SL3OSC_LBGDQS_MASK 0x000C0000U
+
+/*Loopback DQS Shift*/
+#undef DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT
+#undef DDR_PHY_DX8SL3OSC_LBDQSS_MASK
+#define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 17
+#define DDR_PHY_DX8SL3OSC_LBDQSS_MASK 0x00020000U
+
+/*PHY High-Speed Reset*/
+#undef DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT
+#undef DDR_PHY_DX8SL3OSC_PHYHRST_MASK
+#define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 16
+#define DDR_PHY_DX8SL3OSC_PHYHRST_MASK 0x00010000U
+
+/*PHY FIFO Reset*/
+#undef DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT
+#undef DDR_PHY_DX8SL3OSC_PHYFRST_MASK
+#define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 15
+#define DDR_PHY_DX8SL3OSC_PHYFRST_MASK 0x00008000U
+
+/*Delay Line Test Start*/
+#undef DDR_PHY_DX8SL3OSC_DLTST_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_DLTST_SHIFT
+#undef DDR_PHY_DX8SL3OSC_DLTST_MASK
+#define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_DLTST_SHIFT 14
+#define DDR_PHY_DX8SL3OSC_DLTST_MASK 0x00004000U
+
+/*Delay Line Test Mode*/
+#undef DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT
+#undef DDR_PHY_DX8SL3OSC_DLTMODE_MASK
+#define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 13
+#define DDR_PHY_DX8SL3OSC_DLTMODE_MASK 0x00002000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT
+#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK
+#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 11
+#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 0x00001800U
+
+/*Oscillator Mode Write-Data Delay Line Select*/
+#undef DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT
+#undef DDR_PHY_DX8SL3OSC_OSCWDDL_MASK
+#define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 9
+#define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 0x00000600U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT
+#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK
+#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 7
+#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 0x00000180U
+
+/*Oscillator Mode Write-Leveling Delay Line Select*/
+#undef DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT
+#undef DDR_PHY_DX8SL3OSC_OSCWDL_MASK
+#define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 5
+#define DDR_PHY_DX8SL3OSC_OSCWDL_MASK 0x00000060U
+
+/*Oscillator Mode Division*/
+#undef DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT
+#undef DDR_PHY_DX8SL3OSC_OSCDIV_MASK
+#define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 1
+#define DDR_PHY_DX8SL3OSC_OSCDIV_MASK 0x0000001EU
+
+/*Oscillator Enable*/
+#undef DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_OSCEN_SHIFT
+#undef DDR_PHY_DX8SL3OSC_OSCEN_MASK
+#define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 0
+#define DDR_PHY_DX8SL3OSC_OSCEN_MASK 0x00000001U
+
/*Reserved. Return zeroes on reads.*/
#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL
#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT
@@ -15616,6 +16180,158 @@
#define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 0
#define DDR_PHY_DX8SL3IOCR_DXRXM_MASK 0x000007FFU
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK
+#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 30
+#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 0xC0000000U
+
+/*Enable Clock Gating for DX ddr_clk*/
+#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT
+#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK
+#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 28
+#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 0x30000000U
+
+/*Enable Clock Gating for DX ctl_rd_clk*/
+#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT
+#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK
+#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 26
+#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 0x0C000000U
+
+/*Enable Clock Gating for DX ctl_clk*/
+#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT
+#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK
+#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 24
+#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 0x03000000U
+
+/*Selects the level to which clocks will be stalled when clock gating is enabled.*/
+#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT
+#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK
+#define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 22
+#define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 0x00C00000U
+
+/*Loopback Mode*/
+#undef DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_LBMODE_SHIFT
+#undef DDR_PHY_DX8SL4OSC_LBMODE_MASK
+#define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 21
+#define DDR_PHY_DX8SL4OSC_LBMODE_MASK 0x00200000U
+
+/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
+#undef DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT
+#undef DDR_PHY_DX8SL4OSC_LBGSDQS_MASK
+#define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 20
+#define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 0x00100000U
+
+/*Loopback DQS Gating*/
+#undef DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT
+#undef DDR_PHY_DX8SL4OSC_LBGDQS_MASK
+#define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 18
+#define DDR_PHY_DX8SL4OSC_LBGDQS_MASK 0x000C0000U
+
+/*Loopback DQS Shift*/
+#undef DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT
+#undef DDR_PHY_DX8SL4OSC_LBDQSS_MASK
+#define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 17
+#define DDR_PHY_DX8SL4OSC_LBDQSS_MASK 0x00020000U
+
+/*PHY High-Speed Reset*/
+#undef DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT
+#undef DDR_PHY_DX8SL4OSC_PHYHRST_MASK
+#define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 16
+#define DDR_PHY_DX8SL4OSC_PHYHRST_MASK 0x00010000U
+
+/*PHY FIFO Reset*/
+#undef DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT
+#undef DDR_PHY_DX8SL4OSC_PHYFRST_MASK
+#define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 15
+#define DDR_PHY_DX8SL4OSC_PHYFRST_MASK 0x00008000U
+
+/*Delay Line Test Start*/
+#undef DDR_PHY_DX8SL4OSC_DLTST_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_DLTST_SHIFT
+#undef DDR_PHY_DX8SL4OSC_DLTST_MASK
+#define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_DLTST_SHIFT 14
+#define DDR_PHY_DX8SL4OSC_DLTST_MASK 0x00004000U
+
+/*Delay Line Test Mode*/
+#undef DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT
+#undef DDR_PHY_DX8SL4OSC_DLTMODE_MASK
+#define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 13
+#define DDR_PHY_DX8SL4OSC_DLTMODE_MASK 0x00002000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT
+#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK
+#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 11
+#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 0x00001800U
+
+/*Oscillator Mode Write-Data Delay Line Select*/
+#undef DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT
+#undef DDR_PHY_DX8SL4OSC_OSCWDDL_MASK
+#define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 9
+#define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 0x00000600U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT
+#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK
+#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 7
+#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 0x00000180U
+
+/*Oscillator Mode Write-Leveling Delay Line Select*/
+#undef DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT
+#undef DDR_PHY_DX8SL4OSC_OSCWDL_MASK
+#define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 5
+#define DDR_PHY_DX8SL4OSC_OSCWDL_MASK 0x00000060U
+
+/*Oscillator Mode Division*/
+#undef DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT
+#undef DDR_PHY_DX8SL4OSC_OSCDIV_MASK
+#define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 1
+#define DDR_PHY_DX8SL4OSC_OSCDIV_MASK 0x0000001EU
+
+/*Oscillator Enable*/
+#undef DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_OSCEN_SHIFT
+#undef DDR_PHY_DX8SL4OSC_OSCEN_MASK
+#define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 0
+#define DDR_PHY_DX8SL4OSC_OSCEN_MASK 0x00000001U
+
/*Reserved. Return zeroes on reads.*/
#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL
#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT
@@ -22022,208 +22738,208 @@
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 12
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00001000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 13
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00002000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 14
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00004000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 15
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00008000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 16
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00010000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 17
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00020000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 18
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00040000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 19
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00080000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 20
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00100000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 21
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00200000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 22
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00400000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 23
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00800000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 24
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x01000000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 25
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x02000000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 0
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00000001U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 1
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00000002U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 2
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00000004U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 3
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00000008U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 4
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00000010U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 5
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00000020U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 6
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00000040U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 7
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00000080U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 8
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00000100U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 9
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00000200U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 10
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x00000400U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 11
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x00000800U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
@@ -23716,10 +24432,14 @@
#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 0x00000000
#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 0
#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 0x00000001U
+#undef CRL_APB_RST_LPD_IOU2_OFFSET
+#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
#undef CRL_APB_RST_LPD_IOU0_OFFSET
#define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230
#undef CRL_APB_RST_LPD_IOU2_OFFSET
#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
+#undef IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET
+#define IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET 0XFF180390
#undef CRL_APB_RST_LPD_TOP_OFFSET
#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
#undef CRF_APB_RST_FPD_TOP_OFFSET
@@ -23732,6 +24452,8 @@
#define IOU_SLCR_SD_CONFIG_REG2_OFFSET 0XFF180320
#undef IOU_SLCR_SD_CONFIG_REG1_OFFSET
#define IOU_SLCR_SD_CONFIG_REG1_OFFSET 0XFF18031C
+#undef IOU_SLCR_SD_CONFIG_REG3_OFFSET
+#define IOU_SLCR_SD_CONFIG_REG3_OFFSET 0XFF180324
#undef CRL_APB_RST_LPD_IOU2_OFFSET
#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
#undef CRL_APB_RST_LPD_IOU2_OFFSET
@@ -23766,6 +24488,18 @@
#define APU_ACE_CTRL_OFFSET 0XFD5C0060
#undef RTC_CONTROL_OFFSET
#define RTC_CONTROL_OFFSET 0XFFA60040
+#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET
+#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET 0XFF260020
+#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET
+#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET 0XFF260000
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK
+#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL 0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 20
+#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK 0x00100000U
/*GEM 3 reset*/
#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
@@ -23783,6 +24517,14 @@
#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0
#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U
+/*0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI*/
+#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL
+#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT
+#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK
+#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x00000007
+#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2
+#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U
+
/*USB 0 reset for control registers*/
#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
@@ -23952,6 +24694,16 @@
#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 23
#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 0x7F800000U
+/*This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf
+ rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon
+ s Fh - Ch = Reserved*/
+#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL
+#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT
+#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK
+#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL 0x06070607
+#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT 22
+#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK 0x03C00000U
+
/*Block level reset*/
#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL
#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT
@@ -24442,6 +25194,80 @@
#define RTC_CONTROL_BATTERY_DISABLE_DEFVAL 0x01000000
#define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31
#define RTC_CONTROL_BATTERY_DISABLE_MASK 0x80000000U
+
+/*Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz.*/
+#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL
+#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT
+#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK
+#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL
+#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT 0
+#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK 0xFFFFFFFFU
+
+/*Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing.*/
+#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL
+#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT
+#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK
+#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL 0x00000000
+#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT 0
+#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK 0x00000001U
+#undef LPD_XPPU_CFG_IEN_OFFSET
+#define LPD_XPPU_CFG_IEN_OFFSET 0XFF980018
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT
+#undef LPD_XPPU_CFG_IEN_APER_PARITY_MASK
+#define LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT 7
+#define LPD_XPPU_CFG_IEN_APER_PARITY_MASK 0x00000080U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL
+#undef LPD_XPPU_CFG_IEN_APER_TZ_SHIFT
+#undef LPD_XPPU_CFG_IEN_APER_TZ_MASK
+#define LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_APER_TZ_SHIFT 6
+#define LPD_XPPU_CFG_IEN_APER_TZ_MASK 0x00000040U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL
+#undef LPD_XPPU_CFG_IEN_APER_PERM_SHIFT
+#undef LPD_XPPU_CFG_IEN_APER_PERM_MASK
+#define LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_APER_PERM_SHIFT 5
+#define LPD_XPPU_CFG_IEN_APER_PERM_MASK 0x00000020U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT
+#undef LPD_XPPU_CFG_IEN_MID_PARITY_MASK
+#define LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT 3
+#define LPD_XPPU_CFG_IEN_MID_PARITY_MASK 0x00000008U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_MID_RO_DEFVAL
+#undef LPD_XPPU_CFG_IEN_MID_RO_SHIFT
+#undef LPD_XPPU_CFG_IEN_MID_RO_MASK
+#define LPD_XPPU_CFG_IEN_MID_RO_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_MID_RO_SHIFT 2
+#define LPD_XPPU_CFG_IEN_MID_RO_MASK 0x00000004U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL
+#undef LPD_XPPU_CFG_IEN_MID_MISS_SHIFT
+#undef LPD_XPPU_CFG_IEN_MID_MISS_MASK
+#define LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_MID_MISS_SHIFT 1
+#define LPD_XPPU_CFG_IEN_MID_MISS_MASK 0x00000002U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_INV_APB_DEFVAL
+#undef LPD_XPPU_CFG_IEN_INV_APB_SHIFT
+#undef LPD_XPPU_CFG_IEN_INV_APB_MASK
+#define LPD_XPPU_CFG_IEN_INV_APB_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_INV_APB_SHIFT 0
+#define LPD_XPPU_CFG_IEN_INV_APB_MASK 0x00000001U
#undef SERDES_PLL_REF_SEL0_OFFSET
#define SERDES_PLL_REF_SEL0_OFFSET 0XFD410000
#undef SERDES_PLL_REF_SEL1_OFFSET
@@ -24508,6 +25334,126 @@
#define SERDES_L3_TX_DIG_TM_61_OFFSET 0XFD40C0F4
#undef SERDES_L3_TXPMA_ST_0_OFFSET
#define SERDES_L3_TXPMA_ST_0_OFFSET 0XFD40CB00
+#undef SERDES_L0_TM_AUX_0_OFFSET
+#define SERDES_L0_TM_AUX_0_OFFSET 0XFD4010CC
+#undef SERDES_L2_TM_AUX_0_OFFSET
+#define SERDES_L2_TM_AUX_0_OFFSET 0XFD4090CC
+#undef SERDES_L0_TM_DIG_8_OFFSET
+#define SERDES_L0_TM_DIG_8_OFFSET 0XFD401074
+#undef SERDES_L1_TM_DIG_8_OFFSET
+#define SERDES_L1_TM_DIG_8_OFFSET 0XFD405074
+#undef SERDES_L2_TM_DIG_8_OFFSET
+#define SERDES_L2_TM_DIG_8_OFFSET 0XFD409074
+#undef SERDES_L3_TM_DIG_8_OFFSET
+#define SERDES_L3_TM_DIG_8_OFFSET 0XFD40D074
+#undef SERDES_L0_TM_MISC2_OFFSET
+#define SERDES_L0_TM_MISC2_OFFSET 0XFD40189C
+#undef SERDES_L0_TM_IQ_ILL1_OFFSET
+#define SERDES_L0_TM_IQ_ILL1_OFFSET 0XFD4018F8
+#undef SERDES_L0_TM_IQ_ILL2_OFFSET
+#define SERDES_L0_TM_IQ_ILL2_OFFSET 0XFD4018FC
+#undef SERDES_L0_TM_ILL12_OFFSET
+#define SERDES_L0_TM_ILL12_OFFSET 0XFD401990
+#undef SERDES_L0_TM_E_ILL1_OFFSET
+#define SERDES_L0_TM_E_ILL1_OFFSET 0XFD401924
+#undef SERDES_L0_TM_E_ILL2_OFFSET
+#define SERDES_L0_TM_E_ILL2_OFFSET 0XFD401928
+#undef SERDES_L0_TM_IQ_ILL3_OFFSET
+#define SERDES_L0_TM_IQ_ILL3_OFFSET 0XFD401900
+#undef SERDES_L0_TM_E_ILL3_OFFSET
+#define SERDES_L0_TM_E_ILL3_OFFSET 0XFD40192C
+#undef SERDES_L0_TM_ILL8_OFFSET
+#define SERDES_L0_TM_ILL8_OFFSET 0XFD401980
+#undef SERDES_L0_TM_IQ_ILL8_OFFSET
+#define SERDES_L0_TM_IQ_ILL8_OFFSET 0XFD401914
+#undef SERDES_L0_TM_IQ_ILL9_OFFSET
+#define SERDES_L0_TM_IQ_ILL9_OFFSET 0XFD401918
+#undef SERDES_L0_TM_E_ILL8_OFFSET
+#define SERDES_L0_TM_E_ILL8_OFFSET 0XFD401940
+#undef SERDES_L0_TM_E_ILL9_OFFSET
+#define SERDES_L0_TM_E_ILL9_OFFSET 0XFD401944
+#undef SERDES_L2_TM_MISC2_OFFSET
+#define SERDES_L2_TM_MISC2_OFFSET 0XFD40989C
+#undef SERDES_L2_TM_IQ_ILL1_OFFSET
+#define SERDES_L2_TM_IQ_ILL1_OFFSET 0XFD4098F8
+#undef SERDES_L2_TM_IQ_ILL2_OFFSET
+#define SERDES_L2_TM_IQ_ILL2_OFFSET 0XFD4098FC
+#undef SERDES_L2_TM_ILL12_OFFSET
+#define SERDES_L2_TM_ILL12_OFFSET 0XFD409990
+#undef SERDES_L2_TM_E_ILL1_OFFSET
+#define SERDES_L2_TM_E_ILL1_OFFSET 0XFD409924
+#undef SERDES_L2_TM_E_ILL2_OFFSET
+#define SERDES_L2_TM_E_ILL2_OFFSET 0XFD409928
+#undef SERDES_L2_TM_IQ_ILL3_OFFSET
+#define SERDES_L2_TM_IQ_ILL3_OFFSET 0XFD409900
+#undef SERDES_L2_TM_E_ILL3_OFFSET
+#define SERDES_L2_TM_E_ILL3_OFFSET 0XFD40992C
+#undef SERDES_L2_TM_ILL8_OFFSET
+#define SERDES_L2_TM_ILL8_OFFSET 0XFD409980
+#undef SERDES_L2_TM_IQ_ILL8_OFFSET
+#define SERDES_L2_TM_IQ_ILL8_OFFSET 0XFD409914
+#undef SERDES_L2_TM_IQ_ILL9_OFFSET
+#define SERDES_L2_TM_IQ_ILL9_OFFSET 0XFD409918
+#undef SERDES_L2_TM_E_ILL8_OFFSET
+#define SERDES_L2_TM_E_ILL8_OFFSET 0XFD409940
+#undef SERDES_L2_TM_E_ILL9_OFFSET
+#define SERDES_L2_TM_E_ILL9_OFFSET 0XFD409944
+#undef SERDES_L3_TM_MISC2_OFFSET
+#define SERDES_L3_TM_MISC2_OFFSET 0XFD40D89C
+#undef SERDES_L3_TM_IQ_ILL1_OFFSET
+#define SERDES_L3_TM_IQ_ILL1_OFFSET 0XFD40D8F8
+#undef SERDES_L3_TM_IQ_ILL2_OFFSET
+#define SERDES_L3_TM_IQ_ILL2_OFFSET 0XFD40D8FC
+#undef SERDES_L3_TM_ILL12_OFFSET
+#define SERDES_L3_TM_ILL12_OFFSET 0XFD40D990
+#undef SERDES_L3_TM_E_ILL1_OFFSET
+#define SERDES_L3_TM_E_ILL1_OFFSET 0XFD40D924
+#undef SERDES_L3_TM_E_ILL2_OFFSET
+#define SERDES_L3_TM_E_ILL2_OFFSET 0XFD40D928
+#undef SERDES_L3_TM_ILL11_OFFSET
+#define SERDES_L3_TM_ILL11_OFFSET 0XFD40D98C
+#undef SERDES_L3_TM_IQ_ILL3_OFFSET
+#define SERDES_L3_TM_IQ_ILL3_OFFSET 0XFD40D900
+#undef SERDES_L3_TM_E_ILL3_OFFSET
+#define SERDES_L3_TM_E_ILL3_OFFSET 0XFD40D92C
+#undef SERDES_L3_TM_ILL8_OFFSET
+#define SERDES_L3_TM_ILL8_OFFSET 0XFD40D980
+#undef SERDES_L3_TM_IQ_ILL8_OFFSET
+#define SERDES_L3_TM_IQ_ILL8_OFFSET 0XFD40D914
+#undef SERDES_L3_TM_IQ_ILL9_OFFSET
+#define SERDES_L3_TM_IQ_ILL9_OFFSET 0XFD40D918
+#undef SERDES_L3_TM_E_ILL8_OFFSET
+#define SERDES_L3_TM_E_ILL8_OFFSET 0XFD40D940
+#undef SERDES_L3_TM_E_ILL9_OFFSET
+#define SERDES_L3_TM_E_ILL9_OFFSET 0XFD40D944
+#undef SERDES_L0_TM_DIG_21_OFFSET
+#define SERDES_L0_TM_DIG_21_OFFSET 0XFD4010A8
+#undef SERDES_L0_TM_DIG_10_OFFSET
+#define SERDES_L0_TM_DIG_10_OFFSET 0XFD40107C
+#undef SERDES_L0_TM_RST_DLY_OFFSET
+#define SERDES_L0_TM_RST_DLY_OFFSET 0XFD4019A4
+#undef SERDES_L0_TM_ANA_BYP_15_OFFSET
+#define SERDES_L0_TM_ANA_BYP_15_OFFSET 0XFD401038
+#undef SERDES_L0_TM_ANA_BYP_12_OFFSET
+#define SERDES_L0_TM_ANA_BYP_12_OFFSET 0XFD40102C
+#undef SERDES_L1_TM_RST_DLY_OFFSET
+#define SERDES_L1_TM_RST_DLY_OFFSET 0XFD4059A4
+#undef SERDES_L1_TM_ANA_BYP_15_OFFSET
+#define SERDES_L1_TM_ANA_BYP_15_OFFSET 0XFD405038
+#undef SERDES_L1_TM_ANA_BYP_12_OFFSET
+#define SERDES_L1_TM_ANA_BYP_12_OFFSET 0XFD40502C
+#undef SERDES_L2_TM_RST_DLY_OFFSET
+#define SERDES_L2_TM_RST_DLY_OFFSET 0XFD4099A4
+#undef SERDES_L2_TM_ANA_BYP_15_OFFSET
+#define SERDES_L2_TM_ANA_BYP_15_OFFSET 0XFD409038
+#undef SERDES_L2_TM_ANA_BYP_12_OFFSET
+#define SERDES_L2_TM_ANA_BYP_12_OFFSET 0XFD40902C
+#undef SERDES_L3_TM_RST_DLY_OFFSET
+#define SERDES_L3_TM_RST_DLY_OFFSET 0XFD40D9A4
+#undef SERDES_L3_TM_ANA_BYP_15_OFFSET
+#define SERDES_L3_TM_ANA_BYP_15_OFFSET 0XFD40D038
+#undef SERDES_L3_TM_ANA_BYP_12_OFFSET
+#define SERDES_L3_TM_ANA_BYP_12_OFFSET 0XFD40D02C
#undef SERDES_ICM_CFG0_OFFSET
#define SERDES_ICM_CFG0_OFFSET 0XFD410010
#undef SERDES_ICM_CFG1_OFFSET
@@ -24516,10 +25462,22 @@
#define SERDES_L1_TXPMD_TM_45_OFFSET 0XFD404CB4
#undef SERDES_L1_TX_ANA_TM_118_OFFSET
#define SERDES_L1_TX_ANA_TM_118_OFFSET 0XFD4041D8
+#undef SERDES_L3_TX_ANA_TM_118_OFFSET
+#define SERDES_L3_TX_ANA_TM_118_OFFSET 0XFD40C1D8
+#undef SERDES_L3_TM_CDR5_OFFSET
+#define SERDES_L3_TM_CDR5_OFFSET 0XFD40DC14
+#undef SERDES_L3_TM_CDR16_OFFSET
+#define SERDES_L3_TM_CDR16_OFFSET 0XFD40DC40
+#undef SERDES_L3_TM_EQ0_OFFSET
+#define SERDES_L3_TM_EQ0_OFFSET 0XFD40D94C
+#undef SERDES_L3_TM_EQ1_OFFSET
+#define SERDES_L3_TM_EQ1_OFFSET 0XFD40D950
#undef SERDES_L1_TXPMD_TM_48_OFFSET
#define SERDES_L1_TXPMD_TM_48_OFFSET 0XFD404CC0
#undef SERDES_L1_TX_ANA_TM_18_OFFSET
#define SERDES_L1_TX_ANA_TM_18_OFFSET 0XFD404048
+#undef SERDES_L3_TX_ANA_TM_18_OFFSET
+#define SERDES_L3_TX_ANA_TM_18_OFFSET 0XFD40C048
/*PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
@@ -24921,6 +25879,486 @@
#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT 4
#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK 0x000000F0U
+/*Spare- not used*/
+#undef SERDES_L0_TM_AUX_0_BIT_2_DEFVAL
+#undef SERDES_L0_TM_AUX_0_BIT_2_SHIFT
+#undef SERDES_L0_TM_AUX_0_BIT_2_MASK
+#define SERDES_L0_TM_AUX_0_BIT_2_DEFVAL 0x00000000
+#define SERDES_L0_TM_AUX_0_BIT_2_SHIFT 5
+#define SERDES_L0_TM_AUX_0_BIT_2_MASK 0x00000020U
+
+/*Spare- not used*/
+#undef SERDES_L2_TM_AUX_0_BIT_2_DEFVAL
+#undef SERDES_L2_TM_AUX_0_BIT_2_SHIFT
+#undef SERDES_L2_TM_AUX_0_BIT_2_MASK
+#define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL 0x00000000
+#define SERDES_L2_TM_AUX_0_BIT_2_SHIFT 5
+#define SERDES_L2_TM_AUX_0_BIT_2_MASK 0x00000020U
+
+/*Enable Eye Surf*/
+#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL
+#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT
+#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK
+#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000
+#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
+#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
+
+/*Enable Eye Surf*/
+#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL
+#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT
+#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK
+#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000
+#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
+#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
+
+/*Enable Eye Surf*/
+#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL
+#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT
+#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK
+#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000
+#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
+#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
+
+/*Enable Eye Surf*/
+#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL
+#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT
+#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK
+#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000
+#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
+#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
+
+/*ILL calib counts BYPASSED with calcode bits*/
+#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
+#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
+#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000
+#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7
+#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U
+
+/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
+#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
+#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
+#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
+#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000
+#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0
+#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU
+
+/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
+#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
+#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
+#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
+#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000
+#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0
+#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU
+
+/*G1A pll ctr bypass value*/
+#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
+#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
+#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
+#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000
+#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0
+#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU
+
+/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
+#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
+#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
+#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000
+#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0
+#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU
+
+/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
+#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
+#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
+#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000
+#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0
+#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU
+
+/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
+#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
+#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
+#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
+#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000
+#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0
+#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU
+
+/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
+#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
+#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
+#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000
+#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0
+#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU
+
+/*ILL calibration code change wait time*/
+#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
+#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
+#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002
+#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0
+#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU
+
+/*IQ ILL polytrim bypass value*/
+#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
+#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
+#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000
+#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0
+#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU
+
+/*bypass IQ polytrim*/
+#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
+#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
+#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000
+#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0
+#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U
+
+/*E ILL polytrim bypass value*/
+#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
+#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000
+#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0
+#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU
+
+/*bypass E polytrim*/
+#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
+#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
+#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000
+#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0
+#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U
+
+/*ILL calib counts BYPASSED with calcode bits*/
+#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
+#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
+#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000
+#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7
+#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U
+
+/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
+#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
+#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
+#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
+#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000
+#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0
+#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU
+
+/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
+#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
+#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
+#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
+#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000
+#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0
+#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU
+
+/*G1A pll ctr bypass value*/
+#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
+#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
+#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
+#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000
+#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0
+#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU
+
+/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
+#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
+#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
+#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000
+#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0
+#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU
+
+/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
+#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
+#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
+#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000
+#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0
+#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU
+
+/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
+#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
+#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
+#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
+#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000
+#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0
+#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU
+
+/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
+#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
+#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
+#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000
+#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0
+#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU
+
+/*ILL calibration code change wait time*/
+#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
+#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
+#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002
+#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0
+#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU
+
+/*IQ ILL polytrim bypass value*/
+#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
+#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
+#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000
+#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0
+#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU
+
+/*bypass IQ polytrim*/
+#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
+#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
+#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000
+#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0
+#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U
+
+/*E ILL polytrim bypass value*/
+#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
+#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000
+#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0
+#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU
+
+/*bypass E polytrim*/
+#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
+#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
+#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000
+#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0
+#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U
+
+/*ILL calib counts BYPASSED with calcode bits*/
+#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
+#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
+#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000
+#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7
+#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U
+
+/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
+#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
+#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
+#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
+#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000
+#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0
+#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU
+
+/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
+#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
+#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
+#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
+#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000
+#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0
+#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU
+
+/*G1A pll ctr bypass value*/
+#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
+#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
+#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
+#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000
+#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0
+#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU
+
+/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
+#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
+#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
+#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000
+#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0
+#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU
+
+/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
+#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
+#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
+#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000
+#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0
+#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU
+
+/*G2A_PCIe1 PLL ctr bypass value*/
+#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL
+#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT
+#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK
+#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL 0x00000000
+#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT 4
+#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK 0x000000F0U
+
+/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
+#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
+#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
+#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
+#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000
+#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0
+#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU
+
+/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
+#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
+#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
+#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000
+#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0
+#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU
+
+/*ILL calibration code change wait time*/
+#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
+#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
+#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002
+#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0
+#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU
+
+/*IQ ILL polytrim bypass value*/
+#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
+#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
+#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000
+#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0
+#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU
+
+/*bypass IQ polytrim*/
+#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
+#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
+#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000
+#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0
+#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U
+
+/*E ILL polytrim bypass value*/
+#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
+#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000
+#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0
+#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU
+
+/*bypass E polytrim*/
+#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
+#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
+#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000
+#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0
+#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U
+
+/*pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20*/
+#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL
+#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT
+#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK
+#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL 0x00000000
+#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT 0
+#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK 0x00000003U
+
+/*CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001*/
+#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL
+#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
+#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK
+#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001
+#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0
+#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU
+
+/*Delay apb reset by specified amount*/
+#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL
+#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT
+#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK
+#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
+#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 0
+#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_15*/
+#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
+#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
+#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
+#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
+#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_12*/
+#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
+#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
+#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
+#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
+#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
+
+/*Delay apb reset by specified amount*/
+#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL
+#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT
+#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK
+#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
+#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 0
+#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_15*/
+#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
+#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
+#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
+#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
+#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_12*/
+#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
+#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
+#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
+#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
+#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
+
+/*Delay apb reset by specified amount*/
+#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL
+#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT
+#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK
+#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
+#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 0
+#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_15*/
+#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
+#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
+#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
+#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
+#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_12*/
+#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
+#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
+#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
+#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
+#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
+
+/*Delay apb reset by specified amount*/
+#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL
+#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT
+#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK
+#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
+#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 0
+#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_15*/
+#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
+#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
+#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
+#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
+#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_12*/
+#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
+#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
+#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
+#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
+#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
+
/*Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
, 7 - Unused*/
#undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL
@@ -25005,6 +26443,62 @@
#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0
#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U
+/*Test register force for enabling/disablign TX deemphasis bits <17:0>*/
+#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL
+#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
+#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK
+#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000
+#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0
+#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U
+
+/*FPHL FSM accumulate cycles*/
+#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL
+#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT
+#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK
+#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL 0x00000000
+#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT 5
+#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK 0x000000E0U
+
+/*FFL Phase0 int gain aka 2ol SD update rate*/
+#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL
+#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT
+#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK
+#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL 0x00000000
+#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT 0
+#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK 0x0000001FU
+
+/*FFL Phase0 prop gain aka 1ol SD update rate*/
+#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL
+#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT
+#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK
+#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL 0x00000000
+#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT 0
+#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK 0x0000001FU
+
+/*EQ stg 2 controls BYPASSED*/
+#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL
+#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT
+#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK
+#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL 0x00000000
+#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT 5
+#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK 0x00000020U
+
+/*EQ STG2 RL PROG*/
+#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL
+#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT
+#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK
+#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL 0x00000000
+#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT 0
+#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK 0x00000003U
+
+/*EQ stg 2 preamp mode val*/
+#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL
+#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT
+#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK
+#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL 0x00000000
+#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT 2
+#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK 0x00000004U
+
/*Margining factor value*/
#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL
#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
@@ -25020,10 +26514,20 @@
#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002
#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0
#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU
+
+/*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/
+#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL
+#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
+#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK
+#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002
+#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0
+#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU
#undef CRL_APB_RST_LPD_TOP_OFFSET
#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
#undef USB3_0_FPD_POWER_PRSNT_OFFSET
#define USB3_0_FPD_POWER_PRSNT_OFFSET 0XFF9D0080
+#undef USB3_0_FPD_PIPE_CLK_OFFSET
+#define USB3_0_FPD_PIPE_CLK_OFFSET 0XFF9D007C
#undef CRL_APB_RST_LPD_TOP_OFFSET
#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
#undef CRL_APB_RST_LPD_IOU0_OFFSET
@@ -25044,8 +26548,6 @@
#define USB3_0_XHCI_GUSB2PHYCFG_OFFSET 0XFE20C200
#undef USB3_0_XHCI_GFLADJ_OFFSET
#define USB3_0_XHCI_GFLADJ_OFFSET 0XFE20C630
-#undef PCIE_ATTRIB_ATTR_37_OFFSET
-#define PCIE_ATTRIB_ATTR_37_OFFSET 0XFD480094
#undef PCIE_ATTRIB_ATTR_25_OFFSET
#define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064
#undef PCIE_ATTRIB_ATTR_7_OFFSET
@@ -25120,6 +26622,30 @@
#define PCIE_ATTRIB_ATTR_79_OFFSET 0XFD48013C
#undef PCIE_ATTRIB_ATTR_43_OFFSET
#define PCIE_ATTRIB_ATTR_43_OFFSET 0XFD4800AC
+#undef PCIE_ATTRIB_ATTR_48_OFFSET
+#define PCIE_ATTRIB_ATTR_48_OFFSET 0XFD4800C0
+#undef PCIE_ATTRIB_ATTR_46_OFFSET
+#define PCIE_ATTRIB_ATTR_46_OFFSET 0XFD4800B8
+#undef PCIE_ATTRIB_ATTR_47_OFFSET
+#define PCIE_ATTRIB_ATTR_47_OFFSET 0XFD4800BC
+#undef PCIE_ATTRIB_ATTR_44_OFFSET
+#define PCIE_ATTRIB_ATTR_44_OFFSET 0XFD4800B0
+#undef PCIE_ATTRIB_ATTR_45_OFFSET
+#define PCIE_ATTRIB_ATTR_45_OFFSET 0XFD4800B4
+#undef PCIE_ATTRIB_CB_OFFSET
+#define PCIE_ATTRIB_CB_OFFSET 0XFD48031C
+#undef PCIE_ATTRIB_ATTR_35_OFFSET
+#define PCIE_ATTRIB_ATTR_35_OFFSET 0XFD48008C
+#undef CRF_APB_RST_FPD_TOP_OFFSET
+#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
+#undef SATA_AHCI_VENDOR_PP2C_OFFSET
+#define SATA_AHCI_VENDOR_PP2C_OFFSET 0XFD0C00AC
+#undef SATA_AHCI_VENDOR_PP3C_OFFSET
+#define SATA_AHCI_VENDOR_PP3C_OFFSET 0XFD0C00B0
+#undef SATA_AHCI_VENDOR_PP4C_OFFSET
+#define SATA_AHCI_VENDOR_PP4C_OFFSET 0XFD0C00B4
+#undef SATA_AHCI_VENDOR_PP5C_OFFSET
+#define SATA_AHCI_VENDOR_PP5C_OFFSET 0XFD0C00B8
/*USB 0 reset for control registers*/
#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
@@ -25137,6 +26663,14 @@
#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 0
#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U
+/*This bit is used to choose between PIPE clock coming from SerDes and the suspend clk*/
+#undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL
+#undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT
+#undef USB3_0_FPD_PIPE_CLK_OPTION_MASK
+#define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL
+#define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 0
+#define USB3_0_FPD_PIPE_CLK_OPTION_MASK 0x00000001U
+
/*USB 0 sleep circuit reset*/
#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
@@ -25185,14 +26719,6 @@
#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19
#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U
-/*PCIE control block level reset*/
-#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL
-#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
-#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK
-#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE
-#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17
-#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U
-
/*PCIE bridge block level reset (AXI interface)*/
#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL
#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
@@ -25278,20 +26804,6 @@
#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7
#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U
-/*Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
- figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
- ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
- r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
- t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
- g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
- when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.*/
-#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL
-#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT
-#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK
-#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 0x00000000
-#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 6
-#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 0x00000040U
-
/*Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
@@ -25357,51 +26869,6 @@
#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8
#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U
-/*Status Read value of PLL Lock*/
-#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
-#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
-#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
-#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
-#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
-#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
-#define SERDES_L0_PLL_STATUS_READ_1_OFFSET 0XFD4023E4
-
-/*Status Read value of PLL Lock*/
-#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
-#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
-#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
-#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
-#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
-#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
-#define SERDES_L1_PLL_STATUS_READ_1_OFFSET 0XFD4063E4
-
-/*Status Read value of PLL Lock*/
-#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
-#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
-#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
-#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
-#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
-#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
-#define SERDES_L2_PLL_STATUS_READ_1_OFFSET 0XFD40A3E4
-
-/*Status Read value of PLL Lock*/
-#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
-#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
-#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
-#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
-#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
-#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
-#define SERDES_L3_PLL_STATUS_READ_1_OFFSET 0XFD40E3E4
-
-/*Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
- gister.; EP=0x0001; RP=0x0001*/
-#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL
-#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
-#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK
-#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF
-#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14
-#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U
-
/*If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001*/
#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL
@@ -25827,6 +27294,15 @@
#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 9
#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 0x00000200U
+/*Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
+ gister.; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U
+
/*Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L
_REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000*/
#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL
@@ -25957,6 +27433,229 @@
#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 0x00000100
#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 8
#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 0x00000100U
+
+/*MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note
+ hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL
+#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT
+#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK
+#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL
+#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT 0
+#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK 0x000007FFU
+
+/*MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001;
+ P=0x0000*/
+#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
+#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
+#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK
+#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
+#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0
+#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x0000FFFFU
+
+/*MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000;
+ P=0x0000*/
+#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
+#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
+#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK
+#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
+#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0
+#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x00001FFFU
+
+/*MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
+ 0x0001; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL
+#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
+#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK
+#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL
+#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 0
+#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFFFU
+
+/*MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
+ 0x1000; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL
+#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
+#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK
+#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 0x00008000
+#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 3
+#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFF8U
+
+/*DT837748 Enable*/
+#undef PCIE_ATTRIB_CB_CB1_DEFVAL
+#undef PCIE_ATTRIB_CB_CB1_SHIFT
+#undef PCIE_ATTRIB_CB_CB1_MASK
+#define PCIE_ATTRIB_CB_CB1_DEFVAL 0x00000001
+#define PCIE_ATTRIB_CB_CB1_SHIFT 1
+#define PCIE_ATTRIB_CB_CB1_MASK 0x00000002U
+
+/*Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc
+ ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL
+#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT
+#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK
+#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 0x00001FFD
+#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 12
+#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 0x00003000U
+
+/*PCIE control block level reset*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U
+
+/*Status Read value of PLL Lock*/
+#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
+#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
+#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
+#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
+#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
+#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
+#define SERDES_L0_PLL_STATUS_READ_1_OFFSET 0XFD4023E4
+
+/*Status Read value of PLL Lock*/
+#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
+#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
+#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
+#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
+#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
+#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
+#define SERDES_L1_PLL_STATUS_READ_1_OFFSET 0XFD4063E4
+
+/*Status Read value of PLL Lock*/
+#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
+#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
+#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
+#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
+#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
+#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
+#define SERDES_L2_PLL_STATUS_READ_1_OFFSET 0XFD40A3E4
+
+/*Status Read value of PLL Lock*/
+#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
+#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
+#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
+#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
+#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
+#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
+#define SERDES_L3_PLL_STATUS_READ_1_OFFSET 0XFD40E3E4
+
+/*CIBGMN: COMINIT Burst Gap Minimum.*/
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK
+#define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL 0x28184D1B
+#define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT 0
+#define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK 0x000000FFU
+
+/*CIBGMX: COMINIT Burst Gap Maximum.*/
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK
+#define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL 0x28184D1B
+#define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT 8
+#define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK 0x0000FF00U
+
+/*CIBGN: COMINIT Burst Gap Nominal.*/
+#undef SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL
+#undef SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT
+#undef SATA_AHCI_VENDOR_PP2C_CIBGN_MASK
+#define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL 0x28184D1B
+#define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT 16
+#define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK 0x00FF0000U
+
+/*CINMP: COMINIT Negate Minimum Period.*/
+#undef SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL
+#undef SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT
+#undef SATA_AHCI_VENDOR_PP2C_CINMP_MASK
+#define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL 0x28184D1B
+#define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT 24
+#define SATA_AHCI_VENDOR_PP2C_CINMP_MASK 0xFF000000U
+
+/*CWBGMN: COMWAKE Burst Gap Minimum.*/
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK
+#define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL 0x0E081906
+#define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT 0
+#define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK 0x000000FFU
+
+/*CWBGMX: COMWAKE Burst Gap Maximum.*/
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK
+#define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL 0x0E081906
+#define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT 8
+#define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK 0x0000FF00U
+
+/*CWBGN: COMWAKE Burst Gap Nominal.*/
+#undef SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL
+#undef SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT
+#undef SATA_AHCI_VENDOR_PP3C_CWBGN_MASK
+#define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL 0x0E081906
+#define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT 16
+#define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK 0x00FF0000U
+
+/*CWNMP: COMWAKE Negate Minimum Period.*/
+#undef SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL
+#undef SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT
+#undef SATA_AHCI_VENDOR_PP3C_CWNMP_MASK
+#define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL 0x0E081906
+#define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT 24
+#define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK 0xFF000000U
+
+/*BMX: COM Burst Maximum.*/
+#undef SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL
+#undef SATA_AHCI_VENDOR_PP4C_BMX_SHIFT
+#undef SATA_AHCI_VENDOR_PP4C_BMX_MASK
+#define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL 0x064A0813
+#define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT 0
+#define SATA_AHCI_VENDOR_PP4C_BMX_MASK 0x000000FFU
+
+/*BNM: COM Burst Nominal.*/
+#undef SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL
+#undef SATA_AHCI_VENDOR_PP4C_BNM_SHIFT
+#undef SATA_AHCI_VENDOR_PP4C_BNM_MASK
+#define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL 0x064A0813
+#define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT 8
+#define SATA_AHCI_VENDOR_PP4C_BNM_MASK 0x0000FF00U
+
+/*SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det
+ rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa
+ Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of
+ 500ns based on a 150MHz PMCLK.*/
+#undef SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL
+#undef SATA_AHCI_VENDOR_PP4C_SFD_SHIFT
+#undef SATA_AHCI_VENDOR_PP4C_SFD_MASK
+#define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL 0x064A0813
+#define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT 16
+#define SATA_AHCI_VENDOR_PP4C_SFD_MASK 0x00FF0000U
+
+/*PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th
+ value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128*/
+#undef SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL
+#undef SATA_AHCI_VENDOR_PP4C_PTST_SHIFT
+#undef SATA_AHCI_VENDOR_PP4C_PTST_MASK
+#define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL 0x064A0813
+#define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT 24
+#define SATA_AHCI_VENDOR_PP4C_PTST_MASK 0xFF000000U
+
+/*RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed.*/
+#undef SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL
+#undef SATA_AHCI_VENDOR_PP5C_RIT_SHIFT
+#undef SATA_AHCI_VENDOR_PP5C_RIT_MASK
+#define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL 0x3FFC96A4
+#define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT 0
+#define SATA_AHCI_VENDOR_PP5C_RIT_MASK 0x000FFFFFU
+
+/*RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha
+ completed, for a fast SERDES it is suggested that this value be 54.2us / 4*/
+#undef SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL
+#undef SATA_AHCI_VENDOR_PP5C_RCT_SHIFT
+#undef SATA_AHCI_VENDOR_PP5C_RCT_MASK
+#define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL 0x3FFC96A4
+#define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT 20
+#define SATA_AHCI_VENDOR_PP5C_RCT_MASK 0xFFF00000U
#undef CRL_APB_RST_LPD_TOP_OFFSET
#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
#undef CRL_APB_RST_LPD_IOU0_OFFSET
@@ -26155,6 +27854,13 @@ extern "C" {
int psu_init ();
unsigned long psu_ps_pl_isolation_removal_data();
unsigned long psu_ps_pl_reset_config_data();
+ int psu_protection();
+ int psu_fpd_protection();
+ int psu_ocm_protection();
+ int psu_ddr_protection();
+ int psu_lpd_protection();
+ int psu_protection_lock();
+ unsigned long psu_apply_master_tz();
#ifdef __cplusplus
}
#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl
index ce5a46e85..b6d9c0418 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl
@@ -521,69 +521,6 @@ set psu_pll_init_data {
set psu_clock_init_data {
# : CLOCK CONTROL SLCR REGISTER
- # Register : GEM0_REF_CTRL @ 0XFF5E0050
-
- # Clock active for the RX channel
- # PSU_CRL_APB_GEM0_REF_CTRL_RX_CLKACT 0x1
-
- # Clock active signal. Switch to 0 to disable the clock
- # PSU_CRL_APB_GEM0_REF_CTRL_CLKACT 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR1 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR0 0x8
-
- # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- # clock. This is not usually an issue, but designers must be aware.)
- # PSU_CRL_APB_GEM0_REF_CTRL_SRCSEL 0x0
-
- # This register controls this reference clock
- #(OFFSET, MASK, VALUE) (0XFF5E0050, 0x063F3F07U ,0x06010800U) */
- mask_write 0XFF5E0050 0x063F3F07 0x06010800
- # Register : GEM1_REF_CTRL @ 0XFF5E0054
-
- # Clock active for the RX channel
- # PSU_CRL_APB_GEM1_REF_CTRL_RX_CLKACT 0x1
-
- # Clock active signal. Switch to 0 to disable the clock
- # PSU_CRL_APB_GEM1_REF_CTRL_CLKACT 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR1 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR0 0x8
-
- # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- # clock. This is not usually an issue, but designers must be aware.)
- # PSU_CRL_APB_GEM1_REF_CTRL_SRCSEL 0x0
-
- # This register controls this reference clock
- #(OFFSET, MASK, VALUE) (0XFF5E0054, 0x063F3F07U ,0x06010800U) */
- mask_write 0XFF5E0054 0x063F3F07 0x06010800
- # Register : GEM2_REF_CTRL @ 0XFF5E0058
-
- # Clock active for the RX channel
- # PSU_CRL_APB_GEM2_REF_CTRL_RX_CLKACT 0x1
-
- # Clock active signal. Switch to 0 to disable the clock
- # PSU_CRL_APB_GEM2_REF_CTRL_CLKACT 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR1 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR0 0x8
-
- # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- # clock. This is not usually an issue, but designers must be aware.)
- # PSU_CRL_APB_GEM2_REF_CTRL_SRCSEL 0x0
-
- # This register controls this reference clock
- #(OFFSET, MASK, VALUE) (0XFF5E0058, 0x063F3F07U ,0x06010800U) */
- mask_write 0XFF5E0058 0x063F3F07 0x06010800
# Register : GEM3_REF_CTRL @ 0XFF5E005C
# Clock active for the RX channel
@@ -605,24 +542,6 @@ set psu_clock_init_data {
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U) */
mask_write 0XFF5E005C 0x063F3F07 0x06010C00
- # Register : GEM_TSU_REF_CTRL @ 0XFF5E0100
-
- # 6 bit divider
- # PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6
-
- # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- # clock. This is not usually an issue, but designers must be aware.)
- # PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x2
-
- # 6 bit divider
- # PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1
-
- # Clock active signal. Switch to 0 to disable the clock
- # PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1
-
- # This register controls this reference clock
- #(OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010602U) */
- mask_write 0XFF5E0100 0x013F3F07 0x01010602
# Register : USB0_BUS_REF_CTRL @ 0XFF5E0060
# Clock active signal. Switch to 0 to disable the clock
@@ -641,24 +560,6 @@ set psu_clock_init_data {
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U) */
mask_write 0XFF5E0060 0x023F3F07 0x02010600
- # Register : USB1_BUS_REF_CTRL @ 0XFF5E0064
-
- # Clock active signal. Switch to 0 to disable the clock
- # PSU_CRL_APB_USB1_BUS_REF_CTRL_CLKACT 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0 0x4
-
- # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- # clock. This is not usually an issue, but designers must be aware.)
- # PSU_CRL_APB_USB1_BUS_REF_CTRL_SRCSEL 0x0
-
- # This register controls this reference clock
- #(OFFSET, MASK, VALUE) (0XFF5E0064, 0x023F3F07U ,0x02010400U) */
- mask_write 0XFF5E0064 0x023F3F07 0x02010400
# Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C
# Clock active signal. Switch to 0 to disable the clock
@@ -695,24 +596,6 @@ set psu_clock_init_data {
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U) */
mask_write 0XFF5E0068 0x013F3F07 0x01010C00
- # Register : SDIO0_REF_CTRL @ 0XFF5E006C
-
- # Clock active signal. Switch to 0 to disable the clock
- # PSU_CRL_APB_SDIO0_REF_CTRL_CLKACT 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR1 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR0 0x7
-
- # 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- # clock. This is not usually an issue, but designers must be aware.)
- # PSU_CRL_APB_SDIO0_REF_CTRL_SRCSEL 0x2
-
- # This register controls this reference clock
- #(OFFSET, MASK, VALUE) (0XFF5E006C, 0x013F3F07U ,0x01010702U) */
- mask_write 0XFF5E006C 0x013F3F07 0x01010702
# Register : SDIO1_REF_CTRL @ 0XFF5E0070
# Clock active signal. Switch to 0 to disable the clock
@@ -811,60 +694,6 @@ set psu_clock_init_data {
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U) */
mask_write 0XFF5E0124 0x013F3F07 0x01010F00
- # Register : SPI0_REF_CTRL @ 0XFF5E007C
-
- # Clock active signal. Switch to 0 to disable the clock
- # PSU_CRL_APB_SPI0_REF_CTRL_CLKACT 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0 0x7
-
- # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- # clock. This is not usually an issue, but designers must be aware.)
- # PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL 0x2
-
- # This register controls this reference clock
- #(OFFSET, MASK, VALUE) (0XFF5E007C, 0x013F3F07U ,0x01010702U) */
- mask_write 0XFF5E007C 0x013F3F07 0x01010702
- # Register : SPI1_REF_CTRL @ 0XFF5E0080
-
- # Clock active signal. Switch to 0 to disable the clock
- # PSU_CRL_APB_SPI1_REF_CTRL_CLKACT 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0 0x7
-
- # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- # clock. This is not usually an issue, but designers must be aware.)
- # PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL 0x2
-
- # This register controls this reference clock
- #(OFFSET, MASK, VALUE) (0XFF5E0080, 0x013F3F07U ,0x01010702U) */
- mask_write 0XFF5E0080 0x013F3F07 0x01010702
- # Register : CAN0_REF_CTRL @ 0XFF5E0084
-
- # Clock active signal. Switch to 0 to disable the clock
- # PSU_CRL_APB_CAN0_REF_CTRL_CLKACT 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR1 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR0 0xa
-
- # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- # clock. This is not usually an issue, but designers must be aware.)
- # PSU_CRL_APB_CAN0_REF_CTRL_SRCSEL 0x0
-
- # This register controls this reference clock
- #(OFFSET, MASK, VALUE) (0XFF5E0084, 0x013F3F07U ,0x01010A00U) */
- mask_write 0XFF5E0084 0x013F3F07 0x01010A00
# Register : CAN1_REF_CTRL @ 0XFF5E0088
# Clock active signal. Switch to 0 to disable the clock
@@ -914,21 +743,6 @@ set psu_clock_init_data {
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U) */
mask_write 0XFF5E009C 0x01003F07 0x01000602
- # Register : CSU_PLL_CTRL @ 0XFF5E00A0
-
- # Clock active signal. Switch to 0 to disable the clock
- # PSU_CRL_APB_CSU_PLL_CTRL_CLKACT 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_CSU_PLL_CTRL_DIVISOR0 0x3
-
- # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- # clock. This is not usually an issue, but designers must be aware.)
- # PSU_CRL_APB_CSU_PLL_CTRL_SRCSEL 0x2
-
- # This register controls this reference clock
- #(OFFSET, MASK, VALUE) (0XFF5E00A0, 0x01003F07U ,0x01000302U) */
- mask_write 0XFF5E00A0 0x01003F07 0x01000302
# Register : PCAP_CTRL @ 0XFF5E00A4
# Clock active signal. Switch to 0 to disable the clock
@@ -989,24 +803,6 @@ set psu_clock_init_data {
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U) */
mask_write 0XFF5E00B0 0x01003F07 0x01000602
- # Register : NAND_REF_CTRL @ 0XFF5E00B4
-
- # Clock active signal. Switch to 0 to disable the clock
- # PSU_CRL_APB_NAND_REF_CTRL_CLKACT 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_NAND_REF_CTRL_DIVISOR1 0x1
-
- # 6 bit divider
- # PSU_CRL_APB_NAND_REF_CTRL_DIVISOR0 0xa
-
- # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- # clock. This is not usually an issue, but designers must be aware.)
- # PSU_CRL_APB_NAND_REF_CTRL_SRCSEL 0x0
-
- # This register controls this reference clock
- #(OFFSET, MASK, VALUE) (0XFF5E00B4, 0x013F3F07U ,0x01010A00U) */
- mask_write 0XFF5E00B4 0x013F3F07 0x01010A00
# Register : ADMA_REF_CTRL @ 0XFF5E00B8
# Clock active signal. Switch to 0 to disable the clock
@@ -1362,21 +1158,6 @@ set psu_clock_init_data {
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U) */
mask_write 0XFD1A00C4 0x01003F07 0x01000502
- # Register : GTGREF0_REF_CTRL @ 0XFD1A00C8
-
- # 6 bit divider
- # PSU_CRF_APB_GTGREF0_REF_CTRL_DIVISOR0 0x4
-
- # 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
- # he new clock. This is not usually an issue, but designers must be aware.)
- # PSU_CRF_APB_GTGREF0_REF_CTRL_SRCSEL 0x0
-
- # Clock active signal. Switch to 0 to disable the clock
- # PSU_CRF_APB_GTGREF0_REF_CTRL_CLKACT 0x1
-
- # This register controls this reference clock
- #(OFFSET, MASK, VALUE) (0XFD1A00C8, 0x01003F07U ,0x01000400U) */
- mask_write 0XFD1A00C8 0x01003F07 0x01000400
# Register : DBG_TSTMP_CTRL @ 0XFD1A00F8
# 6 bit divider
@@ -2246,17 +2027,17 @@ set psu_ddr_init_data {
# ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t
# is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L
# DDR2/LPDDR3/LPDDR4 devices.
- # PSU_DDRC_DRAMTMG7_T_CKPDE 0x1
+ # PSU_DDRC_DRAMTMG7_T_CKPDE 0x6
# This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable
# time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO=
# , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti
# g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
- # PSU_DDRC_DRAMTMG7_T_CKPDX 0x1
+ # PSU_DDRC_DRAMTMG7_T_CKPDX 0x6
# SDRAM Timing Register 7
- #(OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000101U) */
- mask_write 0XFD07011C 0x00000F0F 0x00000101
+ #(OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U) */
+ mask_write 0XFD07011C 0x00000F0F 0x00000606
# Register : DRAMTMG8 @ 0XFD070120
# tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT
@@ -2503,14 +2284,14 @@ set psu_ddr_init_data {
# s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20
# 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107
# cycles - 0xE - 262144 cycles - 0xF - Unlimited
- # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x4
+ # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0
# Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled
# PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1
# DFI Low Power Configuration Register 0
- #(OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000141U) */
- mask_write 0XFD070198 0x0FF1F1F1 0x07000141
+ #(OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U) */
+ mask_write 0XFD070198 0x0FF1F1F1 0x07000101
# Register : DFILPCFG1 @ 0XFD07019C
# Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0
@@ -3906,11 +3687,52 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0
# Refresh Period
- # PSU_DDR_PHY_PGCR2_TREFPRD 0x12302
+ # PSU_DDR_PHY_PGCR2_TREFPRD 0x10028
# PHY General Configuration Register 2
- #(OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F12302U) */
- mask_write 0XFD080018 0xFFFFFFFF 0x00F12302
+ #(OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10028U) */
+ mask_write 0XFD080018 0xFFFFFFFF 0x00F10028
+ # Register : PGCR3 @ 0XFD08001C
+
+ # CKN Enable
+ # PSU_DDR_PHY_PGCR3_CKNEN 0x55
+
+ # CK Enable
+ # PSU_DDR_PHY_PGCR3_CKEN 0xaa
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_PGCR3_RESERVED_15 0x0
+
+ # Enable Clock Gating for AC [0] ctl_rd_clk
+ # PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2
+
+ # Enable Clock Gating for AC [0] ddr_clk
+ # PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2
+
+ # Enable Clock Gating for AC [0] ctl_clk
+ # PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_PGCR3_RESERVED_8 0x0
+
+ # Controls DDL Bypass Modes
+ # PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2
+
+ # IO Loop-Back Select
+ # PSU_DDR_PHY_PGCR3_IOLB 0x0
+
+ # AC Receive FIFO Read Mode
+ # PSU_DDR_PHY_PGCR3_RDMODE 0x0
+
+ # Read FIFO Reset Disable
+ # PSU_DDR_PHY_PGCR3_DISRST 0x0
+
+ # Clock Level when Clock Gating
+ # PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0
+
+ # PHY General Configuration Register 3
+ #(OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U) */
+ mask_write 0XFD08001C 0xFFFFFFFF 0x55AA5480
# Register : PGCR5 @ 0XFD080024
# Frequency B Ratio Term
@@ -4093,17 +3915,17 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DTPR0_RESERVED_15 0x0
# Precharge command period
- # PSU_DDR_PHY_DTPR0_TRP 0x12
+ # PSU_DDR_PHY_DTPR0_TRP 0xf
# Reserved. Return zeroes on reads.
# PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0
# Internal read to precharge command delay
- # PSU_DDR_PHY_DTPR0_TRTP 0x8
+ # PSU_DDR_PHY_DTPR0_TRTP 0x9
# DRAM Timing Parameters Register 0
- #(OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06241208U) */
- mask_write 0XFD080110 0xFFFFFFFF 0x06241208
+ #(OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F09U) */
+ mask_write 0XFD080110 0xFFFFFFFF 0x06240F09
# Register : DTPR1 @ 0XFD080114
# Reserved. Return zeroes on reads.
@@ -4183,11 +4005,11 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0
# DQS output access time from CK/CK# (LPDDR2/3 only)
- # PSU_DDR_PHY_DTPR3_TDQSCK 0x4
+ # PSU_DDR_PHY_DTPR3_TDQSCK 0x0
# DRAM Timing Parameters Register 3
- #(OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000804U) */
- mask_write 0XFD08011C 0xFFFFFFFF 0x83000804
+ #(OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U) */
+ mask_write 0XFD08011C 0xFFFFFFFF 0x83000800
# Register : DTPR4 @ 0XFD080120
# Reserved. Return zeroes on reads.
@@ -4360,6 +4182,37 @@ set psu_ddr_init_data {
# RDIMM General Configuration Register 1
#(OFFSET, MASK, VALUE) (0XFD080144, 0xFFFFFFFFU ,0x00000C80U) */
mask_write 0XFD080144 0xFFFFFFFF 0x00000C80
+ # Register : RDIMMCR0 @ 0XFD080150
+
+ # DDR4/DDR3 Control Word 7
+ # PSU_DDR_PHY_RDIMMCR0_RC7 0x0
+
+ # DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved
+ # PSU_DDR_PHY_RDIMMCR0_RC6 0x0
+
+ # DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)
+ # PSU_DDR_PHY_RDIMMCR0_RC5 0x0
+
+ # DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C
+ # aracteristics Control Word)
+ # PSU_DDR_PHY_RDIMMCR0_RC4 0x0
+
+ # DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr
+ # ver Characteristrics Control Word)
+ # PSU_DDR_PHY_RDIMMCR0_RC3 0x0
+
+ # DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)
+ # PSU_DDR_PHY_RDIMMCR0_RC2 0x0
+
+ # DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)
+ # PSU_DDR_PHY_RDIMMCR0_RC1 0x0
+
+ # DDR4/DDR3 Control Word 0 (Global Features Control Word)
+ # PSU_DDR_PHY_RDIMMCR0_RC0 0x0
+
+ # RDIMM Control Register 0
+ #(OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U) */
+ mask_write 0XFD080150 0xFFFFFFFF 0x00000000
# Register : RDIMMCR1 @ 0XFD080154
# Control Word 15
@@ -4703,7 +4556,7 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0
# Data Training Debug Rank Select
- # PSU_DDR_PHY_DTCR0_DTDRS 0x1
+ # PSU_DDR_PHY_DTCR0_DTDRS 0x0
# Data Training with Early/Extended Gate
# PSU_DDR_PHY_DTCR0_DTEXG 0x0
@@ -4721,7 +4574,7 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DTCR0_DTDBS 0x0
# Data Training read DBI deskewing configuration
- # PSU_DDR_PHY_DTCR0_DTRDBITR 0x0
+ # PSU_DDR_PHY_DTCR0_DTRDBITR 0x2
# Reserved. Return zeroes on reads.
# PSU_DDR_PHY_DTCR0_RESERVED_13 0x0
@@ -4745,8 +4598,8 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DTCR0_DTRPTN 0x7
# Data Training Configuration Register 0
- #(OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x810011C7U) */
- mask_write 0XFD080200 0xFFFFFFFF 0x810011C7
+ #(OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U) */
+ mask_write 0XFD080200 0xFFFFFFFF 0x800091C7
# Register : DTCR1 @ 0XFD080204
# Rank Enable.
@@ -4812,6 +4665,14 @@ set psu_ddr_init_data {
# CA Training Register 0
#(OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U) */
mask_write 0XFD080240 0xFFFFFFFF 0x00141054
+ # Register : BISTLSR @ 0XFD080414
+
+ # LFSR seed for pseudo-random BIST patterns
+ # PSU_DDR_PHY_BISTLSR_SEED 0x12341000
+
+ # BIST LFSR Seed Register
+ #(OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U) */
+ mask_write 0XFD080414 0xFFFFFFFF 0x12341000
# Register : RIOCR5 @ 0XFD0804F4
# Reserved. Return zeroes on reads.
@@ -5045,13 +4906,13 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_VTCR1_SHREN 0x1
# Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training
- # PSU_DDR_PHY_VTCR1_TVREFIO 0x4
+ # PSU_DDR_PHY_VTCR1_TVREFIO 0x7
# Eye LCDL Offset value for VREF training
- # PSU_DDR_PHY_VTCR1_EOFF 0x1
+ # PSU_DDR_PHY_VTCR1_EOFF 0x0
# Number of LCDL Eye points for which VREF training is repeated
- # PSU_DDR_PHY_VTCR1_ENUM 0x1
+ # PSU_DDR_PHY_VTCR1_ENUM 0x0
# HOST (IO) internal VREF training Enable
# PSU_DDR_PHY_VTCR1_HVEN 0x1
@@ -5060,8 +4921,66 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_VTCR1_HVIO 0x1
# VREF Training Control Register 1
- #(OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F0018FU) */
- mask_write 0XFD08052C 0xFFFFFFFF 0x07F0018F
+ #(OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U) */
+ mask_write 0XFD08052C 0xFFFFFFFF 0x07F001E3
+ # Register : ACBDLR1 @ 0XFD080544
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0
+
+ # Delay select for the BDL on Parity.
+ # PSU_DDR_PHY_ACBDLR1_PARBD 0x0
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0
+
+ # Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE.
+ # PSU_DDR_PHY_ACBDLR1_A16BD 0x0
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0
+
+ # Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS.
+ # PSU_DDR_PHY_ACBDLR1_A17BD 0x0
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0
+
+ # Delay select for the BDL on ACTN.
+ # PSU_DDR_PHY_ACBDLR1_ACTBD 0x0
+
+ # AC Bit Delay Line Register 1
+ #(OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U) */
+ mask_write 0XFD080544 0xFFFFFFFF 0x00000000
+ # Register : ACBDLR2 @ 0XFD080548
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0
+
+ # Delay select for the BDL on BG[1].
+ # PSU_DDR_PHY_ACBDLR2_BG1BD 0x0
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0
+
+ # Delay select for the BDL on BG[0].
+ # PSU_DDR_PHY_ACBDLR2_BG0BD 0x0
+
+ # Reser.ved Return zeroes on reads.
+ # PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0
+
+ # Delay select for the BDL on BA[1].
+ # PSU_DDR_PHY_ACBDLR2_BA1BD 0x0
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0
+
+ # Delay select for the BDL on BA[0].
+ # PSU_DDR_PHY_ACBDLR2_BA0BD 0x0
+
+ # AC Bit Delay Line Register 2
+ #(OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U) */
+ mask_write 0XFD080548 0xFFFFFFFF 0x00000000
# Register : ACBDLR6 @ 0XFD080558
# Reserved. Return zeroes on reads.
@@ -5149,6 +5068,35 @@ set psu_ddr_init_data {
# AC Bit Delay Line Register 8
#(OFFSET, MASK, VALUE) (0XFD080560, 0xFFFFFFFFU ,0x00000000U) */
mask_write 0XFD080560 0xFFFFFFFF 0x00000000
+ # Register : ACBDLR9 @ 0XFD080564
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0
+
+ # Delay select for the BDL on Address A[15].
+ # PSU_DDR_PHY_ACBDLR9_A15BD 0x0
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0
+
+ # Delay select for the BDL on Address A[14].
+ # PSU_DDR_PHY_ACBDLR9_A14BD 0x0
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0
+
+ # Delay select for the BDL on Address A[13].
+ # PSU_DDR_PHY_ACBDLR9_A13BD 0x0
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0
+
+ # Delay select for the BDL on Address A[12].
+ # PSU_DDR_PHY_ACBDLR9_A12BD 0x0
+
+ # AC Bit Delay Line Register 9
+ #(OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U) */
+ mask_write 0XFD080564 0xFFFFFFFF 0x00000000
# Register : ZQCR @ 0XFD080680
# Reserved. Return zeroes on reads.
@@ -5430,17 +5378,17 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0
# Byte Lane internal VREF Select for Rank 1
- # PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x55
+ # PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x4f
# Reserved. Returns zeros on reads.
# PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0
# Byte Lane internal VREF Select for Rank 0
- # PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x55
+ # PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x4f
# DATX8 n General Configuration Register 5
- #(OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09095555U) */
- mask_write 0XFD080714 0xFFFFFFFF 0x09095555
+ #(OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09094F4FU) */
+ mask_write 0XFD080714 0xFFFFFFFF 0x09094F4F
# Register : DX0GCR6 @ 0XFD080718
# Reserved. Returns zeros on reads.
@@ -5631,17 +5579,17 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0
# Byte Lane internal VREF Select for Rank 1
- # PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x55
+ # PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x4f
# Reserved. Returns zeros on reads.
# PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0
# Byte Lane internal VREF Select for Rank 0
- # PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x55
+ # PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x4f
# DATX8 n General Configuration Register 5
- #(OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09095555U) */
- mask_write 0XFD080814 0xFFFFFFFF 0x09095555
+ #(OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09094F4FU) */
+ mask_write 0XFD080814 0xFFFFFFFF 0x09094F4F
# Register : DX1GCR6 @ 0XFD080818
# Reserved. Returns zeros on reads.
@@ -5867,17 +5815,17 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0
# Byte Lane internal VREF Select for Rank 1
- # PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x55
+ # PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x4f
# Reserved. Returns zeros on reads.
# PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0
# Byte Lane internal VREF Select for Rank 0
- # PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x55
+ # PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x4f
# DATX8 n General Configuration Register 5
- #(OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09095555U) */
- mask_write 0XFD080914 0xFFFFFFFF 0x09095555
+ #(OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09094F4FU) */
+ mask_write 0XFD080914 0xFFFFFFFF 0x09094F4F
# Register : DX2GCR6 @ 0XFD080918
# Reserved. Returns zeros on reads.
@@ -6103,17 +6051,17 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0
# Byte Lane internal VREF Select for Rank 1
- # PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x55
+ # PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x4f
# Reserved. Returns zeros on reads.
# PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0
# Byte Lane internal VREF Select for Rank 0
- # PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x55
+ # PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x4f
# DATX8 n General Configuration Register 5
- #(OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09095555U) */
- mask_write 0XFD080A14 0xFFFFFFFF 0x09095555
+ #(OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09094F4FU) */
+ mask_write 0XFD080A14 0xFFFFFFFF 0x09094F4F
# Register : DX3GCR6 @ 0XFD080A18
# Reserved. Returns zeros on reads.
@@ -6339,17 +6287,17 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0
# Byte Lane internal VREF Select for Rank 1
- # PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x55
+ # PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x4f
# Reserved. Returns zeros on reads.
# PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0
# Byte Lane internal VREF Select for Rank 0
- # PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x55
+ # PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x4f
# DATX8 n General Configuration Register 5
- #(OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09095555U) */
- mask_write 0XFD080B14 0xFFFFFFFF 0x09095555
+ #(OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09094F4FU) */
+ mask_write 0XFD080B14 0xFFFFFFFF 0x09094F4F
# Register : DX4GCR6 @ 0XFD080B18
# Reserved. Returns zeros on reads.
@@ -6575,17 +6523,17 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0
# Byte Lane internal VREF Select for Rank 1
- # PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x55
+ # PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x4f
# Reserved. Returns zeros on reads.
# PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0
# Byte Lane internal VREF Select for Rank 0
- # PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x55
+ # PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x4f
# DATX8 n General Configuration Register 5
- #(OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09095555U) */
- mask_write 0XFD080C14 0xFFFFFFFF 0x09095555
+ #(OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09094F4FU) */
+ mask_write 0XFD080C14 0xFFFFFFFF 0x09094F4F
# Register : DX5GCR6 @ 0XFD080C18
# Reserved. Returns zeros on reads.
@@ -6811,17 +6759,17 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0
# Byte Lane internal VREF Select for Rank 1
- # PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x55
+ # PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x4f
# Reserved. Returns zeros on reads.
# PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0
# Byte Lane internal VREF Select for Rank 0
- # PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x55
+ # PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x4f
# DATX8 n General Configuration Register 5
- #(OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09095555U) */
- mask_write 0XFD080D14 0xFFFFFFFF 0x09095555
+ #(OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09094F4FU) */
+ mask_write 0XFD080D14 0xFFFFFFFF 0x09094F4F
# Register : DX6GCR6 @ 0XFD080D18
# Reserved. Returns zeros on reads.
@@ -7047,17 +6995,17 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0
# Byte Lane internal VREF Select for Rank 1
- # PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x55
+ # PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x4f
# Reserved. Returns zeros on reads.
# PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0
# Byte Lane internal VREF Select for Rank 0
- # PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x55
+ # PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x4f
# DATX8 n General Configuration Register 5
- #(OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09095555U) */
- mask_write 0XFD080E14 0xFFFFFFFF 0x09095555
+ #(OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09094F4FU) */
+ mask_write 0XFD080E14 0xFFFFFFFF 0x09094F4F
# Register : DX7GCR6 @ 0XFD080E18
# Reserved. Returns zeros on reads.
@@ -7283,17 +7231,17 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0
# Byte Lane internal VREF Select for Rank 1
- # PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x55
+ # PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x4f
# Reserved. Returns zeros on reads.
# PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0
# Byte Lane internal VREF Select for Rank 0
- # PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x55
+ # PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x4f
# DATX8 n General Configuration Register 5
- #(OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09095555U) */
- mask_write 0XFD080F14 0xFFFFFFFF 0x09095555
+ #(OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09094F4FU) */
+ mask_write 0XFD080F14 0xFFFFFFFF 0x09094F4F
# Register : DX8GCR6 @ 0XFD080F18
# Reserved. Returns zeros on reads.
@@ -7369,6 +7317,68 @@ set psu_ddr_init_data {
# DATX8 n General Timing Register 0
#(OFFSET, MASK, VALUE) (0XFD080FC0, 0xFFFFFFFFU ,0x00020000U) */
mask_write 0XFD080FC0 0xFFFFFFFF 0x00020000
+ # Register : DX8SL0OSC @ 0XFD081400
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0
+
+ # Enable Clock Gating for DX ddr_clk
+ # PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2
+
+ # Enable Clock Gating for DX ctl_rd_clk
+ # PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2
+
+ # Enable Clock Gating for DX ctl_clk
+ # PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2
+
+ # Selects the level to which clocks will be stalled when clock gating is enabled.
+ # PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0
+
+ # Loopback Mode
+ # PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0
+
+ # Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
+ # PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0
+
+ # Loopback DQS Gating
+ # PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0
+
+ # Loopback DQS Shift
+ # PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0
+
+ # PHY High-Speed Reset
+ # PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1
+
+ # PHY FIFO Reset
+ # PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1
+
+ # Delay Line Test Start
+ # PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0
+
+ # Delay Line Test Mode
+ # PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0
+
+ # Reserved. Caution, do not write to this register field.
+ # PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3
+
+ # Oscillator Mode Write-Data Delay Line Select
+ # PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3
+
+ # Reserved. Caution, do not write to this register field.
+ # PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3
+
+ # Oscillator Mode Write-Leveling Delay Line Select
+ # PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3
+
+ # Oscillator Mode Division
+ # PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf
+
+ # Oscillator Enable
+ # PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0
+
+ # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
+ #(OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU) */
+ mask_write 0XFD081400 0xFFFFFFFF 0x2A019FFE
# Register : DX8SL0DQSCTL @ 0XFD08141C
# Reserved. Return zeroes on reads.
@@ -7408,14 +7418,14 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3
# DQS_N Resistor
- # PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0xc
+ # PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0
# DQS Resistor
- # PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x4
+ # PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0
# DATX8 0-1 DQS Control Register
- #(OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x012643C4U) */
- mask_write 0XFD08141C 0xFFFFFFFF 0x012643C4
+ #(OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U) */
+ mask_write 0XFD08141C 0xFFFFFFFF 0x01264300
# Register : DX8SL0DXCTL2 @ 0XFD08142C
# Reserved. Return zeroes on reads.
@@ -7428,7 +7438,7 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0
# OE Extension during Pre-amble
- # PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x0
+ # PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1
# Reserved. Return zeroes on reads.
# PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0
@@ -7467,8 +7477,8 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0
# DATX8 0-1 DX Control Register 2
- #(OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00001800U) */
- mask_write 0XFD08142C 0xFFFFFFFF 0x00001800
+ #(OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U) */
+ mask_write 0XFD08142C 0xFFFFFFFF 0x00041800
# Register : DX8SL0IOCR @ 0XFD081430
# Reserved. Return zeroes on reads.
@@ -7492,6 +7502,68 @@ set psu_ddr_init_data {
# DATX8 0-1 I/O Configuration Register
#(OFFSET, MASK, VALUE) (0XFD081430, 0xFFFFFFFFU ,0x70800000U) */
mask_write 0XFD081430 0xFFFFFFFF 0x70800000
+ # Register : DX8SL1OSC @ 0XFD081440
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0
+
+ # Enable Clock Gating for DX ddr_clk
+ # PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2
+
+ # Enable Clock Gating for DX ctl_rd_clk
+ # PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2
+
+ # Enable Clock Gating for DX ctl_clk
+ # PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2
+
+ # Selects the level to which clocks will be stalled when clock gating is enabled.
+ # PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0
+
+ # Loopback Mode
+ # PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0
+
+ # Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
+ # PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0
+
+ # Loopback DQS Gating
+ # PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0
+
+ # Loopback DQS Shift
+ # PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0
+
+ # PHY High-Speed Reset
+ # PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1
+
+ # PHY FIFO Reset
+ # PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1
+
+ # Delay Line Test Start
+ # PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0
+
+ # Delay Line Test Mode
+ # PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0
+
+ # Reserved. Caution, do not write to this register field.
+ # PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3
+
+ # Oscillator Mode Write-Data Delay Line Select
+ # PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3
+
+ # Reserved. Caution, do not write to this register field.
+ # PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3
+
+ # Oscillator Mode Write-Leveling Delay Line Select
+ # PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3
+
+ # Oscillator Mode Division
+ # PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf
+
+ # Oscillator Enable
+ # PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0
+
+ # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
+ #(OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU) */
+ mask_write 0XFD081440 0xFFFFFFFF 0x2A019FFE
# Register : DX8SL1DQSCTL @ 0XFD08145C
# Reserved. Return zeroes on reads.
@@ -7531,14 +7603,14 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3
# DQS_N Resistor
- # PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0xc
+ # PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0
# DQS Resistor
- # PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x4
+ # PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0
# DATX8 0-1 DQS Control Register
- #(OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x012643C4U) */
- mask_write 0XFD08145C 0xFFFFFFFF 0x012643C4
+ #(OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U) */
+ mask_write 0XFD08145C 0xFFFFFFFF 0x01264300
# Register : DX8SL1DXCTL2 @ 0XFD08146C
# Reserved. Return zeroes on reads.
@@ -7551,7 +7623,7 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0
# OE Extension during Pre-amble
- # PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x0
+ # PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1
# Reserved. Return zeroes on reads.
# PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0
@@ -7590,8 +7662,8 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0
# DATX8 0-1 DX Control Register 2
- #(OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00001800U) */
- mask_write 0XFD08146C 0xFFFFFFFF 0x00001800
+ #(OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U) */
+ mask_write 0XFD08146C 0xFFFFFFFF 0x00041800
# Register : DX8SL1IOCR @ 0XFD081470
# Reserved. Return zeroes on reads.
@@ -7615,16 +7687,78 @@ set psu_ddr_init_data {
# DATX8 0-1 I/O Configuration Register
#(OFFSET, MASK, VALUE) (0XFD081470, 0xFFFFFFFFU ,0x70800000U) */
mask_write 0XFD081470 0xFFFFFFFF 0x70800000
- # Register : DX8SL2DQSCTL @ 0XFD08149C
+ # Register : DX8SL2OSC @ 0XFD081480
# Reserved. Return zeroes on reads.
- # PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0
+ # PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0
- # Read Path Rise-to-Rise Mode
- # PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1
+ # Enable Clock Gating for DX ddr_clk
+ # PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2
- # Reserved. Return zeroes on reads.
- # PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0
+ # Enable Clock Gating for DX ctl_rd_clk
+ # PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2
+
+ # Enable Clock Gating for DX ctl_clk
+ # PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2
+
+ # Selects the level to which clocks will be stalled when clock gating is enabled.
+ # PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0
+
+ # Loopback Mode
+ # PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0
+
+ # Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
+ # PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0
+
+ # Loopback DQS Gating
+ # PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0
+
+ # Loopback DQS Shift
+ # PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0
+
+ # PHY High-Speed Reset
+ # PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1
+
+ # PHY FIFO Reset
+ # PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1
+
+ # Delay Line Test Start
+ # PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0
+
+ # Delay Line Test Mode
+ # PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0
+
+ # Reserved. Caution, do not write to this register field.
+ # PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3
+
+ # Oscillator Mode Write-Data Delay Line Select
+ # PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3
+
+ # Reserved. Caution, do not write to this register field.
+ # PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3
+
+ # Oscillator Mode Write-Leveling Delay Line Select
+ # PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3
+
+ # Oscillator Mode Division
+ # PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf
+
+ # Oscillator Enable
+ # PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0
+
+ # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
+ #(OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU) */
+ mask_write 0XFD081480 0xFFFFFFFF 0x2A019FFE
+ # Register : DX8SL2DQSCTL @ 0XFD08149C
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0
+
+ # Read Path Rise-to-Rise Mode
+ # PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0
# Write Path Rise-to-Rise Mode
# PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE 0x1
@@ -7654,14 +7788,14 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3
# DQS_N Resistor
- # PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0xc
+ # PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0
# DQS Resistor
- # PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x4
+ # PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0
# DATX8 0-1 DQS Control Register
- #(OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x012643C4U) */
- mask_write 0XFD08149C 0xFFFFFFFF 0x012643C4
+ #(OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U) */
+ mask_write 0XFD08149C 0xFFFFFFFF 0x01264300
# Register : DX8SL2DXCTL2 @ 0XFD0814AC
# Reserved. Return zeroes on reads.
@@ -7674,7 +7808,7 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0
# OE Extension during Pre-amble
- # PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x0
+ # PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1
# Reserved. Return zeroes on reads.
# PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0
@@ -7713,8 +7847,8 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0
# DATX8 0-1 DX Control Register 2
- #(OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00001800U) */
- mask_write 0XFD0814AC 0xFFFFFFFF 0x00001800
+ #(OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U) */
+ mask_write 0XFD0814AC 0xFFFFFFFF 0x00041800
# Register : DX8SL2IOCR @ 0XFD0814B0
# Reserved. Return zeroes on reads.
@@ -7738,6 +7872,68 @@ set psu_ddr_init_data {
# DATX8 0-1 I/O Configuration Register
#(OFFSET, MASK, VALUE) (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U) */
mask_write 0XFD0814B0 0xFFFFFFFF 0x70800000
+ # Register : DX8SL3OSC @ 0XFD0814C0
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0
+
+ # Enable Clock Gating for DX ddr_clk
+ # PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2
+
+ # Enable Clock Gating for DX ctl_rd_clk
+ # PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2
+
+ # Enable Clock Gating for DX ctl_clk
+ # PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2
+
+ # Selects the level to which clocks will be stalled when clock gating is enabled.
+ # PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0
+
+ # Loopback Mode
+ # PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0
+
+ # Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
+ # PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0
+
+ # Loopback DQS Gating
+ # PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0
+
+ # Loopback DQS Shift
+ # PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0
+
+ # PHY High-Speed Reset
+ # PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1
+
+ # PHY FIFO Reset
+ # PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1
+
+ # Delay Line Test Start
+ # PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0
+
+ # Delay Line Test Mode
+ # PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0
+
+ # Reserved. Caution, do not write to this register field.
+ # PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3
+
+ # Oscillator Mode Write-Data Delay Line Select
+ # PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3
+
+ # Reserved. Caution, do not write to this register field.
+ # PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3
+
+ # Oscillator Mode Write-Leveling Delay Line Select
+ # PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3
+
+ # Oscillator Mode Division
+ # PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf
+
+ # Oscillator Enable
+ # PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0
+
+ # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
+ #(OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU) */
+ mask_write 0XFD0814C0 0xFFFFFFFF 0x2A019FFE
# Register : DX8SL3DQSCTL @ 0XFD0814DC
# Reserved. Return zeroes on reads.
@@ -7777,14 +7973,14 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3
# DQS_N Resistor
- # PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0xc
+ # PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0
# DQS Resistor
- # PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x4
+ # PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0
# DATX8 0-1 DQS Control Register
- #(OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x012643C4U) */
- mask_write 0XFD0814DC 0xFFFFFFFF 0x012643C4
+ #(OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U) */
+ mask_write 0XFD0814DC 0xFFFFFFFF 0x01264300
# Register : DX8SL3DXCTL2 @ 0XFD0814EC
# Reserved. Return zeroes on reads.
@@ -7797,7 +7993,7 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0
# OE Extension during Pre-amble
- # PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x0
+ # PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1
# Reserved. Return zeroes on reads.
# PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0
@@ -7836,8 +8032,8 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0
# DATX8 0-1 DX Control Register 2
- #(OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00001800U) */
- mask_write 0XFD0814EC 0xFFFFFFFF 0x00001800
+ #(OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U) */
+ mask_write 0XFD0814EC 0xFFFFFFFF 0x00041800
# Register : DX8SL3IOCR @ 0XFD0814F0
# Reserved. Return zeroes on reads.
@@ -7861,6 +8057,68 @@ set psu_ddr_init_data {
# DATX8 0-1 I/O Configuration Register
#(OFFSET, MASK, VALUE) (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U) */
mask_write 0XFD0814F0 0xFFFFFFFF 0x70800000
+ # Register : DX8SL4OSC @ 0XFD081500
+
+ # Reserved. Return zeroes on reads.
+ # PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0
+
+ # Enable Clock Gating for DX ddr_clk
+ # PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x2
+
+ # Enable Clock Gating for DX ctl_rd_clk
+ # PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x2
+
+ # Enable Clock Gating for DX ctl_clk
+ # PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x2
+
+ # Selects the level to which clocks will be stalled when clock gating is enabled.
+ # PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0
+
+ # Loopback Mode
+ # PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0
+
+ # Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
+ # PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0
+
+ # Loopback DQS Gating
+ # PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0
+
+ # Loopback DQS Shift
+ # PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0
+
+ # PHY High-Speed Reset
+ # PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1
+
+ # PHY FIFO Reset
+ # PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1
+
+ # Delay Line Test Start
+ # PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0
+
+ # Delay Line Test Mode
+ # PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0
+
+ # Reserved. Caution, do not write to this register field.
+ # PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3
+
+ # Oscillator Mode Write-Data Delay Line Select
+ # PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3
+
+ # Reserved. Caution, do not write to this register field.
+ # PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3
+
+ # Oscillator Mode Write-Leveling Delay Line Select
+ # PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3
+
+ # Oscillator Mode Division
+ # PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf
+
+ # Oscillator Enable
+ # PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0
+
+ # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
+ #(OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU) */
+ mask_write 0XFD081500 0xFFFFFFFF 0x2A019FFE
# Register : DX8SL4DQSCTL @ 0XFD08151C
# Reserved. Return zeroes on reads.
@@ -7900,14 +8158,14 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3
# DQS_N Resistor
- # PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0xc
+ # PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0
# DQS Resistor
- # PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x4
+ # PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0
# DATX8 0-1 DQS Control Register
- #(OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x012643C4U) */
- mask_write 0XFD08151C 0xFFFFFFFF 0x012643C4
+ #(OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01264300U) */
+ mask_write 0XFD08151C 0xFFFFFFFF 0x01264300
# Register : DX8SL4DXCTL2 @ 0XFD08152C
# Reserved. Return zeroes on reads.
@@ -7920,7 +8178,7 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0
# OE Extension during Pre-amble
- # PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x0
+ # PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1
# Reserved. Return zeroes on reads.
# PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0
@@ -7959,8 +8217,8 @@ set psu_ddr_init_data {
# PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0
# DATX8 0-1 DX Control Register 2
- #(OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00001800U) */
- mask_write 0XFD08152C 0xFFFFFFFF 0x00001800
+ #(OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U) */
+ mask_write 0XFD08152C 0xFFFFFFFF 0x00041800
# Register : DX8SL4IOCR @ 0XFD081530
# Reserved. Return zeroes on reads.
@@ -8717,7 +8975,7 @@ set psu_mio_init_data {
# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
# n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
- # PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 1
+ # PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0
# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
# , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
@@ -8727,8 +8985,8 @@ set psu_mio_init_data {
# PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0
# Configures MIO Pin 26 peripheral interface mapping
- #(OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000008U) */
- mask_write 0XFF180068 0x000000FE 0x00000008
+ #(OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U) */
+ mask_write 0XFF180068 0x000000FE 0x00000000
# Register : MIO_PIN_27 @ 0XFF18006C
# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)
@@ -8740,7 +8998,7 @@ set psu_mio_init_data {
# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
# n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
# t, dp_aux_data_out- (Dp Aux Data)
- # PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 0
+ # PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3
# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
# , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
@@ -8750,8 +9008,8 @@ set psu_mio_init_data {
# PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0
# Configures MIO Pin 27 peripheral interface mapping
- #(OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000000U) */
- mask_write 0XFF18006C 0x000000FE 0x00000000
+ #(OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U) */
+ mask_write 0XFF18006C 0x000000FE 0x00000018
# Register : MIO_PIN_28 @ 0XFF180070
# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)
@@ -8762,7 +9020,7 @@ set psu_mio_init_data {
# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
# n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
- # PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 0
+ # PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3
# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
# , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
@@ -8771,8 +9029,8 @@ set psu_mio_init_data {
# PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0
# Configures MIO Pin 28 peripheral interface mapping
- #(OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000000U) */
- mask_write 0XFF180070 0x000000FE 0x00000000
+ #(OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U) */
+ mask_write 0XFF180070 0x000000FE 0x00000018
# Register : MIO_PIN_29 @ 0XFF180074
# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)
@@ -8784,7 +9042,7 @@ set psu_mio_init_data {
# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
# n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
# t, dp_aux_data_out- (Dp Aux Data)
- # PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 0
+ # PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3
# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
# , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
@@ -8794,8 +9052,8 @@ set psu_mio_init_data {
# PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0
# Configures MIO Pin 29 peripheral interface mapping
- #(OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000000U) */
- mask_write 0XFF180074 0x000000FE 0x00000000
+ #(OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U) */
+ mask_write 0XFF180074 0x000000FE 0x00000018
# Register : MIO_PIN_30 @ 0XFF180078
# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)
@@ -8806,7 +9064,7 @@ set psu_mio_init_data {
# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
# n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
- # PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 0
+ # PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3
# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
# , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
@@ -8816,8 +9074,8 @@ set psu_mio_init_data {
# PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0
# Configures MIO Pin 30 peripheral interface mapping
- #(OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000000U) */
- mask_write 0XFF180078 0x000000FE 0x00000000
+ #(OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U) */
+ mask_write 0XFF180078 0x000000FE 0x00000018
# Register : MIO_PIN_31 @ 0XFF18007C
# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)
@@ -9923,26 +10181,26 @@ set psu_mio_init_data {
# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1
# Master Tri-state Enable for pin 26, active high
- # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 1
+ # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0
# Master Tri-state Enable for pin 27, active high
# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0
# Master Tri-state Enable for pin 28, active high
- # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 0
+ # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1
# Master Tri-state Enable for pin 29, active high
# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0
# Master Tri-state Enable for pin 30, active high
- # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 0
+ # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1
# Master Tri-state Enable for pin 31, active high
# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0
# MIO pin Tri-state Enables, 31:0
- #(OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x06240000U) */
- mask_write 0XFF180204 0xFFFFFFFF 0x06240000
+ #(OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U) */
+ mask_write 0XFF180204 0xFFFFFFFF 0x52240000
# Register : MIO_MST_TRI1 @ 0XFF180208
# Master Tri-state Enable for pin 32, active high
@@ -11611,6 +11869,15 @@ set psu_mio_init_data {
set psu_peripherals_init_data {
# : RESET BLOCKS
+ # : TIMESTAMP
+ # Register : RST_LPD_IOU2 @ 0XFF5E0238
+
+ # Block level reset
+ # PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0
+
+ # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+ #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00100000U ,0x00000000U) */
+ mask_write 0XFF5E0238 0x00100000 0x00000000
# : ENET
# Register : RST_LPD_IOU0 @ 0XFF5E0230
@@ -11629,6 +11896,15 @@ set psu_peripherals_init_data {
# Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
#(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) */
mask_write 0XFF5E0238 0x00000001 0x00000000
+ # : QSPI TAP DELAY
+ # Register : IOU_TAPDLY_BYPASS @ 0XFF180390
+
+ # 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI
+ # PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1
+
+ # IOU tap delay bypass for the LQSPI and NAND controllers
+ #(OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) */
+ mask_write 0XFF180390 0x00000004 0x00000004
# : NAND
# : USB
# Register : RST_LPD_TOP @ 0XFF5E023C
@@ -11728,6 +12004,17 @@ set psu_peripherals_init_data {
# SD Config Register 1
#(OFFSET, MASK, VALUE) (0XFF18031C, 0x7F800000U ,0x63800000U) */
mask_write 0XFF18031C 0x7F800000 0x63800000
+ # : SD1 RETUNER
+ # Register : SD_CONFIG_REG3 @ 0XFF180324
+
+ # This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf
+ # rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon
+ # s Fh - Ch = Reserved
+ # PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0
+
+ # SD Config Register 3
+ #(OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U) */
+ mask_write 0XFF180324 0x03C00000 0x00000000
# : CAN
# Register : RST_LPD_IOU2 @ 0XFF5E0238
@@ -12024,6 +12311,25 @@ set psu_peripherals_init_data {
# This register controls various functionalities within the RTC
#(OFFSET, MASK, VALUE) (0XFFA60040, 0x80000000U ,0x80000000U) */
mask_write 0XFFA60040 0x80000000 0x80000000
+ # : TIMESTAMP COUNTER
+ # Register : base_frequency_ID_register @ 0XFF260020
+
+ # Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz.
+ # PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5e100
+
+ # Program this register to match the clock frequency of the timestamp generator, in ticks per second. For example, for a 50 MHz
+ # clock, program 0x02FAF080. This register is not accessible to the read-only programming interface.
+ #(OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5E100U) */
+ mask_write 0XFF260020 0xFFFFFFFF 0x05F5E100
+ # Register : counter_control_register @ 0XFF260000
+
+ # Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing.
+ # PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1
+
+ # Controls the counter increments. This register is not accessible to the read-only programming interface.
+ #(OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U) */
+ mask_write 0XFF260000 0x00000001 0x00000001
+ # : TTC SRC SELECT
}
set psu_post_config_data {
@@ -12035,6 +12341,75 @@ set psu_peripherals_powerdwn_data {
# : POWER DOWN TRIGGER
}
+set psu_lpd_xppu_data {
+ # : XPPU INTERRUPT ENABLE
+ # Register : IEN @ 0XFF980018
+
+ # See Interuppt Status Register for details
+ # PSU_LPD_XPPU_CFG_IEN_APER_PARITY 0X1
+
+ # See Interuppt Status Register for details
+ # PSU_LPD_XPPU_CFG_IEN_APER_TZ 0X1
+
+ # See Interuppt Status Register for details
+ # PSU_LPD_XPPU_CFG_IEN_APER_PERM 0X1
+
+ # See Interuppt Status Register for details
+ # PSU_LPD_XPPU_CFG_IEN_MID_PARITY 0X1
+
+ # See Interuppt Status Register for details
+ # PSU_LPD_XPPU_CFG_IEN_MID_RO 0X1
+
+ # See Interuppt Status Register for details
+ # PSU_LPD_XPPU_CFG_IEN_MID_MISS 0X1
+
+ # See Interuppt Status Register for details
+ # PSU_LPD_XPPU_CFG_IEN_INV_APB 0X1
+
+ # Interrupt Enable Register
+ #(OFFSET, MASK, VALUE) (0XFF980018, 0x000000EFU ,0x000000EFU) */
+ mask_write 0XFF980018 0x000000EF 0x000000EF
+}
+
+set psu_ddr_xmpu0_data {
+}
+
+set psu_ddr_xmpu1_data {
+}
+
+set psu_ddr_xmpu2_data {
+}
+
+set psu_ddr_xmpu3_data {
+}
+
+set psu_ddr_xmpu4_data {
+}
+
+set psu_ddr_xmpu5_data {
+}
+
+set psu_ocm_xmpu_data {
+}
+
+set psu_fpd_xmpu_data {
+}
+
+set psu_protection_lock_data {
+}
+
+set psu_apply_master_tz {
+ # : RPU
+ # : DP TZ
+ # : SATA TZ
+ # : PCIE TZ
+ # : USB TZ
+ # : SD TZ
+ # : GEM TZ
+ # : QSPI TZ
+ # : NAND TZ
+}
+
set psu_serdes_init_data {
# : SERDES INITIALIZATION
# : GT REFERENCE CLOCK SOURCE SELECTION
@@ -12145,59 +12520,59 @@ set psu_serdes_init_data {
# Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368
# Spread Spectrum No of Steps [7:0]
- # PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x0
+ # PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0
# Spread Spectrum No of Steps bits 7:0
- #(OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x00000000U) */
- mask_write 0XFD40E368 0x000000FF 0x00000000
+ #(OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U) */
+ mask_write 0XFD40E368 0x000000FF 0x000000E0
# Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C
# Spread Spectrum No of Steps [10:8]
- # PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x0
+ # PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
# Spread Spectrum No of Steps bits 10:8
- #(OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000000U) */
- mask_write 0XFD40E36C 0x00000007 0x00000000
+ #(OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U) */
+ mask_write 0XFD40E36C 0x00000007 0x00000003
# Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368
# Spread Spectrum No of Steps [7:0]
- # PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x0
+ # PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58
# Spread Spectrum No of Steps bits 7:0
- #(OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000000U) */
- mask_write 0XFD406368 0x000000FF 0x00000000
+ #(OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U) */
+ mask_write 0XFD406368 0x000000FF 0x00000058
# Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C
# Spread Spectrum No of Steps [10:8]
- # PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x0
+ # PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
# Spread Spectrum No of Steps bits 10:8
- #(OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000000U) */
- mask_write 0XFD40636C 0x00000007 0x00000000
+ #(OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U) */
+ mask_write 0XFD40636C 0x00000007 0x00000003
# Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370
# Step Size for Spread Spectrum [7:0]
- # PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x0
+ # PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C
# Step Size for Spread Spectrum LSB
- #(OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x00000000U) */
- mask_write 0XFD406370 0x000000FF 0x00000000
+ #(OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU) */
+ mask_write 0XFD406370 0x000000FF 0x0000007C
# Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374
# Step Size for Spread Spectrum [15:8]
- # PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x0
+ # PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33
# Step Size for Spread Spectrum 1
- #(OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000000U) */
- mask_write 0XFD406374 0x000000FF 0x00000000
+ #(OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U) */
+ mask_write 0XFD406374 0x000000FF 0x00000033
# Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378
# Step Size for Spread Spectrum [23:16]
- # PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x0
+ # PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2
# Step Size for Spread Spectrum 2
- #(OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000000U) */
- mask_write 0XFD406378 0x000000FF 0x00000000
+ #(OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U) */
+ mask_write 0XFD406378 0x000000FF 0x00000002
# Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C
# Step Size for Spread Spectrum [25:24]
@@ -12253,27 +12628,27 @@ set psu_serdes_init_data {
# Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370
# Step Size for Spread Spectrum [7:0]
- # PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x0
+ # PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9
# Step Size for Spread Spectrum LSB
- #(OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x00000000U) */
- mask_write 0XFD40E370 0x000000FF 0x00000000
+ #(OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U) */
+ mask_write 0XFD40E370 0x000000FF 0x000000C9
# Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374
# Step Size for Spread Spectrum [15:8]
- # PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x0
+ # PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2
# Step Size for Spread Spectrum 1
- #(OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x00000000U) */
- mask_write 0XFD40E374 0x000000FF 0x00000000
+ #(OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U) */
+ mask_write 0XFD40E374 0x000000FF 0x000000D2
# Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378
# Step Size for Spread Spectrum [23:16]
- # PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x0
+ # PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1
# Step Size for Spread Spectrum 2
- #(OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000000U) */
- mask_write 0XFD40E378 0x000000FF 0x00000000
+ #(OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U) */
+ mask_write 0XFD40E378 0x000000FF 0x00000001
# Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C
# Step Size for Spread Spectrum [25:24]
@@ -12360,6 +12735,491 @@ set psu_serdes_init_data {
# Opmode Info
#(OFFSET, MASK, VALUE) (0XFD40CB00, 0x000000F0U ,0x000000F0U) */
mask_write 0XFD40CB00 0x000000F0 0x000000F0
+ # : ENABLE CHICKEN BIT FOR PCIE AND USB
+ # Register : L0_TM_AUX_0 @ 0XFD4010CC
+
+ # Spare- not used
+ # PSU_SERDES_L0_TM_AUX_0_BIT_2 1
+
+ # Spare registers
+ #(OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U) */
+ mask_write 0XFD4010CC 0x00000020 0x00000020
+ # Register : L2_TM_AUX_0 @ 0XFD4090CC
+
+ # Spare- not used
+ # PSU_SERDES_L2_TM_AUX_0_BIT_2 1
+
+ # Spare registers
+ #(OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U) */
+ mask_write 0XFD4090CC 0x00000020 0x00000020
+ # : ENABLING EYE SURF
+ # Register : L0_TM_DIG_8 @ 0XFD401074
+
+ # Enable Eye Surf
+ # PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1
+
+ # Test modes for Elastic buffer and enabling Eye Surf
+ #(OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U) */
+ mask_write 0XFD401074 0x00000010 0x00000010
+ # Register : L1_TM_DIG_8 @ 0XFD405074
+
+ # Enable Eye Surf
+ # PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1
+
+ # Test modes for Elastic buffer and enabling Eye Surf
+ #(OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U) */
+ mask_write 0XFD405074 0x00000010 0x00000010
+ # Register : L2_TM_DIG_8 @ 0XFD409074
+
+ # Enable Eye Surf
+ # PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1
+
+ # Test modes for Elastic buffer and enabling Eye Surf
+ #(OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U) */
+ mask_write 0XFD409074 0x00000010 0x00000010
+ # Register : L3_TM_DIG_8 @ 0XFD40D074
+
+ # Enable Eye Surf
+ # PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1
+
+ # Test modes for Elastic buffer and enabling Eye Surf
+ #(OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U) */
+ mask_write 0XFD40D074 0x00000010 0x00000010
+ # : ILL SETTINGS FOR GAIN AND LOCK SETTINGS
+ # Register : L0_TM_MISC2 @ 0XFD40189C
+
+ # ILL calib counts BYPASSED with calcode bits
+ # PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
+
+ # sampler cal
+ #(OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U) */
+ mask_write 0XFD40189C 0x00000080 0x00000080
+ # Register : L0_TM_IQ_ILL1 @ 0XFD4018F8
+
+ # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ # PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64
+
+ # iqpi cal code
+ #(OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U) */
+ mask_write 0XFD4018F8 0x000000FF 0x00000064
+ # Register : L0_TM_IQ_ILL2 @ 0XFD4018FC
+
+ # IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ # PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64
+
+ # iqpi cal code
+ #(OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U) */
+ mask_write 0XFD4018FC 0x000000FF 0x00000064
+ # Register : L0_TM_ILL12 @ 0XFD401990
+
+ # G1A pll ctr bypass value
+ # PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11
+
+ # ill pll counter values
+ #(OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U) */
+ mask_write 0XFD401990 0x000000FF 0x00000011
+ # Register : L0_TM_E_ILL1 @ 0XFD401924
+
+ # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ # PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4
+
+ # epi cal code
+ #(OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U) */
+ mask_write 0XFD401924 0x000000FF 0x00000004
+ # Register : L0_TM_E_ILL2 @ 0XFD401928
+
+ # E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ # PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE
+
+ # epi cal code
+ #(OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU) */
+ mask_write 0XFD401928 0x000000FF 0x000000FE
+ # Register : L0_TM_IQ_ILL3 @ 0XFD401900
+
+ # IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ # PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64
+
+ # iqpi cal code
+ #(OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U) */
+ mask_write 0XFD401900 0x000000FF 0x00000064
+ # Register : L0_TM_E_ILL3 @ 0XFD40192C
+
+ # E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ # PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0
+
+ # epi cal code
+ #(OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U) */
+ mask_write 0XFD40192C 0x000000FF 0x00000000
+ # Register : L0_TM_ILL8 @ 0XFD401980
+
+ # ILL calibration code change wait time
+ # PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
+
+ # ILL cal routine control
+ #(OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU) */
+ mask_write 0XFD401980 0x000000FF 0x000000FF
+ # Register : L0_TM_IQ_ILL8 @ 0XFD401914
+
+ # IQ ILL polytrim bypass value
+ # PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
+
+ # iqpi polytrim
+ #(OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U) */
+ mask_write 0XFD401914 0x000000FF 0x000000F7
+ # Register : L0_TM_IQ_ILL9 @ 0XFD401918
+
+ # bypass IQ polytrim
+ # PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
+
+ # enables for lf,constant gm trim and polytirm
+ #(OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U) */
+ mask_write 0XFD401918 0x00000001 0x00000001
+ # Register : L0_TM_E_ILL8 @ 0XFD401940
+
+ # E ILL polytrim bypass value
+ # PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
+
+ # epi polytrim
+ #(OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U) */
+ mask_write 0XFD401940 0x000000FF 0x000000F7
+ # Register : L0_TM_E_ILL9 @ 0XFD401944
+
+ # bypass E polytrim
+ # PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
+
+ # enables for lf,constant gm trim and polytirm
+ #(OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U) */
+ mask_write 0XFD401944 0x00000001 0x00000001
+ # Register : L2_TM_MISC2 @ 0XFD40989C
+
+ # ILL calib counts BYPASSED with calcode bits
+ # PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
+
+ # sampler cal
+ #(OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U) */
+ mask_write 0XFD40989C 0x00000080 0x00000080
+ # Register : L2_TM_IQ_ILL1 @ 0XFD4098F8
+
+ # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ # PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A
+
+ # iqpi cal code
+ #(OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU) */
+ mask_write 0XFD4098F8 0x000000FF 0x0000001A
+ # Register : L2_TM_IQ_ILL2 @ 0XFD4098FC
+
+ # IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ # PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A
+
+ # iqpi cal code
+ #(OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU) */
+ mask_write 0XFD4098FC 0x000000FF 0x0000001A
+ # Register : L2_TM_ILL12 @ 0XFD409990
+
+ # G1A pll ctr bypass value
+ # PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10
+
+ # ill pll counter values
+ #(OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U) */
+ mask_write 0XFD409990 0x000000FF 0x00000010
+ # Register : L2_TM_E_ILL1 @ 0XFD409924
+
+ # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ # PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE
+
+ # epi cal code
+ #(OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU) */
+ mask_write 0XFD409924 0x000000FF 0x000000FE
+ # Register : L2_TM_E_ILL2 @ 0XFD409928
+
+ # E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ # PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0
+
+ # epi cal code
+ #(OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U) */
+ mask_write 0XFD409928 0x000000FF 0x00000000
+ # Register : L2_TM_IQ_ILL3 @ 0XFD409900
+
+ # IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ # PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A
+
+ # iqpi cal code
+ #(OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU) */
+ mask_write 0XFD409900 0x000000FF 0x0000001A
+ # Register : L2_TM_E_ILL3 @ 0XFD40992C
+
+ # E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ # PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0
+
+ # epi cal code
+ #(OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U) */
+ mask_write 0XFD40992C 0x000000FF 0x00000000
+ # Register : L2_TM_ILL8 @ 0XFD409980
+
+ # ILL calibration code change wait time
+ # PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
+
+ # ILL cal routine control
+ #(OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU) */
+ mask_write 0XFD409980 0x000000FF 0x000000FF
+ # Register : L2_TM_IQ_ILL8 @ 0XFD409914
+
+ # IQ ILL polytrim bypass value
+ # PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
+
+ # iqpi polytrim
+ #(OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U) */
+ mask_write 0XFD409914 0x000000FF 0x000000F7
+ # Register : L2_TM_IQ_ILL9 @ 0XFD409918
+
+ # bypass IQ polytrim
+ # PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
+
+ # enables for lf,constant gm trim and polytirm
+ #(OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U) */
+ mask_write 0XFD409918 0x00000001 0x00000001
+ # Register : L2_TM_E_ILL8 @ 0XFD409940
+
+ # E ILL polytrim bypass value
+ # PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
+
+ # epi polytrim
+ #(OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U) */
+ mask_write 0XFD409940 0x000000FF 0x000000F7
+ # Register : L2_TM_E_ILL9 @ 0XFD409944
+
+ # bypass E polytrim
+ # PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
+
+ # enables for lf,constant gm trim and polytirm
+ #(OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U) */
+ mask_write 0XFD409944 0x00000001 0x00000001
+ # Register : L3_TM_MISC2 @ 0XFD40D89C
+
+ # ILL calib counts BYPASSED with calcode bits
+ # PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
+
+ # sampler cal
+ #(OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U) */
+ mask_write 0XFD40D89C 0x00000080 0x00000080
+ # Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8
+
+ # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ # PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D
+
+ # iqpi cal code
+ #(OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU) */
+ mask_write 0XFD40D8F8 0x000000FF 0x0000007D
+ # Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC
+
+ # IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ # PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D
+
+ # iqpi cal code
+ #(OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU) */
+ mask_write 0XFD40D8FC 0x000000FF 0x0000007D
+ # Register : L3_TM_ILL12 @ 0XFD40D990
+
+ # G1A pll ctr bypass value
+ # PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1
+
+ # ill pll counter values
+ #(OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U) */
+ mask_write 0XFD40D990 0x000000FF 0x00000001
+ # Register : L3_TM_E_ILL1 @ 0XFD40D924
+
+ # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ # PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C
+
+ # epi cal code
+ #(OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU) */
+ mask_write 0XFD40D924 0x000000FF 0x0000009C
+ # Register : L3_TM_E_ILL2 @ 0XFD40D928
+
+ # E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ # PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39
+
+ # epi cal code
+ #(OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U) */
+ mask_write 0XFD40D928 0x000000FF 0x00000039
+ # Register : L3_TM_ILL11 @ 0XFD40D98C
+
+ # G2A_PCIe1 PLL ctr bypass value
+ # PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2
+
+ # ill pll counter values
+ #(OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U) */
+ mask_write 0XFD40D98C 0x000000F0 0x00000020
+ # Register : L3_TM_IQ_ILL3 @ 0XFD40D900
+
+ # IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ # PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D
+
+ # iqpi cal code
+ #(OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU) */
+ mask_write 0XFD40D900 0x000000FF 0x0000007D
+ # Register : L3_TM_E_ILL3 @ 0XFD40D92C
+
+ # E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ # PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64
+
+ # epi cal code
+ #(OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U) */
+ mask_write 0XFD40D92C 0x000000FF 0x00000064
+ # Register : L3_TM_ILL8 @ 0XFD40D980
+
+ # ILL calibration code change wait time
+ # PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
+
+ # ILL cal routine control
+ #(OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU) */
+ mask_write 0XFD40D980 0x000000FF 0x000000FF
+ # Register : L3_TM_IQ_ILL8 @ 0XFD40D914
+
+ # IQ ILL polytrim bypass value
+ # PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
+
+ # iqpi polytrim
+ #(OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U) */
+ mask_write 0XFD40D914 0x000000FF 0x000000F7
+ # Register : L3_TM_IQ_ILL9 @ 0XFD40D918
+
+ # bypass IQ polytrim
+ # PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
+
+ # enables for lf,constant gm trim and polytirm
+ #(OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U) */
+ mask_write 0XFD40D918 0x00000001 0x00000001
+ # Register : L3_TM_E_ILL8 @ 0XFD40D940
+
+ # E ILL polytrim bypass value
+ # PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
+
+ # epi polytrim
+ #(OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U) */
+ mask_write 0XFD40D940 0x000000FF 0x000000F7
+ # Register : L3_TM_E_ILL9 @ 0XFD40D944
+
+ # bypass E polytrim
+ # PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
+
+ # enables for lf,constant gm trim and polytirm
+ #(OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U) */
+ mask_write 0XFD40D944 0x00000001 0x00000001
+ # : SYMBOL LOCK AND WAIT
+ # Register : L0_TM_DIG_21 @ 0XFD4010A8
+
+ # pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20
+ # PSU_SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH 0x11
+
+ # Control symbol alignment locking - wait counts
+ #(OFFSET, MASK, VALUE) (0XFD4010A8, 0x00000003U ,0x00000003U) */
+ mask_write 0XFD4010A8 0x00000003 0x00000003
+ # Register : L0_TM_DIG_10 @ 0XFD40107C
+
+ # CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
+ # PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0xF
+
+ # test control for changing cdr lock wait time
+ #(OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x0000000FU) */
+ mask_write 0XFD40107C 0x0000000F 0x0000000F
+ # : SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG
+ # Register : L0_TM_RST_DLY @ 0XFD4019A4
+
+ # Delay apb reset by specified amount
+ # PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF
+
+ # reset delay for apb reset w.r.t pso of hsrx
+ #(OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU) */
+ mask_write 0XFD4019A4 0x000000FF 0x000000FF
+ # Register : L0_TM_ANA_BYP_15 @ 0XFD401038
+
+ # Enable Bypass for <7> of TM_ANA_BYPS_15
+ # PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
+
+ # Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
+ #(OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U) */
+ mask_write 0XFD401038 0x00000040 0x00000040
+ # Register : L0_TM_ANA_BYP_12 @ 0XFD40102C
+
+ # Enable Bypass for <7> of TM_ANA_BYPS_12
+ # PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
+
+ # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
+ #(OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U) */
+ mask_write 0XFD40102C 0x00000040 0x00000040
+ # Register : L1_TM_RST_DLY @ 0XFD4059A4
+
+ # Delay apb reset by specified amount
+ # PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF
+
+ # reset delay for apb reset w.r.t pso of hsrx
+ #(OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU) */
+ mask_write 0XFD4059A4 0x000000FF 0x000000FF
+ # Register : L1_TM_ANA_BYP_15 @ 0XFD405038
+
+ # Enable Bypass for <7> of TM_ANA_BYPS_15
+ # PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
+
+ # Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
+ #(OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U) */
+ mask_write 0XFD405038 0x00000040 0x00000040
+ # Register : L1_TM_ANA_BYP_12 @ 0XFD40502C
+
+ # Enable Bypass for <7> of TM_ANA_BYPS_12
+ # PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
+
+ # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
+ #(OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U) */
+ mask_write 0XFD40502C 0x00000040 0x00000040
+ # Register : L2_TM_RST_DLY @ 0XFD4099A4
+
+ # Delay apb reset by specified amount
+ # PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF
+
+ # reset delay for apb reset w.r.t pso of hsrx
+ #(OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU) */
+ mask_write 0XFD4099A4 0x000000FF 0x000000FF
+ # Register : L2_TM_ANA_BYP_15 @ 0XFD409038
+
+ # Enable Bypass for <7> of TM_ANA_BYPS_15
+ # PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
+
+ # Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
+ #(OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U) */
+ mask_write 0XFD409038 0x00000040 0x00000040
+ # Register : L2_TM_ANA_BYP_12 @ 0XFD40902C
+
+ # Enable Bypass for <7> of TM_ANA_BYPS_12
+ # PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
+
+ # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
+ #(OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U) */
+ mask_write 0XFD40902C 0x00000040 0x00000040
+ # Register : L3_TM_RST_DLY @ 0XFD40D9A4
+
+ # Delay apb reset by specified amount
+ # PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF
+
+ # reset delay for apb reset w.r.t pso of hsrx
+ #(OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU) */
+ mask_write 0XFD40D9A4 0x000000FF 0x000000FF
+ # Register : L3_TM_ANA_BYP_15 @ 0XFD40D038
+
+ # Enable Bypass for <7> of TM_ANA_BYPS_15
+ # PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
+
+ # Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
+ #(OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U) */
+ mask_write 0XFD40D038 0x00000040 0x00000040
+ # Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C
+
+ # Enable Bypass for <7> of TM_ANA_BYPS_12
+ # PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
+
+ # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
+ #(OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U) */
+ mask_write 0XFD40D02C 0x00000040 0x00000040
# : GT LANE SETTINGS
# Register : ICM_CFG0 @ 0XFD410010
@@ -12417,6 +13277,54 @@ set psu_serdes_init_data {
# Enable Override of TX deemphasis
#(OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U) */
mask_write 0XFD4041D8 0x00000001 0x00000001
+ # Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8
+
+ # Test register force for enabling/disablign TX deemphasis bits <17:0>
+ # PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
+
+ # Enable Override of TX deemphasis
+ #(OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U) */
+ mask_write 0XFD40C1D8 0x00000001 0x00000001
+ # : CDR AND RX EQUALIZATION SETTINGS
+ # Register : L3_TM_CDR5 @ 0XFD40DC14
+
+ # FPHL FSM accumulate cycles
+ # PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7
+
+ # FFL Phase0 int gain aka 2ol SD update rate
+ # PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6
+
+ # Fast phase lock controls -- FSM accumulator cycle control and phase 0 int gain control.
+ #(OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U) */
+ mask_write 0XFD40DC14 0x000000FF 0x000000E6
+ # Register : L3_TM_CDR16 @ 0XFD40DC40
+
+ # FFL Phase0 prop gain aka 1ol SD update rate
+ # PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC
+
+ # Fast phase lock controls -- phase 0 prop gain
+ #(OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU) */
+ mask_write 0XFD40DC40 0x0000001F 0x0000000C
+ # Register : L3_TM_EQ0 @ 0XFD40D94C
+
+ # EQ stg 2 controls BYPASSED
+ # PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1
+
+ # eq stg1 and stg2 controls
+ #(OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U) */
+ mask_write 0XFD40D94C 0x00000020 0x00000020
+ # Register : L3_TM_EQ1 @ 0XFD40D950
+
+ # EQ STG2 RL PROG
+ # PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2
+
+ # EQ stg 2 preamp mode val
+ # PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1
+
+ # eq stg1 and stg2 controls
+ #(OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U) */
+ mask_write 0XFD40D950 0x00000007 0x00000006
+ # : GEM SERDES SETTINGS
# : ENABLE PRE EMPHAIS AND VOLTAGE SWING
# Register : L1_TXPMD_TM_48 @ 0XFD404CC0
@@ -12434,6 +13342,14 @@ set psu_serdes_init_data {
# Override for PIPE TX de-emphasis
#(OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U) */
mask_write 0XFD404048 0x000000FF 0x00000000
+ # Register : L3_TX_ANA_TM_18 @ 0XFD40C048
+
+ # pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
+ # PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1
+
+ # Override for PIPE TX de-emphasis
+ #(OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U) */
+ mask_write 0XFD40C048 0x000000FF 0x00000001
}
set psu_resetout_init_data {
@@ -12456,6 +13372,14 @@ set psu_resetout_init_data {
# fpd_power_prsnt
#(OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) */
mask_write 0XFF9D0080 0x00000001 0x00000001
+ # Register : fpd_pipe_clk @ 0XFF9D007C
+
+ # This bit is used to choose between PIPE clock coming from SerDes and the suspend clk
+ # PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0
+
+ # fpd_pipe_clk
+ #(OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) */
+ mask_write 0XFF9D007C 0x00000001 0x00000000
# :
# Register : RST_LPD_TOP @ 0XFF5E023C
@@ -12494,21 +13418,18 @@ set psu_resetout_init_data {
# FPD Block level software controlled reset
#(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U) */
mask_write 0XFD1A0100 0x00000002 0x00000000
- # : PUTTING PCIE IN RESET
+ # : PUTTING PCIE CFG AND BRIDGE IN RESET
# Register : RST_FPD_TOP @ 0XFD1A0100
# PCIE config reset
# PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0
- # PCIE control block level reset
- # PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0
-
# PCIE bridge block level reset (AXI interface)
# PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0
# FPD Block level software controlled reset
- #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x00000000U) */
- mask_write 0XFD1A0100 0x000E0000 0x00000000
+ #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U) */
+ mask_write 0XFD1A0100 0x000C0000 0x00000000
# : PUTTING DP IN RESET
# Register : RST_FPD_TOP @ 0XFD1A0100
@@ -12544,7 +13465,7 @@ set psu_resetout_init_data {
# . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
# UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger
# alue. Note: This field is valid only in device mode.
- # PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0X9
+ # PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9
# Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
# of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
@@ -12552,7 +13473,7 @@ set psu_resetout_init_data {
# ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
# off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
# ng hibernation. - This bit is valid only in device mode.
- # PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0X0
+ # PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0
# Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
# _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
@@ -12561,42 +13482,33 @@ set psu_resetout_init_data {
# n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
# d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
# d.
- # PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0X0
+ # PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0
# USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
# Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. -
# 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
# in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
# active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.
- # PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0X0
-
- # Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
- # figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
- # ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
- # r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
- # t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
- # g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
- # when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.
- # PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0X1
+ # PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0
# Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
# full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
# ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
# B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.
- # PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0X0
+ # PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0
# ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
# e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
# ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
# lected through DWC_USB3_HSPHY_INTERFACE.
- # PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0X1
+ # PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1
# PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
# 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same
# lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
# ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
# any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.
- # PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0X0
+ # PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0
# HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
# a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for
@@ -12606,13 +13518,13 @@ set psu_resetout_init_data {
# ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
# clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
# 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times
- # PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0X7
+ # PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7
# Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either
# he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple
# ented.
- #(OFFSET, MASK, VALUE) (0XFE20C200, 0x00003FFFU ,0x00002457U) */
- mask_write 0XFE20C200 0x00003FFF 0x00002457
+ #(OFFSET, MASK, VALUE) (0XFE20C200, 0x00003FBFU ,0x00002417U) */
+ mask_write 0XFE20C200 0x00003FBF 0x00002417
# Register : GFLADJ @ 0XFE20C630
# This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register
@@ -12624,7 +13536,7 @@ set psu_resetout_init_data {
# uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
# ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
# RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)
- # PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0X0
+ # PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0
# Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res
# ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio
@@ -12632,40 +13544,7 @@ set psu_resetout_init_data {
# rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal.
#(OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U) */
mask_write 0XFE20C630 0x003FFF00 0x00000000
- # : CHECK PLL LOCK FOR LANE0
- # Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4
-
- # Status Read value of PLL Lock
- # PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
- mask_poll 0XFD4023E4 0x00000010
- # : CHECK PLL LOCK FOR LANE1
- # Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4
-
- # Status Read value of PLL Lock
- # PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
- mask_poll 0XFD4063E4 0x00000010
- # : CHECK PLL LOCK FOR LANE2
- # Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4
-
- # Status Read value of PLL Lock
- # PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
- mask_poll 0XFD40A3E4 0x00000010
- # : CHECK PLL LOCK FOR LANE3
- # Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4
-
- # Status Read value of PLL Lock
- # PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
- mask_poll 0XFD40E3E4 0x00000010
# : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON.
- # Register : ATTR_37 @ 0XFD480094
-
- # Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
- # gister.; EP=0x0001; RP=0x0001
- # PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0X1
-
- # ATTR_37
- #(OFFSET, MASK, VALUE) (0XFD480094, 0x00004000U ,0x00004000U) */
- mask_write 0XFD480094 0x00004000 0x00004000
# Register : ATTR_25 @ 0XFD480064
# If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
@@ -13029,9 +13908,13 @@ set psu_resetout_init_data {
# Required for Root.; EP=0x0000; RP=0x0001
# PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1
+ # Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
+ # gister.; EP=0x0001; RP=0x0001
+ # PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1
+
# ATTR_37
- #(OFFSET, MASK, VALUE) (0XFD480094, 0x00000200U ,0x00000200U) */
- mask_write 0XFD480094 0x00000200 0x00000200
+ #(OFFSET, MASK, VALUE) (0XFD480094, 0x00004200U ,0x00004200U) */
+ mask_write 0XFD480094 0x00004200 0x00004200
# Register : ATTR_93 @ 0XFD480174
# Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L
@@ -13138,6 +14021,173 @@ set psu_resetout_init_data {
# ATTR_43
#(OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U) */
mask_write 0XFD4800AC 0x00000100 0x00000000
+ # Register : ATTR_48 @ 0XFD4800C0
+
+ # MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note
+ # hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000
+ # PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0
+
+ # ATTR_48
+ #(OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U) */
+ mask_write 0XFD4800C0 0x000007FF 0x00000000
+ # Register : ATTR_46 @ 0XFD4800B8
+
+ # MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001;
+ # P=0x0000
+ # PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0
+
+ # ATTR_46
+ #(OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U) */
+ mask_write 0XFD4800B8 0x0000FFFF 0x00000000
+ # Register : ATTR_47 @ 0XFD4800BC
+
+ # MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000;
+ # P=0x0000
+ # PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0
+
+ # ATTR_47
+ #(OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U) */
+ mask_write 0XFD4800BC 0x00001FFF 0x00000000
+ # Register : ATTR_44 @ 0XFD4800B0
+
+ # MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
+ # 0x0001; RP=0x0000
+ # PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0
+
+ # ATTR_44
+ #(OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U) */
+ mask_write 0XFD4800B0 0x0000FFFF 0x00000000
+ # Register : ATTR_45 @ 0XFD4800B4
+
+ # MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
+ # 0x1000; RP=0x0000
+ # PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0
+
+ # ATTR_45
+ #(OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U) */
+ mask_write 0XFD4800B4 0x0000FFF8 0x00000000
+ # Register : CB @ 0XFD48031C
+
+ # DT837748 Enable
+ # PSU_PCIE_ATTRIB_CB_CB1 0x0
+
+ # ECO Register 1
+ #(OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U) */
+ mask_write 0XFD48031C 0x00000002 0x00000000
+ # Register : ATTR_35 @ 0XFD48008C
+
+ # Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc
+ # ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001
+ # PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0
+
+ # ATTR_35
+ #(OFFSET, MASK, VALUE) (0XFD48008C, 0x00003000U ,0x00000000U) */
+ mask_write 0XFD48008C 0x00003000 0x00000000
+ # : PUTTING PCIE CONTROL IN RESET
+ # Register : RST_FPD_TOP @ 0XFD1A0100
+
+ # PCIE control block level reset
+ # PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0
+
+ # FPD Block level software controlled reset
+ #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U) */
+ mask_write 0XFD1A0100 0x00020000 0x00000000
+ # : CHECK PLL LOCK FOR LANE0
+ # Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4
+
+ # Status Read value of PLL Lock
+ # PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
+ mask_poll 0XFD4023E4 0x00000010
+ # : CHECK PLL LOCK FOR LANE1
+ # Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4
+
+ # Status Read value of PLL Lock
+ # PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
+ mask_poll 0XFD4063E4 0x00000010
+ # : CHECK PLL LOCK FOR LANE2
+ # Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4
+
+ # Status Read value of PLL Lock
+ # PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
+ mask_poll 0XFD40A3E4 0x00000010
+ # : CHECK PLL LOCK FOR LANE3
+ # Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4
+
+ # Status Read value of PLL Lock
+ # PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
+ mask_poll 0XFD40E3E4 0x00000010
+ # : SATA AHCI VENDOR SETTING
+ # Register : PP2C @ 0XFD0C00AC
+
+ # CIBGMN: COMINIT Burst Gap Minimum.
+ # PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18
+
+ # CIBGMX: COMINIT Burst Gap Maximum.
+ # PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40
+
+ # CIBGN: COMINIT Burst Gap Nominal.
+ # PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18
+
+ # CINMP: COMINIT Negate Minimum Period.
+ # PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28
+
+ # PP2C - Port Phy2Cfg Register. This register controls the configuration of the Phy Control OOB timing for the COMINIT paramete
+ # s for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
+ #(OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U) */
+ mask_write 0XFD0C00AC 0xFFFFFFFF 0x28184018
+ # Register : PP3C @ 0XFD0C00B0
+
+ # CWBGMN: COMWAKE Burst Gap Minimum.
+ # PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06
+
+ # CWBGMX: COMWAKE Burst Gap Maximum.
+ # PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14
+
+ # CWBGN: COMWAKE Burst Gap Nominal.
+ # PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08
+
+ # CWNMP: COMWAKE Negate Minimum Period.
+ # PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E
+
+ # PP3C - Port Phy3CfgRegister. This register controls the configuration of the Phy Control OOB timing for the COMWAKE parameter
+ # for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
+ #(OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U) */
+ mask_write 0XFD0C00B0 0xFFFFFFFF 0x0E081406
+ # Register : PP4C @ 0XFD0C00B4
+
+ # BMX: COM Burst Maximum.
+ # PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13
+
+ # BNM: COM Burst Nominal.
+ # PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08
+
+ # SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det
+ # rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa
+ # Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of
+ # 500ns based on a 150MHz PMCLK.
+ # PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A
+
+ # PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th
+ # value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128
+ # PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06
+
+ # PP4C - Port Phy4Cfg Register. This register controls the configuration of the Phy Control Burst timing for the COM parameters
+ # for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
+ #(OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U) */
+ mask_write 0XFD0C00B4 0xFFFFFFFF 0x064A0813
+ # Register : PP5C @ 0XFD0C00B8
+
+ # RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed.
+ # PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4
+
+ # RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha
+ # completed, for a fast SERDES it is suggested that this value be 54.2us / 4
+ # PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF
+
+ # PP5C - Port Phy5Cfg Register. This register controls the configuration of the Phy Control Retry Interval timing for either Po
+ # t 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
+ #(OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U) */
+ mask_write 0XFD0C00B8 0xFFFFFFFF 0x3FFC96A4
}
set psu_resetin_init_data {
@@ -13438,9 +14488,15 @@ proc init_serdes {} {
proc poll { addr mask data} {
set curval "0x[string range [mrd -force $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
+ set count 1
while { $maskedval != $data } {
set curval "0x[string range [mrd -force $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
+ set count [ expr { $count + 1 } ]
+ if { $count == 100000000 } {
+ puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
+ break
+ }
}
}
@@ -13465,13 +14521,97 @@ proc init_peripheral {} {
mask_write 0xFD690030 0x00000001 0x00000000
}
+proc psu_init_xppu_aper_ram {} {
+ set APER_OFFSET 0xFF981000
+ set i 0
+ while { $i <= 400 } {
+ mask_write $APER_OFFSET 0xF80FFFFF 0x08080000
+ set APER_OFFSET [ expr $APER_OFFSET + 4 ]
+ set APER_OFFSET "0x[format %08X [ expr $APER_OFFSET] ]"
+ set i [ expr { $i + 1 } ]
+ }
+
+}
+proc psu_lpd_protection {} {
+ set saved_mode [configparams force-mem-accesses]
+ configparams force-mem-accesses 1
+
+ psu_init_xppu_aper_ram;
+ variable psu_lpd_xppu_data
+ init_ps [subst {$psu_lpd_xppu_data }]
+
+ configparams force-mem-accesses $saved_mode
+}
+
+proc psu_ddr_protection {} {
+ set saved_mode [configparams force-mem-accesses]
+ configparams force-mem-accesses 1
+
+ variable psu_ddr_xmpu0_data
+ variable psu_ddr_xmpu1_data
+ variable psu_ddr_xmpu2_data
+ variable psu_ddr_xmpu3_data
+ variable psu_ddr_xmpu4_data
+ variable psu_ddr_xmpu5_data
+ init_ps [subst {$psu_ddr_xmpu0_data $psu_ddr_xmpu1_data $psu_ddr_xmpu2_data $psu_ddr_xmpu3_data $psu_ddr_xmpu4_data $psu_ddr_xmpu5_data}]
+
+ configparams force-mem-accesses $saved_mode
+}
+
+proc psu_ocm_protection {} {
+ set saved_mode [configparams force-mem-accesses]
+ configparams force-mem-accesses 1
+
+ variable psu_ocm_xmpu_data
+ init_ps [subst {$psu_ocm_xmpu_data }]
+
+ configparams force-mem-accesses $saved_mode
+}
+
+proc psu_fpd_protection {} {
+ set saved_mode [configparams force-mem-accesses]
+ configparams force-mem-accesses 1
+
+ variable psu_fpd_xmpu_data
+ init_ps [subst {$psu_fpd_xmpu_data }]
+
+ configparams force-mem-accesses $saved_mode
+}
+
+proc psu_protection_lock {} {
+ set saved_mode [configparams force-mem-accesses]
+ configparams force-mem-accesses 1
+
+ variable psu_protection_lock_data
+ init_ps [subst {$psu_protection_lock_data }]
+
+ configparams force-mem-accesses $saved_mode
+}
+
+proc psu_protection {} {
+ psu_ddr_protection
+ psu_ocm_protection
+ psu_fpd_protection
+ psu_lpd_protection
+}
+
proc psu_ddr_phybringup_data {} {
-mwr -force 0xFD090000 0x0000A845
-mwr -force 0xFD090004 0x003FFFFF
-mwr -force 0xFD09000C 0x00000010
-mwr -force 0xFD090010 0x00000010
+set dpll_divisor [expr {(0x00003F00 & [mrd -force -value 0xFD1A0080]) >> 0x00000008 }]
+ psu_mask_write 0xFD1A0080 0x00003F00 0x00000500
+ psu_mask_write 0xFD080028 0x00000001 0x00000001
+mwr -force 0xFD080004 0x00040003
+mask_poll 0xFD080030 0x00000001
+ psu_mask_write 0xFD080684 0x06000000 0x02000000
+ psu_mask_write 0xFD0806A4 0x06000000 0x02000000
+ psu_mask_write 0xFD0806C4 0x06000000 0x02000000
+ psu_mask_write 0xFD0806E4 0x06000000 0x02000000
+ psu_mask_write 0xFD1A0080 0x3F00 [expr {($dpll_divisor << 8)}]
+mwr -force 0xFD080004 0x40040071
+mask_poll 0xFD080030 0x00000001
+mwr -force 0xFD080004 0x40040001
+mask_poll 0xFD080030 0x00000001
poll 0xFD080030 0x0000000F 0x0000000F
psu_mask_write 0xFD080004 0x00000001 0x00000001
@@ -13505,29 +14645,34 @@ poll 0xFD080030 0x00000FFF 0x00000FFF
# Run Vref training in static read mode
-mwr -force 0xFD080200 0x110011C7
+mwr -force 0xFD080200 0x100091C7
mwr -force 0xFD080018 0x00F01EF2
-mwr -force 0xFD08001C 0x55AA0098
-mwr -force 0xFD08142C 0x00001830
-mwr -force 0xFD08146C 0x00001830
-mwr -force 0xFD0814AC 0x00001830
-mwr -force 0xFD0814EC 0x00001830
-mwr -force 0xFD08152C 0x00001830
+mwr -force 0xFD08001C 0x55AA5498
+mwr -force 0xFD08142C 0x00041830
+mwr -force 0xFD08146C 0x00041830
+mwr -force 0xFD0814AC 0x00041830
+mwr -force 0xFD0814EC 0x00041830
+mwr -force 0xFD08152C 0x00041830
psu_mask_write 0xFD080004 0xFFFFFFFF 0x00060001
#trigger VreFPHY training
-poll 0xFD080030 0x00004001 0x00004001
+poll 0xFD080030 0x00000C01 0x00000C01
#//Poll PUB_PGSR0 for Trng complete
- # Vref training is complete, disabling static read mode
-mwr -force 0xFD080200 0x810011C7
+mwr -force 0xFD080200 0x800091C7
mwr -force 0xFD080018 0x00F12302
-mwr -force 0xFD08001C 0x55AA0080
-mwr -force 0xFD08142C 0x00001800
-mwr -force 0xFD08146C 0x00001800
-mwr -force 0xFD0814AC 0x00001800
-mwr -force 0xFD0814EC 0x00001800
-mwr -force 0xFD08152C 0x00001800
+mwr -force 0xFD08001C 0x55AA5480
+mwr -force 0xFD08142C 0x00041800
+mwr -force 0xFD08146C 0x00041800
+mwr -force 0xFD0814AC 0x00041800
+mwr -force 0xFD0814EC 0x00041800
+mwr -force 0xFD08152C 0x00041800
+psu_mask_write 0xFD080004 0xFFFFFFFF 0x0000C001
+
+ #trigger VreFPHY training
+poll 0xFD080030 0x00004001 0x00004001
+
+ #//Poll PUB_PGSR0 for Trng complete
mwr -force 0xFD070180 0x01000040
mwr -force 0xFD070060 0x00000000
psu_mask_write 0xFD080014 0x00000040 0x00000000
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c
index a6cdc38f1..8ed7cf1dc 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c
@@ -19,8 +19,17 @@
******************************************************************************/
#include
+#include
#include "psu_init_gpl.h"
+int mask_pollOnValue(u32 add , u32 mask, u32 value );
+
+int mask_poll(u32 add , u32 mask );
+
+void mask_delay(u32 delay);
+
+u32 mask_read(u32 add , u32 mask );
+
static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned long val)
{
unsigned long RegVal = 0x0;
@@ -30,6 +39,14 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
Xil_Out32 (offset, RegVal);
}
+ void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) {
+ int rdata =0;
+ rdata = Xil_In32(addr);
+ rdata = rdata & (~mask);
+ rdata = rdata | (value << shift);
+ Xil_Out32(addr,rdata);
+ }
+
unsigned long psu_pll_init_data() {
// : RPLL INIT
/*Register : RPLL_CFG @ 0XFF5E0034
@@ -841,99 +858,6 @@ unsigned long psu_pll_init_data() {
}
unsigned long psu_clock_init_data() {
// : CLOCK CONTROL SLCR REGISTER
- /*Register : GEM0_REF_CTRL @ 0XFF5E0050
-
- Clock active for the RX channel
- PSU_CRL_APB_GEM0_REF_CTRL_RX_CLKACT 0x1
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_GEM0_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR0 0x8
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_GEM0_REF_CTRL_SRCSEL 0x0
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E0050, 0x063F3F07U ,0x06010800U)
- RegMask = (CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM0_REF_CTRL_CLKACT_MASK | CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT
- | 0x00000008U << CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000000U << CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_GEM0_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010800U);
- /*############################################################################################################################ */
-
- /*Register : GEM1_REF_CTRL @ 0XFF5E0054
-
- Clock active for the RX channel
- PSU_CRL_APB_GEM1_REF_CTRL_RX_CLKACT 0x1
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_GEM1_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR0 0x8
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_GEM1_REF_CTRL_SRCSEL 0x0
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E0054, 0x063F3F07U ,0x06010800U)
- RegMask = (CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM1_REF_CTRL_CLKACT_MASK | CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT
- | 0x00000008U << CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000000U << CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_GEM1_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010800U);
- /*############################################################################################################################ */
-
- /*Register : GEM2_REF_CTRL @ 0XFF5E0058
-
- Clock active for the RX channel
- PSU_CRL_APB_GEM2_REF_CTRL_RX_CLKACT 0x1
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_GEM2_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR0 0x8
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_GEM2_REF_CTRL_SRCSEL 0x0
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E0058, 0x063F3F07U ,0x06010800U)
- RegMask = (CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM2_REF_CTRL_CLKACT_MASK | CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT
- | 0x00000008U << CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000000U << CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_GEM2_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010800U);
- /*############################################################################################################################ */
-
/*Register : GEM3_REF_CTRL @ 0XFF5E005C
Clock active for the RX channel
@@ -965,33 +889,6 @@ unsigned long psu_clock_init_data() {
PSU_Mask_Write (CRL_APB_GEM3_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010C00U);
/*############################################################################################################################ */
- /*Register : GEM_TSU_REF_CTRL @ 0XFF5E0100
-
- 6 bit divider
- PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x2
-
- 6 bit divider
- PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010602U)
- RegMask = (CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK | CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK | 0 );
-
- RegVal = ((0x00000006U << CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000002U << CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT
- | 0x00000001U << CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT
- | 0x00000001U << CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_GEM_TSU_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010602U);
- /*############################################################################################################################ */
-
/*Register : USB0_BUS_REF_CTRL @ 0XFF5E0060
Clock active signal. Switch to 0 to disable the clock
@@ -1019,33 +916,6 @@ unsigned long psu_clock_init_data() {
PSU_Mask_Write (CRL_APB_USB0_BUS_REF_CTRL_OFFSET ,0x023F3F07U ,0x02010600U);
/*############################################################################################################################ */
- /*Register : USB1_BUS_REF_CTRL @ 0XFF5E0064
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_USB1_BUS_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0 0x4
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_USB1_BUS_REF_CTRL_SRCSEL 0x0
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E0064, 0x023F3F07U ,0x02010400U)
- RegMask = (CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT
- | 0x00000004U << CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000000U << CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_USB1_BUS_REF_CTRL_OFFSET ,0x023F3F07U ,0x02010400U);
- /*############################################################################################################################ */
-
/*Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C
Clock active signal. Switch to 0 to disable the clock
@@ -1100,33 +970,6 @@ unsigned long psu_clock_init_data() {
PSU_Mask_Write (CRL_APB_QSPI_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010C00U);
/*############################################################################################################################ */
- /*Register : SDIO0_REF_CTRL @ 0XFF5E006C
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_SDIO0_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR0 0x7
-
- 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_SDIO0_REF_CTRL_SRCSEL 0x2
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E006C, 0x013F3F07U ,0x01010702U)
- RegMask = (CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT
- | 0x00000007U << CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000002U << CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_SDIO0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010702U);
- /*############################################################################################################################ */
-
/*Register : SDIO1_REF_CTRL @ 0XFF5E0070
Clock active signal. Switch to 0 to disable the clock
@@ -1276,87 +1119,6 @@ unsigned long psu_clock_init_data() {
PSU_Mask_Write (CRL_APB_I2C1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
/*############################################################################################################################ */
- /*Register : SPI0_REF_CTRL @ 0XFF5E007C
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_SPI0_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0 0x7
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL 0x2
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E007C, 0x013F3F07U ,0x01010702U)
- RegMask = (CRL_APB_SPI0_REF_CTRL_CLKACT_MASK | CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK | CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK | CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT
- | 0x00000007U << CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000002U << CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_SPI0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010702U);
- /*############################################################################################################################ */
-
- /*Register : SPI1_REF_CTRL @ 0XFF5E0080
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_SPI1_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0 0x7
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL 0x2
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E0080, 0x013F3F07U ,0x01010702U)
- RegMask = (CRL_APB_SPI1_REF_CTRL_CLKACT_MASK | CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT
- | 0x00000007U << CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000002U << CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_SPI1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010702U);
- /*############################################################################################################################ */
-
- /*Register : CAN0_REF_CTRL @ 0XFF5E0084
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_CAN0_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR0 0xa
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_CAN0_REF_CTRL_SRCSEL 0x0
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E0084, 0x013F3F07U ,0x01010A00U)
- RegMask = (CRL_APB_CAN0_REF_CTRL_CLKACT_MASK | CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT
- | 0x0000000AU << CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000000U << CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_CAN0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010A00U);
- /*############################################################################################################################ */
-
/*Register : CAN1_REF_CTRL @ 0XFF5E0088
Clock active signal. Switch to 0 to disable the clock
@@ -1431,29 +1193,6 @@ unsigned long psu_clock_init_data() {
PSU_Mask_Write (CRL_APB_IOU_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
/*############################################################################################################################ */
- /*Register : CSU_PLL_CTRL @ 0XFF5E00A0
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_CSU_PLL_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_CSU_PLL_CTRL_DIVISOR0 0x3
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_CSU_PLL_CTRL_SRCSEL 0x2
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E00A0, 0x01003F07U ,0x01000302U)
- RegMask = (CRL_APB_CSU_PLL_CTRL_CLKACT_MASK | CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK | CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT
- | 0x00000003U << CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT
- | 0x00000002U << CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_CSU_PLL_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
- /*############################################################################################################################ */
-
/*Register : PCAP_CTRL @ 0XFF5E00A4
Clock active signal. Switch to 0 to disable the clock
@@ -1546,33 +1285,6 @@ unsigned long psu_clock_init_data() {
PSU_Mask_Write (CRL_APB_DBG_LPD_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
/*############################################################################################################################ */
- /*Register : NAND_REF_CTRL @ 0XFF5E00B4
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRL_APB_NAND_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRL_APB_NAND_REF_CTRL_DIVISOR1 0x1
-
- 6 bit divider
- PSU_CRL_APB_NAND_REF_CTRL_DIVISOR0 0xa
-
- 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)
- PSU_CRL_APB_NAND_REF_CTRL_SRCSEL 0x0
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E00B4, 0x013F3F07U ,0x01010A00U)
- RegMask = (CRL_APB_NAND_REF_CTRL_CLKACT_MASK | CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK | CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK | CRL_APB_NAND_REF_CTRL_SRCSEL_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT
- | 0x00000001U << CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT
- | 0x0000000AU << CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000000U << CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_NAND_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010A00U);
- /*############################################################################################################################ */
-
/*Register : ADMA_REF_CTRL @ 0XFF5E00B8
Clock active signal. Switch to 0 to disable the clock
@@ -2112,29 +1824,6 @@ unsigned long psu_clock_init_data() {
PSU_Mask_Write (CRF_APB_TOPSW_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000502U);
/*############################################################################################################################ */
- /*Register : GTGREF0_REF_CTRL @ 0XFD1A00C8
-
- 6 bit divider
- PSU_CRF_APB_GTGREF0_REF_CTRL_DIVISOR0 0x4
-
- 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
- he new clock. This is not usually an issue, but designers must be aware.)
- PSU_CRF_APB_GTGREF0_REF_CTRL_SRCSEL 0x0
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRF_APB_GTGREF0_REF_CTRL_CLKACT 0x1
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFD1A00C8, 0x01003F07U ,0x01000400U)
- RegMask = (CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK | CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK | CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK | 0 );
-
- RegVal = ((0x00000004U << CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT
- | 0x00000000U << CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT
- | 0x00000001U << CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRF_APB_GTGREF0_REF_CTRL_OFFSET ,0x01003F07U ,0x01000400U);
- /*############################################################################################################################ */
-
/*Register : DBG_TSTMP_CTRL @ 0XFD1A00F8
6 bit divider
@@ -3305,22 +2994,22 @@ unsigned long psu_ddr_init_data() {
ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t
is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L
DDR2/LPDDR3/LPDDR4 devices.
- PSU_DDRC_DRAMTMG7_T_CKPDE 0x1
+ PSU_DDRC_DRAMTMG7_T_CKPDE 0x6
This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable
time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO=
, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti
g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
- PSU_DDRC_DRAMTMG7_T_CKPDX 0x1
+ PSU_DDRC_DRAMTMG7_T_CKPDX 0x6
SDRAM Timing Register 7
- (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000101U)
+ (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U)
RegMask = (DDRC_DRAMTMG7_T_CKPDE_MASK | DDRC_DRAMTMG7_T_CKPDX_MASK | 0 );
- RegVal = ((0x00000001U << DDRC_DRAMTMG7_T_CKPDE_SHIFT
- | 0x00000001U << DDRC_DRAMTMG7_T_CKPDX_SHIFT
+ RegVal = ((0x00000006U << DDRC_DRAMTMG7_T_CKPDE_SHIFT
+ | 0x00000006U << DDRC_DRAMTMG7_T_CKPDX_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDRC_DRAMTMG7_OFFSET ,0x00000F0FU ,0x00000101U);
+ PSU_Mask_Write (DDRC_DRAMTMG7_OFFSET ,0x00000F0FU ,0x00000606U);
/*############################################################################################################################ */
/*Register : DRAMTMG8 @ 0XFD070120
@@ -3643,13 +3332,13 @@ unsigned long psu_ddr_init_data() {
s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20
8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107
cycles - 0xE - 262144 cycles - 0xF - Unlimited
- PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x4
+ PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0
Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled
PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1
DFI Low Power Configuration Register 0
- (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000141U)
+ (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U)
RegMask = (DDRC_DFILPCFG0_DFI_TLP_RESP_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK | DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK | 0 );
RegVal = ((0x00000007U << DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT
@@ -3657,10 +3346,10 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT
| 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT
| 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT
- | 0x00000004U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT
+ | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT
| 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDRC_DFILPCFG0_OFFSET ,0x0FF1F1F1U ,0x07000141U);
+ PSU_Mask_Write (DDRC_DFILPCFG0_OFFSET ,0x0FF1F1F1U ,0x07000101U);
/*############################################################################################################################ */
/*Register : DFILPCFG1 @ 0XFD07019C
@@ -5607,10 +5296,10 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0
Refresh Period
- PSU_DDR_PHY_PGCR2_TREFPRD 0x12302
+ PSU_DDR_PHY_PGCR2_TREFPRD 0x10028
PHY General Configuration Register 2
- (OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F12302U)
+ (OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10028U)
RegMask = (DDR_PHY_PGCR2_CLRTSTAT_MASK | DDR_PHY_PGCR2_CLRZCAL_MASK | DDR_PHY_PGCR2_CLRPERR_MASK | DDR_PHY_PGCR2_ICPC_MASK | DDR_PHY_PGCR2_DTPMXTMR_MASK | DDR_PHY_PGCR2_INITFSMBYP_MASK | DDR_PHY_PGCR2_PLLFSMBYP_MASK | DDR_PHY_PGCR2_TREFPRD_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_PGCR2_CLRTSTAT_SHIFT
@@ -5620,9 +5309,67 @@ unsigned long psu_ddr_init_data() {
| 0x0000000FU << DDR_PHY_PGCR2_DTPMXTMR_SHIFT
| 0x00000000U << DDR_PHY_PGCR2_INITFSMBYP_SHIFT
| 0x00000000U << DDR_PHY_PGCR2_PLLFSMBYP_SHIFT
- | 0x00012302U << DDR_PHY_PGCR2_TREFPRD_SHIFT
+ | 0x00010028U << DDR_PHY_PGCR2_TREFPRD_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_PGCR2_OFFSET ,0xFFFFFFFFU ,0x00F10028U);
+ /*############################################################################################################################ */
+
+ /*Register : PGCR3 @ 0XFD08001C
+
+ CKN Enable
+ PSU_DDR_PHY_PGCR3_CKNEN 0x55
+
+ CK Enable
+ PSU_DDR_PHY_PGCR3_CKEN 0xaa
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_PGCR3_RESERVED_15 0x0
+
+ Enable Clock Gating for AC [0] ctl_rd_clk
+ PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2
+
+ Enable Clock Gating for AC [0] ddr_clk
+ PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2
+
+ Enable Clock Gating for AC [0] ctl_clk
+ PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_PGCR3_RESERVED_8 0x0
+
+ Controls DDL Bypass Modes
+ PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2
+
+ IO Loop-Back Select
+ PSU_DDR_PHY_PGCR3_IOLB 0x0
+
+ AC Receive FIFO Read Mode
+ PSU_DDR_PHY_PGCR3_RDMODE 0x0
+
+ Read FIFO Reset Disable
+ PSU_DDR_PHY_PGCR3_DISRST 0x0
+
+ Clock Level when Clock Gating
+ PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0
+
+ PHY General Configuration Register 3
+ (OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U)
+ RegMask = (DDR_PHY_PGCR3_CKNEN_MASK | DDR_PHY_PGCR3_CKEN_MASK | DDR_PHY_PGCR3_RESERVED_15_MASK | DDR_PHY_PGCR3_GATEACRDCLK_MASK | DDR_PHY_PGCR3_GATEACDDRCLK_MASK | DDR_PHY_PGCR3_GATEACCTLCLK_MASK | DDR_PHY_PGCR3_RESERVED_8_MASK | DDR_PHY_PGCR3_DDLBYPMODE_MASK | DDR_PHY_PGCR3_IOLB_MASK | DDR_PHY_PGCR3_RDMODE_MASK | DDR_PHY_PGCR3_DISRST_MASK | DDR_PHY_PGCR3_CLKLEVEL_MASK | 0 );
+
+ RegVal = ((0x00000055U << DDR_PHY_PGCR3_CKNEN_SHIFT
+ | 0x000000AAU << DDR_PHY_PGCR3_CKEN_SHIFT
+ | 0x00000000U << DDR_PHY_PGCR3_RESERVED_15_SHIFT
+ | 0x00000002U << DDR_PHY_PGCR3_GATEACRDCLK_SHIFT
+ | 0x00000002U << DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT
+ | 0x00000002U << DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT
+ | 0x00000000U << DDR_PHY_PGCR3_RESERVED_8_SHIFT
+ | 0x00000002U << DDR_PHY_PGCR3_DDLBYPMODE_SHIFT
+ | 0x00000000U << DDR_PHY_PGCR3_IOLB_SHIFT
+ | 0x00000000U << DDR_PHY_PGCR3_RDMODE_SHIFT
+ | 0x00000000U << DDR_PHY_PGCR3_DISRST_SHIFT
+ | 0x00000000U << DDR_PHY_PGCR3_CLKLEVEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_PGCR2_OFFSET ,0xFFFFFFFFU ,0x00F12302U);
+ PSU_Mask_Write (DDR_PHY_PGCR3_OFFSET ,0xFFFFFFFFU ,0x55AA5480U);
/*############################################################################################################################ */
/*Register : PGCR5 @ 0XFD080024
@@ -5878,16 +5625,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DTPR0_RESERVED_15 0x0
Precharge command period
- PSU_DDR_PHY_DTPR0_TRP 0x12
+ PSU_DDR_PHY_DTPR0_TRP 0xf
Reserved. Return zeroes on reads.
PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0
Internal read to precharge command delay
- PSU_DDR_PHY_DTPR0_TRTP 0x8
+ PSU_DDR_PHY_DTPR0_TRTP 0x9
DRAM Timing Parameters Register 0
- (OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06241208U)
+ (OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F09U)
RegMask = (DDR_PHY_DTPR0_RESERVED_31_29_MASK | DDR_PHY_DTPR0_TRRD_MASK | DDR_PHY_DTPR0_RESERVED_23_MASK | DDR_PHY_DTPR0_TRAS_MASK | DDR_PHY_DTPR0_RESERVED_15_MASK | DDR_PHY_DTPR0_TRP_MASK | DDR_PHY_DTPR0_RESERVED_7_5_MASK | DDR_PHY_DTPR0_TRTP_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DTPR0_RESERVED_31_29_SHIFT
@@ -5895,11 +5642,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DTPR0_RESERVED_23_SHIFT
| 0x00000024U << DDR_PHY_DTPR0_TRAS_SHIFT
| 0x00000000U << DDR_PHY_DTPR0_RESERVED_15_SHIFT
- | 0x00000012U << DDR_PHY_DTPR0_TRP_SHIFT
+ | 0x0000000FU << DDR_PHY_DTPR0_TRP_SHIFT
| 0x00000000U << DDR_PHY_DTPR0_RESERVED_7_5_SHIFT
- | 0x00000008U << DDR_PHY_DTPR0_TRTP_SHIFT
+ | 0x00000009U << DDR_PHY_DTPR0_TRTP_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DTPR0_OFFSET ,0xFFFFFFFFU ,0x06241208U);
+ PSU_Mask_Write (DDR_PHY_DTPR0_OFFSET ,0xFFFFFFFFU ,0x06240F09U);
/*############################################################################################################################ */
/*Register : DTPR1 @ 0XFD080114
@@ -6007,10 +5754,10 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0
DQS output access time from CK/CK# (LPDDR2/3 only)
- PSU_DDR_PHY_DTPR3_TDQSCK 0x4
+ PSU_DDR_PHY_DTPR3_TDQSCK 0x0
DRAM Timing Parameters Register 3
- (OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000804U)
+ (OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U)
RegMask = (DDR_PHY_DTPR3_TOFDX_MASK | DDR_PHY_DTPR3_TCCD_MASK | DDR_PHY_DTPR3_TDLLK_MASK | DDR_PHY_DTPR3_RESERVED_15_12_MASK | DDR_PHY_DTPR3_TDQSCKMAX_MASK | DDR_PHY_DTPR3_RESERVED_7_3_MASK | DDR_PHY_DTPR3_TDQSCK_MASK | 0 );
RegVal = ((0x00000004U << DDR_PHY_DTPR3_TOFDX_SHIFT
@@ -6019,9 +5766,9 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DTPR3_RESERVED_15_12_SHIFT
| 0x00000008U << DDR_PHY_DTPR3_TDQSCKMAX_SHIFT
| 0x00000000U << DDR_PHY_DTPR3_RESERVED_7_3_SHIFT
- | 0x00000004U << DDR_PHY_DTPR3_TDQSCK_SHIFT
+ | 0x00000000U << DDR_PHY_DTPR3_TDQSCK_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DTPR3_OFFSET ,0xFFFFFFFFU ,0x83000804U);
+ PSU_Mask_Write (DDR_PHY_DTPR3_OFFSET ,0xFFFFFFFFU ,0x83000800U);
/*############################################################################################################################ */
/*Register : DTPR4 @ 0XFD080120
@@ -6270,6 +6017,50 @@ unsigned long psu_ddr_init_data() {
PSU_Mask_Write (DDR_PHY_RDIMMGCR1_OFFSET ,0xFFFFFFFFU ,0x00000C80U);
/*############################################################################################################################ */
+ /*Register : RDIMMCR0 @ 0XFD080150
+
+ DDR4/DDR3 Control Word 7
+ PSU_DDR_PHY_RDIMMCR0_RC7 0x0
+
+ DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved
+ PSU_DDR_PHY_RDIMMCR0_RC6 0x0
+
+ DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)
+ PSU_DDR_PHY_RDIMMCR0_RC5 0x0
+
+ DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C
+ aracteristics Control Word)
+ PSU_DDR_PHY_RDIMMCR0_RC4 0x0
+
+ DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr
+ ver Characteristrics Control Word)
+ PSU_DDR_PHY_RDIMMCR0_RC3 0x0
+
+ DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)
+ PSU_DDR_PHY_RDIMMCR0_RC2 0x0
+
+ DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)
+ PSU_DDR_PHY_RDIMMCR0_RC1 0x0
+
+ DDR4/DDR3 Control Word 0 (Global Features Control Word)
+ PSU_DDR_PHY_RDIMMCR0_RC0 0x0
+
+ RDIMM Control Register 0
+ (OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U)
+ RegMask = (DDR_PHY_RDIMMCR0_RC7_MASK | DDR_PHY_RDIMMCR0_RC6_MASK | DDR_PHY_RDIMMCR0_RC5_MASK | DDR_PHY_RDIMMCR0_RC4_MASK | DDR_PHY_RDIMMCR0_RC3_MASK | DDR_PHY_RDIMMCR0_RC2_MASK | DDR_PHY_RDIMMCR0_RC1_MASK | DDR_PHY_RDIMMCR0_RC0_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_RDIMMCR0_RC7_SHIFT
+ | 0x00000000U << DDR_PHY_RDIMMCR0_RC6_SHIFT
+ | 0x00000000U << DDR_PHY_RDIMMCR0_RC5_SHIFT
+ | 0x00000000U << DDR_PHY_RDIMMCR0_RC4_SHIFT
+ | 0x00000000U << DDR_PHY_RDIMMCR0_RC3_SHIFT
+ | 0x00000000U << DDR_PHY_RDIMMCR0_RC2_SHIFT
+ | 0x00000000U << DDR_PHY_RDIMMCR0_RC1_SHIFT
+ | 0x00000000U << DDR_PHY_RDIMMCR0_RC0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_RDIMMCR0_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+ /*############################################################################################################################ */
+
/*Register : RDIMMCR1 @ 0XFD080154
Control Word 15
@@ -6767,7 +6558,7 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0
Data Training Debug Rank Select
- PSU_DDR_PHY_DTCR0_DTDRS 0x1
+ PSU_DDR_PHY_DTCR0_DTDRS 0x0
Data Training with Early/Extended Gate
PSU_DDR_PHY_DTCR0_DTEXG 0x0
@@ -6785,7 +6576,7 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DTCR0_DTDBS 0x0
Data Training read DBI deskewing configuration
- PSU_DDR_PHY_DTCR0_DTRDBITR 0x0
+ PSU_DDR_PHY_DTCR0_DTRDBITR 0x2
Reserved. Return zeroes on reads.
PSU_DDR_PHY_DTCR0_RESERVED_13 0x0
@@ -6809,18 +6600,18 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DTCR0_DTRPTN 0x7
Data Training Configuration Register 0
- (OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x810011C7U)
+ (OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U)
RegMask = (DDR_PHY_DTCR0_RFSHDT_MASK | DDR_PHY_DTCR0_RESERVED_27_26_MASK | DDR_PHY_DTCR0_DTDRS_MASK | DDR_PHY_DTCR0_DTEXG_MASK | DDR_PHY_DTCR0_DTEXD_MASK | DDR_PHY_DTCR0_DTDSTP_MASK | DDR_PHY_DTCR0_DTDEN_MASK | DDR_PHY_DTCR0_DTDBS_MASK | DDR_PHY_DTCR0_DTRDBITR_MASK | DDR_PHY_DTCR0_RESERVED_13_MASK | DDR_PHY_DTCR0_DTWBDDM_MASK | DDR_PHY_DTCR0_RFSHEN_MASK | DDR_PHY_DTCR0_DTCMPD_MASK | DDR_PHY_DTCR0_DTMPR_MASK | DDR_PHY_DTCR0_RESERVED_5_4_MASK | DDR_PHY_DTCR0_DTRPTN_MASK | 0 );
RegVal = ((0x00000008U << DDR_PHY_DTCR0_RFSHDT_SHIFT
| 0x00000000U << DDR_PHY_DTCR0_RESERVED_27_26_SHIFT
- | 0x00000001U << DDR_PHY_DTCR0_DTDRS_SHIFT
+ | 0x00000000U << DDR_PHY_DTCR0_DTDRS_SHIFT
| 0x00000000U << DDR_PHY_DTCR0_DTEXG_SHIFT
| 0x00000000U << DDR_PHY_DTCR0_DTEXD_SHIFT
| 0x00000000U << DDR_PHY_DTCR0_DTDSTP_SHIFT
| 0x00000000U << DDR_PHY_DTCR0_DTDEN_SHIFT
| 0x00000000U << DDR_PHY_DTCR0_DTDBS_SHIFT
- | 0x00000000U << DDR_PHY_DTCR0_DTRDBITR_SHIFT
+ | 0x00000002U << DDR_PHY_DTCR0_DTRDBITR_SHIFT
| 0x00000000U << DDR_PHY_DTCR0_RESERVED_13_SHIFT
| 0x00000001U << DDR_PHY_DTCR0_DTWBDDM_SHIFT
| 0x00000001U << DDR_PHY_DTCR0_RFSHEN_SHIFT
@@ -6829,7 +6620,7 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DTCR0_RESERVED_5_4_SHIFT
| 0x00000007U << DDR_PHY_DTCR0_DTRPTN_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DTCR0_OFFSET ,0xFFFFFFFFU ,0x810011C7U);
+ PSU_Mask_Write (DDR_PHY_DTCR0_OFFSET ,0xFFFFFFFFU ,0x800091C7U);
/*############################################################################################################################ */
/*Register : DTCR1 @ 0XFD080204
@@ -6925,6 +6716,20 @@ unsigned long psu_ddr_init_data() {
PSU_Mask_Write (DDR_PHY_CATR0_OFFSET ,0xFFFFFFFFU ,0x00141054U);
/*############################################################################################################################ */
+ /*Register : BISTLSR @ 0XFD080414
+
+ LFSR seed for pseudo-random BIST patterns
+ PSU_DDR_PHY_BISTLSR_SEED 0x12341000
+
+ BIST LFSR Seed Register
+ (OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U)
+ RegMask = (DDR_PHY_BISTLSR_SEED_MASK | 0 );
+
+ RegVal = ((0x12341000U << DDR_PHY_BISTLSR_SEED_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_BISTLSR_OFFSET ,0xFFFFFFFFU ,0x12341000U);
+ /*############################################################################################################################ */
+
/*Register : RIOCR5 @ 0XFD0804F4
Reserved. Return zeroes on reads.
@@ -7250,13 +7055,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_VTCR1_SHREN 0x1
Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training
- PSU_DDR_PHY_VTCR1_TVREFIO 0x4
+ PSU_DDR_PHY_VTCR1_TVREFIO 0x7
Eye LCDL Offset value for VREF training
- PSU_DDR_PHY_VTCR1_EOFF 0x1
+ PSU_DDR_PHY_VTCR1_EOFF 0x0
Number of LCDL Eye points for which VREF training is repeated
- PSU_DDR_PHY_VTCR1_ENUM 0x1
+ PSU_DDR_PHY_VTCR1_ENUM 0x0
HOST (IO) internal VREF training Enable
PSU_DDR_PHY_VTCR1_HVEN 0x1
@@ -7265,7 +7070,7 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_VTCR1_HVIO 0x1
VREF Training Control Register 1
- (OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F0018FU)
+ (OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U)
RegMask = (DDR_PHY_VTCR1_HVSS_MASK | DDR_PHY_VTCR1_RESERVED_27_MASK | DDR_PHY_VTCR1_HVMAX_MASK | DDR_PHY_VTCR1_RESERVED_19_MASK | DDR_PHY_VTCR1_HVMIN_MASK | DDR_PHY_VTCR1_RESERVED_11_MASK | DDR_PHY_VTCR1_SHRNK_MASK | DDR_PHY_VTCR1_SHREN_MASK | DDR_PHY_VTCR1_TVREFIO_MASK | DDR_PHY_VTCR1_EOFF_MASK | DDR_PHY_VTCR1_ENUM_MASK | DDR_PHY_VTCR1_HVEN_MASK | DDR_PHY_VTCR1_HVIO_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_VTCR1_HVSS_SHIFT
@@ -7276,69 +7081,153 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_VTCR1_RESERVED_11_SHIFT
| 0x00000000U << DDR_PHY_VTCR1_SHRNK_SHIFT
| 0x00000001U << DDR_PHY_VTCR1_SHREN_SHIFT
- | 0x00000004U << DDR_PHY_VTCR1_TVREFIO_SHIFT
- | 0x00000001U << DDR_PHY_VTCR1_EOFF_SHIFT
- | 0x00000001U << DDR_PHY_VTCR1_ENUM_SHIFT
+ | 0x00000007U << DDR_PHY_VTCR1_TVREFIO_SHIFT
+ | 0x00000000U << DDR_PHY_VTCR1_EOFF_SHIFT
+ | 0x00000000U << DDR_PHY_VTCR1_ENUM_SHIFT
| 0x00000001U << DDR_PHY_VTCR1_HVEN_SHIFT
| 0x00000001U << DDR_PHY_VTCR1_HVIO_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_VTCR1_OFFSET ,0xFFFFFFFFU ,0x07F0018FU);
+ PSU_Mask_Write (DDR_PHY_VTCR1_OFFSET ,0xFFFFFFFFU ,0x07F001E3U);
/*############################################################################################################################ */
- /*Register : ACBDLR6 @ 0XFD080558
+ /*Register : ACBDLR1 @ 0XFD080544
Reserved. Return zeroes on reads.
- PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0
+ PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0
- Delay select for the BDL on Address A[3].
- PSU_DDR_PHY_ACBDLR6_A03BD 0x0
+ Delay select for the BDL on Parity.
+ PSU_DDR_PHY_ACBDLR1_PARBD 0x0
Reserved. Return zeroes on reads.
- PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0
+ PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0
- Delay select for the BDL on Address A[2].
- PSU_DDR_PHY_ACBDLR6_A02BD 0x0
+ Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE.
+ PSU_DDR_PHY_ACBDLR1_A16BD 0x0
Reserved. Return zeroes on reads.
- PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0
+ PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0
- Delay select for the BDL on Address A[1].
- PSU_DDR_PHY_ACBDLR6_A01BD 0x0
+ Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS.
+ PSU_DDR_PHY_ACBDLR1_A17BD 0x0
Reserved. Return zeroes on reads.
- PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0
+ PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0
- Delay select for the BDL on Address A[0].
- PSU_DDR_PHY_ACBDLR6_A00BD 0x0
+ Delay select for the BDL on ACTN.
+ PSU_DDR_PHY_ACBDLR1_ACTBD 0x0
- AC Bit Delay Line Register 6
- (OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U)
- RegMask = (DDR_PHY_ACBDLR6_RESERVED_31_30_MASK | DDR_PHY_ACBDLR6_A03BD_MASK | DDR_PHY_ACBDLR6_RESERVED_23_22_MASK | DDR_PHY_ACBDLR6_A02BD_MASK | DDR_PHY_ACBDLR6_RESERVED_15_14_MASK | DDR_PHY_ACBDLR6_A01BD_MASK | DDR_PHY_ACBDLR6_RESERVED_7_6_MASK | DDR_PHY_ACBDLR6_A00BD_MASK | 0 );
+ AC Bit Delay Line Register 1
+ (OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U)
+ RegMask = (DDR_PHY_ACBDLR1_RESERVED_31_30_MASK | DDR_PHY_ACBDLR1_PARBD_MASK | DDR_PHY_ACBDLR1_RESERVED_23_22_MASK | DDR_PHY_ACBDLR1_A16BD_MASK | DDR_PHY_ACBDLR1_RESERVED_15_14_MASK | DDR_PHY_ACBDLR1_A17BD_MASK | DDR_PHY_ACBDLR1_RESERVED_7_6_MASK | DDR_PHY_ACBDLR1_ACTBD_MASK | 0 );
- RegVal = ((0x00000000U << DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT
- | 0x00000000U << DDR_PHY_ACBDLR6_A03BD_SHIFT
- | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT
- | 0x00000000U << DDR_PHY_ACBDLR6_A02BD_SHIFT
- | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT
- | 0x00000000U << DDR_PHY_ACBDLR6_A01BD_SHIFT
- | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT
- | 0x00000000U << DDR_PHY_ACBDLR6_A00BD_SHIFT
+ RegVal = ((0x00000000U << DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR1_PARBD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR1_A16BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR1_A17BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR1_ACTBD_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_ACBDLR6_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+ PSU_Mask_Write (DDR_PHY_ACBDLR1_OFFSET ,0xFFFFFFFFU ,0x00000000U);
/*############################################################################################################################ */
- /*Register : ACBDLR7 @ 0XFD08055C
+ /*Register : ACBDLR2 @ 0XFD080548
Reserved. Return zeroes on reads.
- PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0
+ PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0
- Delay select for the BDL on Address A[7].
- PSU_DDR_PHY_ACBDLR7_A07BD 0x0
+ Delay select for the BDL on BG[1].
+ PSU_DDR_PHY_ACBDLR2_BG1BD 0x0
Reserved. Return zeroes on reads.
- PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0
+ PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0
- Delay select for the BDL on Address A[6].
+ Delay select for the BDL on BG[0].
+ PSU_DDR_PHY_ACBDLR2_BG0BD 0x0
+
+ Reser.ved Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0
+
+ Delay select for the BDL on BA[1].
+ PSU_DDR_PHY_ACBDLR2_BA1BD 0x0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0
+
+ Delay select for the BDL on BA[0].
+ PSU_DDR_PHY_ACBDLR2_BA0BD 0x0
+
+ AC Bit Delay Line Register 2
+ (OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U)
+ RegMask = (DDR_PHY_ACBDLR2_RESERVED_31_30_MASK | DDR_PHY_ACBDLR2_BG1BD_MASK | DDR_PHY_ACBDLR2_RESERVED_23_22_MASK | DDR_PHY_ACBDLR2_BG0BD_MASK | DDR_PHY_ACBDLR2_RESERVED_15_14_MASK | DDR_PHY_ACBDLR2_BA1BD_MASK | DDR_PHY_ACBDLR2_RESERVED_7_6_MASK | DDR_PHY_ACBDLR2_BA0BD_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR2_BG1BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR2_BG0BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR2_BA1BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR2_BA0BD_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_ACBDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : ACBDLR6 @ 0XFD080558
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0
+
+ Delay select for the BDL on Address A[3].
+ PSU_DDR_PHY_ACBDLR6_A03BD 0x0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0
+
+ Delay select for the BDL on Address A[2].
+ PSU_DDR_PHY_ACBDLR6_A02BD 0x0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0
+
+ Delay select for the BDL on Address A[1].
+ PSU_DDR_PHY_ACBDLR6_A01BD 0x0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0
+
+ Delay select for the BDL on Address A[0].
+ PSU_DDR_PHY_ACBDLR6_A00BD 0x0
+
+ AC Bit Delay Line Register 6
+ (OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U)
+ RegMask = (DDR_PHY_ACBDLR6_RESERVED_31_30_MASK | DDR_PHY_ACBDLR6_A03BD_MASK | DDR_PHY_ACBDLR6_RESERVED_23_22_MASK | DDR_PHY_ACBDLR6_A02BD_MASK | DDR_PHY_ACBDLR6_RESERVED_15_14_MASK | DDR_PHY_ACBDLR6_A01BD_MASK | DDR_PHY_ACBDLR6_RESERVED_7_6_MASK | DDR_PHY_ACBDLR6_A00BD_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR6_A03BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR6_A02BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR6_A01BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR6_A00BD_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_ACBDLR6_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : ACBDLR7 @ 0XFD08055C
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0
+
+ Delay select for the BDL on Address A[7].
+ PSU_DDR_PHY_ACBDLR7_A07BD 0x0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0
+
+ Delay select for the BDL on Address A[6].
PSU_DDR_PHY_ACBDLR7_A06BD 0x0
Reserved. Return zeroes on reads.
@@ -7411,6 +7300,48 @@ unsigned long psu_ddr_init_data() {
PSU_Mask_Write (DDR_PHY_ACBDLR8_OFFSET ,0xFFFFFFFFU ,0x00000000U);
/*############################################################################################################################ */
+ /*Register : ACBDLR9 @ 0XFD080564
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0
+
+ Delay select for the BDL on Address A[15].
+ PSU_DDR_PHY_ACBDLR9_A15BD 0x0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0
+
+ Delay select for the BDL on Address A[14].
+ PSU_DDR_PHY_ACBDLR9_A14BD 0x0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0
+
+ Delay select for the BDL on Address A[13].
+ PSU_DDR_PHY_ACBDLR9_A13BD 0x0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0
+
+ Delay select for the BDL on Address A[12].
+ PSU_DDR_PHY_ACBDLR9_A12BD 0x0
+
+ AC Bit Delay Line Register 9
+ (OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U)
+ RegMask = (DDR_PHY_ACBDLR9_RESERVED_31_30_MASK | DDR_PHY_ACBDLR9_A15BD_MASK | DDR_PHY_ACBDLR9_RESERVED_23_22_MASK | DDR_PHY_ACBDLR9_A14BD_MASK | DDR_PHY_ACBDLR9_RESERVED_15_14_MASK | DDR_PHY_ACBDLR9_A13BD_MASK | DDR_PHY_ACBDLR9_RESERVED_7_6_MASK | DDR_PHY_ACBDLR9_A12BD_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR9_A15BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR9_A14BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR9_A13BD_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT
+ | 0x00000000U << DDR_PHY_ACBDLR9_A12BD_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_ACBDLR9_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+ /*############################################################################################################################ */
+
/*Register : ZQCR @ 0XFD080680
Reserved. Return zeroes on reads.
@@ -7803,16 +7734,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX0GCR5_RESERVED_31_MASK | DDR_PHY_DX0GCR5_DXREFISELR3_MASK | DDR_PHY_DX0GCR5_RESERVED_23_MASK | DDR_PHY_DX0GCR5_DXREFISELR2_MASK | DDR_PHY_DX0GCR5_RESERVED_15_MASK | DDR_PHY_DX0GCR5_DXREFISELR1_MASK | DDR_PHY_DX0GCR5_RESERVED_7_MASK | DDR_PHY_DX0GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX0GCR5_RESERVED_31_SHIFT
@@ -7820,11 +7751,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX0GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX0GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX0GCR6 @ 0XFD080718
@@ -8091,16 +8022,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX1GCR5_RESERVED_31_MASK | DDR_PHY_DX1GCR5_DXREFISELR3_MASK | DDR_PHY_DX1GCR5_RESERVED_23_MASK | DDR_PHY_DX1GCR5_DXREFISELR2_MASK | DDR_PHY_DX1GCR5_RESERVED_15_MASK | DDR_PHY_DX1GCR5_DXREFISELR1_MASK | DDR_PHY_DX1GCR5_RESERVED_7_MASK | DDR_PHY_DX1GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX1GCR5_RESERVED_31_SHIFT
@@ -8108,11 +8039,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX1GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX1GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX1GCR6 @ 0XFD080818
@@ -8429,16 +8360,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX2GCR5_RESERVED_31_MASK | DDR_PHY_DX2GCR5_DXREFISELR3_MASK | DDR_PHY_DX2GCR5_RESERVED_23_MASK | DDR_PHY_DX2GCR5_DXREFISELR2_MASK | DDR_PHY_DX2GCR5_RESERVED_15_MASK | DDR_PHY_DX2GCR5_DXREFISELR1_MASK | DDR_PHY_DX2GCR5_RESERVED_7_MASK | DDR_PHY_DX2GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX2GCR5_RESERVED_31_SHIFT
@@ -8446,11 +8377,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX2GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX2GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX2GCR6 @ 0XFD080918
@@ -8767,16 +8698,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX3GCR5_RESERVED_31_MASK | DDR_PHY_DX3GCR5_DXREFISELR3_MASK | DDR_PHY_DX3GCR5_RESERVED_23_MASK | DDR_PHY_DX3GCR5_DXREFISELR2_MASK | DDR_PHY_DX3GCR5_RESERVED_15_MASK | DDR_PHY_DX3GCR5_DXREFISELR1_MASK | DDR_PHY_DX3GCR5_RESERVED_7_MASK | DDR_PHY_DX3GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX3GCR5_RESERVED_31_SHIFT
@@ -8784,11 +8715,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX3GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX3GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX3GCR6 @ 0XFD080A18
@@ -9105,16 +9036,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX4GCR5_RESERVED_31_MASK | DDR_PHY_DX4GCR5_DXREFISELR3_MASK | DDR_PHY_DX4GCR5_RESERVED_23_MASK | DDR_PHY_DX4GCR5_DXREFISELR2_MASK | DDR_PHY_DX4GCR5_RESERVED_15_MASK | DDR_PHY_DX4GCR5_DXREFISELR1_MASK | DDR_PHY_DX4GCR5_RESERVED_7_MASK | DDR_PHY_DX4GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX4GCR5_RESERVED_31_SHIFT
@@ -9122,11 +9053,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX4GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX4GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX4GCR6 @ 0XFD080B18
@@ -9443,16 +9374,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX5GCR5_RESERVED_31_MASK | DDR_PHY_DX5GCR5_DXREFISELR3_MASK | DDR_PHY_DX5GCR5_RESERVED_23_MASK | DDR_PHY_DX5GCR5_DXREFISELR2_MASK | DDR_PHY_DX5GCR5_RESERVED_15_MASK | DDR_PHY_DX5GCR5_DXREFISELR1_MASK | DDR_PHY_DX5GCR5_RESERVED_7_MASK | DDR_PHY_DX5GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX5GCR5_RESERVED_31_SHIFT
@@ -9460,11 +9391,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX5GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX5GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX5GCR6 @ 0XFD080C18
@@ -9781,16 +9712,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX6GCR5_RESERVED_31_MASK | DDR_PHY_DX6GCR5_DXREFISELR3_MASK | DDR_PHY_DX6GCR5_RESERVED_23_MASK | DDR_PHY_DX6GCR5_DXREFISELR2_MASK | DDR_PHY_DX6GCR5_RESERVED_15_MASK | DDR_PHY_DX6GCR5_DXREFISELR1_MASK | DDR_PHY_DX6GCR5_RESERVED_7_MASK | DDR_PHY_DX6GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX6GCR5_RESERVED_31_SHIFT
@@ -9798,11 +9729,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX6GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX6GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX6GCR6 @ 0XFD080D18
@@ -10119,16 +10050,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX7GCR5_RESERVED_31_MASK | DDR_PHY_DX7GCR5_DXREFISELR3_MASK | DDR_PHY_DX7GCR5_RESERVED_23_MASK | DDR_PHY_DX7GCR5_DXREFISELR2_MASK | DDR_PHY_DX7GCR5_RESERVED_15_MASK | DDR_PHY_DX7GCR5_DXREFISELR1_MASK | DDR_PHY_DX7GCR5_RESERVED_7_MASK | DDR_PHY_DX7GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX7GCR5_RESERVED_31_SHIFT
@@ -10136,11 +10067,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX7GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX7GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX7GCR6 @ 0XFD080E18
@@ -10457,16 +10388,16 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0
Byte Lane internal VREF Select for Rank 1
- PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x55
+ PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x4f
Reserved. Returns zeros on reads.
PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0
Byte Lane internal VREF Select for Rank 0
- PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x55
+ PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x4f
DATX8 n General Configuration Register 5
- (OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09095555U)
+ (OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09094F4FU)
RegMask = (DDR_PHY_DX8GCR5_RESERVED_31_MASK | DDR_PHY_DX8GCR5_DXREFISELR3_MASK | DDR_PHY_DX8GCR5_RESERVED_23_MASK | DDR_PHY_DX8GCR5_DXREFISELR2_MASK | DDR_PHY_DX8GCR5_RESERVED_15_MASK | DDR_PHY_DX8GCR5_DXREFISELR1_MASK | DDR_PHY_DX8GCR5_RESERVED_7_MASK | DDR_PHY_DX8GCR5_DXREFISELR0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8GCR5_RESERVED_31_SHIFT
@@ -10474,11 +10405,11 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_23_SHIFT
| 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT
| 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_15_SHIFT
- | 0x00000055U << DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT
+ | 0x0000004FU << DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT
| 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_7_SHIFT
- | 0x00000055U << DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT
+ | 0x0000004FU << DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+ PSU_Mask_Write (DDR_PHY_DX8GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
/*############################################################################################################################ */
/*Register : DX8GCR6 @ 0XFD080F18
@@ -10591,6 +10522,92 @@ unsigned long psu_ddr_init_data() {
PSU_Mask_Write (DDR_PHY_DX8GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
/*############################################################################################################################ */
+ /*Register : DX8SL0OSC @ 0XFD081400
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0
+
+ Enable Clock Gating for DX ddr_clk
+ PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2
+
+ Enable Clock Gating for DX ctl_rd_clk
+ PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2
+
+ Enable Clock Gating for DX ctl_clk
+ PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2
+
+ Selects the level to which clocks will be stalled when clock gating is enabled.
+ PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0
+
+ Loopback Mode
+ PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0
+
+ Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
+ PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0
+
+ Loopback DQS Gating
+ PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0
+
+ Loopback DQS Shift
+ PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0
+
+ PHY High-Speed Reset
+ PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1
+
+ PHY FIFO Reset
+ PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1
+
+ Delay Line Test Start
+ PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0
+
+ Delay Line Test Mode
+ PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3
+
+ Oscillator Mode Write-Data Delay Line Select
+ PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3
+
+ Oscillator Mode Write-Leveling Delay Line Select
+ PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3
+
+ Oscillator Mode Division
+ PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf
+
+ Oscillator Enable
+ PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0
+
+ DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
+ (OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU)
+ RegMask = (DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL0OSC_LBMODE_MASK | DDR_PHY_DX8SL0OSC_LBGSDQS_MASK | DDR_PHY_DX8SL0OSC_LBGDQS_MASK | DDR_PHY_DX8SL0OSC_LBDQSS_MASK | DDR_PHY_DX8SL0OSC_PHYHRST_MASK | DDR_PHY_DX8SL0OSC_PHYFRST_MASK | DDR_PHY_DX8SL0OSC_DLTST_MASK | DDR_PHY_DX8SL0OSC_DLTMODE_MASK | DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL0OSC_OSCWDDL_MASK | DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL0OSC_OSCWDL_MASK | DDR_PHY_DX8SL0OSC_OSCDIV_MASK | DDR_PHY_DX8SL0OSC_OSCEN_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0OSC_LBMODE_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0OSC_DLTST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT
+ | 0x0000000FU << DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0OSC_OSCEN_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_DX8SL0OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
+ /*############################################################################################################################ */
+
/*Register : DX8SL0DQSCTL @ 0XFD08141C
Reserved. Return zeroes on reads.
@@ -10630,13 +10647,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3
DQS_N Resistor
- PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0xc
+ PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0
DQS Resistor
- PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x4
+ PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0
DATX8 0-1 DQS Control Register
- (OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x012643C4U)
+ (OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U)
RegMask = (DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL0DQSCTL_DXSR_MASK | DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT
@@ -10651,10 +10668,10 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT
| 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT
| 0x00000003U << DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT
- | 0x0000000CU << DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT
- | 0x00000004U << DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL0DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+ PSU_Mask_Write (DDR_PHY_DX8SL0DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
/*############################################################################################################################ */
/*Register : DX8SL0DXCTL2 @ 0XFD08142C
@@ -10669,7 +10686,7 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0
OE Extension during Pre-amble
- PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x0
+ PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1
Reserved. Return zeroes on reads.
PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0
@@ -10708,13 +10725,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0
DATX8 0-1 DX Control Register 2
- (OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00001800U)
+ (OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U)
RegMask = (DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL0DXCTL2_IOAG_MASK | DDR_PHY_DX8SL0DXCTL2_IOLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL0DXCTL2_RDBI_MASK | DDR_PHY_DX8SL0DXCTL2_WDBI_MASK | DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL0DXCTL2_DISRST_MASK | DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT
| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT
| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT
- | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT
| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT
| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT
| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT
@@ -10728,7 +10745,7 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT
| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL0DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+ PSU_Mask_Write (DDR_PHY_DX8SL0DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
/*############################################################################################################################ */
/*Register : DX8SL0IOCR @ 0XFD081430
@@ -10765,6 +10782,92 @@ unsigned long psu_ddr_init_data() {
PSU_Mask_Write (DDR_PHY_DX8SL0IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
/*############################################################################################################################ */
+ /*Register : DX8SL1OSC @ 0XFD081440
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0
+
+ Enable Clock Gating for DX ddr_clk
+ PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2
+
+ Enable Clock Gating for DX ctl_rd_clk
+ PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2
+
+ Enable Clock Gating for DX ctl_clk
+ PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2
+
+ Selects the level to which clocks will be stalled when clock gating is enabled.
+ PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0
+
+ Loopback Mode
+ PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0
+
+ Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
+ PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0
+
+ Loopback DQS Gating
+ PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0
+
+ Loopback DQS Shift
+ PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0
+
+ PHY High-Speed Reset
+ PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1
+
+ PHY FIFO Reset
+ PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1
+
+ Delay Line Test Start
+ PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0
+
+ Delay Line Test Mode
+ PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3
+
+ Oscillator Mode Write-Data Delay Line Select
+ PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3
+
+ Oscillator Mode Write-Leveling Delay Line Select
+ PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3
+
+ Oscillator Mode Division
+ PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf
+
+ Oscillator Enable
+ PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0
+
+ DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
+ (OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU)
+ RegMask = (DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL1OSC_LBMODE_MASK | DDR_PHY_DX8SL1OSC_LBGSDQS_MASK | DDR_PHY_DX8SL1OSC_LBGDQS_MASK | DDR_PHY_DX8SL1OSC_LBDQSS_MASK | DDR_PHY_DX8SL1OSC_PHYHRST_MASK | DDR_PHY_DX8SL1OSC_PHYFRST_MASK | DDR_PHY_DX8SL1OSC_DLTST_MASK | DDR_PHY_DX8SL1OSC_DLTMODE_MASK | DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL1OSC_OSCWDDL_MASK | DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL1OSC_OSCWDL_MASK | DDR_PHY_DX8SL1OSC_OSCDIV_MASK | DDR_PHY_DX8SL1OSC_OSCEN_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1OSC_LBMODE_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1OSC_DLTST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT
+ | 0x0000000FU << DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1OSC_OSCEN_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_DX8SL1OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
+ /*############################################################################################################################ */
+
/*Register : DX8SL1DQSCTL @ 0XFD08145C
Reserved. Return zeroes on reads.
@@ -10804,13 +10907,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3
DQS_N Resistor
- PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0xc
+ PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0
DQS Resistor
- PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x4
+ PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0
DATX8 0-1 DQS Control Register
- (OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x012643C4U)
+ (OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U)
RegMask = (DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL1DQSCTL_DXSR_MASK | DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT
@@ -10825,10 +10928,10 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT
| 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT
| 0x00000003U << DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT
- | 0x0000000CU << DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT
- | 0x00000004U << DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL1DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+ PSU_Mask_Write (DDR_PHY_DX8SL1DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
/*############################################################################################################################ */
/*Register : DX8SL1DXCTL2 @ 0XFD08146C
@@ -10843,7 +10946,7 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0
OE Extension during Pre-amble
- PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x0
+ PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1
Reserved. Return zeroes on reads.
PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0
@@ -10882,13 +10985,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0
DATX8 0-1 DX Control Register 2
- (OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00001800U)
+ (OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U)
RegMask = (DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL1DXCTL2_IOAG_MASK | DDR_PHY_DX8SL1DXCTL2_IOLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL1DXCTL2_RDBI_MASK | DDR_PHY_DX8SL1DXCTL2_WDBI_MASK | DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL1DXCTL2_DISRST_MASK | DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT
| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT
| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT
- | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT
| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT
| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT
| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT
@@ -10902,7 +11005,7 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT
| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL1DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+ PSU_Mask_Write (DDR_PHY_DX8SL1DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
/*############################################################################################################################ */
/*Register : DX8SL1IOCR @ 0XFD081470
@@ -10939,6 +11042,92 @@ unsigned long psu_ddr_init_data() {
PSU_Mask_Write (DDR_PHY_DX8SL1IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
/*############################################################################################################################ */
+ /*Register : DX8SL2OSC @ 0XFD081480
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0
+
+ Enable Clock Gating for DX ddr_clk
+ PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2
+
+ Enable Clock Gating for DX ctl_rd_clk
+ PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2
+
+ Enable Clock Gating for DX ctl_clk
+ PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2
+
+ Selects the level to which clocks will be stalled when clock gating is enabled.
+ PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0
+
+ Loopback Mode
+ PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0
+
+ Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
+ PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0
+
+ Loopback DQS Gating
+ PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0
+
+ Loopback DQS Shift
+ PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0
+
+ PHY High-Speed Reset
+ PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1
+
+ PHY FIFO Reset
+ PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1
+
+ Delay Line Test Start
+ PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0
+
+ Delay Line Test Mode
+ PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3
+
+ Oscillator Mode Write-Data Delay Line Select
+ PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3
+
+ Oscillator Mode Write-Leveling Delay Line Select
+ PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3
+
+ Oscillator Mode Division
+ PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf
+
+ Oscillator Enable
+ PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0
+
+ DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
+ (OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU)
+ RegMask = (DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL2OSC_LBMODE_MASK | DDR_PHY_DX8SL2OSC_LBGSDQS_MASK | DDR_PHY_DX8SL2OSC_LBGDQS_MASK | DDR_PHY_DX8SL2OSC_LBDQSS_MASK | DDR_PHY_DX8SL2OSC_PHYHRST_MASK | DDR_PHY_DX8SL2OSC_PHYFRST_MASK | DDR_PHY_DX8SL2OSC_DLTST_MASK | DDR_PHY_DX8SL2OSC_DLTMODE_MASK | DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL2OSC_OSCWDDL_MASK | DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL2OSC_OSCWDL_MASK | DDR_PHY_DX8SL2OSC_OSCDIV_MASK | DDR_PHY_DX8SL2OSC_OSCEN_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2OSC_LBMODE_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2OSC_DLTST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT
+ | 0x0000000FU << DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2OSC_OSCEN_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_DX8SL2OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
+ /*############################################################################################################################ */
+
/*Register : DX8SL2DQSCTL @ 0XFD08149C
Reserved. Return zeroes on reads.
@@ -10978,13 +11167,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3
DQS_N Resistor
- PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0xc
+ PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0
DQS Resistor
- PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x4
+ PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0
DATX8 0-1 DQS Control Register
- (OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x012643C4U)
+ (OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U)
RegMask = (DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL2DQSCTL_DXSR_MASK | DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT
@@ -10999,10 +11188,10 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT
| 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT
| 0x00000003U << DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT
- | 0x0000000CU << DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT
- | 0x00000004U << DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL2DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+ PSU_Mask_Write (DDR_PHY_DX8SL2DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
/*############################################################################################################################ */
/*Register : DX8SL2DXCTL2 @ 0XFD0814AC
@@ -11017,7 +11206,7 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0
OE Extension during Pre-amble
- PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x0
+ PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1
Reserved. Return zeroes on reads.
PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0
@@ -11056,13 +11245,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0
DATX8 0-1 DX Control Register 2
- (OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00001800U)
+ (OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U)
RegMask = (DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL2DXCTL2_IOAG_MASK | DDR_PHY_DX8SL2DXCTL2_IOLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL2DXCTL2_RDBI_MASK | DDR_PHY_DX8SL2DXCTL2_WDBI_MASK | DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL2DXCTL2_DISRST_MASK | DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT
| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT
| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT
- | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT
| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT
| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT
| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT
@@ -11076,7 +11265,7 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT
| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL2DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+ PSU_Mask_Write (DDR_PHY_DX8SL2DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
/*############################################################################################################################ */
/*Register : DX8SL2IOCR @ 0XFD0814B0
@@ -11113,6 +11302,92 @@ unsigned long psu_ddr_init_data() {
PSU_Mask_Write (DDR_PHY_DX8SL2IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
/*############################################################################################################################ */
+ /*Register : DX8SL3OSC @ 0XFD0814C0
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0
+
+ Enable Clock Gating for DX ddr_clk
+ PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2
+
+ Enable Clock Gating for DX ctl_rd_clk
+ PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2
+
+ Enable Clock Gating for DX ctl_clk
+ PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2
+
+ Selects the level to which clocks will be stalled when clock gating is enabled.
+ PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0
+
+ Loopback Mode
+ PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0
+
+ Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
+ PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0
+
+ Loopback DQS Gating
+ PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0
+
+ Loopback DQS Shift
+ PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0
+
+ PHY High-Speed Reset
+ PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1
+
+ PHY FIFO Reset
+ PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1
+
+ Delay Line Test Start
+ PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0
+
+ Delay Line Test Mode
+ PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3
+
+ Oscillator Mode Write-Data Delay Line Select
+ PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3
+
+ Oscillator Mode Write-Leveling Delay Line Select
+ PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3
+
+ Oscillator Mode Division
+ PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf
+
+ Oscillator Enable
+ PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0
+
+ DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
+ (OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU)
+ RegMask = (DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL3OSC_LBMODE_MASK | DDR_PHY_DX8SL3OSC_LBGSDQS_MASK | DDR_PHY_DX8SL3OSC_LBGDQS_MASK | DDR_PHY_DX8SL3OSC_LBDQSS_MASK | DDR_PHY_DX8SL3OSC_PHYHRST_MASK | DDR_PHY_DX8SL3OSC_PHYFRST_MASK | DDR_PHY_DX8SL3OSC_DLTST_MASK | DDR_PHY_DX8SL3OSC_DLTMODE_MASK | DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL3OSC_OSCWDDL_MASK | DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL3OSC_OSCWDL_MASK | DDR_PHY_DX8SL3OSC_OSCDIV_MASK | DDR_PHY_DX8SL3OSC_OSCEN_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3OSC_LBMODE_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3OSC_DLTST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT
+ | 0x0000000FU << DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3OSC_OSCEN_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_DX8SL3OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
+ /*############################################################################################################################ */
+
/*Register : DX8SL3DQSCTL @ 0XFD0814DC
Reserved. Return zeroes on reads.
@@ -11152,13 +11427,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3
DQS_N Resistor
- PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0xc
+ PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0
DQS Resistor
- PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x4
+ PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0
DATX8 0-1 DQS Control Register
- (OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x012643C4U)
+ (OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U)
RegMask = (DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL3DQSCTL_DXSR_MASK | DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT
@@ -11173,10 +11448,10 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT
| 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT
| 0x00000003U << DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT
- | 0x0000000CU << DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT
- | 0x00000004U << DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL3DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+ PSU_Mask_Write (DDR_PHY_DX8SL3DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
/*############################################################################################################################ */
/*Register : DX8SL3DXCTL2 @ 0XFD0814EC
@@ -11191,7 +11466,7 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0
OE Extension during Pre-amble
- PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x0
+ PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1
Reserved. Return zeroes on reads.
PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0
@@ -11230,13 +11505,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0
DATX8 0-1 DX Control Register 2
- (OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00001800U)
+ (OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U)
RegMask = (DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL3DXCTL2_IOAG_MASK | DDR_PHY_DX8SL3DXCTL2_IOLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL3DXCTL2_RDBI_MASK | DDR_PHY_DX8SL3DXCTL2_WDBI_MASK | DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL3DXCTL2_DISRST_MASK | DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT
| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT
| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT
- | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT
| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT
| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT
| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT
@@ -11250,7 +11525,7 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT
| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL3DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+ PSU_Mask_Write (DDR_PHY_DX8SL3DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
/*############################################################################################################################ */
/*Register : DX8SL3IOCR @ 0XFD0814F0
@@ -11287,6 +11562,92 @@ unsigned long psu_ddr_init_data() {
PSU_Mask_Write (DDR_PHY_DX8SL3IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
/*############################################################################################################################ */
+ /*Register : DX8SL4OSC @ 0XFD081500
+
+ Reserved. Return zeroes on reads.
+ PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0
+
+ Enable Clock Gating for DX ddr_clk
+ PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x2
+
+ Enable Clock Gating for DX ctl_rd_clk
+ PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x2
+
+ Enable Clock Gating for DX ctl_clk
+ PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x2
+
+ Selects the level to which clocks will be stalled when clock gating is enabled.
+ PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0
+
+ Loopback Mode
+ PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0
+
+ Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
+ PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0
+
+ Loopback DQS Gating
+ PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0
+
+ Loopback DQS Shift
+ PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0
+
+ PHY High-Speed Reset
+ PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1
+
+ PHY FIFO Reset
+ PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1
+
+ Delay Line Test Start
+ PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0
+
+ Delay Line Test Mode
+ PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3
+
+ Oscillator Mode Write-Data Delay Line Select
+ PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3
+
+ Reserved. Caution, do not write to this register field.
+ PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3
+
+ Oscillator Mode Write-Leveling Delay Line Select
+ PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3
+
+ Oscillator Mode Division
+ PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf
+
+ Oscillator Enable
+ PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0
+
+ DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
+ (OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU)
+ RegMask = (DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL4OSC_LBMODE_MASK | DDR_PHY_DX8SL4OSC_LBGSDQS_MASK | DDR_PHY_DX8SL4OSC_LBGDQS_MASK | DDR_PHY_DX8SL4OSC_LBDQSS_MASK | DDR_PHY_DX8SL4OSC_PHYHRST_MASK | DDR_PHY_DX8SL4OSC_PHYFRST_MASK | DDR_PHY_DX8SL4OSC_DLTST_MASK | DDR_PHY_DX8SL4OSC_DLTMODE_MASK | DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL4OSC_OSCWDDL_MASK | DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL4OSC_OSCWDL_MASK | DDR_PHY_DX8SL4OSC_OSCDIV_MASK | DDR_PHY_DX8SL4OSC_OSCEN_MASK | 0 );
+
+ RegVal = ((0x00000000U << DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT
+ | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4OSC_LBMODE_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4OSC_DLTST_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT
+ | 0x00000003U << DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT
+ | 0x0000000FU << DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4OSC_OSCEN_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (DDR_PHY_DX8SL4OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
+ /*############################################################################################################################ */
+
/*Register : DX8SL4DQSCTL @ 0XFD08151C
Reserved. Return zeroes on reads.
@@ -11326,13 +11687,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3
DQS_N Resistor
- PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0xc
+ PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0
DQS Resistor
- PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x4
+ PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0
DATX8 0-1 DQS Control Register
- (OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x012643C4U)
+ (OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01264300U)
RegMask = (DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL4DQSCTL_DXSR_MASK | DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT
@@ -11347,10 +11708,10 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT
| 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT
| 0x00000003U << DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT
- | 0x0000000CU << DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT
- | 0x00000004U << DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT
+ | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL4DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+ PSU_Mask_Write (DDR_PHY_DX8SL4DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
/*############################################################################################################################ */
/*Register : DX8SL4DXCTL2 @ 0XFD08152C
@@ -11365,7 +11726,7 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0
OE Extension during Pre-amble
- PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x0
+ PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1
Reserved. Return zeroes on reads.
PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0
@@ -11404,13 +11765,13 @@ unsigned long psu_ddr_init_data() {
PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0
DATX8 0-1 DX Control Register 2
- (OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00001800U)
+ (OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U)
RegMask = (DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL4DXCTL2_IOAG_MASK | DDR_PHY_DX8SL4DXCTL2_IOLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL4DXCTL2_RDBI_MASK | DDR_PHY_DX8SL4DXCTL2_WDBI_MASK | DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL4DXCTL2_DISRST_MASK | DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT
| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT
| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT
- | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT
+ | 0x00000001U << DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT
| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT
| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT
| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT
@@ -11424,7 +11785,7 @@ unsigned long psu_ddr_init_data() {
| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT
| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DX8SL4DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+ PSU_Mask_Write (DDR_PHY_DX8SL4DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
/*############################################################################################################################ */
/*Register : DX8SL4IOCR @ 0XFD081530
@@ -12478,7 +12839,7 @@ unsigned long psu_mio_init_data() {
Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
- PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 1
+ PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0
Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
@@ -12488,15 +12849,15 @@ unsigned long psu_mio_init_data() {
PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0
Configures MIO Pin 26 peripheral interface mapping
- (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000008U)
+ (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U)
RegMask = (IOU_SLCR_MIO_PIN_26_L0_SEL_MASK | IOU_SLCR_MIO_PIN_26_L1_SEL_MASK | IOU_SLCR_MIO_PIN_26_L2_SEL_MASK | IOU_SLCR_MIO_PIN_26_L3_SEL_MASK | 0 );
RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT
- | 0x00000001U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
+ | 0x00000000U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (IOU_SLCR_MIO_PIN_26_OFFSET ,0x000000FEU ,0x00000008U);
+ PSU_Mask_Write (IOU_SLCR_MIO_PIN_26_OFFSET ,0x000000FEU ,0x00000000U);
/*############################################################################################################################ */
/*Register : MIO_PIN_27 @ 0XFF18006C
@@ -12510,7 +12871,7 @@ unsigned long psu_mio_init_data() {
Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
t, dp_aux_data_out- (Dp Aux Data)
- PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 0
+ PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3
Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
@@ -12520,15 +12881,15 @@ unsigned long psu_mio_init_data() {
PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0
Configures MIO Pin 27 peripheral interface mapping
- (OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U)
RegMask = (IOU_SLCR_MIO_PIN_27_L0_SEL_MASK | IOU_SLCR_MIO_PIN_27_L1_SEL_MASK | IOU_SLCR_MIO_PIN_27_L2_SEL_MASK | IOU_SLCR_MIO_PIN_27_L3_SEL_MASK | 0 );
RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT
- | 0x00000000U << IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
+ | 0x00000003U << IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (IOU_SLCR_MIO_PIN_27_OFFSET ,0x000000FEU ,0x00000000U);
+ PSU_Mask_Write (IOU_SLCR_MIO_PIN_27_OFFSET ,0x000000FEU ,0x00000018U);
/*############################################################################################################################ */
/*Register : MIO_PIN_28 @ 0XFF180070
@@ -12541,7 +12902,7 @@ unsigned long psu_mio_init_data() {
Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
- PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 0
+ PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3
Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
@@ -12550,15 +12911,15 @@ unsigned long psu_mio_init_data() {
PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0
Configures MIO Pin 28 peripheral interface mapping
- (OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U)
RegMask = (IOU_SLCR_MIO_PIN_28_L0_SEL_MASK | IOU_SLCR_MIO_PIN_28_L1_SEL_MASK | IOU_SLCR_MIO_PIN_28_L2_SEL_MASK | IOU_SLCR_MIO_PIN_28_L3_SEL_MASK | 0 );
RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT
- | 0x00000000U << IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
+ | 0x00000003U << IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (IOU_SLCR_MIO_PIN_28_OFFSET ,0x000000FEU ,0x00000000U);
+ PSU_Mask_Write (IOU_SLCR_MIO_PIN_28_OFFSET ,0x000000FEU ,0x00000018U);
/*############################################################################################################################ */
/*Register : MIO_PIN_29 @ 0XFF180074
@@ -12572,7 +12933,7 @@ unsigned long psu_mio_init_data() {
Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
t, dp_aux_data_out- (Dp Aux Data)
- PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 0
+ PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3
Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
@@ -12582,15 +12943,15 @@ unsigned long psu_mio_init_data() {
PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0
Configures MIO Pin 29 peripheral interface mapping
- (OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U)
RegMask = (IOU_SLCR_MIO_PIN_29_L0_SEL_MASK | IOU_SLCR_MIO_PIN_29_L1_SEL_MASK | IOU_SLCR_MIO_PIN_29_L2_SEL_MASK | IOU_SLCR_MIO_PIN_29_L3_SEL_MASK | 0 );
RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT
- | 0x00000000U << IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
+ | 0x00000003U << IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (IOU_SLCR_MIO_PIN_29_OFFSET ,0x000000FEU ,0x00000000U);
+ PSU_Mask_Write (IOU_SLCR_MIO_PIN_29_OFFSET ,0x000000FEU ,0x00000018U);
/*############################################################################################################################ */
/*Register : MIO_PIN_30 @ 0XFF180078
@@ -12603,7 +12964,7 @@ unsigned long psu_mio_init_data() {
Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
- PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 0
+ PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3
Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
@@ -12613,15 +12974,15 @@ unsigned long psu_mio_init_data() {
PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0
Configures MIO Pin 30 peripheral interface mapping
- (OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U)
RegMask = (IOU_SLCR_MIO_PIN_30_L0_SEL_MASK | IOU_SLCR_MIO_PIN_30_L1_SEL_MASK | IOU_SLCR_MIO_PIN_30_L2_SEL_MASK | IOU_SLCR_MIO_PIN_30_L3_SEL_MASK | 0 );
RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT
- | 0x00000000U << IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
+ | 0x00000003U << IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (IOU_SLCR_MIO_PIN_30_OFFSET ,0x000000FEU ,0x00000000U);
+ PSU_Mask_Write (IOU_SLCR_MIO_PIN_30_OFFSET ,0x000000FEU ,0x00000018U);
/*############################################################################################################################ */
/*Register : MIO_PIN_31 @ 0XFF18007C
@@ -14152,25 +14513,25 @@ unsigned long psu_mio_init_data() {
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1
Master Tri-state Enable for pin 26, active high
- PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 1
+ PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0
Master Tri-state Enable for pin 27, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0
Master Tri-state Enable for pin 28, active high
- PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 0
+ PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1
Master Tri-state Enable for pin 29, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0
Master Tri-state Enable for pin 30, active high
- PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 0
+ PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1
Master Tri-state Enable for pin 31, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0
MIO pin Tri-state Enables, 31:0
- (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x06240000U)
+ (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U)
RegMask = (IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK | 0 );
RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT
@@ -14199,14 +14560,14 @@ unsigned long psu_mio_init_data() {
| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT
| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT
| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT
- | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
+ | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT
- | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
+ | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT
- | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
+ | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI0_OFFSET ,0xFFFFFFFFU ,0x06240000U);
+ PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI0_OFFSET ,0xFFFFFFFFU ,0x52240000U);
/*############################################################################################################################ */
/*Register : MIO_MST_TRI1 @ 0XFF180208
@@ -16501,6 +16862,21 @@ unsigned long psu_mio_init_data() {
}
unsigned long psu_peripherals_init_data() {
// : RESET BLOCKS
+ // : TIMESTAMP
+ /*Register : RST_LPD_IOU2 @ 0XFF5E0238
+
+ Block level reset
+ PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0
+
+ Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+ (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00100000U ,0x00000000U)
+ RegMask = (CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK | 0 );
+
+ RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00100000U ,0x00000000U);
+ /*############################################################################################################################ */
+
// : ENET
/*Register : RST_LPD_IOU0 @ 0XFF5E0230
@@ -16531,6 +16907,21 @@ unsigned long psu_peripherals_init_data() {
PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000001U ,0x00000000U);
/*############################################################################################################################ */
+ // : QSPI TAP DELAY
+ /*Register : IOU_TAPDLY_BYPASS @ 0XFF180390
+
+ 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI
+ PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1
+
+ IOU tap delay bypass for the LQSPI and NAND controllers
+ (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U)
+ RegMask = (IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK | 0 );
+
+ RegVal = ((0x00000001U << IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET ,0x00000004U ,0x00000004U);
+ /*############################################################################################################################ */
+
// : NAND
// : USB
/*Register : RST_LPD_TOP @ 0XFF5E023C
@@ -16681,6 +17072,23 @@ unsigned long psu_peripherals_init_data() {
PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG1_OFFSET ,0x7F800000U ,0x63800000U);
/*############################################################################################################################ */
+ // : SD1 RETUNER
+ /*Register : SD_CONFIG_REG3 @ 0XFF180324
+
+ This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf
+ rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon
+ s Fh - Ch = Reserved
+ PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0
+
+ SD Config Register 3
+ (OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U)
+ RegMask = (IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK | 0 );
+
+ RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG3_OFFSET ,0x03C00000U ,0x00000000U);
+ /*############################################################################################################################ */
+
// : CAN
/*Register : RST_LPD_IOU2 @ 0XFF5E0238
@@ -17121,6 +17529,37 @@ unsigned long psu_peripherals_init_data() {
PSU_Mask_Write (RTC_CONTROL_OFFSET ,0x80000000U ,0x80000000U);
/*############################################################################################################################ */
+ // : TIMESTAMP COUNTER
+ /*Register : base_frequency_ID_register @ 0XFF260020
+
+ Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz.
+ PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5e100
+
+ Program this register to match the clock frequency of the timestamp generator, in ticks per second. For example, for a 50 MHz
+ clock, program 0x02FAF080. This register is not accessible to the read-only programming interface.
+ (OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5E100U)
+ RegMask = (IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK | 0 );
+
+ RegVal = ((0x05F5E100U << IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET ,0xFFFFFFFFU ,0x05F5E100U);
+ /*############################################################################################################################ */
+
+ /*Register : counter_control_register @ 0XFF260000
+
+ Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing.
+ PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1
+
+ Controls the counter increments. This register is not accessible to the read-only programming interface.
+ (OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U)
+ RegMask = (IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK | 0 );
+
+ RegVal = ((0x00000001U << IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ // : TTC SRC SELECT
return 1;
}
@@ -17135,14 +17574,106 @@ unsigned long psu_peripherals_powerdwn_data() {
return 1;
}
-unsigned long psu_serdes_init_data() {
- // : SERDES INITIALIZATION
- // : GT REFERENCE CLOCK SOURCE SELECTION
- /*Register : PLL_REF_SEL0 @ 0XFD410000
+unsigned long psu_lpd_xppu_data() {
+ // : XPPU INTERRUPT ENABLE
+ /*Register : IEN @ 0XFF980018
- PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
- 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
- Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_APER_PARITY 0X1
+
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_APER_TZ 0X1
+
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_APER_PERM 0X1
+
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_MID_PARITY 0X1
+
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_MID_RO 0X1
+
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_MID_MISS 0X1
+
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_INV_APB 0X1
+
+ Interrupt Enable Register
+ (OFFSET, MASK, VALUE) (0XFF980018, 0x000000EFU ,0x000000EFU)
+ RegMask = (LPD_XPPU_CFG_IEN_APER_PARITY_MASK | LPD_XPPU_CFG_IEN_APER_TZ_MASK | LPD_XPPU_CFG_IEN_APER_PERM_MASK | LPD_XPPU_CFG_IEN_MID_PARITY_MASK | LPD_XPPU_CFG_IEN_MID_RO_MASK | LPD_XPPU_CFG_IEN_MID_MISS_MASK | LPD_XPPU_CFG_IEN_INV_APB_MASK | 0 );
+
+ RegVal = ((0x00000001U << LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_APER_TZ_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_APER_PERM_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_MID_RO_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_MID_MISS_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_INV_APB_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (LPD_XPPU_CFG_IEN_OFFSET ,0x000000EFU ,0x000000EFU);
+ /*############################################################################################################################ */
+
+
+ return 1;
+}
+unsigned long psu_ddr_xmpu0_data() {
+
+ return 1;
+}
+unsigned long psu_ddr_xmpu1_data() {
+
+ return 1;
+}
+unsigned long psu_ddr_xmpu2_data() {
+
+ return 1;
+}
+unsigned long psu_ddr_xmpu3_data() {
+
+ return 1;
+}
+unsigned long psu_ddr_xmpu4_data() {
+
+ return 1;
+}
+unsigned long psu_ddr_xmpu5_data() {
+
+ return 1;
+}
+unsigned long psu_ocm_xmpu_data() {
+
+ return 1;
+}
+unsigned long psu_fpd_xmpu_data() {
+
+ return 1;
+}
+unsigned long psu_protection_lock_data() {
+
+ return 1;
+}
+unsigned long psu_apply_master_tz() {
+ // : RPU
+ // : DP TZ
+ // : SATA TZ
+ // : PCIE TZ
+ // : USB TZ
+ // : SD TZ
+ // : GEM TZ
+ // : QSPI TZ
+ // : NAND TZ
+
+ return 1;
+}
+unsigned long psu_serdes_init_data() {
+ // : SERDES INITIALIZATION
+ // : GT REFERENCE CLOCK SOURCE SELECTION
+ /*Register : PLL_REF_SEL0 @ 0XFD410000
+
+ PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
+ 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+ Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD
PLL0 Reference Selection Register
@@ -17313,99 +17844,99 @@ unsigned long psu_serdes_init_data() {
/*Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368
Spread Spectrum No of Steps [7:0]
- PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x0
+ PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0
Spread Spectrum No of Steps bits 7:0
- (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U)
RegMask = (SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+ RegVal = ((0x000000E0U << SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x000000E0U);
/*############################################################################################################################ */
/*Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C
Spread Spectrum No of Steps [10:8]
- PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x0
+ PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
Spread Spectrum No of Steps bits 10:8
- (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U)
RegMask = (SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+ RegVal = ((0x00000003U << SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
/*############################################################################################################################ */
/*Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368
Spread Spectrum No of Steps [7:0]
- PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x0
+ PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58
Spread Spectrum No of Steps bits 7:0
- (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U)
RegMask = (SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+ RegVal = ((0x00000058U << SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000058U);
/*############################################################################################################################ */
/*Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C
Spread Spectrum No of Steps [10:8]
- PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x0
+ PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
Spread Spectrum No of Steps bits 10:8
- (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U)
RegMask = (SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+ RegVal = ((0x00000003U << SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000000U);
+ PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
/*############################################################################################################################ */
/*Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370
Step Size for Spread Spectrum [7:0]
- PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x0
+ PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C
Step Size for Spread Spectrum LSB
- (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU)
RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+ RegVal = ((0x0000007CU << SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x0000007CU);
/*############################################################################################################################ */
/*Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374
Step Size for Spread Spectrum [15:8]
- PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x0
+ PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33
Step Size for Spread Spectrum 1
- (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U)
RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+ RegVal = ((0x00000033U << SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000033U);
/*############################################################################################################################ */
/*Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378
Step Size for Spread Spectrum [23:16]
- PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x0
+ PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2
Step Size for Spread Spectrum 2
- (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U)
RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+ RegVal = ((0x00000002U << SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U);
/*############################################################################################################################ */
/*Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C
@@ -17497,43 +18028,43 @@ unsigned long psu_serdes_init_data() {
/*Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370
Step Size for Spread Spectrum [7:0]
- PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x0
+ PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9
Step Size for Spread Spectrum LSB
- (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U)
RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+ RegVal = ((0x000000C9U << SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000C9U);
/*############################################################################################################################ */
/*Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374
Step Size for Spread Spectrum [15:8]
- PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x0
+ PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2
Step Size for Spread Spectrum 1
- (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U)
RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+ RegVal = ((0x000000D2U << SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x000000D2U);
/*############################################################################################################################ */
/*Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378
Step Size for Spread Spectrum [23:16]
- PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x0
+ PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1
Step Size for Spread Spectrum 2
- (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000000U)
+ (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U)
RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000001U);
/*############################################################################################################################ */
/*Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C
@@ -17674,6 +18205,851 @@ unsigned long psu_serdes_init_data() {
PSU_Mask_Write (SERDES_L3_TXPMA_ST_0_OFFSET ,0x000000F0U ,0x000000F0U);
/*############################################################################################################################ */
+ // : ENABLE CHICKEN BIT FOR PCIE AND USB
+ /*Register : L0_TM_AUX_0 @ 0XFD4010CC
+
+ Spare- not used
+ PSU_SERDES_L0_TM_AUX_0_BIT_2 1
+
+ Spare registers
+ (OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U)
+ RegMask = (SERDES_L0_TM_AUX_0_BIT_2_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L0_TM_AUX_0_BIT_2_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_AUX_0 @ 0XFD4090CC
+
+ Spare- not used
+ PSU_SERDES_L2_TM_AUX_0_BIT_2 1
+
+ Spare registers
+ (OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U)
+ RegMask = (SERDES_L2_TM_AUX_0_BIT_2_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L2_TM_AUX_0_BIT_2_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U);
+ /*############################################################################################################################ */
+
+ // : ENABLING EYE SURF
+ /*Register : L0_TM_DIG_8 @ 0XFD401074
+
+ Enable Eye Surf
+ PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1
+
+ Test modes for Elastic buffer and enabling Eye Surf
+ (OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U)
+ RegMask = (SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
+ /*############################################################################################################################ */
+
+ /*Register : L1_TM_DIG_8 @ 0XFD405074
+
+ Enable Eye Surf
+ PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1
+
+ Test modes for Elastic buffer and enabling Eye Surf
+ (OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U)
+ RegMask = (SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L1_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_DIG_8 @ 0XFD409074
+
+ Enable Eye Surf
+ PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1
+
+ Test modes for Elastic buffer and enabling Eye Surf
+ (OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U)
+ RegMask = (SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_DIG_8 @ 0XFD40D074
+
+ Enable Eye Surf
+ PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1
+
+ Test modes for Elastic buffer and enabling Eye Surf
+ (OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U)
+ RegMask = (SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
+ /*############################################################################################################################ */
+
+ // : ILL SETTINGS FOR GAIN AND LOCK SETTINGS
+ /*Register : L0_TM_MISC2 @ 0XFD40189C
+
+ ILL calib counts BYPASSED with calcode bits
+ PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
+
+ sampler cal
+ (OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U)
+ RegMask = (SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_IQ_ILL1 @ 0XFD4018F8
+
+ IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U)
+ RegMask = (SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 );
+
+ RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x00000064U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_IQ_ILL2 @ 0XFD4018FC
+
+ IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U)
+ RegMask = (SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 );
+
+ RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x00000064U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_ILL12 @ 0XFD401990
+
+ G1A pll ctr bypass value
+ PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11
+
+ ill pll counter values
+ (OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U)
+ RegMask = (SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 );
+
+ RegVal = ((0x00000011U << SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_ILL12_OFFSET ,0x000000FFU ,0x00000011U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_E_ILL1 @ 0XFD401924
+
+ E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U)
+ RegMask = (SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 );
+
+ RegVal = ((0x00000004U << SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_E_ILL1_OFFSET ,0x000000FFU ,0x00000004U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_E_ILL2 @ 0XFD401928
+
+ E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU)
+ RegMask = (SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 );
+
+ RegVal = ((0x000000FEU << SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_E_ILL2_OFFSET ,0x000000FFU ,0x000000FEU);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_IQ_ILL3 @ 0XFD401900
+
+ IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U)
+ RegMask = (SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 );
+
+ RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x00000064U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_E_ILL3 @ 0XFD40192C
+
+ E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U)
+ RegMask = (SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 );
+
+ RegVal = ((0x00000000U << SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_ILL8 @ 0XFD401980
+
+ ILL calibration code change wait time
+ PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
+
+ ILL cal routine control
+ (OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 );
+
+ RegVal = ((0x000000FFU << SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_IQ_ILL8 @ 0XFD401914
+
+ IQ ILL polytrim bypass value
+ PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
+
+ iqpi polytrim
+ (OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U)
+ RegMask = (SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 );
+
+ RegVal = ((0x000000F7U << SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_IQ_ILL9 @ 0XFD401918
+
+ bypass IQ polytrim
+ PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
+
+ enables for lf,constant gm trim and polytirm
+ (OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_E_ILL8 @ 0XFD401940
+
+ E ILL polytrim bypass value
+ PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
+
+ epi polytrim
+ (OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U)
+ RegMask = (SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 );
+
+ RegVal = ((0x000000F7U << SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_E_ILL9 @ 0XFD401944
+
+ bypass E polytrim
+ PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
+
+ enables for lf,constant gm trim and polytirm
+ (OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_MISC2 @ 0XFD40989C
+
+ ILL calib counts BYPASSED with calcode bits
+ PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
+
+ sampler cal
+ (OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U)
+ RegMask = (SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_IQ_ILL1 @ 0XFD4098F8
+
+ IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU)
+ RegMask = (SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 );
+
+ RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000001AU);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_IQ_ILL2 @ 0XFD4098FC
+
+ IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU)
+ RegMask = (SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 );
+
+ RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000001AU);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_ILL12 @ 0XFD409990
+
+ G1A pll ctr bypass value
+ PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10
+
+ ill pll counter values
+ (OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U)
+ RegMask = (SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 );
+
+ RegVal = ((0x00000010U << SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_ILL12_OFFSET ,0x000000FFU ,0x00000010U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_E_ILL1 @ 0XFD409924
+
+ E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU)
+ RegMask = (SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 );
+
+ RegVal = ((0x000000FEU << SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_E_ILL1_OFFSET ,0x000000FFU ,0x000000FEU);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_E_ILL2 @ 0XFD409928
+
+ E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U)
+ RegMask = (SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 );
+
+ RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_IQ_ILL3 @ 0XFD409900
+
+ IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU)
+ RegMask = (SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 );
+
+ RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000001AU);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_E_ILL3 @ 0XFD40992C
+
+ E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U)
+ RegMask = (SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 );
+
+ RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_ILL8 @ 0XFD409980
+
+ ILL calibration code change wait time
+ PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
+
+ ILL cal routine control
+ (OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 );
+
+ RegVal = ((0x000000FFU << SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_IQ_ILL8 @ 0XFD409914
+
+ IQ ILL polytrim bypass value
+ PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
+
+ iqpi polytrim
+ (OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U)
+ RegMask = (SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 );
+
+ RegVal = ((0x000000F7U << SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_IQ_ILL9 @ 0XFD409918
+
+ bypass IQ polytrim
+ PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
+
+ enables for lf,constant gm trim and polytirm
+ (OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_E_ILL8 @ 0XFD409940
+
+ E ILL polytrim bypass value
+ PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
+
+ epi polytrim
+ (OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U)
+ RegMask = (SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 );
+
+ RegVal = ((0x000000F7U << SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_E_ILL9 @ 0XFD409944
+
+ bypass E polytrim
+ PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
+
+ enables for lf,constant gm trim and polytirm
+ (OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_MISC2 @ 0XFD40D89C
+
+ ILL calib counts BYPASSED with calcode bits
+ PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
+
+ sampler cal
+ (OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U)
+ RegMask = (SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8
+
+ IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU)
+ RegMask = (SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 );
+
+ RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000007DU);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC
+
+ IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU)
+ RegMask = (SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 );
+
+ RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000007DU);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_ILL12 @ 0XFD40D990
+
+ G1A pll ctr bypass value
+ PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1
+
+ ill pll counter values
+ (OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U)
+ RegMask = (SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_ILL12_OFFSET ,0x000000FFU ,0x00000001U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_E_ILL1 @ 0XFD40D924
+
+ E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU)
+ RegMask = (SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 );
+
+ RegVal = ((0x0000009CU << SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_E_ILL1_OFFSET ,0x000000FFU ,0x0000009CU);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_E_ILL2 @ 0XFD40D928
+
+ E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U)
+ RegMask = (SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 );
+
+ RegVal = ((0x00000039U << SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000039U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_ILL11 @ 0XFD40D98C
+
+ G2A_PCIe1 PLL ctr bypass value
+ PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2
+
+ ill pll counter values
+ (OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U)
+ RegMask = (SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK | 0 );
+
+ RegVal = ((0x00000002U << SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_ILL11_OFFSET ,0x000000F0U ,0x00000020U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_IQ_ILL3 @ 0XFD40D900
+
+ IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D
+
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU)
+ RegMask = (SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 );
+
+ RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000007DU);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_E_ILL3 @ 0XFD40D92C
+
+ E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64
+
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U)
+ RegMask = (SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 );
+
+ RegVal = ((0x00000064U << SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000064U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_ILL8 @ 0XFD40D980
+
+ ILL calibration code change wait time
+ PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
+
+ ILL cal routine control
+ (OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 );
+
+ RegVal = ((0x000000FFU << SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_IQ_ILL8 @ 0XFD40D914
+
+ IQ ILL polytrim bypass value
+ PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
+
+ iqpi polytrim
+ (OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U)
+ RegMask = (SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 );
+
+ RegVal = ((0x000000F7U << SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_IQ_ILL9 @ 0XFD40D918
+
+ bypass IQ polytrim
+ PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
+
+ enables for lf,constant gm trim and polytirm
+ (OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_E_ILL8 @ 0XFD40D940
+
+ E ILL polytrim bypass value
+ PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
+
+ epi polytrim
+ (OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U)
+ RegMask = (SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 );
+
+ RegVal = ((0x000000F7U << SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_E_ILL9 @ 0XFD40D944
+
+ bypass E polytrim
+ PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
+
+ enables for lf,constant gm trim and polytirm
+ (OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ // : SYMBOL LOCK AND WAIT
+ /*Register : L0_TM_DIG_21 @ 0XFD4010A8
+
+ pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20
+ PSU_SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH 0x11
+
+ Control symbol alignment locking - wait counts
+ (OFFSET, MASK, VALUE) (0XFD4010A8, 0x00000003U ,0x00000003U)
+ RegMask = (SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK | 0 );
+
+ RegVal = ((0x00000011U << SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_DIG_21_OFFSET ,0x00000003U ,0x00000003U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_DIG_10 @ 0XFD40107C
+
+ CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
+ PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0xF
+
+ test control for changing cdr lock wait time
+ (OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x0000000FU)
+ RegMask = (SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK | 0 );
+
+ RegVal = ((0x0000000FU << SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_DIG_10_OFFSET ,0x0000000FU ,0x0000000FU);
+ /*############################################################################################################################ */
+
+ // : SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG
+ /*Register : L0_TM_RST_DLY @ 0XFD4019A4
+
+ Delay apb reset by specified amount
+ PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF
+
+ reset delay for apb reset w.r.t pso of hsrx
+ (OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK | 0 );
+
+ RegVal = ((0x000000FFU << SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_ANA_BYP_15 @ 0XFD401038
+
+ Enable Bypass for <7> of TM_ANA_BYPS_15
+ PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
+
+ Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
+ (OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
+ /*############################################################################################################################ */
+
+ /*Register : L0_TM_ANA_BYP_12 @ 0XFD40102C
+
+ Enable Bypass for <7> of TM_ANA_BYPS_12
+ PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
+
+ Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
+ (OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
+ /*############################################################################################################################ */
+
+ /*Register : L1_TM_RST_DLY @ 0XFD4059A4
+
+ Delay apb reset by specified amount
+ PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF
+
+ reset delay for apb reset w.r.t pso of hsrx
+ (OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK | 0 );
+
+ RegVal = ((0x000000FFU << SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L1_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
+ /*############################################################################################################################ */
+
+ /*Register : L1_TM_ANA_BYP_15 @ 0XFD405038
+
+ Enable Bypass for <7> of TM_ANA_BYPS_15
+ PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
+
+ Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
+ (OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
+ /*############################################################################################################################ */
+
+ /*Register : L1_TM_ANA_BYP_12 @ 0XFD40502C
+
+ Enable Bypass for <7> of TM_ANA_BYPS_12
+ PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
+
+ Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
+ (OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_RST_DLY @ 0XFD4099A4
+
+ Delay apb reset by specified amount
+ PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF
+
+ reset delay for apb reset w.r.t pso of hsrx
+ (OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK | 0 );
+
+ RegVal = ((0x000000FFU << SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_ANA_BYP_15 @ 0XFD409038
+
+ Enable Bypass for <7> of TM_ANA_BYPS_15
+ PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
+
+ Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
+ (OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
+ /*############################################################################################################################ */
+
+ /*Register : L2_TM_ANA_BYP_12 @ 0XFD40902C
+
+ Enable Bypass for <7> of TM_ANA_BYPS_12
+ PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
+
+ Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
+ (OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_RST_DLY @ 0XFD40D9A4
+
+ Delay apb reset by specified amount
+ PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF
+
+ reset delay for apb reset w.r.t pso of hsrx
+ (OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK | 0 );
+
+ RegVal = ((0x000000FFU << SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_ANA_BYP_15 @ 0XFD40D038
+
+ Enable Bypass for <7> of TM_ANA_BYPS_15
+ PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
+
+ Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
+ (OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C
+
+ Enable Bypass for <7> of TM_ANA_BYPS_12
+ PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
+
+ Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
+ (OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
+ /*############################################################################################################################ */
+
// : GT LANE SETTINGS
/*Register : ICM_CFG0 @ 0XFD410010
@@ -17719,48 +19095,128 @@ unsigned long psu_serdes_init_data() {
// : ENABLE SERIAL DATA MUX DEEMPH
/*Register : L1_TXPMD_TM_45 @ 0XFD404CB4
- Enable/disable DP post2 path
- PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1
+ Enable/disable DP post2 path
+ PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1
+
+ Override enable/disable of DP post2 path
+ PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1
+
+ Override enable/disable of DP post1 path
+ PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1
+
+ Enable/disable DP main path
+ PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1
+
+ Override enable/disable of DP main path
+ PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1
+
+ Post or pre or main DP path selection
+ (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U)
+ RegMask = (SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
+ | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
+ | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
+ | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
+ | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L1_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U);
+ /*############################################################################################################################ */
+
+ /*Register : L1_TX_ANA_TM_118 @ 0XFD4041D8
+
+ Test register force for enabling/disablign TX deemphasis bits <17:0>
+ PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
+
+ Enable Override of TX deemphasis
+ (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L1_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8
+
+ Test register force for enabling/disablign TX deemphasis bits <17:0>
+ PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
+
+ Enable Override of TX deemphasis
+ (OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
+ /*############################################################################################################################ */
+
+ // : CDR AND RX EQUALIZATION SETTINGS
+ /*Register : L3_TM_CDR5 @ 0XFD40DC14
+
+ FPHL FSM accumulate cycles
+ PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7
+
+ FFL Phase0 int gain aka 2ol SD update rate
+ PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6
+
+ Fast phase lock controls -- FSM accumulator cycle control and phase 0 int gain control.
+ (OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U)
+ RegMask = (SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK | SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK | 0 );
+
+ RegVal = ((0x00000007U << SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT
+ | 0x00000006U << SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_CDR5_OFFSET ,0x000000FFU ,0x000000E6U);
+ /*############################################################################################################################ */
+
+ /*Register : L3_TM_CDR16 @ 0XFD40DC40
+
+ FFL Phase0 prop gain aka 1ol SD update rate
+ PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC
- Override enable/disable of DP post2 path
- PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1
+ Fast phase lock controls -- phase 0 prop gain
+ (OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU)
+ RegMask = (SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK | 0 );
- Override enable/disable of DP post1 path
- PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1
+ RegVal = ((0x0000000CU << SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_CDR16_OFFSET ,0x0000001FU ,0x0000000CU);
+ /*############################################################################################################################ */
- Enable/disable DP main path
- PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1
+ /*Register : L3_TM_EQ0 @ 0XFD40D94C
- Override enable/disable of DP main path
- PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1
+ EQ stg 2 controls BYPASSED
+ PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1
- Post or pre or main DP path selection
- (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U)
- RegMask = (SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK | 0 );
+ eq stg1 and stg2 controls
+ (OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U)
+ RegMask = (SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
- | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
- | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
- | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
- | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U);
+ PSU_Mask_Write (SERDES_L3_TM_EQ0_OFFSET ,0x00000020U ,0x00000020U);
/*############################################################################################################################ */
- /*Register : L1_TX_ANA_TM_118 @ 0XFD4041D8
+ /*Register : L3_TM_EQ1 @ 0XFD40D950
- Test register force for enabling/disablign TX deemphasis bits <17:0>
- PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
+ EQ STG2 RL PROG
+ PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2
- Enable Override of TX deemphasis
- (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U)
- RegMask = (SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 );
+ EQ stg 2 preamp mode val
+ PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1
- RegVal = ((0x00000001U << SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
+ eq stg1 and stg2 controls
+ (OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U)
+ RegMask = (SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK | SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK | 0 );
+
+ RegVal = ((0x00000002U << SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT
+ | 0x00000001U << SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
+ PSU_Mask_Write (SERDES_L3_TM_EQ1_OFFSET ,0x00000007U ,0x00000006U);
/*############################################################################################################################ */
+ // : GEM SERDES SETTINGS
// : ENABLE PRE EMPHAIS AND VOLTAGE SWING
/*Register : L1_TXPMD_TM_48 @ 0XFD404CC0
@@ -17790,6 +19246,20 @@ unsigned long psu_serdes_init_data() {
PSU_Mask_Write (SERDES_L1_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000000U);
/*############################################################################################################################ */
+ /*Register : L3_TX_ANA_TM_18 @ 0XFD40C048
+
+ pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
+ PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1
+
+ Override for PIPE TX de-emphasis
+ (OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U)
+ RegMask = (SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK | 0 );
+
+ RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000001U);
+ /*############################################################################################################################ */
+
return 1;
}
@@ -17825,6 +19295,20 @@ unsigned long psu_resetout_init_data() {
PSU_Mask_Write (USB3_0_FPD_POWER_PRSNT_OFFSET ,0x00000001U ,0x00000001U);
/*############################################################################################################################ */
+ /*Register : fpd_pipe_clk @ 0XFF9D007C
+
+ This bit is used to choose between PIPE clock coming from SerDes and the suspend clk
+ PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0
+
+ fpd_pipe_clk
+ (OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U)
+ RegMask = (USB3_0_FPD_PIPE_CLK_OPTION_MASK | 0 );
+
+ RegVal = ((0x00000000U << USB3_0_FPD_PIPE_CLK_OPTION_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (USB3_0_FPD_PIPE_CLK_OFFSET ,0x00000001U ,0x00000000U);
+ /*############################################################################################################################ */
+
// :
/*Register : RST_LPD_TOP @ 0XFF5E023C
@@ -17888,27 +19372,23 @@ unsigned long psu_resetout_init_data() {
PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000000U);
/*############################################################################################################################ */
- // : PUTTING PCIE IN RESET
+ // : PUTTING PCIE CFG AND BRIDGE IN RESET
/*Register : RST_FPD_TOP @ 0XFD1A0100
PCIE config reset
PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0
- PCIE control block level reset
- PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0
-
PCIE bridge block level reset (AXI interface)
PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0
FPD Block level software controlled reset
- (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x00000000U)
- RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | 0 );
+ (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U)
+ RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | 0 );
RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
- | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
| 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000E0000U ,0x00000000U);
+ PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000C0000U ,0x00000000U);
/*############################################################################################################################ */
// : PUTTING DP IN RESET
@@ -17964,7 +19444,7 @@ unsigned long psu_resetout_init_data() {
. The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger
alue. Note: This field is valid only in device mode.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0X9
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9
Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
@@ -17972,7 +19452,7 @@ unsigned long psu_resetout_init_data() {
ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
ng hibernation. - This bit is valid only in device mode.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0X0
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0
Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
_n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
@@ -17981,42 +19461,33 @@ unsigned long psu_resetout_init_data() {
n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
d.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0X0
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0
USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. -
'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0X0
-
- Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
- figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
- ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
- r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
- t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
- g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
- when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0X1
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0
Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0X0
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0
ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
lected through DWC_USB3_HSPHY_INTERFACE.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0X1
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1
PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same
lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0X0
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0
HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for
@@ -18026,25 +19497,24 @@ unsigned long psu_resetout_init_data() {
ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times
- PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0X7
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7
Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either
he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple
ented.
- (OFFSET, MASK, VALUE) (0XFE20C200, 0x00003FFFU ,0x00002457U)
- RegMask = (USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK | USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK | USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK | USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK | USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK | USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK | 0 );
+ (OFFSET, MASK, VALUE) (0XFE20C200, 0x00003FBFU ,0x00002417U)
+ RegMask = (USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK | USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK | USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK | USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK | USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK | 0 );
RegVal = ((0x00000009U << USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT
| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT
| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT
| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT
- | 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT
| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT
| 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT
| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT
| 0x00000007U << USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (USB3_0_XHCI_GUSB2PHYCFG_OFFSET ,0x00003FFFU ,0x00002457U);
+ PSU_Mask_Write (USB3_0_XHCI_GUSB2PHYCFG_OFFSET ,0x00003FBFU ,0x00002417U);
/*############################################################################################################################ */
/*Register : GFLADJ @ 0XFE20C630
@@ -18058,7 +19528,7 @@ unsigned long psu_resetout_init_data() {
uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)
- PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0X0
+ PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0
Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res
ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio
@@ -18070,64 +19540,9 @@ unsigned long psu_resetout_init_data() {
RegVal = ((0x00000000U << USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT
| 0 ) & RegMask); */
PSU_Mask_Write (USB3_0_XHCI_GFLADJ_OFFSET ,0x003FFF00U ,0x00000000U);
- /*############################################################################################################################ */
-
- // : CHECK PLL LOCK FOR LANE0
- /*Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4
-
- Status Read value of PLL Lock
- PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
- (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U) */
- mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET,0x00000010U);
-
- /*############################################################################################################################ */
-
- // : CHECK PLL LOCK FOR LANE1
- /*Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4
-
- Status Read value of PLL Lock
- PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
- (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U) */
- mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET,0x00000010U);
-
- /*############################################################################################################################ */
-
- // : CHECK PLL LOCK FOR LANE2
- /*Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4
-
- Status Read value of PLL Lock
- PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
- (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U) */
- mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET,0x00000010U);
-
- /*############################################################################################################################ */
-
- // : CHECK PLL LOCK FOR LANE3
- /*Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4
-
- Status Read value of PLL Lock
- PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
- (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U) */
- mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET,0x00000010U);
-
/*############################################################################################################################ */
// : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON.
- /*Register : ATTR_37 @ 0XFD480094
-
- Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
- gister.; EP=0x0001; RP=0x0001
- PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0X1
-
- ATTR_37
- (OFFSET, MASK, VALUE) (0XFD480094, 0x00004000U ,0x00004000U)
- RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK | 0 );
-
- RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00004000U ,0x00004000U);
- /*############################################################################################################################ */
-
/*Register : ATTR_25 @ 0XFD480064
If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
@@ -18659,13 +20074,18 @@ unsigned long psu_resetout_init_data() {
Required for Root.; EP=0x0000; RP=0x0001
PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1
+ Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
+ gister.; EP=0x0001; RP=0x0001
+ PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1
+
ATTR_37
- (OFFSET, MASK, VALUE) (0XFD480094, 0x00000200U ,0x00000200U)
- RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK | 0 );
+ (OFFSET, MASK, VALUE) (0XFD480094, 0x00004200U ,0x00004200U)
+ RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK | PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK | 0 );
RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT
+ | 0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00000200U ,0x00000200U);
+ PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00004200U ,0x00004200U);
/*############################################################################################################################ */
/*Register : ATTR_93 @ 0XFD480174
@@ -18839,6 +20259,271 @@ unsigned long psu_resetout_init_data() {
PSU_Mask_Write (PCIE_ATTRIB_ATTR_43_OFFSET ,0x00000100U ,0x00000000U);
/*############################################################################################################################ */
+ /*Register : ATTR_48 @ 0XFD4800C0
+
+ MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note
+ hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000
+ PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0
+
+ ATTR_48
+ (OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U)
+ RegMask = (PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK | 0 );
+
+ RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (PCIE_ATTRIB_ATTR_48_OFFSET ,0x000007FFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : ATTR_46 @ 0XFD4800B8
+
+ MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001;
+ P=0x0000
+ PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0
+
+ ATTR_46
+ (OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U)
+ RegMask = (PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK | 0 );
+
+ RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (PCIE_ATTRIB_ATTR_46_OFFSET ,0x0000FFFFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : ATTR_47 @ 0XFD4800BC
+
+ MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000;
+ P=0x0000
+ PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0
+
+ ATTR_47
+ (OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U)
+ RegMask = (PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK | 0 );
+
+ RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (PCIE_ATTRIB_ATTR_47_OFFSET ,0x00001FFFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : ATTR_44 @ 0XFD4800B0
+
+ MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
+ 0x0001; RP=0x0000
+ PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0
+
+ ATTR_44
+ (OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U)
+ RegMask = (PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK | 0 );
+
+ RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (PCIE_ATTRIB_ATTR_44_OFFSET ,0x0000FFFFU ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : ATTR_45 @ 0XFD4800B4
+
+ MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
+ 0x1000; RP=0x0000
+ PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0
+
+ ATTR_45
+ (OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U)
+ RegMask = (PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK | 0 );
+
+ RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (PCIE_ATTRIB_ATTR_45_OFFSET ,0x0000FFF8U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : CB @ 0XFD48031C
+
+ DT837748 Enable
+ PSU_PCIE_ATTRIB_CB_CB1 0x0
+
+ ECO Register 1
+ (OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U)
+ RegMask = (PCIE_ATTRIB_CB_CB1_MASK | 0 );
+
+ RegVal = ((0x00000000U << PCIE_ATTRIB_CB_CB1_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (PCIE_ATTRIB_CB_OFFSET ,0x00000002U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : ATTR_35 @ 0XFD48008C
+
+ Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc
+ ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001
+ PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0
+
+ ATTR_35
+ (OFFSET, MASK, VALUE) (0XFD48008C, 0x00003000U ,0x00000000U)
+ RegMask = (PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK | 0 );
+
+ RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (PCIE_ATTRIB_ATTR_35_OFFSET ,0x00003000U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ // : PUTTING PCIE CONTROL IN RESET
+ /*Register : RST_FPD_TOP @ 0XFD1A0100
+
+ PCIE control block level reset
+ PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0
+
+ FPD Block level software controlled reset
+ (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U)
+ RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | 0 );
+
+ RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00020000U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ // : CHECK PLL LOCK FOR LANE0
+ /*Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4
+
+ Status Read value of PLL Lock
+ PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
+ (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U) */
+ mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+
+ /*############################################################################################################################ */
+
+ // : CHECK PLL LOCK FOR LANE1
+ /*Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4
+
+ Status Read value of PLL Lock
+ PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
+ (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U) */
+ mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+
+ /*############################################################################################################################ */
+
+ // : CHECK PLL LOCK FOR LANE2
+ /*Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4
+
+ Status Read value of PLL Lock
+ PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
+ (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U) */
+ mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+
+ /*############################################################################################################################ */
+
+ // : CHECK PLL LOCK FOR LANE3
+ /*Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4
+
+ Status Read value of PLL Lock
+ PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
+ (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U) */
+ mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+
+ /*############################################################################################################################ */
+
+ // : SATA AHCI VENDOR SETTING
+ /*Register : PP2C @ 0XFD0C00AC
+
+ CIBGMN: COMINIT Burst Gap Minimum.
+ PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18
+
+ CIBGMX: COMINIT Burst Gap Maximum.
+ PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40
+
+ CIBGN: COMINIT Burst Gap Nominal.
+ PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18
+
+ CINMP: COMINIT Negate Minimum Period.
+ PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28
+
+ PP2C - Port Phy2Cfg Register. This register controls the configuration of the Phy Control OOB timing for the COMINIT paramete
+ s for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
+ (OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U)
+ RegMask = (SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK | SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK | SATA_AHCI_VENDOR_PP2C_CIBGN_MASK | SATA_AHCI_VENDOR_PP2C_CINMP_MASK | 0 );
+
+ RegVal = ((0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT
+ | 0x00000040U << SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT
+ | 0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT
+ | 0x00000028U << SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SATA_AHCI_VENDOR_PP2C_OFFSET ,0xFFFFFFFFU ,0x28184018U);
+ /*############################################################################################################################ */
+
+ /*Register : PP3C @ 0XFD0C00B0
+
+ CWBGMN: COMWAKE Burst Gap Minimum.
+ PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06
+
+ CWBGMX: COMWAKE Burst Gap Maximum.
+ PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14
+
+ CWBGN: COMWAKE Burst Gap Nominal.
+ PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08
+
+ CWNMP: COMWAKE Negate Minimum Period.
+ PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E
+
+ PP3C - Port Phy3CfgRegister. This register controls the configuration of the Phy Control OOB timing for the COMWAKE parameter
+ for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
+ (OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U)
+ RegMask = (SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK | SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK | SATA_AHCI_VENDOR_PP3C_CWBGN_MASK | SATA_AHCI_VENDOR_PP3C_CWNMP_MASK | 0 );
+
+ RegVal = ((0x00000006U << SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT
+ | 0x00000014U << SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT
+ | 0x00000008U << SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT
+ | 0x0000000EU << SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SATA_AHCI_VENDOR_PP3C_OFFSET ,0xFFFFFFFFU ,0x0E081406U);
+ /*############################################################################################################################ */
+
+ /*Register : PP4C @ 0XFD0C00B4
+
+ BMX: COM Burst Maximum.
+ PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13
+
+ BNM: COM Burst Nominal.
+ PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08
+
+ SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det
+ rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa
+ Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of
+ 500ns based on a 150MHz PMCLK.
+ PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A
+
+ PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th
+ value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128
+ PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06
+
+ PP4C - Port Phy4Cfg Register. This register controls the configuration of the Phy Control Burst timing for the COM parameters
+ for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
+ (OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U)
+ RegMask = (SATA_AHCI_VENDOR_PP4C_BMX_MASK | SATA_AHCI_VENDOR_PP4C_BNM_MASK | SATA_AHCI_VENDOR_PP4C_SFD_MASK | SATA_AHCI_VENDOR_PP4C_PTST_MASK | 0 );
+
+ RegVal = ((0x00000013U << SATA_AHCI_VENDOR_PP4C_BMX_SHIFT
+ | 0x00000008U << SATA_AHCI_VENDOR_PP4C_BNM_SHIFT
+ | 0x0000004AU << SATA_AHCI_VENDOR_PP4C_SFD_SHIFT
+ | 0x00000006U << SATA_AHCI_VENDOR_PP4C_PTST_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SATA_AHCI_VENDOR_PP4C_OFFSET ,0xFFFFFFFFU ,0x064A0813U);
+ /*############################################################################################################################ */
+
+ /*Register : PP5C @ 0XFD0C00B8
+
+ RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed.
+ PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4
+
+ RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha
+ completed, for a fast SERDES it is suggested that this value be 54.2us / 4
+ PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF
+
+ PP5C - Port Phy5Cfg Register. This register controls the configuration of the Phy Control Retry Interval timing for either Po
+ t 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
+ (OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U)
+ RegMask = (SATA_AHCI_VENDOR_PP5C_RIT_MASK | SATA_AHCI_VENDOR_PP5C_RCT_MASK | 0 );
+
+ RegVal = ((0x000C96A4U << SATA_AHCI_VENDOR_PP5C_RIT_SHIFT
+ | 0x000003FFU << SATA_AHCI_VENDOR_PP5C_RCT_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SATA_AHCI_VENDOR_PP5C_OFFSET ,0xFFFFFFFFU ,0x3FFC96A4U);
+ /*############################################################################################################################ */
+
return 1;
}
@@ -19115,12 +20800,23 @@ unsigned long psu_ddr_phybringup_data() {
unsigned int regval = 0;
- Xil_Out32(0xFD090000U, 0x0000A845U);
- Xil_Out32(0xFD090004U, 0x003FFFFFU);
- Xil_Out32(0xFD09000CU, 0x00000010U);
- Xil_Out32(0xFD090010U, 0x00000010U);
+ int dpll_divisor;
+ dpll_divisor = (Xil_In32(0xFD1A0080U) & 0x00003F00U) >> 0x00000008U;
+ prog_reg (0xFD1A0080U, 0x00003F00U, 0x00000008U, 0x00000005U);
+ prog_reg (0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
+ Xil_Out32(0xFD080004U, 0x00040003U);
+ while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U);
+ prog_reg (0xFD080684U, 0x06000000U, 0x00000019U, 0x00000001U);
+ prog_reg (0xFD0806A4U, 0x06000000U, 0x00000019U, 0x00000001U);
+ prog_reg (0xFD0806C4U, 0x06000000U, 0x00000019U, 0x00000001U);
+ prog_reg (0xFD0806E4U, 0x06000000U, 0x00000019U, 0x00000001U);
+ prog_reg (0xFD1A0080, 0x3F00, 0x8, dpll_divisor);
+ Xil_Out32(0xFD080004U, 0x40040071U);
+ while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U);
+ Xil_Out32(0xFD080004U, 0x40040001U);
+ while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U);
// PHY BRINGUP SEQ
- while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000000FU);
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU);
prog_reg (0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
//poll for PHY initialization to complete
while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU);
@@ -19137,14 +20833,14 @@ unsigned long psu_ddr_phybringup_data() {
// Run Vref training in static read mode
- Xil_Out32(0xFD080200U, 0x110011C7U);
+ Xil_Out32(0xFD080200U, 0x100091C7U);
Xil_Out32(0xFD080018U, 0x00F01EF2U);
- Xil_Out32(0xFD08001CU, 0x55AA0098U);
- Xil_Out32(0xFD08142CU, 0x00001830U);
- Xil_Out32(0xFD08146CU, 0x00001830U);
- Xil_Out32(0xFD0814ACU, 0x00001830U);
- Xil_Out32(0xFD0814ECU, 0x00001830U);
- Xil_Out32(0xFD08152CU, 0x00001830U);
+ Xil_Out32(0xFD08001CU, 0x55AA5498U);
+ Xil_Out32(0xFD08142CU, 0x00041830U);
+ Xil_Out32(0xFD08146CU, 0x00041830U);
+ Xil_Out32(0xFD0814ACU, 0x00041830U);
+ Xil_Out32(0xFD0814ECU, 0x00041830U);
+ Xil_Out32(0xFD08152CU, 0x00041830U);
Xil_Out32(0xFD080004, 0x00060001); //PUB_PIR
@@ -19154,14 +20850,22 @@ unsigned long psu_ddr_phybringup_data() {
}
// Vref training is complete, disabling static read mode
- Xil_Out32(0xFD080200U, 0x810011C7U);
+ Xil_Out32(0xFD080200U, 0x800091C7U);
Xil_Out32(0xFD080018U, 0x00F12302U);
- Xil_Out32(0xFD08001CU, 0x55AA0080U);
- Xil_Out32(0xFD08142CU, 0x00001800U);
- Xil_Out32(0xFD08146CU, 0x00001800U);
- Xil_Out32(0xFD0814ACU, 0x00001800U);
- Xil_Out32(0xFD0814ECU, 0x00001800U);
- Xil_Out32(0xFD08152CU, 0x00001800U);
+ Xil_Out32(0xFD08001CU, 0x55AA5480U);
+ Xil_Out32(0xFD08142CU, 0x00041800U);
+ Xil_Out32(0xFD08146CU, 0x00041800U);
+ Xil_Out32(0xFD0814ACU, 0x00041800U);
+ Xil_Out32(0xFD0814ECU, 0x00041800U);
+ Xil_Out32(0xFD08152CU, 0x00041800U);
+
+
+ Xil_Out32(0xFD080004, 0x0000C001); //PUB_PIR
+ regval = Xil_In32(0xFD080030); //PUB_PGSR0
+ while((regval & 0x80000C01) != 0x80000C01){
+ regval = Xil_In32(0xFD080030); //PUB_PGSR0
+ }
+
Xil_Out32(0xFD070180U, 0x01000040U);
Xil_Out32(0xFD070060U, 0x00000000U);
prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
@@ -19191,7 +20895,7 @@ return 1;
int mask_pollOnValue(u32 add , u32 mask, u32 value ) {
- volatile u32 *addr = (volatile u32*) add;
+ volatile u32 *addr = (volatile u32*)(unsigned long) add;
int i = 0;
while ((*addr & mask)!= value) {
if (i == PSU_MASK_POLL_TIME) {
@@ -19204,7 +20908,7 @@ int mask_pollOnValue(u32 add , u32 mask, u32 value ) {
}
int mask_poll(u32 add , u32 mask) {
- volatile u32 *addr = (volatile u32*) add;
+ volatile u32 *addr = (volatile u32*)(unsigned long) add;
int i = 0;
while (!(*addr & mask)) {
if (i == PSU_MASK_POLL_TIME) {
@@ -19221,7 +20925,7 @@ void mask_delay(u32 delay) {
}
u32 mask_read(u32 add , u32 mask ) {
- volatile u32 *addr = (volatile u32*) add;
+ volatile u32 *addr = (volatile u32*)(unsigned long) add;
u32 val = (*addr & mask);
//xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
return val;
@@ -19333,6 +21037,58 @@ void init_peripheral()
tmp_regval &= ~0x00000001;
Xil_Out32(0xFD690030, tmp_regval);
}
+
+int psu_init_xppu_aper_ram() {
+ unsigned long APER_OFFSET = 0xFF981000;
+ int i = 0;
+ for (; i <= 400; i++) {
+ PSU_Mask_Write (APER_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ APER_OFFSET = APER_OFFSET + 0x4;
+ }
+
+ return 0;
+}
+
+int psu_lpd_protection() {
+ psu_init_xppu_aper_ram();
+ psu_lpd_xppu_data();
+ return 0;
+}
+
+int psu_ddr_protection() {
+ psu_ddr_xmpu0_data();
+ psu_ddr_xmpu1_data();
+ psu_ddr_xmpu2_data();
+ psu_ddr_xmpu3_data();
+ psu_ddr_xmpu4_data();
+ psu_ddr_xmpu5_data();
+ return 0;
+}
+int psu_ocm_protection() {
+ psu_ocm_xmpu_data();
+ return 0;
+}
+
+int psu_fpd_protection() {
+ psu_fpd_xmpu_data();
+ return 0;
+}
+
+int psu_protection_lock() {
+ psu_protection_lock_data();
+ return 0;
+}
+
+int psu_protection() {
+ psu_ddr_protection();
+ psu_ocm_protection();
+ psu_fpd_protection();
+ psu_lpd_protection();
+ return 0;
+}
+
+
+
int
psu_init()
{
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h
index ae33f880c..0fb578181 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h
@@ -772,26 +772,14 @@
#define CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL 0x00000000
#define CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT 0
#define CRF_APB_VPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU
-#undef CRL_APB_GEM0_REF_CTRL_OFFSET
-#define CRL_APB_GEM0_REF_CTRL_OFFSET 0XFF5E0050
-#undef CRL_APB_GEM1_REF_CTRL_OFFSET
-#define CRL_APB_GEM1_REF_CTRL_OFFSET 0XFF5E0054
-#undef CRL_APB_GEM2_REF_CTRL_OFFSET
-#define CRL_APB_GEM2_REF_CTRL_OFFSET 0XFF5E0058
#undef CRL_APB_GEM3_REF_CTRL_OFFSET
#define CRL_APB_GEM3_REF_CTRL_OFFSET 0XFF5E005C
-#undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET
-#define CRL_APB_GEM_TSU_REF_CTRL_OFFSET 0XFF5E0100
#undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET
#define CRL_APB_USB0_BUS_REF_CTRL_OFFSET 0XFF5E0060
-#undef CRL_APB_USB1_BUS_REF_CTRL_OFFSET
-#define CRL_APB_USB1_BUS_REF_CTRL_OFFSET 0XFF5E0064
#undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET
#define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 0XFF5E004C
#undef CRL_APB_QSPI_REF_CTRL_OFFSET
#define CRL_APB_QSPI_REF_CTRL_OFFSET 0XFF5E0068
-#undef CRL_APB_SDIO0_REF_CTRL_OFFSET
-#define CRL_APB_SDIO0_REF_CTRL_OFFSET 0XFF5E006C
#undef CRL_APB_SDIO1_REF_CTRL_OFFSET
#define CRL_APB_SDIO1_REF_CTRL_OFFSET 0XFF5E0070
#undef IOU_SLCR_SDIO_CLK_CTRL_OFFSET
@@ -804,20 +792,12 @@
#define CRL_APB_I2C0_REF_CTRL_OFFSET 0XFF5E0120
#undef CRL_APB_I2C1_REF_CTRL_OFFSET
#define CRL_APB_I2C1_REF_CTRL_OFFSET 0XFF5E0124
-#undef CRL_APB_SPI0_REF_CTRL_OFFSET
-#define CRL_APB_SPI0_REF_CTRL_OFFSET 0XFF5E007C
-#undef CRL_APB_SPI1_REF_CTRL_OFFSET
-#define CRL_APB_SPI1_REF_CTRL_OFFSET 0XFF5E0080
-#undef CRL_APB_CAN0_REF_CTRL_OFFSET
-#define CRL_APB_CAN0_REF_CTRL_OFFSET 0XFF5E0084
#undef CRL_APB_CAN1_REF_CTRL_OFFSET
#define CRL_APB_CAN1_REF_CTRL_OFFSET 0XFF5E0088
#undef CRL_APB_CPU_R5_CTRL_OFFSET
#define CRL_APB_CPU_R5_CTRL_OFFSET 0XFF5E0090
#undef CRL_APB_IOU_SWITCH_CTRL_OFFSET
#define CRL_APB_IOU_SWITCH_CTRL_OFFSET 0XFF5E009C
-#undef CRL_APB_CSU_PLL_CTRL_OFFSET
-#define CRL_APB_CSU_PLL_CTRL_OFFSET 0XFF5E00A0
#undef CRL_APB_PCAP_CTRL_OFFSET
#define CRL_APB_PCAP_CTRL_OFFSET 0XFF5E00A4
#undef CRL_APB_LPD_SWITCH_CTRL_OFFSET
@@ -826,8 +806,6 @@
#define CRL_APB_LPD_LSBUS_CTRL_OFFSET 0XFF5E00AC
#undef CRL_APB_DBG_LPD_CTRL_OFFSET
#define CRL_APB_DBG_LPD_CTRL_OFFSET 0XFF5E00B0
-#undef CRL_APB_NAND_REF_CTRL_OFFSET
-#define CRL_APB_NAND_REF_CTRL_OFFSET 0XFF5E00B4
#undef CRL_APB_ADMA_REF_CTRL_OFFSET
#define CRL_APB_ADMA_REF_CTRL_OFFSET 0XFF5E00B8
#undef CRL_APB_PL0_REF_CTRL_OFFSET
@@ -872,8 +850,6 @@
#define CRF_APB_TOPSW_MAIN_CTRL_OFFSET 0XFD1A00C0
#undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET
#define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 0XFD1A00C4
-#undef CRF_APB_GTGREF0_REF_CTRL_OFFSET
-#define CRF_APB_GTGREF0_REF_CTRL_OFFSET 0XFD1A00C8
#undef CRF_APB_DBG_TSTMP_CTRL_OFFSET
#define CRF_APB_DBG_TSTMP_CTRL_OFFSET 0XFD1A00F8
#undef IOU_SLCR_IOU_TTC_APB_CLK_OFFSET
@@ -885,129 +861,6 @@
#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET
#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 0XFF410050
-/*Clock active for the RX channel*/
-#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL
-#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT
-#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK
-#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500
-#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT 26
-#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK 0x04000000U
-
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_GEM0_REF_CTRL_CLKACT_MASK
-#define CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL 0x00002500
-#define CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT 25
-#define CRL_APB_GEM0_REF_CTRL_CLKACT_MASK 0x02000000U
-
-/*6 bit divider*/
-#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL 0x00002500
-#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL 0x00002500
-#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL 0x00002500
-#define CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK 0x00000007U
-
-/*Clock active for the RX channel*/
-#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL
-#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT
-#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK
-#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500
-#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT 26
-#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK 0x04000000U
-
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_GEM1_REF_CTRL_CLKACT_MASK
-#define CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL 0x00002500
-#define CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT 25
-#define CRL_APB_GEM1_REF_CTRL_CLKACT_MASK 0x02000000U
-
-/*6 bit divider*/
-#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL 0x00002500
-#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL 0x00002500
-#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL 0x00002500
-#define CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK 0x00000007U
-
-/*Clock active for the RX channel*/
-#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL
-#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT
-#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK
-#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500
-#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT 26
-#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK 0x04000000U
-
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_GEM2_REF_CTRL_CLKACT_MASK
-#define CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL 0x00002500
-#define CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT 25
-#define CRL_APB_GEM2_REF_CTRL_CLKACT_MASK 0x02000000U
-
-/*6 bit divider*/
-#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL 0x00002500
-#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL 0x00002500
-#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL 0x00002500
-#define CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK 0x00000007U
-
/*Clock active for the RX channel*/
#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL
#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT
@@ -1049,39 +902,6 @@
#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U
-/*6 bit divider*/
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 0x00051000
-#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 0x00051000
-#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 0x00000007U
-
-/*6 bit divider*/
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 0x00051000
-#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK
-#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 0x00051000
-#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 24
-#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 0x01000000U
-
/*Clock active signal. Switch to 0 to disable the clock*/
#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL
#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT
@@ -1115,39 +935,6 @@
#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK
-#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000
-#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT 25
-#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK 0x02000000U
-
-/*6 bit divider*/
-#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
-#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
-#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000
-#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U
-
/*Clock active signal. Switch to 0 to disable the clock*/
#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL
#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT
@@ -1214,39 +1001,6 @@
#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK
-#define CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL 0x01000F00
-#define CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT 24
-#define CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK 0x01000000U
-
-/*6 bit divider*/
-#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00
-#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00
-#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL 0x01000F00
-#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK 0x00000007U
-
/*Clock active signal. Switch to 0 to disable the clock*/
#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL
#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT
@@ -1420,105 +1174,6 @@
#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_SPI0_REF_CTRL_CLKACT_MASK
-#define CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL 0x01001800
-#define CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT 24
-#define CRL_APB_SPI0_REF_CTRL_CLKACT_MASK 0x01000000U
-
-/*6 bit divider*/
-#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
-#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
-#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL 0x01001800
-#define CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK 0x00000007U
-
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_SPI1_REF_CTRL_CLKACT_MASK
-#define CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL 0x01001800
-#define CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT 24
-#define CRL_APB_SPI1_REF_CTRL_CLKACT_MASK 0x01000000U
-
-/*6 bit divider*/
-#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
-#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
-#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL 0x01001800
-#define CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK 0x00000007U
-
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_CAN0_REF_CTRL_CLKACT_MASK
-#define CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL 0x01001800
-#define CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT 24
-#define CRL_APB_CAN0_REF_CTRL_CLKACT_MASK 0x01000000U
-
-/*6 bit divider*/
-#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
-#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
-#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL 0x01001800
-#define CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK 0x00000007U
-
/*Clock active signal. Switch to 0 to disable the clock*/
#undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL
#undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT
@@ -1603,31 +1258,6 @@
#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_CSU_PLL_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT
-#undef CRL_APB_CSU_PLL_CTRL_CLKACT_MASK
-#define CRL_APB_CSU_PLL_CTRL_CLKACT_DEFVAL 0x01001500
-#define CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT 24
-#define CRL_APB_CSU_PLL_CTRL_CLKACT_MASK 0x01000000U
-
-/*6 bit divider*/
-#undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK
-#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_DEFVAL 0x01001500
-#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_CSU_PLL_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK
-#define CRL_APB_CSU_PLL_CTRL_SRCSEL_DEFVAL 0x01001500
-#define CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK 0x00000007U
-
/*Clock active signal. Switch to 0 to disable the clock*/
#undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL
#undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT
@@ -1728,39 +1358,6 @@
#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL
-#undef CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT
-#undef CRL_APB_NAND_REF_CTRL_CLKACT_MASK
-#define CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL 0x00052000
-#define CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT 24
-#define CRL_APB_NAND_REF_CTRL_CLKACT_MASK 0x01000000U
-
-/*6 bit divider*/
-#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL
-#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT
-#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK
-#define CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
-#define CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT 16
-#define CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK 0x003F0000U
-
-/*6 bit divider*/
-#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT
-#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK
-#define CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
-#define CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
- clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL
-#undef CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT
-#undef CRL_APB_NAND_REF_CTRL_SRCSEL_MASK
-#define CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL 0x00052000
-#define CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT 0
-#define CRL_APB_NAND_REF_CTRL_SRCSEL_MASK 0x00000007U
-
/*Clock active signal. Switch to 0 to disable the clock*/
#undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL
#undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT
@@ -2376,31 +1973,6 @@
#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24
#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U
-/*6 bit divider*/
-#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT
-#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK
-#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL 0x00000800
-#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
-/*000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
- he new clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL
-#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT
-#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK
-#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL 0x00000800
-#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT 0
-#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK 0x00000007U
-
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL
-#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT
-#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK
-#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL 0x00000800
-#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT 24
-#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK 0x01000000U
-
/*6 bit divider*/
#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL
#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT
@@ -2702,6 +2274,8 @@
#define DDR_PHY_PGCR0_OFFSET 0XFD080010
#undef DDR_PHY_PGCR2_OFFSET
#define DDR_PHY_PGCR2_OFFSET 0XFD080018
+#undef DDR_PHY_PGCR3_OFFSET
+#define DDR_PHY_PGCR3_OFFSET 0XFD08001C
#undef DDR_PHY_PGCR5_OFFSET
#define DDR_PHY_PGCR5_OFFSET 0XFD080024
#undef DDR_PHY_PTR0_OFFSET
@@ -2730,6 +2304,8 @@
#define DDR_PHY_RDIMMGCR0_OFFSET 0XFD080140
#undef DDR_PHY_RDIMMGCR1_OFFSET
#define DDR_PHY_RDIMMGCR1_OFFSET 0XFD080144
+#undef DDR_PHY_RDIMMCR0_OFFSET
+#define DDR_PHY_RDIMMCR0_OFFSET 0XFD080150
#undef DDR_PHY_RDIMMCR1_OFFSET
#define DDR_PHY_RDIMMCR1_OFFSET 0XFD080154
#undef DDR_PHY_MR0_OFFSET
@@ -2762,6 +2338,8 @@
#define DDR_PHY_DTCR1_OFFSET 0XFD080204
#undef DDR_PHY_CATR0_OFFSET
#define DDR_PHY_CATR0_OFFSET 0XFD080240
+#undef DDR_PHY_BISTLSR_OFFSET
+#define DDR_PHY_BISTLSR_OFFSET 0XFD080414
#undef DDR_PHY_RIOCR5_OFFSET
#define DDR_PHY_RIOCR5_OFFSET 0XFD0804F4
#undef DDR_PHY_ACIOCR0_OFFSET
@@ -2778,12 +2356,18 @@
#define DDR_PHY_VTCR0_OFFSET 0XFD080528
#undef DDR_PHY_VTCR1_OFFSET
#define DDR_PHY_VTCR1_OFFSET 0XFD08052C
+#undef DDR_PHY_ACBDLR1_OFFSET
+#define DDR_PHY_ACBDLR1_OFFSET 0XFD080544
+#undef DDR_PHY_ACBDLR2_OFFSET
+#define DDR_PHY_ACBDLR2_OFFSET 0XFD080548
#undef DDR_PHY_ACBDLR6_OFFSET
#define DDR_PHY_ACBDLR6_OFFSET 0XFD080558
#undef DDR_PHY_ACBDLR7_OFFSET
#define DDR_PHY_ACBDLR7_OFFSET 0XFD08055C
#undef DDR_PHY_ACBDLR8_OFFSET
#define DDR_PHY_ACBDLR8_OFFSET 0XFD080560
+#undef DDR_PHY_ACBDLR9_OFFSET
+#define DDR_PHY_ACBDLR9_OFFSET 0XFD080564
#undef DDR_PHY_ZQCR_OFFSET
#define DDR_PHY_ZQCR_OFFSET 0XFD080680
#undef DDR_PHY_ZQ0PR0_OFFSET
@@ -2916,30 +2500,40 @@
#define DDR_PHY_DX8LCDLR2_OFFSET 0XFD080F88
#undef DDR_PHY_DX8GTR0_OFFSET
#define DDR_PHY_DX8GTR0_OFFSET 0XFD080FC0
+#undef DDR_PHY_DX8SL0OSC_OFFSET
+#define DDR_PHY_DX8SL0OSC_OFFSET 0XFD081400
#undef DDR_PHY_DX8SL0DQSCTL_OFFSET
#define DDR_PHY_DX8SL0DQSCTL_OFFSET 0XFD08141C
#undef DDR_PHY_DX8SL0DXCTL2_OFFSET
#define DDR_PHY_DX8SL0DXCTL2_OFFSET 0XFD08142C
#undef DDR_PHY_DX8SL0IOCR_OFFSET
#define DDR_PHY_DX8SL0IOCR_OFFSET 0XFD081430
+#undef DDR_PHY_DX8SL1OSC_OFFSET
+#define DDR_PHY_DX8SL1OSC_OFFSET 0XFD081440
#undef DDR_PHY_DX8SL1DQSCTL_OFFSET
#define DDR_PHY_DX8SL1DQSCTL_OFFSET 0XFD08145C
#undef DDR_PHY_DX8SL1DXCTL2_OFFSET
#define DDR_PHY_DX8SL1DXCTL2_OFFSET 0XFD08146C
#undef DDR_PHY_DX8SL1IOCR_OFFSET
#define DDR_PHY_DX8SL1IOCR_OFFSET 0XFD081470
+#undef DDR_PHY_DX8SL2OSC_OFFSET
+#define DDR_PHY_DX8SL2OSC_OFFSET 0XFD081480
#undef DDR_PHY_DX8SL2DQSCTL_OFFSET
#define DDR_PHY_DX8SL2DQSCTL_OFFSET 0XFD08149C
#undef DDR_PHY_DX8SL2DXCTL2_OFFSET
#define DDR_PHY_DX8SL2DXCTL2_OFFSET 0XFD0814AC
#undef DDR_PHY_DX8SL2IOCR_OFFSET
#define DDR_PHY_DX8SL2IOCR_OFFSET 0XFD0814B0
+#undef DDR_PHY_DX8SL3OSC_OFFSET
+#define DDR_PHY_DX8SL3OSC_OFFSET 0XFD0814C0
#undef DDR_PHY_DX8SL3DQSCTL_OFFSET
#define DDR_PHY_DX8SL3DQSCTL_OFFSET 0XFD0814DC
#undef DDR_PHY_DX8SL3DXCTL2_OFFSET
#define DDR_PHY_DX8SL3DXCTL2_OFFSET 0XFD0814EC
#undef DDR_PHY_DX8SL3IOCR_OFFSET
#define DDR_PHY_DX8SL3IOCR_OFFSET 0XFD0814F0
+#undef DDR_PHY_DX8SL4OSC_OFFSET
+#define DDR_PHY_DX8SL4OSC_OFFSET 0XFD081500
#undef DDR_PHY_DX8SL4DQSCTL_OFFSET
#define DDR_PHY_DX8SL4DQSCTL_OFFSET 0XFD08151C
#undef DDR_PHY_DX8SL4DXCTL2_OFFSET
@@ -6664,6 +6258,102 @@
#define DDR_PHY_PGCR2_TREFPRD_SHIFT 0
#define DDR_PHY_PGCR2_TREFPRD_MASK 0x0003FFFFU
+/*CKN Enable*/
+#undef DDR_PHY_PGCR3_CKNEN_DEFVAL
+#undef DDR_PHY_PGCR3_CKNEN_SHIFT
+#undef DDR_PHY_PGCR3_CKNEN_MASK
+#define DDR_PHY_PGCR3_CKNEN_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_CKNEN_SHIFT 24
+#define DDR_PHY_PGCR3_CKNEN_MASK 0xFF000000U
+
+/*CK Enable*/
+#undef DDR_PHY_PGCR3_CKEN_DEFVAL
+#undef DDR_PHY_PGCR3_CKEN_SHIFT
+#undef DDR_PHY_PGCR3_CKEN_MASK
+#define DDR_PHY_PGCR3_CKEN_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_CKEN_SHIFT 16
+#define DDR_PHY_PGCR3_CKEN_MASK 0x00FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_PGCR3_RESERVED_15_DEFVAL
+#undef DDR_PHY_PGCR3_RESERVED_15_SHIFT
+#undef DDR_PHY_PGCR3_RESERVED_15_MASK
+#define DDR_PHY_PGCR3_RESERVED_15_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_RESERVED_15_SHIFT 15
+#define DDR_PHY_PGCR3_RESERVED_15_MASK 0x00008000U
+
+/*Enable Clock Gating for AC [0] ctl_rd_clk*/
+#undef DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL
+#undef DDR_PHY_PGCR3_GATEACRDCLK_SHIFT
+#undef DDR_PHY_PGCR3_GATEACRDCLK_MASK
+#define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 13
+#define DDR_PHY_PGCR3_GATEACRDCLK_MASK 0x00006000U
+
+/*Enable Clock Gating for AC [0] ddr_clk*/
+#undef DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL
+#undef DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT
+#undef DDR_PHY_PGCR3_GATEACDDRCLK_MASK
+#define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 11
+#define DDR_PHY_PGCR3_GATEACDDRCLK_MASK 0x00001800U
+
+/*Enable Clock Gating for AC [0] ctl_clk*/
+#undef DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL
+#undef DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT
+#undef DDR_PHY_PGCR3_GATEACCTLCLK_MASK
+#define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 9
+#define DDR_PHY_PGCR3_GATEACCTLCLK_MASK 0x00000600U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_PGCR3_RESERVED_8_DEFVAL
+#undef DDR_PHY_PGCR3_RESERVED_8_SHIFT
+#undef DDR_PHY_PGCR3_RESERVED_8_MASK
+#define DDR_PHY_PGCR3_RESERVED_8_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_RESERVED_8_SHIFT 8
+#define DDR_PHY_PGCR3_RESERVED_8_MASK 0x00000100U
+
+/*Controls DDL Bypass Modes*/
+#undef DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL
+#undef DDR_PHY_PGCR3_DDLBYPMODE_SHIFT
+#undef DDR_PHY_PGCR3_DDLBYPMODE_MASK
+#define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 6
+#define DDR_PHY_PGCR3_DDLBYPMODE_MASK 0x000000C0U
+
+/*IO Loop-Back Select*/
+#undef DDR_PHY_PGCR3_IOLB_DEFVAL
+#undef DDR_PHY_PGCR3_IOLB_SHIFT
+#undef DDR_PHY_PGCR3_IOLB_MASK
+#define DDR_PHY_PGCR3_IOLB_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_IOLB_SHIFT 5
+#define DDR_PHY_PGCR3_IOLB_MASK 0x00000020U
+
+/*AC Receive FIFO Read Mode*/
+#undef DDR_PHY_PGCR3_RDMODE_DEFVAL
+#undef DDR_PHY_PGCR3_RDMODE_SHIFT
+#undef DDR_PHY_PGCR3_RDMODE_MASK
+#define DDR_PHY_PGCR3_RDMODE_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_RDMODE_SHIFT 3
+#define DDR_PHY_PGCR3_RDMODE_MASK 0x00000018U
+
+/*Read FIFO Reset Disable*/
+#undef DDR_PHY_PGCR3_DISRST_DEFVAL
+#undef DDR_PHY_PGCR3_DISRST_SHIFT
+#undef DDR_PHY_PGCR3_DISRST_MASK
+#define DDR_PHY_PGCR3_DISRST_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_DISRST_SHIFT 2
+#define DDR_PHY_PGCR3_DISRST_MASK 0x00000004U
+
+/*Clock Level when Clock Gating*/
+#undef DDR_PHY_PGCR3_CLKLEVEL_DEFVAL
+#undef DDR_PHY_PGCR3_CLKLEVEL_SHIFT
+#undef DDR_PHY_PGCR3_CLKLEVEL_MASK
+#define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 0x55AA0080
+#define DDR_PHY_PGCR3_CLKLEVEL_SHIFT 0
+#define DDR_PHY_PGCR3_CLKLEVEL_MASK 0x00000003U
+
/*Frequency B Ratio Term*/
#undef DDR_PHY_PGCR5_FRQBT_DEFVAL
#undef DDR_PHY_PGCR5_FRQBT_SHIFT
@@ -7673,6 +7363,72 @@
#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 0
#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 0x00003FFFU
+/*DDR4/DDR3 Control Word 7*/
+#undef DDR_PHY_RDIMMCR0_RC7_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC7_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC7_MASK
+#define DDR_PHY_RDIMMCR0_RC7_DEFVAL 0x00000000
+#define DDR_PHY_RDIMMCR0_RC7_SHIFT 28
+#define DDR_PHY_RDIMMCR0_RC7_MASK 0xF0000000U
+
+/*DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved*/
+#undef DDR_PHY_RDIMMCR0_RC6_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC6_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC6_MASK
+#define DDR_PHY_RDIMMCR0_RC6_DEFVAL 0x00000000
+#define DDR_PHY_RDIMMCR0_RC6_SHIFT 24
+#define DDR_PHY_RDIMMCR0_RC6_MASK 0x0F000000U
+
+/*DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)*/
+#undef DDR_PHY_RDIMMCR0_RC5_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC5_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC5_MASK
+#define DDR_PHY_RDIMMCR0_RC5_DEFVAL 0x00000000
+#define DDR_PHY_RDIMMCR0_RC5_SHIFT 20
+#define DDR_PHY_RDIMMCR0_RC5_MASK 0x00F00000U
+
+/*DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C
+ aracteristics Control Word)*/
+#undef DDR_PHY_RDIMMCR0_RC4_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC4_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC4_MASK
+#define DDR_PHY_RDIMMCR0_RC4_DEFVAL 0x00000000
+#define DDR_PHY_RDIMMCR0_RC4_SHIFT 16
+#define DDR_PHY_RDIMMCR0_RC4_MASK 0x000F0000U
+
+/*DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr
+ ver Characteristrics Control Word)*/
+#undef DDR_PHY_RDIMMCR0_RC3_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC3_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC3_MASK
+#define DDR_PHY_RDIMMCR0_RC3_DEFVAL 0x00000000
+#define DDR_PHY_RDIMMCR0_RC3_SHIFT 12
+#define DDR_PHY_RDIMMCR0_RC3_MASK 0x0000F000U
+
+/*DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)*/
+#undef DDR_PHY_RDIMMCR0_RC2_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC2_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC2_MASK
+#define DDR_PHY_RDIMMCR0_RC2_DEFVAL 0x00000000
+#define DDR_PHY_RDIMMCR0_RC2_SHIFT 8
+#define DDR_PHY_RDIMMCR0_RC2_MASK 0x00000F00U
+
+/*DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)*/
+#undef DDR_PHY_RDIMMCR0_RC1_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC1_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC1_MASK
+#define DDR_PHY_RDIMMCR0_RC1_DEFVAL 0x00000000
+#define DDR_PHY_RDIMMCR0_RC1_SHIFT 4
+#define DDR_PHY_RDIMMCR0_RC1_MASK 0x000000F0U
+
+/*DDR4/DDR3 Control Word 0 (Global Features Control Word)*/
+#undef DDR_PHY_RDIMMCR0_RC0_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC0_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC0_MASK
+#define DDR_PHY_RDIMMCR0_RC0_DEFVAL 0x00000000
+#define DDR_PHY_RDIMMCR0_RC0_SHIFT 0
+#define DDR_PHY_RDIMMCR0_RC0_MASK 0x0000000FU
+
/*Control Word 15*/
#undef DDR_PHY_RDIMMCR1_RC15_DEFVAL
#undef DDR_PHY_RDIMMCR1_RC15_SHIFT
@@ -8660,6 +8416,14 @@
#define DDR_PHY_CATR0_CA1BYTE0_SHIFT 0
#define DDR_PHY_CATR0_CA1BYTE0_MASK 0x0000000FU
+/*LFSR seed for pseudo-random BIST patterns*/
+#undef DDR_PHY_BISTLSR_SEED_DEFVAL
+#undef DDR_PHY_BISTLSR_SEED_SHIFT
+#undef DDR_PHY_BISTLSR_SEED_MASK
+#define DDR_PHY_BISTLSR_SEED_DEFVAL
+#define DDR_PHY_BISTLSR_SEED_SHIFT 0
+#define DDR_PHY_BISTLSR_SEED_MASK 0xFFFFFFFFU
+
/*Reserved. Return zeroes on reads.*/
#undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL
#undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT
@@ -9220,6 +8984,134 @@
#define DDR_PHY_VTCR1_HVIO_SHIFT 0
#define DDR_PHY_VTCR1_HVIO_MASK 0x00000001U
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT
+#undef DDR_PHY_ACBDLR1_RESERVED_31_30_MASK
+#define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 30
+#define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 0xC0000000U
+
+/*Delay select for the BDL on Parity.*/
+#undef DDR_PHY_ACBDLR1_PARBD_DEFVAL
+#undef DDR_PHY_ACBDLR1_PARBD_SHIFT
+#undef DDR_PHY_ACBDLR1_PARBD_MASK
+#define DDR_PHY_ACBDLR1_PARBD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR1_PARBD_SHIFT 24
+#define DDR_PHY_ACBDLR1_PARBD_MASK 0x3F000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT
+#undef DDR_PHY_ACBDLR1_RESERVED_23_22_MASK
+#define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 22
+#define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 0x00C00000U
+
+/*Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE.*/
+#undef DDR_PHY_ACBDLR1_A16BD_DEFVAL
+#undef DDR_PHY_ACBDLR1_A16BD_SHIFT
+#undef DDR_PHY_ACBDLR1_A16BD_MASK
+#define DDR_PHY_ACBDLR1_A16BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR1_A16BD_SHIFT 16
+#define DDR_PHY_ACBDLR1_A16BD_MASK 0x003F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT
+#undef DDR_PHY_ACBDLR1_RESERVED_15_14_MASK
+#define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 14
+#define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 0x0000C000U
+
+/*Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS.*/
+#undef DDR_PHY_ACBDLR1_A17BD_DEFVAL
+#undef DDR_PHY_ACBDLR1_A17BD_SHIFT
+#undef DDR_PHY_ACBDLR1_A17BD_MASK
+#define DDR_PHY_ACBDLR1_A17BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR1_A17BD_SHIFT 8
+#define DDR_PHY_ACBDLR1_A17BD_MASK 0x00003F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT
+#undef DDR_PHY_ACBDLR1_RESERVED_7_6_MASK
+#define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 6
+#define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 0x000000C0U
+
+/*Delay select for the BDL on ACTN.*/
+#undef DDR_PHY_ACBDLR1_ACTBD_DEFVAL
+#undef DDR_PHY_ACBDLR1_ACTBD_SHIFT
+#undef DDR_PHY_ACBDLR1_ACTBD_MASK
+#define DDR_PHY_ACBDLR1_ACTBD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR1_ACTBD_SHIFT 0
+#define DDR_PHY_ACBDLR1_ACTBD_MASK 0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT
+#undef DDR_PHY_ACBDLR2_RESERVED_31_30_MASK
+#define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 30
+#define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 0xC0000000U
+
+/*Delay select for the BDL on BG[1].*/
+#undef DDR_PHY_ACBDLR2_BG1BD_DEFVAL
+#undef DDR_PHY_ACBDLR2_BG1BD_SHIFT
+#undef DDR_PHY_ACBDLR2_BG1BD_MASK
+#define DDR_PHY_ACBDLR2_BG1BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR2_BG1BD_SHIFT 24
+#define DDR_PHY_ACBDLR2_BG1BD_MASK 0x3F000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT
+#undef DDR_PHY_ACBDLR2_RESERVED_23_22_MASK
+#define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 22
+#define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 0x00C00000U
+
+/*Delay select for the BDL on BG[0].*/
+#undef DDR_PHY_ACBDLR2_BG0BD_DEFVAL
+#undef DDR_PHY_ACBDLR2_BG0BD_SHIFT
+#undef DDR_PHY_ACBDLR2_BG0BD_MASK
+#define DDR_PHY_ACBDLR2_BG0BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR2_BG0BD_SHIFT 16
+#define DDR_PHY_ACBDLR2_BG0BD_MASK 0x003F0000U
+
+/*Reser.ved Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT
+#undef DDR_PHY_ACBDLR2_RESERVED_15_14_MASK
+#define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 14
+#define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 0x0000C000U
+
+/*Delay select for the BDL on BA[1].*/
+#undef DDR_PHY_ACBDLR2_BA1BD_DEFVAL
+#undef DDR_PHY_ACBDLR2_BA1BD_SHIFT
+#undef DDR_PHY_ACBDLR2_BA1BD_MASK
+#define DDR_PHY_ACBDLR2_BA1BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR2_BA1BD_SHIFT 8
+#define DDR_PHY_ACBDLR2_BA1BD_MASK 0x00003F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT
+#undef DDR_PHY_ACBDLR2_RESERVED_7_6_MASK
+#define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 6
+#define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 0x000000C0U
+
+/*Delay select for the BDL on BA[0].*/
+#undef DDR_PHY_ACBDLR2_BA0BD_DEFVAL
+#undef DDR_PHY_ACBDLR2_BA0BD_SHIFT
+#undef DDR_PHY_ACBDLR2_BA0BD_MASK
+#define DDR_PHY_ACBDLR2_BA0BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR2_BA0BD_SHIFT 0
+#define DDR_PHY_ACBDLR2_BA0BD_MASK 0x0000003FU
+
/*Reserved. Return zeroes on reads.*/
#undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL
#undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT
@@ -9412,6 +9304,70 @@
#define DDR_PHY_ACBDLR8_A08BD_SHIFT 0
#define DDR_PHY_ACBDLR8_A08BD_MASK 0x0000003FU
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT
+#undef DDR_PHY_ACBDLR9_RESERVED_31_30_MASK
+#define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 30
+#define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 0xC0000000U
+
+/*Delay select for the BDL on Address A[15].*/
+#undef DDR_PHY_ACBDLR9_A15BD_DEFVAL
+#undef DDR_PHY_ACBDLR9_A15BD_SHIFT
+#undef DDR_PHY_ACBDLR9_A15BD_MASK
+#define DDR_PHY_ACBDLR9_A15BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR9_A15BD_SHIFT 24
+#define DDR_PHY_ACBDLR9_A15BD_MASK 0x3F000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT
+#undef DDR_PHY_ACBDLR9_RESERVED_23_22_MASK
+#define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 22
+#define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 0x00C00000U
+
+/*Delay select for the BDL on Address A[14].*/
+#undef DDR_PHY_ACBDLR9_A14BD_DEFVAL
+#undef DDR_PHY_ACBDLR9_A14BD_SHIFT
+#undef DDR_PHY_ACBDLR9_A14BD_MASK
+#define DDR_PHY_ACBDLR9_A14BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR9_A14BD_SHIFT 16
+#define DDR_PHY_ACBDLR9_A14BD_MASK 0x003F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT
+#undef DDR_PHY_ACBDLR9_RESERVED_15_14_MASK
+#define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 14
+#define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 0x0000C000U
+
+/*Delay select for the BDL on Address A[13].*/
+#undef DDR_PHY_ACBDLR9_A13BD_DEFVAL
+#undef DDR_PHY_ACBDLR9_A13BD_SHIFT
+#undef DDR_PHY_ACBDLR9_A13BD_MASK
+#define DDR_PHY_ACBDLR9_A13BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR9_A13BD_SHIFT 8
+#define DDR_PHY_ACBDLR9_A13BD_MASK 0x00003F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT
+#undef DDR_PHY_ACBDLR9_RESERVED_7_6_MASK
+#define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 6
+#define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 0x000000C0U
+
+/*Delay select for the BDL on Address A[12].*/
+#undef DDR_PHY_ACBDLR9_A12BD_DEFVAL
+#undef DDR_PHY_ACBDLR9_A12BD_SHIFT
+#undef DDR_PHY_ACBDLR9_A12BD_MASK
+#define DDR_PHY_ACBDLR9_A12BD_DEFVAL 0x00000000
+#define DDR_PHY_ACBDLR9_A12BD_SHIFT 0
+#define DDR_PHY_ACBDLR9_A12BD_MASK 0x0000003FU
+
/*Reserved. Return zeroes on reads.*/
#undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL
#undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT
@@ -14452,6 +14408,158 @@
#define DDR_PHY_DX8GTR0_DGSL_SHIFT 0
#define DDR_PHY_DX8GTR0_DGSL_MASK 0x0000001FU
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK
+#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 30
+#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 0xC0000000U
+
+/*Enable Clock Gating for DX ddr_clk*/
+#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT
+#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK
+#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 28
+#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 0x30000000U
+
+/*Enable Clock Gating for DX ctl_rd_clk*/
+#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT
+#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK
+#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 26
+#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 0x0C000000U
+
+/*Enable Clock Gating for DX ctl_clk*/
+#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT
+#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK
+#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 24
+#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 0x03000000U
+
+/*Selects the level to which clocks will be stalled when clock gating is enabled.*/
+#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT
+#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK
+#define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 22
+#define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 0x00C00000U
+
+/*Loopback Mode*/
+#undef DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_LBMODE_SHIFT
+#undef DDR_PHY_DX8SL0OSC_LBMODE_MASK
+#define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 21
+#define DDR_PHY_DX8SL0OSC_LBMODE_MASK 0x00200000U
+
+/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
+#undef DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT
+#undef DDR_PHY_DX8SL0OSC_LBGSDQS_MASK
+#define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 20
+#define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 0x00100000U
+
+/*Loopback DQS Gating*/
+#undef DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT
+#undef DDR_PHY_DX8SL0OSC_LBGDQS_MASK
+#define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 18
+#define DDR_PHY_DX8SL0OSC_LBGDQS_MASK 0x000C0000U
+
+/*Loopback DQS Shift*/
+#undef DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT
+#undef DDR_PHY_DX8SL0OSC_LBDQSS_MASK
+#define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 17
+#define DDR_PHY_DX8SL0OSC_LBDQSS_MASK 0x00020000U
+
+/*PHY High-Speed Reset*/
+#undef DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT
+#undef DDR_PHY_DX8SL0OSC_PHYHRST_MASK
+#define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 16
+#define DDR_PHY_DX8SL0OSC_PHYHRST_MASK 0x00010000U
+
+/*PHY FIFO Reset*/
+#undef DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT
+#undef DDR_PHY_DX8SL0OSC_PHYFRST_MASK
+#define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 15
+#define DDR_PHY_DX8SL0OSC_PHYFRST_MASK 0x00008000U
+
+/*Delay Line Test Start*/
+#undef DDR_PHY_DX8SL0OSC_DLTST_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_DLTST_SHIFT
+#undef DDR_PHY_DX8SL0OSC_DLTST_MASK
+#define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_DLTST_SHIFT 14
+#define DDR_PHY_DX8SL0OSC_DLTST_MASK 0x00004000U
+
+/*Delay Line Test Mode*/
+#undef DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT
+#undef DDR_PHY_DX8SL0OSC_DLTMODE_MASK
+#define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 13
+#define DDR_PHY_DX8SL0OSC_DLTMODE_MASK 0x00002000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT
+#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK
+#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 11
+#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 0x00001800U
+
+/*Oscillator Mode Write-Data Delay Line Select*/
+#undef DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT
+#undef DDR_PHY_DX8SL0OSC_OSCWDDL_MASK
+#define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 9
+#define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 0x00000600U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT
+#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK
+#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 7
+#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 0x00000180U
+
+/*Oscillator Mode Write-Leveling Delay Line Select*/
+#undef DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT
+#undef DDR_PHY_DX8SL0OSC_OSCWDL_MASK
+#define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 5
+#define DDR_PHY_DX8SL0OSC_OSCWDL_MASK 0x00000060U
+
+/*Oscillator Mode Division*/
+#undef DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT
+#undef DDR_PHY_DX8SL0OSC_OSCDIV_MASK
+#define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 1
+#define DDR_PHY_DX8SL0OSC_OSCDIV_MASK 0x0000001EU
+
+/*Oscillator Enable*/
+#undef DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_OSCEN_SHIFT
+#undef DDR_PHY_DX8SL0OSC_OSCEN_MASK
+#define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 0
+#define DDR_PHY_DX8SL0OSC_OSCEN_MASK 0x00000001U
+
/*Reserved. Return zeroes on reads.*/
#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL
#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT
@@ -14740,6 +14848,158 @@
#define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 0
#define DDR_PHY_DX8SL0IOCR_DXRXM_MASK 0x000007FFU
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK
+#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 30
+#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 0xC0000000U
+
+/*Enable Clock Gating for DX ddr_clk*/
+#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT
+#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK
+#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 28
+#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 0x30000000U
+
+/*Enable Clock Gating for DX ctl_rd_clk*/
+#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT
+#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK
+#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 26
+#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 0x0C000000U
+
+/*Enable Clock Gating for DX ctl_clk*/
+#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT
+#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK
+#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 24
+#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 0x03000000U
+
+/*Selects the level to which clocks will be stalled when clock gating is enabled.*/
+#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT
+#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK
+#define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 22
+#define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 0x00C00000U
+
+/*Loopback Mode*/
+#undef DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_LBMODE_SHIFT
+#undef DDR_PHY_DX8SL1OSC_LBMODE_MASK
+#define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 21
+#define DDR_PHY_DX8SL1OSC_LBMODE_MASK 0x00200000U
+
+/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
+#undef DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT
+#undef DDR_PHY_DX8SL1OSC_LBGSDQS_MASK
+#define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 20
+#define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 0x00100000U
+
+/*Loopback DQS Gating*/
+#undef DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT
+#undef DDR_PHY_DX8SL1OSC_LBGDQS_MASK
+#define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 18
+#define DDR_PHY_DX8SL1OSC_LBGDQS_MASK 0x000C0000U
+
+/*Loopback DQS Shift*/
+#undef DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT
+#undef DDR_PHY_DX8SL1OSC_LBDQSS_MASK
+#define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 17
+#define DDR_PHY_DX8SL1OSC_LBDQSS_MASK 0x00020000U
+
+/*PHY High-Speed Reset*/
+#undef DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT
+#undef DDR_PHY_DX8SL1OSC_PHYHRST_MASK
+#define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 16
+#define DDR_PHY_DX8SL1OSC_PHYHRST_MASK 0x00010000U
+
+/*PHY FIFO Reset*/
+#undef DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT
+#undef DDR_PHY_DX8SL1OSC_PHYFRST_MASK
+#define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 15
+#define DDR_PHY_DX8SL1OSC_PHYFRST_MASK 0x00008000U
+
+/*Delay Line Test Start*/
+#undef DDR_PHY_DX8SL1OSC_DLTST_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_DLTST_SHIFT
+#undef DDR_PHY_DX8SL1OSC_DLTST_MASK
+#define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_DLTST_SHIFT 14
+#define DDR_PHY_DX8SL1OSC_DLTST_MASK 0x00004000U
+
+/*Delay Line Test Mode*/
+#undef DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT
+#undef DDR_PHY_DX8SL1OSC_DLTMODE_MASK
+#define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 13
+#define DDR_PHY_DX8SL1OSC_DLTMODE_MASK 0x00002000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT
+#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK
+#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 11
+#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 0x00001800U
+
+/*Oscillator Mode Write-Data Delay Line Select*/
+#undef DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT
+#undef DDR_PHY_DX8SL1OSC_OSCWDDL_MASK
+#define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 9
+#define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 0x00000600U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT
+#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK
+#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 7
+#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 0x00000180U
+
+/*Oscillator Mode Write-Leveling Delay Line Select*/
+#undef DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT
+#undef DDR_PHY_DX8SL1OSC_OSCWDL_MASK
+#define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 5
+#define DDR_PHY_DX8SL1OSC_OSCWDL_MASK 0x00000060U
+
+/*Oscillator Mode Division*/
+#undef DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT
+#undef DDR_PHY_DX8SL1OSC_OSCDIV_MASK
+#define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 1
+#define DDR_PHY_DX8SL1OSC_OSCDIV_MASK 0x0000001EU
+
+/*Oscillator Enable*/
+#undef DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_OSCEN_SHIFT
+#undef DDR_PHY_DX8SL1OSC_OSCEN_MASK
+#define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 0
+#define DDR_PHY_DX8SL1OSC_OSCEN_MASK 0x00000001U
+
/*Reserved. Return zeroes on reads.*/
#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL
#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT
@@ -15028,6 +15288,158 @@
#define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 0
#define DDR_PHY_DX8SL1IOCR_DXRXM_MASK 0x000007FFU
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK
+#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 30
+#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 0xC0000000U
+
+/*Enable Clock Gating for DX ddr_clk*/
+#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT
+#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK
+#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 28
+#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 0x30000000U
+
+/*Enable Clock Gating for DX ctl_rd_clk*/
+#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT
+#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK
+#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 26
+#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 0x0C000000U
+
+/*Enable Clock Gating for DX ctl_clk*/
+#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT
+#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK
+#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 24
+#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 0x03000000U
+
+/*Selects the level to which clocks will be stalled when clock gating is enabled.*/
+#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT
+#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK
+#define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 22
+#define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 0x00C00000U
+
+/*Loopback Mode*/
+#undef DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_LBMODE_SHIFT
+#undef DDR_PHY_DX8SL2OSC_LBMODE_MASK
+#define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 21
+#define DDR_PHY_DX8SL2OSC_LBMODE_MASK 0x00200000U
+
+/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
+#undef DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT
+#undef DDR_PHY_DX8SL2OSC_LBGSDQS_MASK
+#define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 20
+#define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 0x00100000U
+
+/*Loopback DQS Gating*/
+#undef DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT
+#undef DDR_PHY_DX8SL2OSC_LBGDQS_MASK
+#define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 18
+#define DDR_PHY_DX8SL2OSC_LBGDQS_MASK 0x000C0000U
+
+/*Loopback DQS Shift*/
+#undef DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT
+#undef DDR_PHY_DX8SL2OSC_LBDQSS_MASK
+#define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 17
+#define DDR_PHY_DX8SL2OSC_LBDQSS_MASK 0x00020000U
+
+/*PHY High-Speed Reset*/
+#undef DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT
+#undef DDR_PHY_DX8SL2OSC_PHYHRST_MASK
+#define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 16
+#define DDR_PHY_DX8SL2OSC_PHYHRST_MASK 0x00010000U
+
+/*PHY FIFO Reset*/
+#undef DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT
+#undef DDR_PHY_DX8SL2OSC_PHYFRST_MASK
+#define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 15
+#define DDR_PHY_DX8SL2OSC_PHYFRST_MASK 0x00008000U
+
+/*Delay Line Test Start*/
+#undef DDR_PHY_DX8SL2OSC_DLTST_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_DLTST_SHIFT
+#undef DDR_PHY_DX8SL2OSC_DLTST_MASK
+#define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_DLTST_SHIFT 14
+#define DDR_PHY_DX8SL2OSC_DLTST_MASK 0x00004000U
+
+/*Delay Line Test Mode*/
+#undef DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT
+#undef DDR_PHY_DX8SL2OSC_DLTMODE_MASK
+#define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 13
+#define DDR_PHY_DX8SL2OSC_DLTMODE_MASK 0x00002000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT
+#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK
+#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 11
+#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 0x00001800U
+
+/*Oscillator Mode Write-Data Delay Line Select*/
+#undef DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT
+#undef DDR_PHY_DX8SL2OSC_OSCWDDL_MASK
+#define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 9
+#define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 0x00000600U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT
+#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK
+#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 7
+#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 0x00000180U
+
+/*Oscillator Mode Write-Leveling Delay Line Select*/
+#undef DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT
+#undef DDR_PHY_DX8SL2OSC_OSCWDL_MASK
+#define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 5
+#define DDR_PHY_DX8SL2OSC_OSCWDL_MASK 0x00000060U
+
+/*Oscillator Mode Division*/
+#undef DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT
+#undef DDR_PHY_DX8SL2OSC_OSCDIV_MASK
+#define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 1
+#define DDR_PHY_DX8SL2OSC_OSCDIV_MASK 0x0000001EU
+
+/*Oscillator Enable*/
+#undef DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_OSCEN_SHIFT
+#undef DDR_PHY_DX8SL2OSC_OSCEN_MASK
+#define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 0
+#define DDR_PHY_DX8SL2OSC_OSCEN_MASK 0x00000001U
+
/*Reserved. Return zeroes on reads.*/
#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL
#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT
@@ -15316,6 +15728,158 @@
#define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 0
#define DDR_PHY_DX8SL2IOCR_DXRXM_MASK 0x000007FFU
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK
+#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 30
+#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 0xC0000000U
+
+/*Enable Clock Gating for DX ddr_clk*/
+#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT
+#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK
+#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 28
+#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 0x30000000U
+
+/*Enable Clock Gating for DX ctl_rd_clk*/
+#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT
+#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK
+#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 26
+#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 0x0C000000U
+
+/*Enable Clock Gating for DX ctl_clk*/
+#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT
+#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK
+#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 24
+#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 0x03000000U
+
+/*Selects the level to which clocks will be stalled when clock gating is enabled.*/
+#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT
+#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK
+#define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 22
+#define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 0x00C00000U
+
+/*Loopback Mode*/
+#undef DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_LBMODE_SHIFT
+#undef DDR_PHY_DX8SL3OSC_LBMODE_MASK
+#define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 21
+#define DDR_PHY_DX8SL3OSC_LBMODE_MASK 0x00200000U
+
+/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
+#undef DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT
+#undef DDR_PHY_DX8SL3OSC_LBGSDQS_MASK
+#define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 20
+#define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 0x00100000U
+
+/*Loopback DQS Gating*/
+#undef DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT
+#undef DDR_PHY_DX8SL3OSC_LBGDQS_MASK
+#define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 18
+#define DDR_PHY_DX8SL3OSC_LBGDQS_MASK 0x000C0000U
+
+/*Loopback DQS Shift*/
+#undef DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT
+#undef DDR_PHY_DX8SL3OSC_LBDQSS_MASK
+#define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 17
+#define DDR_PHY_DX8SL3OSC_LBDQSS_MASK 0x00020000U
+
+/*PHY High-Speed Reset*/
+#undef DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT
+#undef DDR_PHY_DX8SL3OSC_PHYHRST_MASK
+#define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 16
+#define DDR_PHY_DX8SL3OSC_PHYHRST_MASK 0x00010000U
+
+/*PHY FIFO Reset*/
+#undef DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT
+#undef DDR_PHY_DX8SL3OSC_PHYFRST_MASK
+#define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 15
+#define DDR_PHY_DX8SL3OSC_PHYFRST_MASK 0x00008000U
+
+/*Delay Line Test Start*/
+#undef DDR_PHY_DX8SL3OSC_DLTST_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_DLTST_SHIFT
+#undef DDR_PHY_DX8SL3OSC_DLTST_MASK
+#define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_DLTST_SHIFT 14
+#define DDR_PHY_DX8SL3OSC_DLTST_MASK 0x00004000U
+
+/*Delay Line Test Mode*/
+#undef DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT
+#undef DDR_PHY_DX8SL3OSC_DLTMODE_MASK
+#define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 13
+#define DDR_PHY_DX8SL3OSC_DLTMODE_MASK 0x00002000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT
+#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK
+#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 11
+#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 0x00001800U
+
+/*Oscillator Mode Write-Data Delay Line Select*/
+#undef DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT
+#undef DDR_PHY_DX8SL3OSC_OSCWDDL_MASK
+#define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 9
+#define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 0x00000600U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT
+#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK
+#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 7
+#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 0x00000180U
+
+/*Oscillator Mode Write-Leveling Delay Line Select*/
+#undef DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT
+#undef DDR_PHY_DX8SL3OSC_OSCWDL_MASK
+#define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 5
+#define DDR_PHY_DX8SL3OSC_OSCWDL_MASK 0x00000060U
+
+/*Oscillator Mode Division*/
+#undef DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT
+#undef DDR_PHY_DX8SL3OSC_OSCDIV_MASK
+#define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 1
+#define DDR_PHY_DX8SL3OSC_OSCDIV_MASK 0x0000001EU
+
+/*Oscillator Enable*/
+#undef DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_OSCEN_SHIFT
+#undef DDR_PHY_DX8SL3OSC_OSCEN_MASK
+#define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 0
+#define DDR_PHY_DX8SL3OSC_OSCEN_MASK 0x00000001U
+
/*Reserved. Return zeroes on reads.*/
#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL
#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT
@@ -15604,6 +16168,158 @@
#define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 0
#define DDR_PHY_DX8SL3IOCR_DXRXM_MASK 0x000007FFU
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK
+#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 30
+#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 0xC0000000U
+
+/*Enable Clock Gating for DX ddr_clk*/
+#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT
+#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK
+#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 28
+#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 0x30000000U
+
+/*Enable Clock Gating for DX ctl_rd_clk*/
+#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT
+#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK
+#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 26
+#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 0x0C000000U
+
+/*Enable Clock Gating for DX ctl_clk*/
+#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT
+#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK
+#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 24
+#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 0x03000000U
+
+/*Selects the level to which clocks will be stalled when clock gating is enabled.*/
+#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT
+#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK
+#define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 22
+#define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 0x00C00000U
+
+/*Loopback Mode*/
+#undef DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_LBMODE_SHIFT
+#undef DDR_PHY_DX8SL4OSC_LBMODE_MASK
+#define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 21
+#define DDR_PHY_DX8SL4OSC_LBMODE_MASK 0x00200000U
+
+/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
+#undef DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT
+#undef DDR_PHY_DX8SL4OSC_LBGSDQS_MASK
+#define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 20
+#define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 0x00100000U
+
+/*Loopback DQS Gating*/
+#undef DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT
+#undef DDR_PHY_DX8SL4OSC_LBGDQS_MASK
+#define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 18
+#define DDR_PHY_DX8SL4OSC_LBGDQS_MASK 0x000C0000U
+
+/*Loopback DQS Shift*/
+#undef DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT
+#undef DDR_PHY_DX8SL4OSC_LBDQSS_MASK
+#define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 17
+#define DDR_PHY_DX8SL4OSC_LBDQSS_MASK 0x00020000U
+
+/*PHY High-Speed Reset*/
+#undef DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT
+#undef DDR_PHY_DX8SL4OSC_PHYHRST_MASK
+#define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 16
+#define DDR_PHY_DX8SL4OSC_PHYHRST_MASK 0x00010000U
+
+/*PHY FIFO Reset*/
+#undef DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT
+#undef DDR_PHY_DX8SL4OSC_PHYFRST_MASK
+#define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 15
+#define DDR_PHY_DX8SL4OSC_PHYFRST_MASK 0x00008000U
+
+/*Delay Line Test Start*/
+#undef DDR_PHY_DX8SL4OSC_DLTST_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_DLTST_SHIFT
+#undef DDR_PHY_DX8SL4OSC_DLTST_MASK
+#define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_DLTST_SHIFT 14
+#define DDR_PHY_DX8SL4OSC_DLTST_MASK 0x00004000U
+
+/*Delay Line Test Mode*/
+#undef DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT
+#undef DDR_PHY_DX8SL4OSC_DLTMODE_MASK
+#define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 13
+#define DDR_PHY_DX8SL4OSC_DLTMODE_MASK 0x00002000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT
+#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK
+#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 11
+#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 0x00001800U
+
+/*Oscillator Mode Write-Data Delay Line Select*/
+#undef DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT
+#undef DDR_PHY_DX8SL4OSC_OSCWDDL_MASK
+#define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 9
+#define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 0x00000600U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT
+#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK
+#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 7
+#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 0x00000180U
+
+/*Oscillator Mode Write-Leveling Delay Line Select*/
+#undef DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT
+#undef DDR_PHY_DX8SL4OSC_OSCWDL_MASK
+#define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 5
+#define DDR_PHY_DX8SL4OSC_OSCWDL_MASK 0x00000060U
+
+/*Oscillator Mode Division*/
+#undef DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT
+#undef DDR_PHY_DX8SL4OSC_OSCDIV_MASK
+#define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 1
+#define DDR_PHY_DX8SL4OSC_OSCDIV_MASK 0x0000001EU
+
+/*Oscillator Enable*/
+#undef DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_OSCEN_SHIFT
+#undef DDR_PHY_DX8SL4OSC_OSCEN_MASK
+#define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 0x00019FFE
+#define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 0
+#define DDR_PHY_DX8SL4OSC_OSCEN_MASK 0x00000001U
+
/*Reserved. Return zeroes on reads.*/
#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL
#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT
@@ -22010,208 +22726,208 @@
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 12
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00001000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 13
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00002000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 14
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00004000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 15
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00008000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 16
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00010000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 17
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00020000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 18
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00040000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 19
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00080000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 20
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00100000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 21
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00200000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 22
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00400000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 23
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00800000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 24
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x01000000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 25
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x02000000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 0
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00000001U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 1
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00000002U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 2
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00000004U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 3
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00000008U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 4
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00000010U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 5
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00000020U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 6
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00000040U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 7
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00000080U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 8
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00000100U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 9
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00000200U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 10
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x00000400U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 11
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x00000800U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
@@ -23704,10 +24420,14 @@
#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 0x00000000
#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 0
#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 0x00000001U
+#undef CRL_APB_RST_LPD_IOU2_OFFSET
+#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
#undef CRL_APB_RST_LPD_IOU0_OFFSET
#define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230
#undef CRL_APB_RST_LPD_IOU2_OFFSET
#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
+#undef IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET
+#define IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET 0XFF180390
#undef CRL_APB_RST_LPD_TOP_OFFSET
#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
#undef CRF_APB_RST_FPD_TOP_OFFSET
@@ -23720,6 +24440,8 @@
#define IOU_SLCR_SD_CONFIG_REG2_OFFSET 0XFF180320
#undef IOU_SLCR_SD_CONFIG_REG1_OFFSET
#define IOU_SLCR_SD_CONFIG_REG1_OFFSET 0XFF18031C
+#undef IOU_SLCR_SD_CONFIG_REG3_OFFSET
+#define IOU_SLCR_SD_CONFIG_REG3_OFFSET 0XFF180324
#undef CRL_APB_RST_LPD_IOU2_OFFSET
#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
#undef CRL_APB_RST_LPD_IOU2_OFFSET
@@ -23754,6 +24476,18 @@
#define APU_ACE_CTRL_OFFSET 0XFD5C0060
#undef RTC_CONTROL_OFFSET
#define RTC_CONTROL_OFFSET 0XFFA60040
+#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET
+#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET 0XFF260020
+#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET
+#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET 0XFF260000
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK
+#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL 0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 20
+#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK 0x00100000U
/*GEM 3 reset*/
#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
@@ -23771,6 +24505,14 @@
#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0
#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U
+/*0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI*/
+#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL
+#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT
+#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK
+#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x00000007
+#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2
+#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U
+
/*USB 0 reset for control registers*/
#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
@@ -23940,6 +24682,16 @@
#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 23
#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 0x7F800000U
+/*This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf
+ rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon
+ s Fh - Ch = Reserved*/
+#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL
+#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT
+#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK
+#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL 0x06070607
+#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT 22
+#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK 0x03C00000U
+
/*Block level reset*/
#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL
#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT
@@ -24430,6 +25182,80 @@
#define RTC_CONTROL_BATTERY_DISABLE_DEFVAL 0x01000000
#define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31
#define RTC_CONTROL_BATTERY_DISABLE_MASK 0x80000000U
+
+/*Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz.*/
+#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL
+#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT
+#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK
+#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL
+#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT 0
+#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK 0xFFFFFFFFU
+
+/*Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing.*/
+#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL
+#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT
+#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK
+#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL 0x00000000
+#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT 0
+#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK 0x00000001U
+#undef LPD_XPPU_CFG_IEN_OFFSET
+#define LPD_XPPU_CFG_IEN_OFFSET 0XFF980018
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT
+#undef LPD_XPPU_CFG_IEN_APER_PARITY_MASK
+#define LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT 7
+#define LPD_XPPU_CFG_IEN_APER_PARITY_MASK 0x00000080U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL
+#undef LPD_XPPU_CFG_IEN_APER_TZ_SHIFT
+#undef LPD_XPPU_CFG_IEN_APER_TZ_MASK
+#define LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_APER_TZ_SHIFT 6
+#define LPD_XPPU_CFG_IEN_APER_TZ_MASK 0x00000040U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL
+#undef LPD_XPPU_CFG_IEN_APER_PERM_SHIFT
+#undef LPD_XPPU_CFG_IEN_APER_PERM_MASK
+#define LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_APER_PERM_SHIFT 5
+#define LPD_XPPU_CFG_IEN_APER_PERM_MASK 0x00000020U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT
+#undef LPD_XPPU_CFG_IEN_MID_PARITY_MASK
+#define LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT 3
+#define LPD_XPPU_CFG_IEN_MID_PARITY_MASK 0x00000008U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_MID_RO_DEFVAL
+#undef LPD_XPPU_CFG_IEN_MID_RO_SHIFT
+#undef LPD_XPPU_CFG_IEN_MID_RO_MASK
+#define LPD_XPPU_CFG_IEN_MID_RO_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_MID_RO_SHIFT 2
+#define LPD_XPPU_CFG_IEN_MID_RO_MASK 0x00000004U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL
+#undef LPD_XPPU_CFG_IEN_MID_MISS_SHIFT
+#undef LPD_XPPU_CFG_IEN_MID_MISS_MASK
+#define LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_MID_MISS_SHIFT 1
+#define LPD_XPPU_CFG_IEN_MID_MISS_MASK 0x00000002U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_INV_APB_DEFVAL
+#undef LPD_XPPU_CFG_IEN_INV_APB_SHIFT
+#undef LPD_XPPU_CFG_IEN_INV_APB_MASK
+#define LPD_XPPU_CFG_IEN_INV_APB_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_INV_APB_SHIFT 0
+#define LPD_XPPU_CFG_IEN_INV_APB_MASK 0x00000001U
#undef SERDES_PLL_REF_SEL0_OFFSET
#define SERDES_PLL_REF_SEL0_OFFSET 0XFD410000
#undef SERDES_PLL_REF_SEL1_OFFSET
@@ -24496,6 +25322,126 @@
#define SERDES_L3_TX_DIG_TM_61_OFFSET 0XFD40C0F4
#undef SERDES_L3_TXPMA_ST_0_OFFSET
#define SERDES_L3_TXPMA_ST_0_OFFSET 0XFD40CB00
+#undef SERDES_L0_TM_AUX_0_OFFSET
+#define SERDES_L0_TM_AUX_0_OFFSET 0XFD4010CC
+#undef SERDES_L2_TM_AUX_0_OFFSET
+#define SERDES_L2_TM_AUX_0_OFFSET 0XFD4090CC
+#undef SERDES_L0_TM_DIG_8_OFFSET
+#define SERDES_L0_TM_DIG_8_OFFSET 0XFD401074
+#undef SERDES_L1_TM_DIG_8_OFFSET
+#define SERDES_L1_TM_DIG_8_OFFSET 0XFD405074
+#undef SERDES_L2_TM_DIG_8_OFFSET
+#define SERDES_L2_TM_DIG_8_OFFSET 0XFD409074
+#undef SERDES_L3_TM_DIG_8_OFFSET
+#define SERDES_L3_TM_DIG_8_OFFSET 0XFD40D074
+#undef SERDES_L0_TM_MISC2_OFFSET
+#define SERDES_L0_TM_MISC2_OFFSET 0XFD40189C
+#undef SERDES_L0_TM_IQ_ILL1_OFFSET
+#define SERDES_L0_TM_IQ_ILL1_OFFSET 0XFD4018F8
+#undef SERDES_L0_TM_IQ_ILL2_OFFSET
+#define SERDES_L0_TM_IQ_ILL2_OFFSET 0XFD4018FC
+#undef SERDES_L0_TM_ILL12_OFFSET
+#define SERDES_L0_TM_ILL12_OFFSET 0XFD401990
+#undef SERDES_L0_TM_E_ILL1_OFFSET
+#define SERDES_L0_TM_E_ILL1_OFFSET 0XFD401924
+#undef SERDES_L0_TM_E_ILL2_OFFSET
+#define SERDES_L0_TM_E_ILL2_OFFSET 0XFD401928
+#undef SERDES_L0_TM_IQ_ILL3_OFFSET
+#define SERDES_L0_TM_IQ_ILL3_OFFSET 0XFD401900
+#undef SERDES_L0_TM_E_ILL3_OFFSET
+#define SERDES_L0_TM_E_ILL3_OFFSET 0XFD40192C
+#undef SERDES_L0_TM_ILL8_OFFSET
+#define SERDES_L0_TM_ILL8_OFFSET 0XFD401980
+#undef SERDES_L0_TM_IQ_ILL8_OFFSET
+#define SERDES_L0_TM_IQ_ILL8_OFFSET 0XFD401914
+#undef SERDES_L0_TM_IQ_ILL9_OFFSET
+#define SERDES_L0_TM_IQ_ILL9_OFFSET 0XFD401918
+#undef SERDES_L0_TM_E_ILL8_OFFSET
+#define SERDES_L0_TM_E_ILL8_OFFSET 0XFD401940
+#undef SERDES_L0_TM_E_ILL9_OFFSET
+#define SERDES_L0_TM_E_ILL9_OFFSET 0XFD401944
+#undef SERDES_L2_TM_MISC2_OFFSET
+#define SERDES_L2_TM_MISC2_OFFSET 0XFD40989C
+#undef SERDES_L2_TM_IQ_ILL1_OFFSET
+#define SERDES_L2_TM_IQ_ILL1_OFFSET 0XFD4098F8
+#undef SERDES_L2_TM_IQ_ILL2_OFFSET
+#define SERDES_L2_TM_IQ_ILL2_OFFSET 0XFD4098FC
+#undef SERDES_L2_TM_ILL12_OFFSET
+#define SERDES_L2_TM_ILL12_OFFSET 0XFD409990
+#undef SERDES_L2_TM_E_ILL1_OFFSET
+#define SERDES_L2_TM_E_ILL1_OFFSET 0XFD409924
+#undef SERDES_L2_TM_E_ILL2_OFFSET
+#define SERDES_L2_TM_E_ILL2_OFFSET 0XFD409928
+#undef SERDES_L2_TM_IQ_ILL3_OFFSET
+#define SERDES_L2_TM_IQ_ILL3_OFFSET 0XFD409900
+#undef SERDES_L2_TM_E_ILL3_OFFSET
+#define SERDES_L2_TM_E_ILL3_OFFSET 0XFD40992C
+#undef SERDES_L2_TM_ILL8_OFFSET
+#define SERDES_L2_TM_ILL8_OFFSET 0XFD409980
+#undef SERDES_L2_TM_IQ_ILL8_OFFSET
+#define SERDES_L2_TM_IQ_ILL8_OFFSET 0XFD409914
+#undef SERDES_L2_TM_IQ_ILL9_OFFSET
+#define SERDES_L2_TM_IQ_ILL9_OFFSET 0XFD409918
+#undef SERDES_L2_TM_E_ILL8_OFFSET
+#define SERDES_L2_TM_E_ILL8_OFFSET 0XFD409940
+#undef SERDES_L2_TM_E_ILL9_OFFSET
+#define SERDES_L2_TM_E_ILL9_OFFSET 0XFD409944
+#undef SERDES_L3_TM_MISC2_OFFSET
+#define SERDES_L3_TM_MISC2_OFFSET 0XFD40D89C
+#undef SERDES_L3_TM_IQ_ILL1_OFFSET
+#define SERDES_L3_TM_IQ_ILL1_OFFSET 0XFD40D8F8
+#undef SERDES_L3_TM_IQ_ILL2_OFFSET
+#define SERDES_L3_TM_IQ_ILL2_OFFSET 0XFD40D8FC
+#undef SERDES_L3_TM_ILL12_OFFSET
+#define SERDES_L3_TM_ILL12_OFFSET 0XFD40D990
+#undef SERDES_L3_TM_E_ILL1_OFFSET
+#define SERDES_L3_TM_E_ILL1_OFFSET 0XFD40D924
+#undef SERDES_L3_TM_E_ILL2_OFFSET
+#define SERDES_L3_TM_E_ILL2_OFFSET 0XFD40D928
+#undef SERDES_L3_TM_ILL11_OFFSET
+#define SERDES_L3_TM_ILL11_OFFSET 0XFD40D98C
+#undef SERDES_L3_TM_IQ_ILL3_OFFSET
+#define SERDES_L3_TM_IQ_ILL3_OFFSET 0XFD40D900
+#undef SERDES_L3_TM_E_ILL3_OFFSET
+#define SERDES_L3_TM_E_ILL3_OFFSET 0XFD40D92C
+#undef SERDES_L3_TM_ILL8_OFFSET
+#define SERDES_L3_TM_ILL8_OFFSET 0XFD40D980
+#undef SERDES_L3_TM_IQ_ILL8_OFFSET
+#define SERDES_L3_TM_IQ_ILL8_OFFSET 0XFD40D914
+#undef SERDES_L3_TM_IQ_ILL9_OFFSET
+#define SERDES_L3_TM_IQ_ILL9_OFFSET 0XFD40D918
+#undef SERDES_L3_TM_E_ILL8_OFFSET
+#define SERDES_L3_TM_E_ILL8_OFFSET 0XFD40D940
+#undef SERDES_L3_TM_E_ILL9_OFFSET
+#define SERDES_L3_TM_E_ILL9_OFFSET 0XFD40D944
+#undef SERDES_L0_TM_DIG_21_OFFSET
+#define SERDES_L0_TM_DIG_21_OFFSET 0XFD4010A8
+#undef SERDES_L0_TM_DIG_10_OFFSET
+#define SERDES_L0_TM_DIG_10_OFFSET 0XFD40107C
+#undef SERDES_L0_TM_RST_DLY_OFFSET
+#define SERDES_L0_TM_RST_DLY_OFFSET 0XFD4019A4
+#undef SERDES_L0_TM_ANA_BYP_15_OFFSET
+#define SERDES_L0_TM_ANA_BYP_15_OFFSET 0XFD401038
+#undef SERDES_L0_TM_ANA_BYP_12_OFFSET
+#define SERDES_L0_TM_ANA_BYP_12_OFFSET 0XFD40102C
+#undef SERDES_L1_TM_RST_DLY_OFFSET
+#define SERDES_L1_TM_RST_DLY_OFFSET 0XFD4059A4
+#undef SERDES_L1_TM_ANA_BYP_15_OFFSET
+#define SERDES_L1_TM_ANA_BYP_15_OFFSET 0XFD405038
+#undef SERDES_L1_TM_ANA_BYP_12_OFFSET
+#define SERDES_L1_TM_ANA_BYP_12_OFFSET 0XFD40502C
+#undef SERDES_L2_TM_RST_DLY_OFFSET
+#define SERDES_L2_TM_RST_DLY_OFFSET 0XFD4099A4
+#undef SERDES_L2_TM_ANA_BYP_15_OFFSET
+#define SERDES_L2_TM_ANA_BYP_15_OFFSET 0XFD409038
+#undef SERDES_L2_TM_ANA_BYP_12_OFFSET
+#define SERDES_L2_TM_ANA_BYP_12_OFFSET 0XFD40902C
+#undef SERDES_L3_TM_RST_DLY_OFFSET
+#define SERDES_L3_TM_RST_DLY_OFFSET 0XFD40D9A4
+#undef SERDES_L3_TM_ANA_BYP_15_OFFSET
+#define SERDES_L3_TM_ANA_BYP_15_OFFSET 0XFD40D038
+#undef SERDES_L3_TM_ANA_BYP_12_OFFSET
+#define SERDES_L3_TM_ANA_BYP_12_OFFSET 0XFD40D02C
#undef SERDES_ICM_CFG0_OFFSET
#define SERDES_ICM_CFG0_OFFSET 0XFD410010
#undef SERDES_ICM_CFG1_OFFSET
@@ -24504,10 +25450,22 @@
#define SERDES_L1_TXPMD_TM_45_OFFSET 0XFD404CB4
#undef SERDES_L1_TX_ANA_TM_118_OFFSET
#define SERDES_L1_TX_ANA_TM_118_OFFSET 0XFD4041D8
+#undef SERDES_L3_TX_ANA_TM_118_OFFSET
+#define SERDES_L3_TX_ANA_TM_118_OFFSET 0XFD40C1D8
+#undef SERDES_L3_TM_CDR5_OFFSET
+#define SERDES_L3_TM_CDR5_OFFSET 0XFD40DC14
+#undef SERDES_L3_TM_CDR16_OFFSET
+#define SERDES_L3_TM_CDR16_OFFSET 0XFD40DC40
+#undef SERDES_L3_TM_EQ0_OFFSET
+#define SERDES_L3_TM_EQ0_OFFSET 0XFD40D94C
+#undef SERDES_L3_TM_EQ1_OFFSET
+#define SERDES_L3_TM_EQ1_OFFSET 0XFD40D950
#undef SERDES_L1_TXPMD_TM_48_OFFSET
#define SERDES_L1_TXPMD_TM_48_OFFSET 0XFD404CC0
#undef SERDES_L1_TX_ANA_TM_18_OFFSET
#define SERDES_L1_TX_ANA_TM_18_OFFSET 0XFD404048
+#undef SERDES_L3_TX_ANA_TM_18_OFFSET
+#define SERDES_L3_TX_ANA_TM_18_OFFSET 0XFD40C048
/*PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
@@ -24909,6 +25867,486 @@
#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT 4
#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK 0x000000F0U
+/*Spare- not used*/
+#undef SERDES_L0_TM_AUX_0_BIT_2_DEFVAL
+#undef SERDES_L0_TM_AUX_0_BIT_2_SHIFT
+#undef SERDES_L0_TM_AUX_0_BIT_2_MASK
+#define SERDES_L0_TM_AUX_0_BIT_2_DEFVAL 0x00000000
+#define SERDES_L0_TM_AUX_0_BIT_2_SHIFT 5
+#define SERDES_L0_TM_AUX_0_BIT_2_MASK 0x00000020U
+
+/*Spare- not used*/
+#undef SERDES_L2_TM_AUX_0_BIT_2_DEFVAL
+#undef SERDES_L2_TM_AUX_0_BIT_2_SHIFT
+#undef SERDES_L2_TM_AUX_0_BIT_2_MASK
+#define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL 0x00000000
+#define SERDES_L2_TM_AUX_0_BIT_2_SHIFT 5
+#define SERDES_L2_TM_AUX_0_BIT_2_MASK 0x00000020U
+
+/*Enable Eye Surf*/
+#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL
+#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT
+#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK
+#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000
+#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
+#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
+
+/*Enable Eye Surf*/
+#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL
+#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT
+#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK
+#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000
+#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
+#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
+
+/*Enable Eye Surf*/
+#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL
+#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT
+#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK
+#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000
+#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
+#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
+
+/*Enable Eye Surf*/
+#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL
+#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT
+#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK
+#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000
+#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
+#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
+
+/*ILL calib counts BYPASSED with calcode bits*/
+#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
+#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
+#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000
+#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7
+#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U
+
+/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
+#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
+#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
+#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
+#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000
+#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0
+#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU
+
+/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
+#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
+#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
+#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
+#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000
+#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0
+#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU
+
+/*G1A pll ctr bypass value*/
+#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
+#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
+#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
+#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000
+#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0
+#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU
+
+/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
+#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
+#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
+#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000
+#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0
+#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU
+
+/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
+#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
+#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
+#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000
+#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0
+#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU
+
+/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
+#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
+#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
+#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
+#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000
+#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0
+#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU
+
+/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
+#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
+#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
+#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000
+#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0
+#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU
+
+/*ILL calibration code change wait time*/
+#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
+#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
+#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002
+#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0
+#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU
+
+/*IQ ILL polytrim bypass value*/
+#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
+#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
+#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000
+#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0
+#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU
+
+/*bypass IQ polytrim*/
+#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
+#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
+#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000
+#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0
+#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U
+
+/*E ILL polytrim bypass value*/
+#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
+#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000
+#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0
+#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU
+
+/*bypass E polytrim*/
+#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
+#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
+#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000
+#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0
+#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U
+
+/*ILL calib counts BYPASSED with calcode bits*/
+#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
+#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
+#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000
+#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7
+#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U
+
+/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
+#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
+#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
+#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
+#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000
+#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0
+#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU
+
+/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
+#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
+#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
+#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
+#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000
+#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0
+#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU
+
+/*G1A pll ctr bypass value*/
+#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
+#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
+#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
+#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000
+#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0
+#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU
+
+/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
+#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
+#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
+#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000
+#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0
+#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU
+
+/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
+#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
+#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
+#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000
+#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0
+#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU
+
+/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
+#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
+#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
+#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
+#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000
+#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0
+#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU
+
+/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
+#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
+#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
+#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000
+#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0
+#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU
+
+/*ILL calibration code change wait time*/
+#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
+#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
+#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002
+#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0
+#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU
+
+/*IQ ILL polytrim bypass value*/
+#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
+#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
+#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000
+#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0
+#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU
+
+/*bypass IQ polytrim*/
+#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
+#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
+#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000
+#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0
+#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U
+
+/*E ILL polytrim bypass value*/
+#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
+#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000
+#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0
+#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU
+
+/*bypass E polytrim*/
+#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
+#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
+#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000
+#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0
+#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U
+
+/*ILL calib counts BYPASSED with calcode bits*/
+#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
+#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
+#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000
+#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7
+#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U
+
+/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
+#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
+#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
+#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
+#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000
+#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0
+#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU
+
+/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
+#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
+#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
+#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
+#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000
+#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0
+#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU
+
+/*G1A pll ctr bypass value*/
+#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
+#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
+#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
+#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000
+#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0
+#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU
+
+/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
+#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
+#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
+#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000
+#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0
+#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU
+
+/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
+#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
+#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
+#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000
+#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0
+#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU
+
+/*G2A_PCIe1 PLL ctr bypass value*/
+#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL
+#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT
+#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK
+#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL 0x00000000
+#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT 4
+#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK 0x000000F0U
+
+/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
+#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
+#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
+#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
+#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000
+#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0
+#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU
+
+/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
+#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
+#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
+#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000
+#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0
+#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU
+
+/*ILL calibration code change wait time*/
+#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
+#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
+#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002
+#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0
+#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU
+
+/*IQ ILL polytrim bypass value*/
+#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
+#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
+#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000
+#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0
+#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU
+
+/*bypass IQ polytrim*/
+#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
+#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
+#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000
+#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0
+#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U
+
+/*E ILL polytrim bypass value*/
+#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
+#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000
+#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0
+#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU
+
+/*bypass E polytrim*/
+#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
+#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
+#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000
+#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0
+#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U
+
+/*pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20*/
+#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL
+#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT
+#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK
+#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL 0x00000000
+#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT 0
+#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK 0x00000003U
+
+/*CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001*/
+#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL
+#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
+#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK
+#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001
+#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0
+#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU
+
+/*Delay apb reset by specified amount*/
+#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL
+#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT
+#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK
+#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
+#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 0
+#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_15*/
+#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
+#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
+#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
+#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
+#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_12*/
+#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
+#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
+#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
+#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
+#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
+
+/*Delay apb reset by specified amount*/
+#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL
+#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT
+#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK
+#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
+#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 0
+#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_15*/
+#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
+#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
+#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
+#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
+#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_12*/
+#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
+#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
+#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
+#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
+#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
+
+/*Delay apb reset by specified amount*/
+#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL
+#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT
+#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK
+#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
+#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 0
+#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_15*/
+#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
+#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
+#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
+#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
+#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_12*/
+#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
+#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
+#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
+#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
+#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
+
+/*Delay apb reset by specified amount*/
+#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL
+#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT
+#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK
+#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
+#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 0
+#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_15*/
+#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
+#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
+#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
+#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
+#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_12*/
+#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
+#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
+#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
+#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
+#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
+
/*Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
, 7 - Unused*/
#undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL
@@ -24993,6 +26431,62 @@
#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0
#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U
+/*Test register force for enabling/disablign TX deemphasis bits <17:0>*/
+#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL
+#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
+#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK
+#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000
+#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0
+#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U
+
+/*FPHL FSM accumulate cycles*/
+#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL
+#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT
+#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK
+#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL 0x00000000
+#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT 5
+#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK 0x000000E0U
+
+/*FFL Phase0 int gain aka 2ol SD update rate*/
+#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL
+#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT
+#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK
+#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL 0x00000000
+#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT 0
+#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK 0x0000001FU
+
+/*FFL Phase0 prop gain aka 1ol SD update rate*/
+#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL
+#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT
+#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK
+#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL 0x00000000
+#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT 0
+#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK 0x0000001FU
+
+/*EQ stg 2 controls BYPASSED*/
+#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL
+#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT
+#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK
+#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL 0x00000000
+#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT 5
+#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK 0x00000020U
+
+/*EQ STG2 RL PROG*/
+#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL
+#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT
+#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK
+#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL 0x00000000
+#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT 0
+#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK 0x00000003U
+
+/*EQ stg 2 preamp mode val*/
+#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL
+#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT
+#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK
+#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL 0x00000000
+#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT 2
+#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK 0x00000004U
+
/*Margining factor value*/
#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL
#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
@@ -25008,10 +26502,20 @@
#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002
#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0
#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU
+
+/*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/
+#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL
+#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
+#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK
+#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002
+#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0
+#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU
#undef CRL_APB_RST_LPD_TOP_OFFSET
#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
#undef USB3_0_FPD_POWER_PRSNT_OFFSET
#define USB3_0_FPD_POWER_PRSNT_OFFSET 0XFF9D0080
+#undef USB3_0_FPD_PIPE_CLK_OFFSET
+#define USB3_0_FPD_PIPE_CLK_OFFSET 0XFF9D007C
#undef CRL_APB_RST_LPD_TOP_OFFSET
#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
#undef CRL_APB_RST_LPD_IOU0_OFFSET
@@ -25032,8 +26536,6 @@
#define USB3_0_XHCI_GUSB2PHYCFG_OFFSET 0XFE20C200
#undef USB3_0_XHCI_GFLADJ_OFFSET
#define USB3_0_XHCI_GFLADJ_OFFSET 0XFE20C630
-#undef PCIE_ATTRIB_ATTR_37_OFFSET
-#define PCIE_ATTRIB_ATTR_37_OFFSET 0XFD480094
#undef PCIE_ATTRIB_ATTR_25_OFFSET
#define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064
#undef PCIE_ATTRIB_ATTR_7_OFFSET
@@ -25108,6 +26610,30 @@
#define PCIE_ATTRIB_ATTR_79_OFFSET 0XFD48013C
#undef PCIE_ATTRIB_ATTR_43_OFFSET
#define PCIE_ATTRIB_ATTR_43_OFFSET 0XFD4800AC
+#undef PCIE_ATTRIB_ATTR_48_OFFSET
+#define PCIE_ATTRIB_ATTR_48_OFFSET 0XFD4800C0
+#undef PCIE_ATTRIB_ATTR_46_OFFSET
+#define PCIE_ATTRIB_ATTR_46_OFFSET 0XFD4800B8
+#undef PCIE_ATTRIB_ATTR_47_OFFSET
+#define PCIE_ATTRIB_ATTR_47_OFFSET 0XFD4800BC
+#undef PCIE_ATTRIB_ATTR_44_OFFSET
+#define PCIE_ATTRIB_ATTR_44_OFFSET 0XFD4800B0
+#undef PCIE_ATTRIB_ATTR_45_OFFSET
+#define PCIE_ATTRIB_ATTR_45_OFFSET 0XFD4800B4
+#undef PCIE_ATTRIB_CB_OFFSET
+#define PCIE_ATTRIB_CB_OFFSET 0XFD48031C
+#undef PCIE_ATTRIB_ATTR_35_OFFSET
+#define PCIE_ATTRIB_ATTR_35_OFFSET 0XFD48008C
+#undef CRF_APB_RST_FPD_TOP_OFFSET
+#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
+#undef SATA_AHCI_VENDOR_PP2C_OFFSET
+#define SATA_AHCI_VENDOR_PP2C_OFFSET 0XFD0C00AC
+#undef SATA_AHCI_VENDOR_PP3C_OFFSET
+#define SATA_AHCI_VENDOR_PP3C_OFFSET 0XFD0C00B0
+#undef SATA_AHCI_VENDOR_PP4C_OFFSET
+#define SATA_AHCI_VENDOR_PP4C_OFFSET 0XFD0C00B4
+#undef SATA_AHCI_VENDOR_PP5C_OFFSET
+#define SATA_AHCI_VENDOR_PP5C_OFFSET 0XFD0C00B8
/*USB 0 reset for control registers*/
#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
@@ -25125,6 +26651,14 @@
#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 0
#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U
+/*This bit is used to choose between PIPE clock coming from SerDes and the suspend clk*/
+#undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL
+#undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT
+#undef USB3_0_FPD_PIPE_CLK_OPTION_MASK
+#define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL
+#define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 0
+#define USB3_0_FPD_PIPE_CLK_OPTION_MASK 0x00000001U
+
/*USB 0 sleep circuit reset*/
#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
@@ -25173,14 +26707,6 @@
#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19
#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U
-/*PCIE control block level reset*/
-#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL
-#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
-#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK
-#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE
-#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17
-#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U
-
/*PCIE bridge block level reset (AXI interface)*/
#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL
#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
@@ -25266,20 +26792,6 @@
#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7
#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U
-/*Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
- figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
- ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
- r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
- t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
- g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
- when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.*/
-#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL
-#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT
-#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK
-#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 0x00000000
-#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 6
-#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 0x00000040U
-
/*Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
@@ -25345,51 +26857,6 @@
#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8
#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U
-/*Status Read value of PLL Lock*/
-#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
-#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
-#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
-#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
-#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
-#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
-#define SERDES_L0_PLL_STATUS_READ_1_OFFSET 0XFD4023E4
-
-/*Status Read value of PLL Lock*/
-#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
-#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
-#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
-#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
-#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
-#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
-#define SERDES_L1_PLL_STATUS_READ_1_OFFSET 0XFD4063E4
-
-/*Status Read value of PLL Lock*/
-#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
-#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
-#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
-#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
-#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
-#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
-#define SERDES_L2_PLL_STATUS_READ_1_OFFSET 0XFD40A3E4
-
-/*Status Read value of PLL Lock*/
-#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
-#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
-#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
-#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
-#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
-#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
-#define SERDES_L3_PLL_STATUS_READ_1_OFFSET 0XFD40E3E4
-
-/*Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
- gister.; EP=0x0001; RP=0x0001*/
-#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL
-#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
-#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK
-#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF
-#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14
-#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U
-
/*If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001*/
#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL
@@ -25815,6 +27282,15 @@
#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 9
#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 0x00000200U
+/*Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
+ gister.; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U
+
/*Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L
_REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000*/
#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL
@@ -25945,6 +27421,229 @@
#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 0x00000100
#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 8
#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 0x00000100U
+
+/*MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note
+ hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL
+#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT
+#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK
+#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL
+#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT 0
+#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK 0x000007FFU
+
+/*MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001;
+ P=0x0000*/
+#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
+#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
+#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK
+#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
+#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0
+#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x0000FFFFU
+
+/*MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000;
+ P=0x0000*/
+#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
+#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
+#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK
+#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
+#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0
+#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x00001FFFU
+
+/*MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
+ 0x0001; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL
+#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
+#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK
+#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL
+#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 0
+#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFFFU
+
+/*MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
+ 0x1000; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL
+#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
+#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK
+#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 0x00008000
+#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 3
+#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFF8U
+
+/*DT837748 Enable*/
+#undef PCIE_ATTRIB_CB_CB1_DEFVAL
+#undef PCIE_ATTRIB_CB_CB1_SHIFT
+#undef PCIE_ATTRIB_CB_CB1_MASK
+#define PCIE_ATTRIB_CB_CB1_DEFVAL 0x00000001
+#define PCIE_ATTRIB_CB_CB1_SHIFT 1
+#define PCIE_ATTRIB_CB_CB1_MASK 0x00000002U
+
+/*Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc
+ ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL
+#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT
+#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK
+#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 0x00001FFD
+#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 12
+#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 0x00003000U
+
+/*PCIE control block level reset*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U
+
+/*Status Read value of PLL Lock*/
+#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
+#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
+#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
+#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
+#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
+#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
+#define SERDES_L0_PLL_STATUS_READ_1_OFFSET 0XFD4023E4
+
+/*Status Read value of PLL Lock*/
+#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
+#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
+#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
+#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
+#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
+#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
+#define SERDES_L1_PLL_STATUS_READ_1_OFFSET 0XFD4063E4
+
+/*Status Read value of PLL Lock*/
+#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
+#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
+#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
+#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
+#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
+#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
+#define SERDES_L2_PLL_STATUS_READ_1_OFFSET 0XFD40A3E4
+
+/*Status Read value of PLL Lock*/
+#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
+#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
+#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
+#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
+#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
+#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
+#define SERDES_L3_PLL_STATUS_READ_1_OFFSET 0XFD40E3E4
+
+/*CIBGMN: COMINIT Burst Gap Minimum.*/
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK
+#define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL 0x28184D1B
+#define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT 0
+#define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK 0x000000FFU
+
+/*CIBGMX: COMINIT Burst Gap Maximum.*/
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK
+#define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL 0x28184D1B
+#define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT 8
+#define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK 0x0000FF00U
+
+/*CIBGN: COMINIT Burst Gap Nominal.*/
+#undef SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL
+#undef SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT
+#undef SATA_AHCI_VENDOR_PP2C_CIBGN_MASK
+#define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL 0x28184D1B
+#define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT 16
+#define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK 0x00FF0000U
+
+/*CINMP: COMINIT Negate Minimum Period.*/
+#undef SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL
+#undef SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT
+#undef SATA_AHCI_VENDOR_PP2C_CINMP_MASK
+#define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL 0x28184D1B
+#define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT 24
+#define SATA_AHCI_VENDOR_PP2C_CINMP_MASK 0xFF000000U
+
+/*CWBGMN: COMWAKE Burst Gap Minimum.*/
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK
+#define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL 0x0E081906
+#define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT 0
+#define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK 0x000000FFU
+
+/*CWBGMX: COMWAKE Burst Gap Maximum.*/
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK
+#define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL 0x0E081906
+#define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT 8
+#define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK 0x0000FF00U
+
+/*CWBGN: COMWAKE Burst Gap Nominal.*/
+#undef SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL
+#undef SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT
+#undef SATA_AHCI_VENDOR_PP3C_CWBGN_MASK
+#define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL 0x0E081906
+#define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT 16
+#define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK 0x00FF0000U
+
+/*CWNMP: COMWAKE Negate Minimum Period.*/
+#undef SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL
+#undef SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT
+#undef SATA_AHCI_VENDOR_PP3C_CWNMP_MASK
+#define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL 0x0E081906
+#define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT 24
+#define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK 0xFF000000U
+
+/*BMX: COM Burst Maximum.*/
+#undef SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL
+#undef SATA_AHCI_VENDOR_PP4C_BMX_SHIFT
+#undef SATA_AHCI_VENDOR_PP4C_BMX_MASK
+#define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL 0x064A0813
+#define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT 0
+#define SATA_AHCI_VENDOR_PP4C_BMX_MASK 0x000000FFU
+
+/*BNM: COM Burst Nominal.*/
+#undef SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL
+#undef SATA_AHCI_VENDOR_PP4C_BNM_SHIFT
+#undef SATA_AHCI_VENDOR_PP4C_BNM_MASK
+#define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL 0x064A0813
+#define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT 8
+#define SATA_AHCI_VENDOR_PP4C_BNM_MASK 0x0000FF00U
+
+/*SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det
+ rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa
+ Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of
+ 500ns based on a 150MHz PMCLK.*/
+#undef SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL
+#undef SATA_AHCI_VENDOR_PP4C_SFD_SHIFT
+#undef SATA_AHCI_VENDOR_PP4C_SFD_MASK
+#define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL 0x064A0813
+#define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT 16
+#define SATA_AHCI_VENDOR_PP4C_SFD_MASK 0x00FF0000U
+
+/*PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th
+ value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128*/
+#undef SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL
+#undef SATA_AHCI_VENDOR_PP4C_PTST_SHIFT
+#undef SATA_AHCI_VENDOR_PP4C_PTST_MASK
+#define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL 0x064A0813
+#define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT 24
+#define SATA_AHCI_VENDOR_PP4C_PTST_MASK 0xFF000000U
+
+/*RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed.*/
+#undef SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL
+#undef SATA_AHCI_VENDOR_PP5C_RIT_SHIFT
+#undef SATA_AHCI_VENDOR_PP5C_RIT_MASK
+#define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL 0x3FFC96A4
+#define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT 0
+#define SATA_AHCI_VENDOR_PP5C_RIT_MASK 0x000FFFFFU
+
+/*RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha
+ completed, for a fast SERDES it is suggested that this value be 54.2us / 4*/
+#undef SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL
+#undef SATA_AHCI_VENDOR_PP5C_RCT_SHIFT
+#undef SATA_AHCI_VENDOR_PP5C_RCT_MASK
+#define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL 0x3FFC96A4
+#define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT 20
+#define SATA_AHCI_VENDOR_PP5C_RCT_MASK 0xFFF00000U
#undef CRL_APB_RST_LPD_TOP_OFFSET
#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
#undef CRL_APB_RST_LPD_IOU0_OFFSET
@@ -26143,6 +27842,13 @@ extern "C" {
int psu_init ();
unsigned long psu_ps_pl_isolation_removal_data();
unsigned long psu_ps_pl_reset_config_data();
+ int psu_protection();
+ int psu_fpd_protection();
+ int psu_ocm_protection();
+ int psu_ddr_protection();
+ int psu_lpd_protection();
+ int psu_protection_lock();
+ unsigned long psu_apply_master_tz();
#ifdef __cplusplus
}
#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf
index be53aba19..01f637605 100644
Binary files a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf and b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf differ