Simplify and improve GIC-less Cortex-R4 port.
Add final tests into RZ/T demo.pull/4/head
Richard Barry
10 years ago
parent
b9f235846f
commit
f19497c3d6
@ -1,159 +0,0 @@
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/*
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FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
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All rights reserved
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***************************************************************************
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* *
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* FreeRTOS tutorial books are available in pdf and paperback. *
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* Complete, revised, and edited pdf reference manuals are also *
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* available. *
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* *
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* Purchasing FreeRTOS documentation will not only help you, by *
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* ensuring you get running as quickly as possible and with an *
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* in-depth knowledge of how to use FreeRTOS, it will also help *
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* the FreeRTOS project to continue with its mission of providing *
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* professional grade, cross platform, de facto standard solutions *
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* for microcontrollers - completely free of charge! *
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* *
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* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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* *
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* Thank you for using FreeRTOS, and thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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>>>NOTE<<< The modification to the GPL is included to allow you to
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distribute a combined work that includes FreeRTOS without being obliged to
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provide the source code for proprietary components outside of the FreeRTOS
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kernel. FreeRTOS is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details. You should have received a copy of the GNU General Public
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License and the FreeRTOS license exception along with FreeRTOS; if not it
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can be viewed here: http://www.freertos.org/a00114.html and also obtained
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by writing to Richard Barry, contact details for whom are available on the
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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#define portNESTING_INTERRUPT_ENTRY() \
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__asm volatile ( \
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".extern ulPortYieldRequired \t\n" \
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".extern ulPortInterruptNesting \t\n" \
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".extern FreeRTOS_SVC_Handler \t\n" \
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/* Return to the interrupted instruction. */ \
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"SUB LR, LR, #4 \t\n" \
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\
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/* Push the return address and SPSR. */ \
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"PUSH {LR} \t\n" \
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"MRS LR, SPSR \t\n" \
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"PUSH {LR} \t\n" \
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\
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/* Change to supervisor mode to allow reentry. */ \
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"CPS #0x13 \t\n" \
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\
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/* Push used registers. */ \
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"PUSH {r0-r4, r12} \t\n" \
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\
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/* Increment nesting count. r3 holds the address */ \
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/* of ulPortInterruptNesting future use. */ \
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"LDR r2, =ulPortInterruptNestingConst \t\n" \
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"LDR r3, [r2] \t\n" \
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\
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"LDR r1, [r3] \t\n" \
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"ADD r4, r1, #1 \t\n" \
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"STR r4, [r3] \t\n" \
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\
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/* Ensure bit 2 of the stack pointer is clear. */ \
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/* r2 holds the bit 2 value for future use. */ \
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"MOV r2, sp \t\n" \
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"AND r2, r2, #4 \t\n" \
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"SUB sp, sp, r2 \t\n" \
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\
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/* Call the interrupt handler. */ \
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"PUSH {r0-r3, LR} " \
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);
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#warning Why is ulPortYieldRequired accessed differently to the other variables?
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#warning R0 seems to being pushed even though it is not used.
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#warning Writing to the EOI register uses R4 on consecutive lines.
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#define portNESTING_INTERRUPT_EXIT() \
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__asm volatile ( \
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"POP {r0-r3, LR} \t\n" \
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"ADD sp, sp, r2 \t\n" \
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" \t\n" \
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"CPSID i \t\n" \
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"DSB \t\n" \
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"ISB \t\n" \
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" \t\n" \
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/* Write to the EOI register. */ \
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"LDR r4, ulICCEOIRConst \t\n" \
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"LDR r4, [r4] \t\n" \
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"STR r0, [r4] \t\n" \
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\
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/* Restore the old nesting count. */ \
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"STR r1, [r3] \t\n" \
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\
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/* A context switch is never performed if the */ \
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/* nesting count is not 0. */ \
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"CMP r1, #0 \t\n" \
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"BNE 1f \t\n" \
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\
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/* Did the interrupt request a context switch? */ \
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/* r1 holds the address of ulPortYieldRequired */ \
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/* and r0 the value of ulPortYieldRequired for */ \
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/* future use. */ \
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"LDR r1, =ulPortYieldRequired \t\n" \
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"LDR r0, [r1] \t\n" \
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"CMP r0, #0 \t\n" \
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"BNE 2f \t\n" \
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\
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"1: \t\n" \
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/* No context switch. Restore used registers, */ \
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/* LR_irq and SPSR before returning. 0x12 is IRQ */ \
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/* mode. */ \
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"POP {r0-r4, r12} \t\n" \
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"CPS #0x12 \t\n" \
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"POP {LR} \t\n" \
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"MSR SPSR_cxsf, LR \t\n" \
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"POP {LR} \t\n" \
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"MOVS PC, LR \t\n" \
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\
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"2: \t\n" \
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/* A context switch is to be performed. */ \
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/* Clear the context switch pending flag. */ \
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"MOV r0, #0 \t\n" \
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"STR r0, [r1] \t\n" \
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\
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/* Restore used registers, LR-irq and */ \
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/* SPSR before saving the context to the */ \
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/* task stack. 0x12 is IRQ mode. */ \
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"POP {r0-r4, r12} \t\n" \
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"CPS #0x12 \t\n" \
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"POP {LR} \t\n" \
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"MSR SPSR_cxsf, LR \t\n" \
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"POP {LR} \t\n" \
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"b FreeRTOS_SVC_Handler \t\n" \
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"ISB \t\n" \
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"ulICCEOIRConst: .word ulICCEOIR \t\n" \
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" ulPortInterruptNestingConst: .word ulPortInterruptNesting " \
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);
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