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Fix spelling typos (#1168)

Browse Source 
* Fix spelling

---------

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
pull/1180/head
ActoryOu 3 months ago committed by GitHub
parent 8225a7f554
commit de276eb023
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GPG Key ID: B5690EEEBB952194
133 changed files with 218 additions and 218 deletions
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8
History.txt
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@ -528,7 +528,7 @@ Changes between FreeRTOS V10.4.3 and FreeRTOS V10.4.4 released May 28 2021
in more files.
+ Other minor updates include adding additional configASSERT() checks and
correcting and improving code comments.
+ Go look at the smp branch to see the progress towards the Symetric
+ Go look at the smp branch to see the progress towards the Symmetric
Multiprocessing Kernel. https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/smp
Changes between FreeRTOS V10.4.2 and FreeRTOS V10.4.3 released December 14 2020
@ -2015,7 +2015,7 @@ Changes between V6.1.0 and V6.1.1 released January 14 2011
Embedded Workbench.
+ Added a new port for the MSP430X core using the IAR Embedded Workbench.
+ Updated all the RX62N demo projects that target the Renesas Demonstration
Kit (RDK) to take into account the revered LED wiring on later hardware
Kit (RDK) to take into account the reversed LED wiring on later hardware
revisions, and the new J-Link debug interface DLL.
+ Updated all the RX62N demo projects so the IO page served by the example
embedded web server works with all web browsers.
@ -3174,7 +3174,7 @@ Changes between V1.2.3 and V1.2.4
xSerialPortInitMinimal() and the function xPortInit() has been renamed
to xSerialPortInit().
+ The function sSerialPutChar() has been renamed cSerialPutChar() and
the function return type chaned to portCHAR.
the function return type changed to portCHAR.
+ The integer and flop tasks now include calls to tskYIELD(), allowing
them to be used with the cooperative scheduler.
+ All the demo applications now use the integer and comtest tasks when the
@ -3308,7 +3308,7 @@ Changes between V1.01 and V1.2.0
ports to allocate a different maximum number of priorities.
+ By default the trace facility is off, previously USE_TRACE_FACILITY
was defined.
+ comtest.c now uses a psuedo random delay between sends. This allows for
+ comtest.c now uses a pseudo random delay between sends. This allows for
better testing as the interrupts do not arrive at regular intervals.
+ Minor change to the Flashlite serial port driver. The driver is written
to demonstrate the scheduler and is not written to be efficient.

2
examples/coverity/README.md
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@ -35,7 +35,7 @@ commands in a terminal:
~~~
2. Create the build files using CMake in a `build` directory:
Singe core FreeRTOS:
Single core FreeRTOS:
~~~
cmake -B build -S examples/coverity
~~~

2
examples/template_configuration/FreeRTOSConfig.h
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@ -643,7 +643,7 @@
* contain the most recent error for that task. */
#define configUSE_POSIX_ERRNO 0
/* Set the following INCLUDE_* constants to 1 to incldue the named API function,
/* Set the following INCLUDE_* constants to 1 to include the named API function,
* or 0 to exclude the named API function. Most linkers will remove unused
* functions even when the constant is 1. */
#define INCLUDE_vTaskPrioritySet 1

2
include/task.h
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@ -2372,7 +2372,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
*
* WARN: This function assumes that the pcWriteBuffer is of length
* configSTATS_BUFFER_MAX_LENGTH. This function is there only for
* backward compatiblity. New applications are recommended to use
* backward compatibility. New applications are recommended to use
* vTaskGetRunTimeStatistics and supply the length of the pcWriteBuffer
* explicitly.
*

2
portable/ARMv8M/non_secure/port.c
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@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/ARMv8M/non_secure/portasm.h
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@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/ARMv8M/non_secure/portmacrocommon.h
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@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/ARMv8M/secure/context/secure_context.c
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@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
/* Ontain a free secure context. */
/* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */

8
portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
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@ -627,8 +627,8 @@ typedef struct _AT91S_MC
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */
#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */
@ -1509,7 +1509,7 @@ typedef struct _AT91S_EMAC
AT91_REG EMAC_ECOL; /* Excessive Collision Register */
AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */
AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
AT91_REG EMAC_RRE; /* Receive Ressource Error Register */
AT91_REG EMAC_RRE; /* Receive Resource Error Register */
AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */
AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */
AT91_REG EMAC_ELE; /* Excessive Length Errors Register */
@ -2393,7 +2393,7 @@ typedef struct _AT91S_TDES
#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
/* ========== Register definition for PDC_ADC peripheral ========== */
#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */

14
portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
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@ -627,8 +627,8 @@ typedef struct _AT91S_MC
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */
#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */
@ -1509,7 +1509,7 @@ typedef struct _AT91S_EMAC
AT91_REG EMAC_ECOL; /* Excessive Collision Register */
AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */
AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
AT91_REG EMAC_RRE; /* Receive Ressource Error Register */
AT91_REG EMAC_RRE; /* Receive Resource Error Register */
AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */
AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */
AT91_REG EMAC_ELE; /* Excessive Length Errors Register */
@ -2393,7 +2393,7 @@ typedef struct _AT91S_TDES
#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
/* ========== Register definition for PDC_ADC peripheral ========== */
#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
@ -3125,9 +3125,9 @@ AT91C_MC_RCB EQU( 0x1 << 0 );
-( MC ) Remap Command Bit
/* - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
AT91C_MC_UNDADD EQU( 0x1 << 0 );
-( MC ) Undefined Addess Abort Status
-( MC ) Undefined Address Abort Status
AT91C_MC_MISADD EQU( 0x1 << 1 );
-( MC ) Misaligned Addess Abort Status
-( MC ) Misaligned Address Abort Status
AT91C_MC_ABTSZ EQU( 0x3 << 8 );
-( MC ) Abort Size Status
AT91C_MC_ABTSZ_BYTE EQU( 0x0 << 8 );
@ -5698,7 +5698,7 @@ AT91C_US_CLKS EQU( 0x3 << 4 );
AT91C_EMAC_SA3H EQU( 0xFFFDC0AC );
-( EMAC ) Specific Address 3 Top, Last 2 bytes
AT91C_EMAC_RRE EQU( 0xFFFDC06C );
-( EMAC ) Receive Ressource Error Register
-( EMAC ) Receive Resource Error Register
AT91C_EMAC_STE EQU( 0xFFFDC084 );
-( EMAC ) SQE Test Error Register
/* - ========== Register definition for PDC_ADC peripheral ========== */

8
portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
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@ -210,7 +210,7 @@
/** \brief Set the next receive transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be received */
char * address, /* \arg address to the next block to be received */
unsigned int bytes ) /* \arg number of bytes to be received */
{
pPDC->PDC_RNPR = ( unsigned int ) address;
@ -222,7 +222,7 @@
/** \brief Set the next transmit transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be transmitted */
char * address, /* \arg address to the next block to be transmitted */
unsigned int bytes ) /* \arg number of bytes to be transmitted */
{
pPDC->PDC_TNPR = ( unsigned int ) address;
@ -234,7 +234,7 @@
/** \brief Set the receive transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be received */
char * address, /* \arg address to the next block to be received */
unsigned int bytes ) /* \arg number of bytes to be received */
{
pPDC->PDC_RPR = ( unsigned int ) address;
@ -246,7 +246,7 @@
/** \brief Set the transmit transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be transmitted */
char * address, /* \arg address to the next block to be transmitted */
unsigned int bytes ) /* \arg number of bytes to be transmitted */
{
pPDC->PDC_TPR = ( unsigned int ) address;

2
portable/GCC/ARM_AARCH64/port.c
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@ -547,7 +547,7 @@ UBaseType_t uxPortSetInterruptMask( void )
* this is not the case (if some bits represent a sub-priority).
*
* The priority grouping is configured by the GIC's binary point register
* (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
* (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest
* possible value (which may be above 0). */
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
}

2
portable/GCC/ARM_CA9/port.c
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@ -562,7 +562,7 @@ uint32_t ulPortSetInterruptMask( void )
* this is not the case (if some bits represent a sub-priority).
*
* The priority grouping is configured by the GIC's binary point register
* (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
* (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest
* possible value (which may be above 0). */
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
}

2
portable/GCC/ARM_CM0/portasm.h
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@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/GCC/ARM_CM23/non_secure/port.c
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@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/GCC/ARM_CM23/non_secure/portasm.h
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@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
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@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/GCC/ARM_CM23/secure/secure_context.c
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@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
/* Ontain a free secure context. */
/* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */

2
portable/GCC/ARM_CM23_NTZ/non_secure/port.c
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@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
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@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
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@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/GCC/ARM_CM33/non_secure/port.c
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@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/GCC/ARM_CM33/non_secure/portasm.h
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@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
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@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/GCC/ARM_CM33/secure/secure_context.c
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@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
/* Ontain a free secure context. */
/* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */

2
portable/GCC/ARM_CM33_NTZ/non_secure/port.c
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@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
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@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
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@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/GCC/ARM_CM35P/non_secure/port.c
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@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/GCC/ARM_CM35P/non_secure/portasm.h
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@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
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@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/GCC/ARM_CM35P/secure/secure_context.c
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@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
/* Ontain a free secure context. */
/* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */

2
portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
Unescape Escape View File

@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h
Unescape Escape View File

@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
Unescape Escape View File

@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/GCC/ARM_CM4_MPU/portmacro.h
Unescape Escape View File

@ -98,7 +98,7 @@ typedef unsigned long UBaseType_t;
#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/GCC/ARM_CM55/non_secure/port.c
Unescape Escape View File

@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/GCC/ARM_CM55/non_secure/portasm.h
Unescape Escape View File

@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
Unescape Escape View File

@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/GCC/ARM_CM55/secure/secure_context.c
Unescape Escape View File

@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
/* Ontain a free secure context. */
/* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */

2
portable/GCC/ARM_CM55_NTZ/non_secure/port.c
Unescape Escape View File

@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h
Unescape Escape View File

@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
Unescape Escape View File

@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/GCC/ARM_CM85/non_secure/port.c
Unescape Escape View File

@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/GCC/ARM_CM85/non_secure/portasm.h
Unescape Escape View File

@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
Unescape Escape View File

@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/GCC/ARM_CM85/secure/secure_context.c
Unescape Escape View File

@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
/* Ontain a free secure context. */
/* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */

2
portable/GCC/ARM_CM85_NTZ/non_secure/port.c
Unescape Escape View File

@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h
Unescape Escape View File

@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
Unescape Escape View File

@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/GCC/ARM_CRx_MPU/port.c
Unescape Escape View File

@ -100,7 +100,7 @@ PRIVILEGED_DATA static BaseType_t prvPortSchedulerRunning = pdFALSE;
* @param ulBufferLength Length of the given buffer.
* @param ulAccessRequested Access requested.
*
* @return pdTRUE if MPU region settins authorizes the requested access to the
* @return pdTRUE if MPU region settings authorizes the requested access to the
* given buffer, pdFALSE otherwise.
*/
PRIVILEGED_FUNCTION static BaseType_t prvMPURegionAuthorizesBuffer( const xMPU_REGION_REGISTERS * xTaskMPURegion,

4
portable/GCC/ARM_CRx_MPU/portmacro.h
Unescape Escape View File

@ -236,7 +236,7 @@ typedef uint32_t TickType_t;
#define portTICK_TYPE_IS_ATOMIC 1
/**
* @brief The number of miliseconds between system ticks.
* @brief The number of milliseconds between system ticks.
*
* @ingroup System Clock
*/
@ -380,7 +380,7 @@ void vPortExitCritical( void );
* @note The processor privilege level is determined by checking the
* mode bits [4:0] of the Current Program Status Register (CPSR).
*
* @return pdTRUE, if the processer is privileged, pdFALSE otherwise.
* @return pdTRUE, if the processor is privileged, pdFALSE otherwise.
*/
BaseType_t xPortIsPrivileged( void );

2
portable/GCC/ARM_CRx_MPU/portmacro_asm.h
Unescape Escape View File

@ -36,7 +36,7 @@ extern "C" {
#include "FreeRTOSConfig.h"
#ifndef configTOTAL_MPU_REGIONS
#error "Set configTOTAL_MPU_REGIONS to the humber of MPU regions in FreeRTOSConfig.h"
#error "Set configTOTAL_MPU_REGIONS to the number of MPU regions in FreeRTOSConfig.h"
#elif( configTOTAL_MPU_REGIONS == 12 )
#define portMPU_TOTAL_REGIONS ( 12UL )
#elif( configTOTAL_MPU_REGIONS == 16 )

2
portable/GCC/AVR32_UC3/port.c
Unescape Escape View File

@ -401,7 +401,7 @@ static void prvSetupTimerInterrupt( void )
#if ( configTICK_USE_TC == 1 )
volatile avr32_tc_t * tc = &AVR32_TC;
/* Options for waveform genration. */
/* Options for waveform generation. */
tc_waveform_opt_t waveform_opt =
{
.channel = configTICK_TC_CHANNEL, /* Channel selection. */

2
portable/IAR/ARM_CA9/port.c
Unescape Escape View File

@ -438,7 +438,7 @@ uint32_t ulPortSetInterruptMask( void )
* this is not the case (if some bits represent a sub-priority).
*
* The priority grouping is configured by the GIC's binary point register
* (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
* (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest
* possible value (which may be above 0). */
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
}

2
portable/IAR/ARM_CM23/non_secure/port.c
Unescape Escape View File

@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/IAR/ARM_CM23/non_secure/portasm.h
Unescape Escape View File

@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
Unescape Escape View File

@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/IAR/ARM_CM23/secure/secure_context.c
Unescape Escape View File

@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
/* Ontain a free secure context. */
/* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */

2
portable/IAR/ARM_CM23_NTZ/non_secure/port.c
Unescape Escape View File

@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
Unescape Escape View File

@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
Unescape Escape View File

@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/IAR/ARM_CM33/non_secure/port.c
Unescape Escape View File

@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/IAR/ARM_CM33/non_secure/portasm.h
Unescape Escape View File

@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
Unescape Escape View File

@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/IAR/ARM_CM33/secure/secure_context.c
Unescape Escape View File

@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
/* Ontain a free secure context. */
/* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */

2
portable/IAR/ARM_CM33_NTZ/non_secure/port.c
Unescape Escape View File

@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
Unescape Escape View File

@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
Unescape Escape View File

@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/IAR/ARM_CM35P/non_secure/port.c
Unescape Escape View File

@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/IAR/ARM_CM35P/non_secure/portasm.h
Unescape Escape View File

@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
Unescape Escape View File

@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/IAR/ARM_CM35P/secure/secure_context.c
Unescape Escape View File

@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
/* Ontain a free secure context. */
/* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */

2
portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
Unescape Escape View File

@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h
Unescape Escape View File

@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
Unescape Escape View File

@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/IAR/ARM_CM4F_MPU/portmacro.h
Unescape Escape View File

@ -100,7 +100,7 @@ typedef unsigned long UBaseType_t;
#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/IAR/ARM_CM55/non_secure/port.c
Unescape Escape View File

@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/IAR/ARM_CM55/non_secure/portasm.h
Unescape Escape View File

@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
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@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/IAR/ARM_CM55/secure/secure_context.c
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@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
/* Ontain a free secure context. */
/* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */

2
portable/IAR/ARM_CM55_NTZ/non_secure/port.c
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@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h
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@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
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@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/IAR/ARM_CM85/non_secure/port.c
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@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/IAR/ARM_CM85/non_secure/portasm.h
Unescape Escape View File

@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
Unescape Escape View File

@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/IAR/ARM_CM85/secure/secure_context.c
Unescape Escape View File

@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
/* Ontain a free secure context. */
/* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */

2
portable/IAR/ARM_CM85_NTZ/non_secure/port.c
Unescape Escape View File

@ -56,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
* on the secure side. The following are the valid configuration seetings:
* on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0

2
portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h
Unescape Escape View File

@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
* @note This is a privileged function and should only be called from the kenrel
* @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

2
portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
Unescape Escape View File

@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )

2
portable/IAR/AVR32_UC3/port.c
Unescape Escape View File

@ -374,7 +374,7 @@ static void prvSetupTimerInterrupt( void )
#if ( configTICK_USE_TC == 1 )
volatile avr32_tc_t * tc = &AVR32_TC;
/* Options for waveform genration. */
/* Options for waveform generation. */
tc_waveform_opt_t waveform_opt =
{
.channel = configTICK_TC_CHANNEL, /* Channel selection. */

4
portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
Unescape Escape View File

@ -562,8 +562,8 @@ typedef struct _AT91S_MC
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */
#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */

4
portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
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@ -487,8 +487,8 @@
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
#define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
#define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */
#define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */
#define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */

8
portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
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@ -627,8 +627,8 @@ typedef struct _AT91S_MC
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */
#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */
@ -1509,7 +1509,7 @@ typedef struct _AT91S_EMAC
AT91_REG EMAC_ECOL; /* Excessive Collision Register */
AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */
AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
AT91_REG EMAC_RRE; /* Receive Ressource Error Register */
AT91_REG EMAC_RRE; /* Receive Resource Error Register */
AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */
AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */
AT91_REG EMAC_ELE; /* Excessive Length Errors Register */
@ -2393,7 +2393,7 @@ typedef struct _AT91S_TDES
#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
/* ========== Register definition for PDC_ADC peripheral ========== */
#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */

8
portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
Unescape Escape View File

@ -411,8 +411,8 @@
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
#define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
#define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */
#define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */
#define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */
@ -1234,7 +1234,7 @@
#define EMAC_ECOL ( 96 ) /* Excessive Collision Register */
#define EMAC_TUND ( 100 ) /* Transmit Underrun Error Register */
#define EMAC_CSE ( 104 ) /* Carrier Sense Error Register */
#define EMAC_RRE ( 108 ) /* Receive Ressource Error Register */
#define EMAC_RRE ( 108 ) /* Receive Resource Error Register */
#define EMAC_ROV ( 112 ) /* Receive Overrun Errors Register */
#define EMAC_RSE ( 116 ) /* Receive Symbol Errors Register */
#define EMAC_ELE ( 120 ) /* Excessive Length Errors Register */
@ -2096,7 +2096,7 @@
#define AT91C_EMAC_SA1H ( 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
#define AT91C_EMAC_CSE ( 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
#define AT91C_EMAC_SA3H ( 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
#define AT91C_EMAC_STE ( 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
/* ========== Register definition for PDC_ADC peripheral ========== */
#define AT91C_ADC_PTSR ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */

8
portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
Unescape Escape View File

@ -627,8 +627,8 @@ typedef struct _AT91S_MC
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */
#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */
@ -1509,7 +1509,7 @@ typedef struct _AT91S_EMAC
AT91_REG EMAC_ECOL; /* Excessive Collision Register */
AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */
AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
AT91_REG EMAC_RRE; /* Receive Ressource Error Register */
AT91_REG EMAC_RRE; /* Receive Resource Error Register */
AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */
AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */
AT91_REG EMAC_ELE; /* Excessive Length Errors Register */
@ -2393,7 +2393,7 @@ typedef struct _AT91S_TDES
#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
/* ========== Register definition for PDC_ADC peripheral ========== */
#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */

8
portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
Unescape Escape View File

@ -411,8 +411,8 @@
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
#define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
#define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */
#define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */
#define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */
@ -1234,7 +1234,7 @@
#define EMAC_ECOL ( 96 ) /* Excessive Collision Register */
#define EMAC_TUND ( 100 ) /* Transmit Underrun Error Register */
#define EMAC_CSE ( 104 ) /* Carrier Sense Error Register */
#define EMAC_RRE ( 108 ) /* Receive Ressource Error Register */
#define EMAC_RRE ( 108 ) /* Receive Resource Error Register */
#define EMAC_ROV ( 112 ) /* Receive Overrun Errors Register */
#define EMAC_RSE ( 116 ) /* Receive Symbol Errors Register */
#define EMAC_ELE ( 120 ) /* Excessive Length Errors Register */
@ -2096,7 +2096,7 @@
#define AT91C_EMAC_SA1H ( 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
#define AT91C_EMAC_CSE ( 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
#define AT91C_EMAC_SA3H ( 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
#define AT91C_EMAC_STE ( 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
/* ========== Register definition for PDC_ADC peripheral ========== */
#define AT91C_ADC_PTSR ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */

16
portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
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@ -60,7 +60,7 @@ __inline void AT91F_MC_EFC_CfgModeReg( AT91PS_MC pMC, /* pointer to a MC co
/**---------------------------------------------------------------------------- */
/** \fn AT91F_MC_EFC_GetModeReg */
/** \brief Return MC EFC Mode Regsiter */
/** \brief Return MC EFC Mode Register */
/**---------------------------------------------------------------------------- */
__inline unsigned int AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) /* pointer to a MC controller */
{
@ -69,7 +69,7 @@ __inline unsigned int AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) /* pointer to a M
/**---------------------------------------------------------------------------- */
/** \fn AT91F_MC_EFC_ComputeFMCN */
/** \brief Return MC EFC Mode Regsiter */
/** \brief Return MC EFC Mode Register */
/**---------------------------------------------------------------------------- */
__inline unsigned int AT91F_MC_EFC_ComputeFMCN( int master_clock ) /* master clock in Hz */
{
@ -123,7 +123,7 @@ __inline unsigned int AT91F_MC_EFC_IsInterruptSet( AT91PS_MC pMC, /* \arg
/** \brief Set the next receive transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be received */
char * address, /* \arg address to the next block to be received */
unsigned int bytes ) /* \arg number of bytes to be received */
{
pPDC->PDC_RNPR = ( unsigned int ) address;
@ -135,7 +135,7 @@ __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC
/** \brief Set the next transmit transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be transmitted */
char * address, /* \arg address to the next block to be transmitted */
unsigned int bytes ) /* \arg number of bytes to be transmitted */
{
pPDC->PDC_TNPR = ( unsigned int ) address;
@ -147,7 +147,7 @@ __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC
/** \brief Set the receive transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be received */
char * address, /* \arg address to the next block to be received */
unsigned int bytes ) /* \arg number of bytes to be received */
{
pPDC->PDC_RPR = ( unsigned int ) address;
@ -159,7 +159,7 @@ __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC con
/** \brief Set the transmit transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be transmitted */
char * address, /* \arg address to the next block to be transmitted */
unsigned int bytes ) /* \arg number of bytes to be transmitted */
{
pPDC->PDC_TPR = ( unsigned int ) address;
@ -742,7 +742,7 @@ __inline unsigned int AT91F_SPI_SendFrame( AT91PS_SPI pSPI,
/**---------------------------------------------------------------------------- */
/** \fn AT91F_SPI_Close */
/** \brief Close SPI: disable IT disable transfert, close PDC */
/** \brief Close SPI: disable IT disable transfer, close PDC */
/**---------------------------------------------------------------------------- */
__inline void AT91F_SPI_Close( AT91PS_SPI pSPI ) /* \arg pointer to a SPI controller */
{
@ -1063,7 +1063,7 @@ __inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg poin
/**---------------------------------------------------------------------------- */
/** \fn AT91F_CKGR_CfgMainOscStartUpTime */
/** \brief Cfg MOR Register according to the main osc startup time */
/** \brief Cfg MORE Register according to the main osc startup time */
/**---------------------------------------------------------------------------- */
__inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */

10
portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
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@ -210,7 +210,7 @@
/** \brief Set the next receive transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be received */
char * address, /* \arg address to the next block to be received */
unsigned int bytes ) /* \arg number of bytes to be received */
{
pPDC->PDC_RNPR = ( unsigned int ) address;
@ -222,7 +222,7 @@
/** \brief Set the next transmit transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be transmitted */
char * address, /* \arg address to the next block to be transmitted */
unsigned int bytes ) /* \arg number of bytes to be transmitted */
{
pPDC->PDC_TNPR = ( unsigned int ) address;
@ -234,7 +234,7 @@
/** \brief Set the receive transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be received */
char * address, /* \arg address to the next block to be received */
unsigned int bytes ) /* \arg number of bytes to be received */
{
pPDC->PDC_RPR = ( unsigned int ) address;
@ -246,7 +246,7 @@
/** \brief Set the transmit transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be transmitted */
char * address, /* \arg address to the next block to be transmitted */
unsigned int bytes ) /* \arg number of bytes to be transmitted */
{
pPDC->PDC_TPR = ( unsigned int ) address;
@ -1054,7 +1054,7 @@
/**---------------------------------------------------------------------------- */
/** \fn AT91F_CKGR_CfgMainOscStartUpTime */
/** \brief Cfg MOR Register according to the main osc startup time */
/** \brief Cfg MORE Register according to the main osc startup time */
/**---------------------------------------------------------------------------- */
__inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */

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