The LPC43xx fast start files are now included.
Richard Barry
13 years ago
parent
a0eb27a69e
commit
cc06119b86
@ -1,53 +0,0 @@
|
||||
IPC demo program based on mailbox
|
||||
-----------------------------------------
|
||||
|
||||
- within the file platform_config.h the user needs to specify the system configuration.
|
||||
|
||||
|
||||
The user can specifiy:
|
||||
|
||||
* which mailboxes are required (host, slave, or both)
|
||||
|
||||
* if the M0 memory has to be initialized to a specific value before download
|
||||
|
||||
* the usage of an optional 32-bit parameter for the mailboxes
|
||||
|
||||
* the availability of a callback function for the mailboxes
|
||||
|
||||
* the priority of the interrupt associated with the IPC communication
|
||||
|
||||
* the memory locations of the M0 code/data, buffers for M0 and M4, location of the mailboxes
|
||||
|
||||
* if the M4 shall download the M0 and start it via INITIALIZE_M0_IMAGE (YES/NO)
|
||||
|
||||
The linker scatter file needs to be consistent with the provided ROM/RAM addresses in case of changes.
|
||||
|
||||
Set it to NO if you want to debug the M0 application separately.
|
||||
|
||||
Set to YES means the M4 will reset, download, and release the M0. In this case, the debug connection could be lost.
|
||||
|
||||
For debugging, in this scenario the .ini file shall be modified, not to download the application but just to connect to the processor.
|
||||
|
||||
|
||||
- according to the number of mailbox desired, if callbacks are enabled, the user has to provide a callback table within the Mx_usr_mbx_callbacks.c file.
|
||||
|
||||
In Mx_usr_mbx_callbacks.h file the mailbox numbering is defined. Within the callback table, each callback gets associated to the related mailbox number.
|
||||
|
||||
The order in the table is not important, since the callback function addresses are plugged-in at runtime by the IPC initialization routines.
|
||||
|
||||
|
||||
- The mailbox table defined in ipc_buffer.c needs also to be updated accordingly to accomodate the desired number of mailboxes. There can be
|
||||
|
||||
|
||||
- since the callbacks are executed within the ISR, their usage is meant for quick operations that need to be performed in reaction to the mailbox event
|
||||
|
||||
For normal application processing, message pending flags are provided and shall rather be used, to avoid increasing unnecessarily interrupt latency
|
||||
|
||||
|
||||
- the type of logical messages for the mailboxes are defined within the Mx_ipc_msg.h file
|
||||
|
||||
|
||||
- the application runs completely from RAM and exchanges messages between the processors, showing how to post and read from the mailboxes.
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,233 @@
|
||||
/**********************************************************************
|
||||
* $Id: lpc43xx_emc.c 8765 2011-12-08 00:51:21Z nxp21346 $ lpc43xx_emc.c 2011-12-07
|
||||
*//**
|
||||
* @file lpc43xx_emc.c
|
||||
* @brief Contains all functions support for Clock Generation and Control
|
||||
* firmware library on lpc43xx
|
||||
* @version 1.0
|
||||
* @date 07. December. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#include "LPC43xx.h"
|
||||
#include "lpc43xx_emc.h"
|
||||
#include "scu.h"
|
||||
|
||||
#define M32(x) *((uint32_t *)x)
|
||||
#define DELAYCYCLES(ns) (ns / ((1.0 / __EMCHZ) * 1E9))
|
||||
|
||||
void emc_WaitMinUS(volatile uint32_t us)
|
||||
{
|
||||
us *= (120000000UL / 1000000) / 3;
|
||||
while(us--);
|
||||
}
|
||||
|
||||
void emc_WaitMinMS(uint32_t ms)
|
||||
{
|
||||
emc_WaitMinUS(ms * 1000);
|
||||
}
|
||||
|
||||
void MemoryPinInit(void)
|
||||
{
|
||||
/* select correct functions on the GPIOs */
|
||||
|
||||
#if 1
|
||||
/* DATA LINES 0..31 > D0..D31 */
|
||||
/* P1_7 - EXTBUS_D0 — External memory data line 0 */
|
||||
scu_pinmux(0x1, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_7: D0 (function 0) errata */
|
||||
scu_pinmux(0x1, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_8: D1 (function 0) errata */
|
||||
scu_pinmux(0x1, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_9: D2 (function 0) errata */
|
||||
scu_pinmux(0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_10: D3 (function 0) errata */
|
||||
scu_pinmux(0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_11: D4 (function 0) errata */
|
||||
scu_pinmux(0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_12: D5 (function 0) errata */
|
||||
scu_pinmux(0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_13: D6 (function 0) errata */
|
||||
scu_pinmux(0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_14: D7 (function 0) errata */
|
||||
scu_pinmux(0x5, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_4: D8 (function 0) errata */
|
||||
scu_pinmux(0x5, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_5: D9 (function 0) errata */
|
||||
scu_pinmux(0x5, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_6: D10 (function 0) errata */
|
||||
scu_pinmux(0x5, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_7: D11 (function 0) errata */
|
||||
scu_pinmux(0x5, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_0: D12 (function 0) errata */
|
||||
scu_pinmux(0x5, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_1: D13 (function 0) errata */
|
||||
scu_pinmux(0x5, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_2: D14 (function 0) errata */
|
||||
scu_pinmux(0x5, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_3: D15 (function 0) errata */
|
||||
#if 0
|
||||
scu_pinmux(0xD, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_2: D16 (function 0) errata */
|
||||
scu_pinmux(0xD, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_3: D17 (function 0) errata */
|
||||
scu_pinmux(0xD, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_4: D18 (function 0) errata */
|
||||
scu_pinmux(0xD, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_5: D19 (function 0) errata */
|
||||
scu_pinmux(0xD, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_6: D20 (function 0) errata */
|
||||
scu_pinmux(0xD, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_7: D21 (function 0) errata */
|
||||
scu_pinmux(0xD, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_8: D22 (function 0) errata */
|
||||
scu_pinmux(0xD, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_9: D23 (function 0) errata */
|
||||
scu_pinmux(0xE, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_5: D24 (function 0) errata */
|
||||
scu_pinmux(0xE, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_6: D25 (function 0) errata */
|
||||
scu_pinmux(0xE, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_7: D26 (function 0) errata */
|
||||
scu_pinmux(0xE, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_8: D27 (function 0) errata */
|
||||
scu_pinmux(0xE, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_9: D28 (function 0) errata */
|
||||
scu_pinmux(0xE, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_10: D29 (function 0) errata */
|
||||
scu_pinmux(0xE, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_11: D30 (function 0) errata */
|
||||
scu_pinmux(0xE, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_12: D31 (function 0) errata */
|
||||
#endif
|
||||
|
||||
/* ADDRESS LINES A0..A11 > A0..A11 */
|
||||
scu_pinmux(0x2, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_9 - EXTBUS_A0 — External memory address line 0 */
|
||||
scu_pinmux(0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_10 - EXTBUS_A1 — External memory address line 1 */
|
||||
scu_pinmux(0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_11 - EXTBUS_A2 — External memory address line 2 */
|
||||
scu_pinmux(0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_12 - EXTBUS_A3 — External memory address line 3 */
|
||||
scu_pinmux(0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_13 - EXTBUS_A4 — External memory address line 4 */
|
||||
scu_pinmux(0x1, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_0 - EXTBUS_A5 — External memory address line 5 */
|
||||
scu_pinmux(0x1, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_1 - EXTBUS_A6 — External memory address line 6 */
|
||||
scu_pinmux(0x1, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_2 - EXTBUS_A7 — External memory address line 7 */
|
||||
scu_pinmux(0x2, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_8 - EXTBUS_A8 — External memory address line 8 */
|
||||
scu_pinmux(0x2, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_7 - EXTBUS_A9 — External memory address line 9 */
|
||||
scu_pinmux(0x2, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_6 - EXTBUS_A10 — External memory address line 10 */
|
||||
scu_pinmux(0x2, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_2 - EXTBUS_A11 — External memory address line 11 */
|
||||
scu_pinmux(0x2, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_1 - EXTBUS_A12 — External memory address line 12 */
|
||||
scu_pinmux(0x2, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_0 - EXTBUS_A13 — External memory address line 13 */
|
||||
scu_pinmux(0x6, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_8 - EXTBUS_A14 — External memory address line 14 */
|
||||
scu_pinmux(0x6, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_7 - EXTBUS_A15 — External memory address line 15 */
|
||||
scu_pinmux(0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_16 - EXTBUS_A16 — External memory address line 16 */
|
||||
scu_pinmux(0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_15 - EXTBUS_A17 — External memory address line 17 */
|
||||
scu_pinmux(0xE, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_0 - EXTBUS_A18 — External memory address line 18 */
|
||||
scu_pinmux(0xE, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_1 - EXTBUS_A19 — External memory address line 19 */
|
||||
scu_pinmux(0xE, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_2 - EXTBUS_A20 — External memory address line 20 */
|
||||
scu_pinmux(0xE, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_3 - EXTBUS_A21 — External memory address line 21 */
|
||||
scu_pinmux(0xE, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_4 - EXTBUS_A22 — External memory address line 22 */
|
||||
scu_pinmux(0xA, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PA_4 - EXTBUS_A23 — External memory address line 23 */
|
||||
|
||||
/* BYTE ENABLES */
|
||||
scu_pinmux(0x1, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_4 - EXTBUS_BLS0 — LOW active Byte Lane select signal 0 */
|
||||
scu_pinmux(0x6, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_6 - EXTBUS_BLS1 — LOW active Byte Lane select signal 1 */
|
||||
scu_pinmux(0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_13 - EXTBUS_BLS2 — LOW active Byte Lane select signal 2 */
|
||||
scu_pinmux(0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_10 - EXTBUS_BLS3 — LOW active Byte Lane select signal 3 */
|
||||
|
||||
scu_pinmux(0x6, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_9: EXTBUS_DYCS0 (function 0) > CS# errata */
|
||||
scu_pinmux(0x1, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_6: WE (function 0) errata */
|
||||
scu_pinmux(0x6, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_4: CAS (function 0) > CAS# errata */
|
||||
scu_pinmux(0x6, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_5: RAS (function 0) > RAS# errata */
|
||||
|
||||
LPC_SCU_CLK(0) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK0: EXTBUS_CLK0 (function 0, from datasheet) > CLK ds */
|
||||
LPC_SCU_CLK(1) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK1: EXTBUS_CLK1 (function 2, from datasheet) */
|
||||
LPC_SCU_CLK(2) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK2: EXTBUS_CLK2 (function 2, from datasheet) */
|
||||
LPC_SCU_CLK(3) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK3: EXTBUS_CLK3 (function 2, from datasheet) */
|
||||
|
||||
scu_pinmux(0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_11: CKEOUT0 (function 0) > CKE errata */
|
||||
scu_pinmux(0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_12: DQMOUT0 (function 0) > DQM0 errata */
|
||||
scu_pinmux(0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_10: DQMOUT1 (function 0) > DQM1 errata */
|
||||
scu_pinmux(0xD, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_0: DQMOUT2 (function 2, from datasheet) > DQM2 errata */
|
||||
scu_pinmux(0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_13: DQMOUT3 (function 3, from datasheet) > DQM3 errata */
|
||||
|
||||
scu_pinmux( 1 , 3 , MD_PLN_FAST , 3 ); //OE
|
||||
scu_pinmux( 1 , 4 , MD_PLN_FAST , 3 ); //BLS0
|
||||
scu_pinmux( 1 , 5 , MD_PLN_FAST , 3 ); //CS0
|
||||
scu_pinmux( 1 , 6 , MD_PLN_FAST , 3 ); //WE
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
void EMCFlashInit(void)
|
||||
{
|
||||
// Hitex board SST39VF3201B Flash
|
||||
// Read Cycle Time 70 nS minimum
|
||||
// Chip Enable Access Time 70 ns maximum
|
||||
// Address Access Time 70 ns max
|
||||
// Toe 35 ns max
|
||||
// CE/OE high to inactive output 16 ns
|
||||
|
||||
/* Set up EMC Controller */
|
||||
LPC_EMC->STATICWAITRD0 = DELAYCYCLES(70)+1;
|
||||
|
||||
LPC_EMC->STATICWAITPAG0 = DELAYCYCLES(70)+1;
|
||||
|
||||
|
||||
LPC_EMC->CONTROL = 0x01;
|
||||
LPC_EMC->STATICCONFIG0 = (1UL<<7) | (1UL);
|
||||
LPC_EMC->STATICWAITOEN0 = DELAYCYCLES(35)+1;
|
||||
|
||||
/*Enable Buffer for External Flash*/
|
||||
LPC_EMC->STATICCONFIG0 |= 1<<19;
|
||||
}
|
||||
|
||||
/* SDRAM refresh time to 16 clock num */
|
||||
#define EMC_SDRAM_REFRESH(freq,time) \
|
||||
(((uint64_t)((uint64_t)time * freq)/16000000000ull)+1)
|
||||
|
||||
void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits)
|
||||
{
|
||||
// adjust the CCU delaye for EMI (default to zero)
|
||||
//LPC_SCU->EMCCLKDELAY = (CLK0_DELAY | (CLKE0_DELAY << 16));
|
||||
// Move all clock delays together
|
||||
LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY)
|
||||
| (CLK0_DELAY << 4)
|
||||
| (CLK0_DELAY << 8)
|
||||
| (CLK0_DELAY << 12));
|
||||
|
||||
/* Initialize EMC to interface with SDRAM */
|
||||
LPC_EMC->CONTROL = 0x00000001; /* Enable the external memory controller */
|
||||
LPC_EMC->CONFIG = 0;
|
||||
|
||||
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14));
|
||||
LPC_EMC->DYNAMICCONFIG2 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14));
|
||||
|
||||
LPC_EMC->DYNAMICRASCAS0 = (3 << 0) | (3 << 8); // aem
|
||||
LPC_EMC->DYNAMICRASCAS2 = (3 << 0) | (3 << 8); // aem
|
||||
|
||||
LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY;
|
||||
|
||||
LPC_EMC->DYNAMICRP = 1; // calculated from xls sheet
|
||||
LPC_EMC->DYNAMICRAS = 3;
|
||||
LPC_EMC->DYNAMICSREX = 5;
|
||||
LPC_EMC->DYNAMICAPR = 0;
|
||||
LPC_EMC->DYNAMICDAL = 4;
|
||||
LPC_EMC->DYNAMICWR = 1;
|
||||
LPC_EMC->DYNAMICRC = 5;
|
||||
LPC_EMC->DYNAMICRFC = 5;
|
||||
LPC_EMC->DYNAMICXSR = 5;
|
||||
LPC_EMC->DYNAMICRRD = 1;
|
||||
LPC_EMC->DYNAMICMRD = 1;
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
|
||||
emc_WaitMinUS(100);
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
|
||||
|
||||
LPC_EMC->DYNAMICREFRESH = 2;
|
||||
emc_WaitMinUS(100);
|
||||
|
||||
LPC_EMC->DYNAMICREFRESH = 50;
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
|
||||
|
||||
if(u32DataBus == 0)
|
||||
{
|
||||
/* burst size 8 */
|
||||
*((volatile uint32_t *)(u32BaseAddr | ((3 | (3 << 4)) << (u32ColAddrBits + 1))));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* burst size 4 */
|
||||
*((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2))));
|
||||
}
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = 0; // EMC_CE_ENABLE | EMC_CS_ENABLE;
|
||||
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE;
|
||||
LPC_EMC->DYNAMICCONFIG1 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE;
|
||||
LPC_EMC->DYNAMICCONFIG2 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE;
|
||||
LPC_EMC->DYNAMICCONFIG3 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE;
|
||||
}
|
||||
|
||||
@ -0,0 +1,79 @@
|
||||
/**********************************************************************
|
||||
* $Id: lpc43xx_emc.h 8765 2011-12-08 00:51:21Z nxp21346 $ lpc43xx_emc.h 2011-12-07
|
||||
*//**
|
||||
* @file lpc43xx_emc.h
|
||||
* @brief Contains all functions support for Clock Generation and Control
|
||||
* firmware library on lpc43xx
|
||||
* @version 1.0
|
||||
* @date 07. December. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#define __CRYSTAL (12000000UL) /* Crystal Oscillator frequency */
|
||||
#define __PLLMULT (15)
|
||||
#define __PLLOUTHZ (__CRYSTAL * __PLLMULT)
|
||||
#define __EMCDIV (2)
|
||||
#define __EMCHZ (__PLLOUTHZ / __EMCDIV)
|
||||
|
||||
void MemoryPinInit(void);
|
||||
void EMCFlashInit(void);
|
||||
|
||||
/* SDRAM Address Base for DYCS0*/
|
||||
#define SDRAM_BASE_ADDR 0x28000000
|
||||
#define FLASH_BASE_ADDR 0x1C000000
|
||||
|
||||
#define EMC_SDRAM_WIDTH_8_BITS 0
|
||||
#define EMC_SDRAM_WIDTH_16_BITS 1
|
||||
#define EMC_SDRAM_WIDTH_32_BITS 2
|
||||
|
||||
#define EMC_SDRAM_SIZE_16_MBITS 0
|
||||
#define EMC_SDRAM_SIZE_64_MBITS 1
|
||||
#define EMC_SDRAM_SIZE_128_MBITS 2
|
||||
#define EMC_SDRAM_SIZE_256_MBITS 3
|
||||
#define EMC_SDRAM_SIZE_512_MBITS 4
|
||||
|
||||
#define EMC_SDRAM_DATA_BUS_16_BITS 0
|
||||
#define EMC_SDRAM_DATA_BUS_32_BITS 1
|
||||
|
||||
#define EMC_B_ENABLE (1 << 19)
|
||||
#define EMC_ENABLE (1 << 0)
|
||||
#define EMC_CE_ENABLE (1 << 0)
|
||||
#define EMC_CS_ENABLE (1 << 1)
|
||||
#define EMC_CLOCK_DELAYED_STRATEGY (0 << 0)
|
||||
#define EMC_COMMAND_DELAYED_STRATEGY (1 << 0)
|
||||
#define EMC_COMMAND_DELAYED_STRATEGY2 (2 << 0)
|
||||
#define EMC_COMMAND_DELAYED_STRATEGY3 (3 << 0)
|
||||
#define EMC_INIT(i) ((i) << 7)
|
||||
#define EMC_NORMAL (0)
|
||||
#define EMC_MODE (1)
|
||||
#define EMC_PRECHARGE_ALL (2)
|
||||
#define EMC_NOP (3)
|
||||
|
||||
/* The Hitex LPC18xx Evaluation board contains a 64Mb SDRAM with a 16-bit data bus */
|
||||
#define SDRAM_SIZE_BYTES (1024UL * 1024UL * 8UL)
|
||||
#define SDRAM_WIDTH EMC_SDRAM_WIDTH_16_BITS
|
||||
#define SDRAM_SIZE_MBITS EMC_SDRAM_SIZE_64_MBITS
|
||||
#define SDRAM_DATA_BUS_BITS EMC_SDRAM_DATA_BUS_16_BITS
|
||||
#define SDRAM_COL_ADDR_BITS 8
|
||||
#define CLK0_DELAY 0
|
||||
|
||||
void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits);
|
||||
void emc_WaitUS(volatile uint32_t us);
|
||||
void emc_WaitMS(uint32_t ms);
|
||||
|
||||
|
||||
@ -1,98 +0,0 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc43xx_scu.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc43xx_scu.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for SCU firmware library on lpc43xx
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup SCU SCU (System Control Unit)
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __SCU_H
|
||||
#define __SCU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Private macros ------------------------------------------------------------- */
|
||||
/** @defgroup SCT_Private_Macros SCT Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Port offset definition */
|
||||
#define PORT_OFFSET 0x80
|
||||
/** Pin offset definition */
|
||||
#define PIN_OFFSET 0x04
|
||||
|
||||
/* Pin modes */
|
||||
#define MD_PUP (0x0<<3)
|
||||
#define MD_BUK (0x1<<3)
|
||||
#define MD_PLN (0x2<<3)
|
||||
#define MD_PDN (0x3<<3)
|
||||
#define MD_EHS (0x1<<5)
|
||||
#define MD_EZI (0x1<<6)
|
||||
#define MD_ZI (0x1<<7)
|
||||
#define MD_EHD0 (0x1<<8)
|
||||
#define MD_EHD1 (0x1<<8)
|
||||
#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
|
||||
// 0xF0
|
||||
|
||||
/* Pin function */
|
||||
#define FUNC0 0x0 /** Function 0 */
|
||||
#define FUNC1 0x1 /** Function 1 */
|
||||
#define FUNC2 0x2 /** Function 2 */
|
||||
#define FUNC3 0x3 /** Function 3 */
|
||||
#define FUNC4 0x4
|
||||
#define FUNC5 0x5
|
||||
#define FUNC6 0x6
|
||||
#define FUNC7 0x7
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup SCU_Public_Functions SCU Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end __SCU_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@ -0,0 +1,103 @@
|
||||
/**********************************************************************
|
||||
* $Id: Hitex_Fast_Startup.c 8763 2011-12-08 00:45:50Z nxp21346 $ lpc43xx_emc.c 2011-12-07
|
||||
*//**
|
||||
* @file lpc43xx_emc.c
|
||||
* @brief Contains all functions support for Clock Generation and Control
|
||||
* firmware library on lpc43xx
|
||||
* @version 1.0
|
||||
* @date 07. December. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#include "LPC43xx.h"
|
||||
#include "lpc43xx_cgu.h"
|
||||
#include "lpc43xx_emc.h"
|
||||
#include "spifi_rom_api.h"
|
||||
|
||||
void WaitMinUS( volatile uint32_t us, uint32_t SystemClock )
|
||||
{
|
||||
us *= (SystemClock / 1000000UL) / 3;
|
||||
while(us--);
|
||||
}
|
||||
|
||||
void WaitMinMS( uint32_t ms, uint32_t SystemClock )
|
||||
{
|
||||
WaitMinUS( ( ms * 1000 ), SystemClock );
|
||||
}
|
||||
|
||||
/* hardware-control routine used by spifi_rom_api.c */
|
||||
void pullMISO(int high) {
|
||||
/* undocumented bit 7 included as 1, Aug 2 2011 */
|
||||
LPC_SCU->SFSP3_6 = high == 0 ? 0xDB /* pull down */
|
||||
: high == 1 ? 0xC3 /* pull up */
|
||||
: 0xD3; /* neither */
|
||||
}
|
||||
|
||||
void Hitex_CGU_Init(void)
|
||||
{
|
||||
|
||||
__disable_irq();
|
||||
MemoryPinInit(); // Make sure EMC is in high-speed pin mode
|
||||
|
||||
/* Set the XTAL oscillator frequency to 12MHz*/
|
||||
CGU_SetXTALOSC(__CRYSTAL);
|
||||
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
|
||||
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M3);
|
||||
|
||||
/* Set PL160M 12*1 = 12 MHz */
|
||||
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
|
||||
CGU_SetPLL1(1);
|
||||
CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
|
||||
|
||||
/* Run SPIFI from PL160M, /2 */
|
||||
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVA);
|
||||
CGU_EnableEntity(CGU_CLKSRC_IDIVA, ENABLE);
|
||||
CGU_SetDIV(CGU_CLKSRC_IDIVA, 2);
|
||||
CGU_EntityConnect(CGU_CLKSRC_IDIVA, CGU_BASE_SPIFI);
|
||||
CGU_UpdateClock();
|
||||
|
||||
LPC_CCU1->CLK_M4_EMCDIV_CFG |= (1<<0) | (1<<5); // Turn on clock / 2
|
||||
LPC_CREG->CREG6 |= (1<<16); // EMC divided by 2
|
||||
LPC_CCU1->CLK_M4_EMC_CFG |= (1<<0); // Turn on clock
|
||||
|
||||
/* Set PL160M @ 12*9=108 MHz */
|
||||
CGU_SetPLL1(9);
|
||||
|
||||
/* Run base M3 clock from PL160M, no division */
|
||||
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3);
|
||||
|
||||
WaitMinMS(10, 108000000UL);
|
||||
|
||||
/* Change the clock to 204 MHz */
|
||||
/* Set PL160M @ 12*15=180 MHz */
|
||||
CGU_SetPLL1(17);
|
||||
|
||||
WaitMinMS(10, 180000000UL);
|
||||
|
||||
CGU_UpdateClock();
|
||||
|
||||
EMCFlashInit();
|
||||
|
||||
vEMC_InitSRDRAM(SDRAM_BASE_ADDR, SDRAM_WIDTH, SDRAM_SIZE_MBITS, SDRAM_DATA_BUS_BITS, SDRAM_COL_ADDR_BITS);
|
||||
LPC_SCU->SFSP3_3 = 0xF3; /* high drive for SCLK */
|
||||
/* IO pins */
|
||||
LPC_SCU->SFSP3_4=LPC_SCU->SFSP3_5=LPC_SCU->SFSP3_6=LPC_SCU->SFSP3_7 = 0xD3;
|
||||
LPC_SCU->SFSP3_8 = 0x13; /* CS doesn't need feedback */
|
||||
|
||||
__enable_irq();
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue