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Update the CMSIS files included in the Red Suite LPC17xx demo.

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pull/4/head
Richard Barry 14 years ago
parent 93b74b6f8d
commit 9fa197fa9c
4 changed files with 1264 additions and 797 deletions
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583
Demo/CORTEX_LPC1768_GCC_RedSuite/src/LPC17xx.h
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@ -1,160 +1,20 @@
#ifndef __LPC17xx_H
#define __LPC17xx_H
/* System Control Block (SCB) includes:
Flash Accelerator Module, Clocking and Power Control, External Interrupts,
Reset, System Control and Status
*/
#define SCB_BASE_ADDR 0x400FC000
#define PCONP_PCTIM0 0x00000002
#define PCONP_PCTIM1 0x00000004
#define PCONP_PCUART0 0x00000008
#define PCONP_PCUART1 0x00000010
#define PCONP_PCPWM1 0x00000040
#define PCONP_PCI2C0 0x00000080
#define PCONP_PCSPI 0x00000100
#define PCONP_PCRTC 0x00000200
#define PCONP_PCSSP1 0x00000400
#define PCONP_PCAD 0x00001000
#define PCONP_PCCAN1 0x00002000
#define PCONP_PCCAN2 0x00004000
#define PCONP_PCGPIO 0x00008000
#define PCONP_PCRIT 0x00010000
#define PCONP_PCMCPWM 0x00020000
#define PCONP_PCQEI 0x00040000
#define PCONP_PCI2C1 0x00080000
#define PCONP_PCSSP0 0x00200000
#define PCONP_PCTIM2 0x00400000
#define PCONP_PCTIM3 0x00800000
#define PCONP_PCUART2 0x01000000
#define PCONP_PCUART3 0x02000000
#define PCONP_PCI2C2 0x04000000
#define PCONP_PCI2S 0x08000000
#define PCONP_PCGPDMA 0x20000000
#define PCONP_PCENET 0x40000000
#define PCONP_PCUSB 0x80000000
#define PLLCON_PLLE 0x00000001
#define PLLCON_PLLC 0x00000002
#define PLLCON_MASK 0x00000003
#define PLLCFG_MUL1 0x00000000
#define PLLCFG_MUL2 0x00000001
#define PLLCFG_MUL3 0x00000002
#define PLLCFG_MUL4 0x00000003
#define PLLCFG_MUL5 0x00000004
#define PLLCFG_MUL6 0x00000005
#define PLLCFG_MUL7 0x00000006
#define PLLCFG_MUL8 0x00000007
#define PLLCFG_MUL9 0x00000008
#define PLLCFG_MUL10 0x00000009
#define PLLCFG_MUL11 0x0000000A
#define PLLCFG_MUL12 0x0000000B
#define PLLCFG_MUL13 0x0000000C
#define PLLCFG_MUL14 0x0000000D
#define PLLCFG_MUL15 0x0000000E
#define PLLCFG_MUL16 0x0000000F
#define PLLCFG_MUL17 0x00000010
#define PLLCFG_MUL18 0x00000011
#define PLLCFG_MUL19 0x00000012
#define PLLCFG_MUL20 0x00000013
#define PLLCFG_MUL21 0x00000014
#define PLLCFG_MUL22 0x00000015
#define PLLCFG_MUL23 0x00000016
#define PLLCFG_MUL24 0x00000017
#define PLLCFG_MUL25 0x00000018
#define PLLCFG_MUL26 0x00000019
#define PLLCFG_MUL27 0x0000001A
#define PLLCFG_MUL28 0x0000001B
#define PLLCFG_MUL29 0x0000001C
#define PLLCFG_MUL30 0x0000001D
#define PLLCFG_MUL31 0x0000001E
#define PLLCFG_MUL32 0x0000001F
#define PLLCFG_MUL33 0x00000020
#define PLLCFG_MUL34 0x00000021
#define PLLCFG_MUL35 0x00000022
#define PLLCFG_MUL36 0x00000023
#define PLLCFG_DIV1 0x00000000
#define PLLCFG_DIV2 0x00010000
#define PLLCFG_DIV3 0x00020000
#define PLLCFG_DIV4 0x00030000
#define PLLCFG_DIV5 0x00040000
#define PLLCFG_DIV6 0x00050000
#define PLLCFG_DIV7 0x00060000
#define PLLCFG_DIV8 0x00070000
#define PLLCFG_DIV9 0x00080000
#define PLLCFG_DIV10 0x00090000
#define PLLCFG_MASK 0x00FF7FFF
#define PLLSTAT_MSEL_MASK 0x00007FFF
#define PLLSTAT_NSEL_MASK 0x00FF0000
#define PLLSTAT_PLLE (1 << 24)
#define PLLSTAT_PLLC (1 << 25)
#define PLLSTAT_PLOCK (1 << 26)
#define PLLFEED_FEED1 0x000000AA
#define PLLFEED_FEED2 0x00000055
#define NVIC_IRQ_WDT 0u // IRQ0, exception number 16
#define NVIC_IRQ_TIMER0 1u // IRQ1, exception number 17
#define NVIC_IRQ_TIMER1 2u // IRQ2, exception number 18
#define NVIC_IRQ_TIMER2 3u // IRQ3, exception number 19
#define NVIC_IRQ_TIMER3 4u // IRQ4, exception number 20
#define NVIC_IRQ_UART0 5u // IRQ5, exception number 21
#define NVIC_IRQ_UART1 6u // IRQ6, exception number 22
#define NVIC_IRQ_UART2 7u // IRQ7, exception number 23
#define NVIC_IRQ_UART3 8u // IRQ8, exception number 24
#define NVIC_IRQ_PWM1 9u // IRQ9, exception number 25
#define NVIC_IRQ_I2C0 10u // IRQ10, exception number 26
#define NVIC_IRQ_I2C1 11u // IRQ11, exception number 27
#define NVIC_IRQ_I2C2 12u // IRQ12, exception number 28
#define NVIC_IRQ_SPI 13u // IRQ13, exception number 29
#define NVIC_IRQ_SSP0 14u // IRQ14, exception number 30
#define NVIC_IRQ_SSP1 15u // IRQ15, exception number 31
#define NVIC_IRQ_PLL0 16u // IRQ16, exception number 32
#define NVIC_IRQ_RTC 17u // IRQ17, exception number 33
#define NVIC_IRQ_EINT0 18u // IRQ18, exception number 34
#define NVIC_IRQ_EINT1 19u // IRQ19, exception number 35
#define NVIC_IRQ_EINT2 20u // IRQ20, exception number 36
#define NVIC_IRQ_EINT3 21u // IRQ21, exception number 37
#define NVIC_IRQ_ADC 22u // IRQ22, exception number 38
#define NVIC_IRQ_BOD 23u // IRQ23, exception number 39
#define NVIC_IRQ_USB 24u // IRQ24, exception number 40
#define NVIC_IRQ_CAN 25u // IRQ25, exception number 41
#define NVIC_IRQ_GPDMA 26u // IRQ26, exception number 42
#define NVIC_IRQ_I2S 27u // IRQ27, exception number 43
#define NVIC_IRQ_ETHERNET 28u // IRQ28, exception number 44
#define NVIC_IRQ_RIT 29u // IRQ29, exception number 45
#define NVIC_IRQ_MCPWM 30u // IRQ30, exception number 46
#define NVIC_IRQ_QE 31u // IRQ31, exception number 47
#define NVIC_IRQ_PLL1 32u // IRQ32, exception number 48
#define NVIC_IRQ_USB_ACT 33u // IRQ33, exception number 49
#define NVIC_IRQ_CAN_ACT 34u // IRQ34, exception number 50
#endif // __LPC17xx_H
#ifndef CMSIS_17xx_H
#define CMSIS_17xx_H
/******************************************************************************
* @file: LPC17xx.h
* @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
/**************************************************************************//**
* @file LPC17xx.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
* NXP LPC17xx Device Series
* @version: V1.1
* @date: 14th May 2009
*----------------------------------------------------------------------------
* @version: V1.09
* @date: 17. March 2010
*
* Copyright (C) 2008 ARM Limited. All rights reserved.
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* ARM Limited (ARM) is supplying this software for use with Cortex-M3
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
@ -219,6 +79,8 @@ typedef enum IRQn
MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
USBActivity_IRQn = 33, /* USB Activity interrupt */
CANActivity_IRQn = 34, /* CAN Activity interrupt */
} IRQn_Type;
@ -234,28 +96,18 @@ typedef enum IRQn
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
//#include "..\core_cm3.h" /* Cortex-M3 processor and core peripherals */
#include "core_cm3.h"
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
#include "system_LPC17xx.h" /* System Header */
/**
* Initialize the system clock
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemFrequency variable.
*/
extern void SystemInit (void);
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/*------------- System Control (SC) ------------------------------------------*/
typedef struct
{
@ -277,7 +129,9 @@ typedef struct
__IO uint32_t CCLKCFG;
__IO uint32_t USBCLKCFG;
__IO uint32_t CLKSRCSEL;
uint32_t RESERVED4[12];
__IO uint32_t CANSLEEPCLR;
__IO uint32_t CANWAKEFLAGS;
uint32_t RESERVED4[10];
__IO uint32_t EXTINT; /* External Interrupts */
uint32_t RESERVED5;
__IO uint32_t EXTMODE;
@ -291,9 +145,9 @@ typedef struct
__IO uint32_t PCLKSEL1;
uint32_t RESERVED8[4];
__IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
uint32_t RESERVED9;
__IO uint32_t DMAREQSEL;
__IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
} SC_TypeDef;
} LPC_SC_TypeDef;
/*------------- Pin Connect Block (PINCON) -----------------------------------*/
typedef struct
@ -325,18 +179,79 @@ typedef struct
__IO uint32_t PINMODE_OD2;
__IO uint32_t PINMODE_OD3;
__IO uint32_t PINMODE_OD4;
} PINCON_TypeDef;
__IO uint32_t I2CPADCFG;
} LPC_PINCON_TypeDef;
/*------------- General Purpose Input/Output (GPIO) --------------------------*/
typedef struct
{
union {
__IO uint32_t FIODIR;
struct {
__IO uint16_t FIODIRL;
__IO uint16_t FIODIRH;
};
struct {
__IO uint8_t FIODIR0;
__IO uint8_t FIODIR1;
__IO uint8_t FIODIR2;
__IO uint8_t FIODIR3;
};
};
uint32_t RESERVED0[3];
union {
__IO uint32_t FIOMASK;
struct {
__IO uint16_t FIOMASKL;
__IO uint16_t FIOMASKH;
};
struct {
__IO uint8_t FIOMASK0;
__IO uint8_t FIOMASK1;
__IO uint8_t FIOMASK2;
__IO uint8_t FIOMASK3;
};
};
union {
__IO uint32_t FIOPIN;
struct {
__IO uint16_t FIOPINL;
__IO uint16_t FIOPINH;
};
struct {
__IO uint8_t FIOPIN0;
__IO uint8_t FIOPIN1;
__IO uint8_t FIOPIN2;
__IO uint8_t FIOPIN3;
};
};
union {
__IO uint32_t FIOSET;
struct {
__IO uint16_t FIOSETL;
__IO uint16_t FIOSETH;
};
struct {
__IO uint8_t FIOSET0;
__IO uint8_t FIOSET1;
__IO uint8_t FIOSET2;
__IO uint8_t FIOSET3;
};
};
union {
__O uint32_t FIOCLR;
} GPIO_TypeDef;
struct {
__O uint16_t FIOCLRL;
__O uint16_t FIOCLRH;
};
struct {
__O uint8_t FIOCLR0;
__O uint8_t FIOCLR1;
__O uint8_t FIOCLR2;
__O uint8_t FIOCLR3;
};
};
} LPC_GPIO_TypeDef;
typedef struct
{
@ -352,7 +267,7 @@ typedef struct
__O uint32_t IO2IntClr;
__IO uint32_t IO2IntEnR;
__IO uint32_t IO2IntEnF;
} GPIOINT_TypeDef;
} LPC_GPIOINT_TypeDef;
/*------------- Timer (TIM) --------------------------------------------------*/
typedef struct
@ -372,9 +287,9 @@ typedef struct
__I uint32_t CR1;
uint32_t RESERVED0[2];
__IO uint32_t EMR;
uint32_t RESERVED1[24];
uint32_t RESERVED1[12];
__IO uint32_t CTCR;
} TIM_TypeDef;
} LPC_TIM_TypeDef;
/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
typedef struct
@ -394,14 +309,15 @@ typedef struct
__I uint32_t CR1;
__I uint32_t CR2;
__I uint32_t CR3;
uint32_t RESERVED0;
__IO uint32_t MR4;
__IO uint32_t MR5;
__IO uint32_t MR6;
__IO uint32_t PCR;
__IO uint32_t LER;
uint32_t RESERVED0[7];
uint32_t RESERVED1[7];
__IO uint32_t CTCR;
} PWM_TypeDef;
} LPC_PWM_TypeDef;
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct
@ -422,7 +338,7 @@ typedef struct
};
__IO uint8_t LCR;
uint8_t RESERVED1[7];
__IO uint8_t LSR;
__I uint8_t LSR;
uint8_t RESERVED2[7];
__IO uint8_t SCR;
uint8_t RESERVED3[3];
@ -432,11 +348,41 @@ typedef struct
__IO uint8_t FDR;
uint8_t RESERVED5[7];
__IO uint8_t TER;
uint8_t RESERVED6[27];
__IO uint8_t RS485CTRL;
uint8_t RESERVED7[3];
__IO uint8_t ADRMATCH;
} UART_TypeDef;
uint8_t RESERVED6[39];
__IO uint32_t FIFOLVL;
} LPC_UART_TypeDef;
typedef struct
{
union {
__I uint8_t RBR;
__O uint8_t THR;
__IO uint8_t DLL;
uint32_t RESERVED0;
};
union {
__IO uint8_t DLM;
__IO uint32_t IER;
};
union {
__I uint32_t IIR;
__O uint8_t FCR;
};
__IO uint8_t LCR;
uint8_t RESERVED1[7];
__I uint8_t LSR;
uint8_t RESERVED2[7];
__IO uint8_t SCR;
uint8_t RESERVED3[3];
__IO uint32_t ACR;
__IO uint8_t ICR;
uint8_t RESERVED4[3];
__IO uint8_t FDR;
uint8_t RESERVED5[7];
__IO uint8_t TER;
uint8_t RESERVED6[39];
__IO uint32_t FIFOLVL;
} LPC_UART0_TypeDef;
typedef struct
{
@ -458,9 +404,9 @@ typedef struct
uint8_t RESERVED1[3];
__IO uint8_t MCR;
uint8_t RESERVED2[3];
__IO uint8_t LSR;
__I uint8_t LSR;
uint8_t RESERVED3[3];
__IO uint8_t MSR;
__I uint8_t MSR;
uint8_t RESERVED4[3];
__IO uint8_t SCR;
uint8_t RESERVED5[3];
@ -475,7 +421,9 @@ typedef struct
__IO uint8_t ADRMATCH;
uint8_t RESERVED10[3];
__IO uint8_t RS485DLY;
} UART1_TypeDef;
uint8_t RESERVED11[3];
__IO uint32_t FIFOLVL;
} LPC_UART1_TypeDef;
/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
typedef struct
@ -486,7 +434,7 @@ typedef struct
__IO uint32_t SPCCR;
uint32_t RESERVED0[3];
__IO uint32_t SPINT;
} SPI_TypeDef;
} LPC_SPI_TypeDef;
/*------------- Synchronous Serial Communication (SSP) -----------------------*/
typedef struct
@ -501,7 +449,7 @@ typedef struct
__IO uint32_t MIS;
__IO uint32_t ICR;
__IO uint32_t DMACR;
} SSP_TypeDef;
} LPC_SSP_TypeDef;
/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
typedef struct
@ -522,7 +470,7 @@ typedef struct
__IO uint32_t I2MASK1;
__IO uint32_t I2MASK2;
__IO uint32_t I2MASK3;
} I2C_TypeDef;
} LPC_I2C_TypeDef;
/*------------- Inter IC Sound (I2S) -----------------------------------------*/
typedef struct
@ -541,7 +489,7 @@ typedef struct
__IO uint32_t I2SRXBITRATE;
__IO uint32_t I2STXMODE;
__IO uint32_t I2SRXMODE;
} I2S_TypeDef;
} LPC_I2S_TypeDef;
/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
typedef struct
@ -551,13 +499,13 @@ typedef struct
__IO uint8_t RICTRL;
uint8_t RESERVED0[3];
__IO uint32_t RICOUNTER;
} RIT_TypeDef;
} LPC_RIT_TypeDef;
/*------------- Real-Time Clock (RTC) ----------------------------------------*/
typedef struct
{
__IO uint8_t ILR;
uint8_t RESERVED0[3];
uint8_t RESERVED0[7];
__IO uint8_t CCR;
uint8_t RESERVED1[3];
__IO uint8_t CIIR;
@ -589,9 +537,9 @@ typedef struct
__IO uint32_t GPREG2;
__IO uint32_t GPREG3;
__IO uint32_t GPREG4;
__IO uint8_t WAKEUPDIS;
__IO uint8_t RTC_AUXEN;
uint8_t RESERVED12[3];
__IO uint8_t PWRCTRL;
__IO uint8_t RTC_AUX;
uint8_t RESERVED13[3];
__IO uint8_t ALSEC;
uint8_t RESERVED14[3];
@ -609,7 +557,7 @@ typedef struct
uint8_t RESERVED20[3];
__IO uint16_t ALYEAR;
uint16_t RESERVED21;
} RTC_TypeDef;
} LPC_RTC_TypeDef;
/*------------- Watchdog Timer (WDT) -----------------------------------------*/
typedef struct
@ -621,7 +569,7 @@ typedef struct
uint8_t RESERVED1[3];
__I uint32_t WDTV;
__IO uint32_t WDCLKSEL;
} WDT_TypeDef;
} LPC_WDT_TypeDef;
/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
typedef struct
@ -640,7 +588,7 @@ typedef struct
__I uint32_t ADDR7;
__I uint32_t ADSTAT;
__IO uint32_t ADTRM;
} ADC_TypeDef;
} LPC_ADC_TypeDef;
/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
typedef struct
@ -648,7 +596,7 @@ typedef struct
__IO uint32_t DACR;
__IO uint32_t DACCTRL;
__IO uint16_t DACCNTVAL;
} DAC_TypeDef;
} LPC_DAC_TypeDef;
/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
typedef struct
@ -683,7 +631,7 @@ typedef struct
__O uint32_t MCINTFLAG_SET;
__O uint32_t MCINTFLAG_CLR;
__O uint32_t MCCAP_CLR;
} MCPWM_TypeDef;
} LPC_MCPWM_TypeDef;
/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
typedef struct
@ -711,13 +659,13 @@ typedef struct
__I uint32_t QEIIE;
__O uint32_t QEICLR;
__O uint32_t QEISET;
} QEI_TypeDef;
} LPC_QEI_TypeDef;
/*------------- Controller Area Network (CAN) --------------------------------*/
typedef struct
{
__IO uint32_t mask[512]; /* ID Masks */
} CANAF_RAM_TypeDef;
} LPC_CANAF_RAM_TypeDef;
typedef struct /* Acceptance Filter Registers */
{
@ -729,14 +677,17 @@ typedef struct /* Acceptance Filter Registers */
__IO uint32_t ENDofTable;
__I uint32_t LUTerrAd;
__I uint32_t LUTerr;
} CANAF_TypeDef;
__IO uint32_t FCANIE;
__IO uint32_t FCANIC0;
__IO uint32_t FCANIC1;
} LPC_CANAF_TypeDef;
typedef struct /* Central Registers */
{
__I uint32_t CANTxSR;
__I uint32_t CANRxSR;
__I uint32_t CANMSR;
} CANCR_TypeDef;
} LPC_CANCR_TypeDef;
typedef struct /* Controller Registers */
{
@ -764,7 +715,7 @@ typedef struct /* Controller Registers */
__IO uint32_t TID3;
__IO uint32_t TDA3;
__IO uint32_t TDB3;
} CAN_TypeDef;
} LPC_CAN_TypeDef;
/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
typedef struct /* Common Registers */
@ -783,7 +734,7 @@ typedef struct /* Common Registers */
__IO uint32_t DMACSoftLSReq;
__IO uint32_t DMACConfig;
__IO uint32_t DMACSync;
} GPDMA_TypeDef;
} LPC_GPDMA_TypeDef;
typedef struct /* Channel Registers */
{
@ -792,7 +743,7 @@ typedef struct /* Channel Registers */
__IO uint32_t DMACCLLI;
__IO uint32_t DMACCControl;
__IO uint32_t DMACCConfig;
} GPDMACH_TypeDef;
} LPC_GPDMACH_TypeDef;
/*------------- Universal Serial Bus (USB) -----------------------------------*/
typedef struct
@ -878,23 +829,25 @@ typedef struct
__O uint32_t USBSysErrIntSet;
uint32_t RESERVED4[15];
union {
__I uint32_t I2C_RX; /* USB OTG I2C Registers */
__O uint32_t I2C_WO;
__O uint32_t I2C_TX;
};
__I uint32_t I2C_STS;
__IO uint32_t I2C_CTL;
__IO uint32_t I2C_CLKHI;
__O uint32_t I2C_CLKLO;
uint32_t RESERVED5[823];
uint32_t RESERVED5[824];
union {
__IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
__IO uint32_t OTGClkCtrl;
} ;
};
union {
__I uint32_t USBClkSt;
__I uint32_t OTGClkSt;
};
} USB_TypeDef;
} LPC_USB_TypeDef;
/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
typedef struct
@ -953,128 +906,130 @@ typedef struct
__IO uint32_t PowerDown;
uint32_t RESERVED8;
__IO uint32_t Module_ID;
} EMAC_TypeDef;
} LPC_EMAC_TypeDef;
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/* Base addresses */
#define FLASH_BASE (0x00000000UL)
#define RAM_BASE (0x10000000UL)
#define GPIO_BASE (0x2009C000UL)
#define APB0_BASE (0x40000000UL)
#define APB1_BASE (0x40080000UL)
#define AHB_BASE (0x50000000UL)
#define CM3_BASE (0xE0000000UL)
#define LPC_FLASH_BASE (0x00000000UL)
#define LPC_RAM_BASE (0x10000000UL)
#define LPC_GPIO_BASE (0x2009C000UL)
#define LPC_APB0_BASE (0x40000000UL)
#define LPC_APB1_BASE (0x40080000UL)
#define LPC_AHB_BASE (0x50000000UL)
#define LPC_CM3_BASE (0xE0000000UL)
/* APB0 peripherals */
#define WDT_BASE (APB0_BASE + 0x00000)
#define TIM0_BASE (APB0_BASE + 0x04000)
#define TIM1_BASE (APB0_BASE + 0x08000)
#define UART0_BASE (APB0_BASE + 0x0C000)
#define UART1_BASE (APB0_BASE + 0x10000)
#define PWM1_BASE (APB0_BASE + 0x18000)
#define I2C0_BASE (APB0_BASE + 0x1C000)
#define SPI_BASE (APB0_BASE + 0x20000)
#define RTC_BASE (APB0_BASE + 0x24000)
#define GPIOINT_BASE (APB0_BASE + 0x28080)
#define PINCON_BASE (APB0_BASE + 0x2C000)
#define SSP1_BASE (APB0_BASE + 0x30000)
#define ADC_BASE (APB0_BASE + 0x34000)
#define CANAF_RAM_BASE (APB0_BASE + 0x38000)
#define CANAF_BASE (APB0_BASE + 0x3C000)
#define CANCR_BASE (APB0_BASE + 0x40000)
#define CAN1_BASE (APB0_BASE + 0x44000)
#define CAN2_BASE (APB0_BASE + 0x48000)
#define I2C1_BASE (APB0_BASE + 0x5C000)
#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
/* APB1 peripherals */
#define SSP0_BASE (APB1_BASE + 0x08000)
#define DAC_BASE (APB1_BASE + 0x0C000)
#define TIM2_BASE (APB1_BASE + 0x10000)
#define TIM3_BASE (APB1_BASE + 0x14000)
#define UART2_BASE (APB1_BASE + 0x18000)
#define UART3_BASE (APB1_BASE + 0x1C000)
#define I2C2_BASE (APB1_BASE + 0x20000)
#define I2S_BASE (APB1_BASE + 0x28000)
#define RIT_BASE (APB1_BASE + 0x30000)
#define MCPWM_BASE (APB1_BASE + 0x38000)
#define QEI_BASE (APB1_BASE + 0x3C000)
#define SC_BASE (APB1_BASE + 0x7C000)
#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
/* AHB peripherals */
#define EMAC_BASE (AHB_BASE + 0x00000)
#define GPDMA_BASE (AHB_BASE + 0x04000)
#define GPDMACH0_BASE (AHB_BASE + 0x04100)
#define GPDMACH1_BASE (AHB_BASE + 0x04120)
#define GPDMACH2_BASE (AHB_BASE + 0x04140)
#define GPDMACH3_BASE (AHB_BASE + 0x04160)
#define GPDMACH4_BASE (AHB_BASE + 0x04180)
#define GPDMACH5_BASE (AHB_BASE + 0x041A0)
#define GPDMACH6_BASE (AHB_BASE + 0x041C0)
#define GPDMACH7_BASE (AHB_BASE + 0x041E0)
#define USB_BASE (AHB_BASE + 0x0C000)
#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
/* GPIOs */
#define GPIO0_BASE (GPIO_BASE + 0x00000)
#define GPIO1_BASE (GPIO_BASE + 0x00020)
#define GPIO2_BASE (GPIO_BASE + 0x00040)
#define GPIO3_BASE (GPIO_BASE + 0x00060)
#define GPIO4_BASE (GPIO_BASE + 0x00080)
#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
#define SC (( SC_TypeDef *) SC_BASE)
#define GPIO0 (( GPIO_TypeDef *) GPIO0_BASE)
#define GPIO1 (( GPIO_TypeDef *) GPIO1_BASE)
#define GPIO2 (( GPIO_TypeDef *) GPIO2_BASE)
#define GPIO3 (( GPIO_TypeDef *) GPIO3_BASE)
#define GPIO4 (( GPIO_TypeDef *) GPIO4_BASE)
#define WDT (( WDT_TypeDef *) WDT_BASE)
#define TIM0 (( TIM_TypeDef *) TIM0_BASE)
#define TIM1 (( TIM_TypeDef *) TIM1_BASE)
#define TIM2 (( TIM_TypeDef *) TIM2_BASE)
#define TIM3 (( TIM_TypeDef *) TIM3_BASE)
#define RIT (( RIT_TypeDef *) RIT_BASE)
#define UART0 (( UART_TypeDef *) UART0_BASE)
#define UART1 (( UART1_TypeDef *) UART1_BASE)
#define UART2 (( UART_TypeDef *) UART2_BASE)
#define UART3 (( UART_TypeDef *) UART3_BASE)
#define PWM1 (( PWM_TypeDef *) PWM1_BASE)
#define I2C0 (( I2C_TypeDef *) I2C0_BASE)
#define I2C1 (( I2C_TypeDef *) I2C1_BASE)
#define I2C2 (( I2C_TypeDef *) I2C2_BASE)
#define I2S (( I2S_TypeDef *) I2S_BASE)
#define SPI (( SPI_TypeDef *) SPI_BASE)
#define RTC (( RTC_TypeDef *) RTC_BASE)
#define GPIOINT (( GPIOINT_TypeDef *) GPIOINT_BASE)
#define PINCON (( PINCON_TypeDef *) PINCON_BASE)
#define SSP0 (( SSP_TypeDef *) SSP0_BASE)
#define SSP1 (( SSP_TypeDef *) SSP1_BASE)
#define ADC (( ADC_TypeDef *) ADC_BASE)
#define DAC (( DAC_TypeDef *) DAC_BASE)
#define CANAF_RAM ((CANAF_RAM_TypeDef *) CANAF_RAM_BASE)
#define CANAF (( CANAF_TypeDef *) CANAF_BASE)
#define CANCR (( CANCR_TypeDef *) CANCR_BASE)
#define CAN1 (( CAN_TypeDef *) CAN1_BASE)
#define CAN2 (( CAN_TypeDef *) CAN2_BASE)
#define MCPWM (( MCPWM_TypeDef *) MCPWM_BASE)
#define QEI (( QEI_TypeDef *) QEI_BASE)
#define EMAC (( EMAC_TypeDef *) EMAC_BASE)
#define GPDMA (( GPDMA_TypeDef *) GPDMA_BASE)
#define GPDMACH0 (( GPDMACH_TypeDef *) GPDMACH0_BASE)
#define GPDMACH1 (( GPDMACH_TypeDef *) GPDMACH1_BASE)
#define GPDMACH2 (( GPDMACH_TypeDef *) GPDMACH2_BASE)
#define GPDMACH3 (( GPDMACH_TypeDef *) GPDMACH3_BASE)
#define GPDMACH4 (( GPDMACH_TypeDef *) GPDMACH4_BASE)
#define GPDMACH5 (( GPDMACH_TypeDef *) GPDMACH5_BASE)
#define GPDMACH6 (( GPDMACH_TypeDef *) GPDMACH6_BASE)
#define GPDMACH7 (( GPDMACH_TypeDef *) GPDMACH7_BASE)
#define USB (( USB_TypeDef *) USB_BASE)
#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
#endif // __LPC17xx_H__
#endif

1175
Demo/CORTEX_LPC1768_GCC_RedSuite/src/core_cm3.h
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File diff suppressed because it is too large Load Diff

123
Demo/CORTEX_LPC1768_GCC_RedSuite/src/cr_startup_lpc17.c
Unescape Escape View File

@ -5,7 +5,7 @@
// | |
// +-+--+ |
// | +--+--+
// +----+ Copyright (c) 2009 Code Red Technologies Ltd.
// +----+ Copyright (c) 2009-10 Code Red Technologies Ltd.
//
// Microcontroller Startup code for use with Red Suite
//
@ -25,22 +25,53 @@
// CODE RED TECHNOLOGIES LTD.
//
//*****************************************************************************
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
// Code Red - if CMSIS is being used, then SystemInit() routine
// will be called by startup code rather than in application's main()
#if defined (__USE_CMSIS)
#include "system_LPC17xx.h"
#endif
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
//
// Forward declaration of the default handlers.
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
//*****************************************************************************
void Reset_Handler(void);
void ResetISR(void) ALIAS(Reset_Handler);
static void NMI_Handler(void);
static void HardFault_Handler(void);
static void MemManage_Handler(void);
static void BusFault_Handler(void);
static void UsageFault_Handler(void);
static void DebugMon_Handler(void);
void ResetISR(void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
WEAK void BusFault_Handler(void);
WEAK void UsageFault_Handler(void);
WEAK void SVCall_Handler(void);
WEAK void DebugMon_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
//*****************************************************************************
//
@ -83,48 +114,49 @@ void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
extern void xPortSysTickHandler(void);
extern void xPortPendSVHandler(void);
extern void vPortSVCHandler( void );
extern void vEMAC_ISR( void );
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern WEAK void __libc_init_array(void);
//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for redlib based applications
// main() is the entry point for newlib based applications
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
//*****************************************************************************
extern WEAK void __main(void);
extern WEAK void main(void);
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
//*****************************************************************************
extern void _vStackTop;
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
//
// The vector table.
// This relies on the linker script to place at correct location in memory.
//
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) =
{
// Core Level - CM3
(void *)&_vStackTop, // The initial stack pointer
Reset_Handler, // The reset handler
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
@ -174,6 +206,8 @@ void (* const g_pfnVectors[])(void) =
MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
};
//*****************************************************************************
@ -196,7 +230,7 @@ extern unsigned long _ebss;
//
//*****************************************************************************
void Reset_Handler(void)
{
ResetISR(void) {
unsigned long *pulSrc, *pulDest;
//
@ -222,21 +256,23 @@ void Reset_Handler(void)
" strlt r2, [r0], #4\n"
" blt zero_loop");
//
// Call C++ library initilisation, if present
//
if (__libc_init_array)
__libc_init_array() ;
#ifdef __USE_CMSIS
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call the application's entry point.
// __main() is the entry point for redlib based applications (which calls main())
// main() is the entry point for newlib based applications
// Call C++ library initialisation
//
if (__main)
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
else
main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
@ -253,42 +289,43 @@ void Reset_Handler(void)
// by a debugger.
//
//*****************************************************************************
static void NMI_Handler(void)
void NMI_Handler(void)
{
while(1)
{
}
}
static void HardFault_Handler(void)
void HardFault_Handler(void)
{
while(1)
{
}
}
static void MemManage_Handler(void)
void MemManage_Handler(void)
{
while(1)
{
}
}
static void BusFault_Handler(void)
void BusFault_Handler(void)
{
while(1)
{
}
}
static void UsageFault_Handler(void)
void UsageFault_Handler(void)
{
while(1)
{
}
}
static void DebugMon_Handler(void)
void DebugMon_Handler(void)
{
while(1)
{
@ -301,7 +338,7 @@ static void DebugMon_Handler(void)
// is not present in the application code.
//
//*****************************************************************************
static void IntDefaultHandler(void)
void IntDefaultHandler(void)
{
//
// Go into an infinite loop.

44
Demo/CORTEX_LPC1768_GCC_RedSuite/src/system_LPC17xx.h
Unescape Escape View File

@ -1,17 +1,19 @@
/******************************************************************************
* @file: system_LPC17xx.h
* @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
/**************************************************************************//**
* @file system_LPC17xx.h
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
* for the NXP LPC17xx Device Series
* @version: V1.0
* @date: 25. Nov. 2008
*----------------------------------------------------------------------------
* @version V1.02
* @date 08. September 2009
*
* Copyright (C) 2008 ARM Limited. All rights reserved.
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* ARM Limited (ARM) is supplying this software for use with Cortex-M3
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
@ -24,7 +26,13 @@
#ifndef __SYSTEM_LPC17xx_H
#define __SYSTEM_LPC17xx_H
extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
@ -34,7 +42,23 @@ extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemFrequency variable.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_LPC17xx_H */

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