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Cortex-M Assert when NVIC implements 8 PRIO bits (#639)

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* Cortex-M Assert when NVIC implements 8 PRIO bits

* Fix CM3 ports

* Fix ARM_CM3_MPU

* Fix ARM CM3

* Fix ARM_CM4_MPU

* Fix ARM_CM4

* Fix GCC ARM_CM7

* Fix IAR ARM ports

* Uncrustify changes

* Fix MikroC_ARM_CM4F port

* Fix MikroC_ARM_CM4F port-(2)

* Fix RVDS ARM ports

* Revert changes for Tasking/ARM_CM4F port

* Revert changes for Tasking/ARM_CM4F port-(2)

* Update port.c

Fix GCC/ARM_CM4F port

* Update port.c

* update GCC\ARM_CM4F port

* update port.c

* Assert to check configMAX_SYSCALL_INTERRUPT_PRIORITY is set to higher priority

* Fix merge error: remove duplicate code

* Fix typos

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-17-174.ec2.internal>
pull/649/head
kar-rahul-aws 2 years ago committed by GitHub
parent 9488ba22d8
commit 99797e14e3
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
17 changed files with 805 additions and 366 deletions
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63
portable/CCS/ARM_CM3/port.c
Unescape Escape View File

@ -219,6 +219,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 ) #if ( configASSERT_DEFINED == 1 )
{ {
volatile uint32_t ulOriginalPriority; volatile uint32_t ulOriginalPriority;
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue; volatile uint8_t ucMaxPriorityValue;
@ -250,20 +251,46 @@ BaseType_t xPortStartScheduler( void )
/* Calculate the maximum acceptable priority group value for the number /* Calculate the maximum acceptable priority group value for the number
* of bits read back. */ * of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{ {
ulMaxPRIGROUPValue--; ulImplementedPrioBits++;
ucMaxPriorityValue <<= ( uint8_t ) 0x01; ucMaxPriorityValue <<= ( uint8_t ) 0x01;
} }
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
* the software to configure PRIGROUP to not have sub-priorities. As
* a result, the least significant bit is always used for sub-priority
* and there are 128 preemption priorities and 2 sub-priorities.
*
* This may cause some confusion in some cases - for example, if
* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
* priority interrupts will be masked in Critical Sections as those
* are at the same preemption priority. This may appear confusing as
* 4 is higher (numerically lower) priority than
* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
* to 4, this confusion does not happen and the behaviour remains the same.
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
{ {
/* Check the CMSIS configuration that defines the number of /* Check the CMSIS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
} }
#endif #endif
@ -272,7 +299,7 @@ BaseType_t xPortStartScheduler( void )
/* Check the FreeRTOS configuration that defines the number of /* Check the FreeRTOS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); configASSERT( ulImplementedPrioBits == configPRIO_BITS );
} }
#endif #endif
@ -379,9 +406,9 @@ void xPortSysTickHandler( void )
/* Enter a critical section but don't use the taskENTER_CRITICAL() /* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */ * method as that will mask interrupts that should exit sleep mode. */
__asm( " cpsid i"); __asm( " cpsid i" );
__asm( " dsb"); __asm( " dsb" );
__asm( " isb"); __asm( " isb" );
/* If a context switch is pending or a task is waiting for the scheduler /* If a context switch is pending or a task is waiting for the scheduler
* to be unsuspended then abandon the low power entry. */ * to be unsuspended then abandon the low power entry. */
@ -389,7 +416,7 @@ void xPortSysTickHandler( void )
{ {
/* Re-enable interrupts - see comments above the cpsid instruction /* Re-enable interrupts - see comments above the cpsid instruction
* above. */ * above. */
__asm( " cpsie i"); __asm( " cpsie i" );
} }
else else
{ {
@ -450,9 +477,9 @@ void xPortSysTickHandler( void )
if( xModifiableIdleTime > 0 ) if( xModifiableIdleTime > 0 )
{ {
__asm( " dsb"); __asm( " dsb" );
__asm( " wfi"); __asm( " wfi" );
__asm( " isb"); __asm( " isb" );
} }
configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
@ -460,17 +487,17 @@ void xPortSysTickHandler( void )
/* Re-enable interrupts to allow the interrupt that brought the MCU /* Re-enable interrupts to allow the interrupt that brought the MCU
* out of sleep mode to execute immediately. See comments above * out of sleep mode to execute immediately. See comments above
* the cpsid instruction above. */ * the cpsid instruction above. */
__asm( " cpsie i"); __asm( " cpsie i" );
__asm( " dsb"); __asm( " dsb" );
__asm( " isb"); __asm( " isb" );
/* Disable interrupts again because the clock is about to be stopped /* Disable interrupts again because the clock is about to be stopped
* and interrupts that execute while the clock is stopped will increase * and interrupts that execute while the clock is stopped will increase
* any slippage between the time maintained by the RTOS and calendar * any slippage between the time maintained by the RTOS and calendar
* time. */ * time. */
__asm( " cpsid i"); __asm( " cpsid i" );
__asm( " dsb"); __asm( " dsb" );
__asm( " isb"); __asm( " isb" );
/* Disable the SysTick clock without reading the /* Disable the SysTick clock without reading the
* portNVIC_SYSTICK_CTRL_REG register to ensure the * portNVIC_SYSTICK_CTRL_REG register to ensure the
@ -578,7 +605,7 @@ void xPortSysTickHandler( void )
vTaskStepTick( ulCompleteTickPeriods ); vTaskStepTick( ulCompleteTickPeriods );
/* Exit with interrupts enabled. */ /* Exit with interrupts enabled. */
__asm( " cpsie i"); __asm( " cpsie i" );
} }
} }

63
portable/CCS/ARM_CM4F/port.c
Unescape Escape View File

@ -238,6 +238,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 ) #if ( configASSERT_DEFINED == 1 )
{ {
volatile uint32_t ulOriginalPriority; volatile uint32_t ulOriginalPriority;
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue; volatile uint8_t ucMaxPriorityValue;
@ -269,20 +270,46 @@ BaseType_t xPortStartScheduler( void )
/* Calculate the maximum acceptable priority group value for the number /* Calculate the maximum acceptable priority group value for the number
* of bits read back. */ * of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{ {
ulMaxPRIGROUPValue--; ulImplementedPrioBits++;
ucMaxPriorityValue <<= ( uint8_t ) 0x01; ucMaxPriorityValue <<= ( uint8_t ) 0x01;
} }
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
* the software to configure PRIGROUP to not have sub-priorities. As
* a result, the least significant bit is always used for sub-priority
* and there are 128 preemption priorities and 2 sub-priorities.
*
* This may cause some confusion in some cases - for example, if
* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
* priority interrupts will be masked in Critical Sections as those
* are at the same preemption priority. This may appear confusing as
* 4 is higher (numerically lower) priority than
* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
* to 4, this confusion does not happen and the behaviour remains the same.
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
{ {
/* Check the CMSIS configuration that defines the number of /* Check the CMSIS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
} }
#endif #endif
@ -291,7 +318,7 @@ BaseType_t xPortStartScheduler( void )
/* Check the FreeRTOS configuration that defines the number of /* Check the FreeRTOS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); configASSERT( ulImplementedPrioBits == configPRIO_BITS );
} }
#endif #endif
@ -404,9 +431,9 @@ void xPortSysTickHandler( void )
/* Enter a critical section but don't use the taskENTER_CRITICAL() /* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */ * method as that will mask interrupts that should exit sleep mode. */
__asm( " cpsid i"); __asm( " cpsid i" );
__asm( " dsb"); __asm( " dsb" );
__asm( " isb"); __asm( " isb" );
/* If a context switch is pending or a task is waiting for the scheduler /* If a context switch is pending or a task is waiting for the scheduler
* to be unsuspended then abandon the low power entry. */ * to be unsuspended then abandon the low power entry. */
@ -414,7 +441,7 @@ void xPortSysTickHandler( void )
{ {
/* Re-enable interrupts - see comments above the cpsid instruction /* Re-enable interrupts - see comments above the cpsid instruction
* above. */ * above. */
__asm( " cpsie i"); __asm( " cpsie i" );
} }
else else
{ {
@ -475,9 +502,9 @@ void xPortSysTickHandler( void )
if( xModifiableIdleTime > 0 ) if( xModifiableIdleTime > 0 )
{ {
__asm( " dsb"); __asm( " dsb" );
__asm( " wfi"); __asm( " wfi" );
__asm( " isb"); __asm( " isb" );
} }
configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
@ -485,17 +512,17 @@ void xPortSysTickHandler( void )
/* Re-enable interrupts to allow the interrupt that brought the MCU /* Re-enable interrupts to allow the interrupt that brought the MCU
* out of sleep mode to execute immediately. See comments above * out of sleep mode to execute immediately. See comments above
* the cpsid instruction above. */ * the cpsid instruction above. */
__asm( " cpsie i"); __asm( " cpsie i" );
__asm( " dsb"); __asm( " dsb" );
__asm( " isb"); __asm( " isb" );
/* Disable interrupts again because the clock is about to be stopped /* Disable interrupts again because the clock is about to be stopped
* and interrupts that execute while the clock is stopped will increase * and interrupts that execute while the clock is stopped will increase
* any slippage between the time maintained by the RTOS and calendar * any slippage between the time maintained by the RTOS and calendar
* time. */ * time. */
__asm( " cpsid i"); __asm( " cpsid i" );
__asm( " dsb"); __asm( " dsb" );
__asm( " isb"); __asm( " isb" );
/* Disable the SysTick clock without reading the /* Disable the SysTick clock without reading the
* portNVIC_SYSTICK_CTRL_REG register to ensure the * portNVIC_SYSTICK_CTRL_REG register to ensure the
@ -603,7 +630,7 @@ void xPortSysTickHandler( void )
vTaskStepTick( ulCompleteTickPeriods ); vTaskStepTick( ulCompleteTickPeriods );
/* Exit with interrupts enabled. */ /* Exit with interrupts enabled. */
__asm( " cpsie i"); __asm( " cpsie i" );
} }
} }

35
portable/GCC/ARM_CM3/port.c
Unescape Escape View File

@ -262,6 +262,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 ) #if ( configASSERT_DEFINED == 1 )
{ {
volatile uint32_t ulOriginalPriority; volatile uint32_t ulOriginalPriority;
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue; volatile uint8_t ucMaxPriorityValue;
@ -293,20 +294,46 @@ BaseType_t xPortStartScheduler( void )
/* Calculate the maximum acceptable priority group value for the number /* Calculate the maximum acceptable priority group value for the number
* of bits read back. */ * of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{ {
ulMaxPRIGROUPValue--; ulImplementedPrioBits++;
ucMaxPriorityValue <<= ( uint8_t ) 0x01; ucMaxPriorityValue <<= ( uint8_t ) 0x01;
} }
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
* the software to configure PRIGROUP to not have sub-priorities. As
* a result, the least significant bit is always used for sub-priority
* and there are 128 preemption priorities and 2 sub-priorities.
*
* This may cause some confusion in some cases - for example, if
* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
* priority interrupts will be masked in Critical Sections as those
* are at the same preemption priority. This may appear confusing as
* 4 is higher (numerically lower) priority than
* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
* to 4, this confusion does not happen and the behaviour remains the same.
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
{ {
/* Check the CMSIS configuration that defines the number of /* Check the CMSIS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
} }
#endif #endif
@ -315,7 +342,7 @@ BaseType_t xPortStartScheduler( void )
/* Check the FreeRTOS configuration that defines the number of /* Check the FreeRTOS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); configASSERT( ulImplementedPrioBits == configPRIO_BITS );
} }
#endif #endif

35
portable/GCC/ARM_CM3_MPU/port.c
Unescape Escape View File

@ -385,6 +385,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 ) #if ( configASSERT_DEFINED == 1 )
{ {
volatile uint32_t ulOriginalPriority; volatile uint32_t ulOriginalPriority;
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue; volatile uint8_t ucMaxPriorityValue;
@ -416,20 +417,46 @@ BaseType_t xPortStartScheduler( void )
/* Calculate the maximum acceptable priority group value for the number /* Calculate the maximum acceptable priority group value for the number
* of bits read back. */ * of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{ {
ulMaxPRIGROUPValue--; ulImplementedPrioBits++;
ucMaxPriorityValue <<= ( uint8_t ) 0x01; ucMaxPriorityValue <<= ( uint8_t ) 0x01;
} }
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
* the software to configure PRIGROUP to not have sub-priorities. As
* a result, the least significant bit is always used for sub-priority
* and there are 128 preemption priorities and 2 sub-priorities.
*
* This may cause some confusion in some cases - for example, if
* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
* priority interrupts will be masked in Critical Sections as those
* are at the same preemption priority. This may appear confusing as
* 4 is higher (numerically lower) priority than
* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
* to 4, this confusion does not happen and the behaviour remains the same.
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
{ {
/* Check the CMSIS configuration that defines the number of /* Check the CMSIS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
} }
#endif #endif
@ -438,7 +465,7 @@ BaseType_t xPortStartScheduler( void )
/* Check the FreeRTOS configuration that defines the number of /* Check the FreeRTOS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); configASSERT( ulImplementedPrioBits == configPRIO_BITS );
} }
#endif #endif

73
portable/GCC/ARM_CM4F/port.c
Unescape Escape View File

@ -251,11 +251,11 @@ static void prvTaskExitError( void )
void vPortSVCHandler( void ) void vPortSVCHandler( void )
{ {
__asm volatile ( __asm volatile (
" ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */ " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
" ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
" ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
" ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
" msr psp, r0 \n"/* Restore the task stack pointer. */ " msr psp, r0 \n" /* Restore the task stack pointer. */
" isb \n" " isb \n"
" mov r0, #0 \n" " mov r0, #0 \n"
" msr basepri, r0 \n" " msr basepri, r0 \n"
@ -274,17 +274,17 @@ static void prvPortStartFirstTask( void )
* would otherwise result in the unnecessary leaving of space in the SVC stack * would otherwise result in the unnecessary leaving of space in the SVC stack
* for lazy saving of FPU registers. */ * for lazy saving of FPU registers. */
__asm volatile ( __asm volatile (
" ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n" " ldr r0, [r0] \n"
" ldr r0, [r0] \n" " ldr r0, [r0] \n"
" msr msp, r0 \n"/* Set the msp back to the start of the stack. */ " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
" mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */ " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
" msr control, r0 \n" " msr control, r0 \n"
" cpsie i \n"/* Globally enable interrupts. */ " cpsie i \n" /* Globally enable interrupts. */
" cpsie f \n" " cpsie f \n"
" dsb \n" " dsb \n"
" isb \n" " isb \n"
" svc 0 \n"/* System call to start first task. */ " svc 0 \n" /* System call to start first task. */
" nop \n" " nop \n"
" .ltorg \n" " .ltorg \n"
); );
@ -305,6 +305,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 ) #if ( configASSERT_DEFINED == 1 )
{ {
volatile uint32_t ulOriginalPriority; volatile uint32_t ulOriginalPriority;
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue; volatile uint8_t ucMaxPriorityValue;
@ -336,20 +337,46 @@ BaseType_t xPortStartScheduler( void )
/* Calculate the maximum acceptable priority group value for the number /* Calculate the maximum acceptable priority group value for the number
* of bits read back. */ * of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{ {
ulMaxPRIGROUPValue--; ulImplementedPrioBits++;
ucMaxPriorityValue <<= ( uint8_t ) 0x01; ucMaxPriorityValue <<= ( uint8_t ) 0x01;
} }
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
* the software to configure PRIGROUP to not have sub-priorities. As
* a result, the least significant bit is always used for sub-priority
* and there are 128 preemption priorities and 2 sub-priorities.
*
* This may cause some confusion in some cases - for example, if
* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
* priority interrupts will be masked in Critical Sections as those
* are at the same preemption priority. This may appear confusing as
* 4 is higher (numerically lower) priority than
* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
* to 4, this confusion does not happen and the behaviour remains the same.
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
{ {
/* Check the CMSIS configuration that defines the number of /* Check the CMSIS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
} }
#endif #endif
@ -358,7 +385,7 @@ BaseType_t xPortStartScheduler( void )
/* Check the FreeRTOS configuration that defines the number of /* Check the FreeRTOS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); configASSERT( ulImplementedPrioBits == configPRIO_BITS );
} }
#endif #endif
@ -453,15 +480,15 @@ void xPortPendSVHandler( void )
" mrs r0, psp \n" " mrs r0, psp \n"
" isb \n" " isb \n"
" \n" " \n"
" ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */ " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
" ldr r2, [r3] \n" " ldr r2, [r3] \n"
" \n" " \n"
" tst r14, #0x10 \n"/* Is the task using the FPU context? If so, push high vfp registers. */ " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
" it eq \n" " it eq \n"
" vstmdbeq r0!, {s16-s31} \n" " vstmdbeq r0!, {s16-s31} \n"
" \n" " \n"
" stmdb r0!, {r4-r11, r14} \n"/* Save the core registers. */ " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */
" str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */ " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
" \n" " \n"
" stmdb sp!, {r0, r3} \n" " stmdb sp!, {r0, r3} \n"
" mov r0, %0 \n" " mov r0, %0 \n"
@ -473,12 +500,12 @@ void xPortPendSVHandler( void )
" msr basepri, r0 \n" " msr basepri, r0 \n"
" ldmia sp!, {r0, r3} \n" " ldmia sp!, {r0, r3} \n"
" \n" " \n"
" ldr r1, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */ " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
" ldr r0, [r1] \n" " ldr r0, [r1] \n"
" \n" " \n"
" ldmia r0!, {r4-r11, r14} \n"/* Pop the core registers. */ " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */
" \n" " \n"
" tst r14, #0x10 \n"/* Is the task using the FPU context? If so, pop the high vfp registers too. */ " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
" it eq \n" " it eq \n"
" vldmiaeq r0!, {s16-s31} \n" " vldmiaeq r0!, {s16-s31} \n"
" \n" " \n"
@ -772,10 +799,10 @@ static void vPortEnableVFP( void )
{ {
__asm volatile __asm volatile
( (
" ldr.w r0, =0xE000ED88 \n"/* The FPU enable bits are in the CPACR. */ " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
" ldr r1, [r0] \n" " ldr r1, [r0] \n"
" \n" " \n"
" orr r1, r1, #( 0xf << 20 ) \n"/* Enable CP10 and CP11 coprocessors, then save back. */ " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
" str r1, [r0] \n" " str r1, [r0] \n"
" bx r14 \n" " bx r14 \n"
" .ltorg \n" " .ltorg \n"

35
portable/GCC/ARM_CM4_MPU/port.c
Unescape Escape View File

@ -428,6 +428,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 ) #if ( configASSERT_DEFINED == 1 )
{ {
volatile uint32_t ulOriginalPriority; volatile uint32_t ulOriginalPriority;
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue; volatile uint8_t ucMaxPriorityValue;
@ -459,20 +460,46 @@ BaseType_t xPortStartScheduler( void )
/* Calculate the maximum acceptable priority group value for the number /* Calculate the maximum acceptable priority group value for the number
* of bits read back. */ * of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{ {
ulMaxPRIGROUPValue--; ulImplementedPrioBits++;
ucMaxPriorityValue <<= ( uint8_t ) 0x01; ucMaxPriorityValue <<= ( uint8_t ) 0x01;
} }
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
* the software to configure PRIGROUP to not have sub-priorities. As
* a result, the least significant bit is always used for sub-priority
* and there are 128 preemption priorities and 2 sub-priorities.
*
* This may cause some confusion in some cases - for example, if
* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
* priority interrupts will be masked in Critical Sections as those
* are at the same preemption priority. This may appear confusing as
* 4 is higher (numerically lower) priority than
* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
* to 4, this confusion does not happen and the behaviour remains the same.
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
{ {
/* Check the CMSIS configuration that defines the number of /* Check the CMSIS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
} }
#endif #endif
@ -481,7 +508,7 @@ BaseType_t xPortStartScheduler( void )
/* Check the FreeRTOS configuration that defines the number of /* Check the FreeRTOS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); configASSERT( ulImplementedPrioBits == configPRIO_BITS );
} }
#endif #endif

77
portable/GCC/ARM_CM7/r0p1/port.c
Unescape Escape View File

@ -245,11 +245,11 @@ static void prvTaskExitError( void )
void vPortSVCHandler( void ) void vPortSVCHandler( void )
{ {
__asm volatile ( __asm volatile (
" ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */ " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
" ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
" ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
" ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
" msr psp, r0 \n"/* Restore the task stack pointer. */ " msr psp, r0 \n" /* Restore the task stack pointer. */
" isb \n" " isb \n"
" mov r0, #0 \n" " mov r0, #0 \n"
" msr basepri, r0 \n" " msr basepri, r0 \n"
@ -268,17 +268,17 @@ static void prvPortStartFirstTask( void )
* would otherwise result in the unnecessary leaving of space in the SVC stack * would otherwise result in the unnecessary leaving of space in the SVC stack
* for lazy saving of FPU registers. */ * for lazy saving of FPU registers. */
__asm volatile ( __asm volatile (
" ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n" " ldr r0, [r0] \n"
" ldr r0, [r0] \n" " ldr r0, [r0] \n"
" msr msp, r0 \n"/* Set the msp back to the start of the stack. */ " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
" mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */ " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
" msr control, r0 \n" " msr control, r0 \n"
" cpsie i \n"/* Globally enable interrupts. */ " cpsie i \n" /* Globally enable interrupts. */
" cpsie f \n" " cpsie f \n"
" dsb \n" " dsb \n"
" isb \n" " isb \n"
" svc 0 \n"/* System call to start first task. */ " svc 0 \n" /* System call to start first task. */
" nop \n" " nop \n"
" .ltorg \n" " .ltorg \n"
); );
@ -293,6 +293,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 ) #if ( configASSERT_DEFINED == 1 )
{ {
volatile uint32_t ulOriginalPriority; volatile uint32_t ulOriginalPriority;
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue; volatile uint8_t ucMaxPriorityValue;
@ -324,20 +325,46 @@ BaseType_t xPortStartScheduler( void )
/* Calculate the maximum acceptable priority group value for the number /* Calculate the maximum acceptable priority group value for the number
* of bits read back. */ * of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{ {
ulMaxPRIGROUPValue--; ulImplementedPrioBits++;
ucMaxPriorityValue <<= ( uint8_t ) 0x01; ucMaxPriorityValue <<= ( uint8_t ) 0x01;
} }
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
* the software to configure PRIGROUP to not have sub-priorities. As
* a result, the least significant bit is always used for sub-priority
* and there are 128 preemption priorities and 2 sub-priorities.
*
* This may cause some confusion in some cases - for example, if
* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
* priority interrupts will be masked in Critical Sections as those
* are at the same preemption priority. This may appear confusing as
* 4 is higher (numerically lower) priority than
* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
* to 4, this confusion does not happen and the behaviour remains the same.
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
{ {
/* Check the CMSIS configuration that defines the number of /* Check the CMSIS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
} }
#endif #endif
@ -346,7 +373,7 @@ BaseType_t xPortStartScheduler( void )
/* Check the FreeRTOS configuration that defines the number of /* Check the FreeRTOS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); configASSERT( ulImplementedPrioBits == configPRIO_BITS );
} }
#endif #endif
@ -441,34 +468,34 @@ void xPortPendSVHandler( void )
" mrs r0, psp \n" " mrs r0, psp \n"
" isb \n" " isb \n"
" \n" " \n"
" ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */ " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
" ldr r2, [r3] \n" " ldr r2, [r3] \n"
" \n" " \n"
" tst r14, #0x10 \n"/* Is the task using the FPU context? If so, push high vfp registers. */ " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
" it eq \n" " it eq \n"
" vstmdbeq r0!, {s16-s31} \n" " vstmdbeq r0!, {s16-s31} \n"
" \n" " \n"
" stmdb r0!, {r4-r11, r14} \n"/* Save the core registers. */ " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */
" str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */ " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
" \n" " \n"
" stmdb sp!, {r0, r3} \n" " stmdb sp!, {r0, r3} \n"
" mov r0, %0 \n" " mov r0, %0 \n"
" cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
" msr basepri, r0 \n" " msr basepri, r0 \n"
" dsb \n" " dsb \n"
" isb \n" " isb \n"
" cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
" bl vTaskSwitchContext \n" " bl vTaskSwitchContext \n"
" mov r0, #0 \n" " mov r0, #0 \n"
" msr basepri, r0 \n" " msr basepri, r0 \n"
" ldmia sp!, {r0, r3} \n" " ldmia sp!, {r0, r3} \n"
" \n" " \n"
" ldr r1, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */ " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
" ldr r0, [r1] \n" " ldr r0, [r1] \n"
" \n" " \n"
" ldmia r0!, {r4-r11, r14} \n"/* Pop the core registers. */ " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */
" \n" " \n"
" tst r14, #0x10 \n"/* Is the task using the FPU context? If so, pop the high vfp registers too. */ " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
" it eq \n" " it eq \n"
" vldmiaeq r0!, {s16-s31} \n" " vldmiaeq r0!, {s16-s31} \n"
" \n" " \n"
@ -762,10 +789,10 @@ static void vPortEnableVFP( void )
{ {
__asm volatile __asm volatile
( (
" ldr.w r0, =0xE000ED88 \n"/* The FPU enable bits are in the CPACR. */ " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
" ldr r1, [r0] \n" " ldr r1, [r0] \n"
" \n" " \n"
" orr r1, r1, #( 0xf << 20 ) \n"/* Enable CP10 and CP11 coprocessors, then save back. */ " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
" str r1, [r0] \n" " str r1, [r0] \n"
" bx r14 \n" " bx r14 \n"
" .ltorg \n" " .ltorg \n"

35
portable/IAR/ARM_CM3/port.c
Unescape Escape View File

@ -211,6 +211,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 ) #if ( configASSERT_DEFINED == 1 )
{ {
volatile uint32_t ulOriginalPriority; volatile uint32_t ulOriginalPriority;
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue; volatile uint8_t ucMaxPriorityValue;
@ -242,20 +243,46 @@ BaseType_t xPortStartScheduler( void )
/* Calculate the maximum acceptable priority group value for the number /* Calculate the maximum acceptable priority group value for the number
* of bits read back. */ * of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{ {
ulMaxPRIGROUPValue--; ulImplementedPrioBits++;
ucMaxPriorityValue <<= ( uint8_t ) 0x01; ucMaxPriorityValue <<= ( uint8_t ) 0x01;
} }
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
* the software to configure PRIGROUP to not have sub-priorities. As
* a result, the least significant bit is always used for sub-priority
* and there are 128 preemption priorities and 2 sub-priorities.
*
* This may cause some confusion in some cases - for example, if
* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
* priority interrupts will be masked in Critical Sections as those
* are at the same preemption priority. This may appear confusing as
* 4 is higher (numerically lower) priority than
* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
* to 4, this confusion does not happen and the behaviour remains the same.
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
{ {
/* Check the CMSIS configuration that defines the number of /* Check the CMSIS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
} }
#endif #endif
@ -264,7 +291,7 @@ BaseType_t xPortStartScheduler( void )
/* Check the FreeRTOS configuration that defines the number of /* Check the FreeRTOS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); configASSERT( ulImplementedPrioBits == configPRIO_BITS );
} }
#endif #endif

35
portable/IAR/ARM_CM4F/port.c
Unescape Escape View File

@ -249,6 +249,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 ) #if ( configASSERT_DEFINED == 1 )
{ {
volatile uint32_t ulOriginalPriority; volatile uint32_t ulOriginalPriority;
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue; volatile uint8_t ucMaxPriorityValue;
@ -280,20 +281,46 @@ BaseType_t xPortStartScheduler( void )
/* Calculate the maximum acceptable priority group value for the number /* Calculate the maximum acceptable priority group value for the number
* of bits read back. */ * of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{ {
ulMaxPRIGROUPValue--; ulImplementedPrioBits++;
ucMaxPriorityValue <<= ( uint8_t ) 0x01; ucMaxPriorityValue <<= ( uint8_t ) 0x01;
} }
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
* the software to configure PRIGROUP to not have sub-priorities. As
* a result, the least significant bit is always used for sub-priority
* and there are 128 preemption priorities and 2 sub-priorities.
*
* This may cause some confusion in some cases - for example, if
* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
* priority interrupts will be masked in Critical Sections as those
* are at the same preemption priority. This may appear confusing as
* 4 is higher (numerically lower) priority than
* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
* to 4, this confusion does not happen and the behaviour remains the same.
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
{ {
/* Check the CMSIS configuration that defines the number of /* Check the CMSIS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
} }
#endif #endif
@ -302,7 +329,7 @@ BaseType_t xPortStartScheduler( void )
/* Check the FreeRTOS configuration that defines the number of /* Check the FreeRTOS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); configASSERT( ulImplementedPrioBits == configPRIO_BITS );
} }
#endif #endif

69
portable/IAR/ARM_CM4F_MPU/port.c
Unescape Escape View File

@ -194,7 +194,7 @@ extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
/** /**
* @brief Enter critical section. * @brief Enter critical section.
*/ */
#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL; void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
#else #else
void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
@ -203,7 +203,7 @@ extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
/** /**
* @brief Exit from critical section. * @brief Exit from critical section.
*/ */
#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL; void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
#else #else
void vPortExitCritical( void ) PRIVILEGED_FUNCTION; void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
@ -316,9 +316,9 @@ void vPortSVCHandler_C( uint32_t * pulParam )
{ {
__asm volatile __asm volatile
( (
" mrs r1, control \n"/* Obtain current control value. */ " mrs r1, control \n" /* Obtain current control value. */
" bic r1, r1, #1 \n"/* Set privilege bit. */ " bic r1, r1, #1 \n" /* Set privilege bit. */
" msr control, r1 \n"/* Write back new control value. */ " msr control, r1 \n" /* Write back new control value. */
::: "r1", "memory" ::: "r1", "memory"
); );
} }
@ -328,9 +328,9 @@ void vPortSVCHandler_C( uint32_t * pulParam )
case portSVC_RAISE_PRIVILEGE: case portSVC_RAISE_PRIVILEGE:
__asm volatile __asm volatile
( (
" mrs r1, control \n"/* Obtain current control value. */ " mrs r1, control \n" /* Obtain current control value. */
" bic r1, r1, #1 \n"/* Set privilege bit. */ " bic r1, r1, #1 \n" /* Set privilege bit. */
" msr control, r1 \n"/* Write back new control value. */ " msr control, r1 \n" /* Write back new control value. */
::: "r1", "memory" ::: "r1", "memory"
); );
break; break;
@ -352,6 +352,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) ); configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
#else #else
/* When using this port on a Cortex-M7 r0p0 or r0p1 core, define /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
* configENABLE_ERRATA_837070_WORKAROUND to 1 in your * configENABLE_ERRATA_837070_WORKAROUND to 1 in your
* FreeRTOSConfig.h. */ * FreeRTOSConfig.h. */
@ -362,6 +363,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 ) #if ( configASSERT_DEFINED == 1 )
{ {
volatile uint32_t ulOriginalPriority; volatile uint32_t ulOriginalPriority;
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue; volatile uint8_t ucMaxPriorityValue;
@ -393,20 +395,46 @@ BaseType_t xPortStartScheduler( void )
/* Calculate the maximum acceptable priority group value for the number /* Calculate the maximum acceptable priority group value for the number
* of bits read back. */ * of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{ {
ulMaxPRIGROUPValue--; ulImplementedPrioBits++;
ucMaxPriorityValue <<= ( uint8_t ) 0x01; ucMaxPriorityValue <<= ( uint8_t ) 0x01;
} }
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
* the software to configure PRIGROUP to not have sub-priorities. As
* a result, the least significant bit is always used for sub-priority
* and there are 128 preemption priorities and 2 sub-priorities.
*
* This may cause some confusion in some cases - for example, if
* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
* priority interrupts will be masked in Critical Sections as those
* are at the same preemption priority. This may appear confusing as
* 4 is higher (numerically lower) priority than
* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
* to 4, this confusion does not happen and the behaviour remains the same.
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
{ {
/* Check the CMSIS configuration that defines the number of /* Check the CMSIS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
} }
#endif #endif
@ -415,7 +443,7 @@ BaseType_t xPortStartScheduler( void )
/* Check the FreeRTOS configuration that defines the number of /* Check the FreeRTOS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); configASSERT( ulImplementedPrioBits == configPRIO_BITS );
} }
#endif #endif
@ -468,7 +496,7 @@ void vPortEndScheduler( void )
void vPortEnterCritical( void ) void vPortEnterCritical( void )
{ {
#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
if( portIS_PRIVILEGED() == pdFALSE ) if( portIS_PRIVILEGED() == pdFALSE )
{ {
portRAISE_PRIVILEGE(); portRAISE_PRIVILEGE();
@ -476,6 +504,7 @@ void vPortEnterCritical( void )
portDISABLE_INTERRUPTS(); portDISABLE_INTERRUPTS();
uxCriticalNesting++; uxCriticalNesting++;
/* This is not the interrupt safe version of the enter critical function so /* This is not the interrupt safe version of the enter critical function so
* assert() if it is being called from an interrupt context. Only API * assert() if it is being called from an interrupt context. Only API
* functions that end in "FromISR" can be used in an interrupt. Only assert if * functions that end in "FromISR" can be used in an interrupt. Only assert if
@ -485,6 +514,7 @@ void vPortEnterCritical( void )
{ {
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
} }
portMEMORY_BARRIER(); portMEMORY_BARRIER();
portRESET_PRIVILEGE(); portRESET_PRIVILEGE();
@ -494,6 +524,7 @@ void vPortEnterCritical( void )
{ {
portDISABLE_INTERRUPTS(); portDISABLE_INTERRUPTS();
uxCriticalNesting++; uxCriticalNesting++;
/* This is not the interrupt safe version of the enter critical function so /* This is not the interrupt safe version of the enter critical function so
* assert() if it is being called from an interrupt context. Only API * assert() if it is being called from an interrupt context. Only API
* functions that end in "FromISR" can be used in an interrupt. Only assert if * functions that end in "FromISR" can be used in an interrupt. Only assert if
@ -504,9 +535,10 @@ void vPortEnterCritical( void )
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
} }
} }
#else #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
portDISABLE_INTERRUPTS(); portDISABLE_INTERRUPTS();
uxCriticalNesting++; uxCriticalNesting++;
/* This is not the interrupt safe version of the enter critical function so /* This is not the interrupt safe version of the enter critical function so
* assert() if it is being called from an interrupt context. Only API * assert() if it is being called from an interrupt context. Only API
* functions that end in "FromISR" can be used in an interrupt. Only assert if * functions that end in "FromISR" can be used in an interrupt. Only assert if
@ -516,13 +548,13 @@ void vPortEnterCritical( void )
{ {
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
} }
#endif #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
void vPortExitCritical( void ) void vPortExitCritical( void )
{ {
#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
if( portIS_PRIVILEGED() == pdFALSE ) if( portIS_PRIVILEGED() == pdFALSE )
{ {
portRAISE_PRIVILEGE(); portRAISE_PRIVILEGE();
@ -535,6 +567,7 @@ void vPortExitCritical( void )
{ {
portENABLE_INTERRUPTS(); portENABLE_INTERRUPTS();
} }
portMEMORY_BARRIER(); portMEMORY_BARRIER();
portRESET_PRIVILEGE(); portRESET_PRIVILEGE();
@ -550,7 +583,7 @@ void vPortExitCritical( void )
portENABLE_INTERRUPTS(); portENABLE_INTERRUPTS();
} }
} }
#else #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
configASSERT( uxCriticalNesting ); configASSERT( uxCriticalNesting );
uxCriticalNesting--; uxCriticalNesting--;
@ -558,7 +591,7 @@ void vPortExitCritical( void )
{ {
portENABLE_INTERRUPTS(); portENABLE_INTERRUPTS();
} }
#endif #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/

35
portable/IAR/ARM_CM7/r0p1/port.c
Unescape Escape View File

@ -237,6 +237,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 ) #if ( configASSERT_DEFINED == 1 )
{ {
volatile uint32_t ulOriginalPriority; volatile uint32_t ulOriginalPriority;
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue; volatile uint8_t ucMaxPriorityValue;
@ -268,20 +269,46 @@ BaseType_t xPortStartScheduler( void )
/* Calculate the maximum acceptable priority group value for the number /* Calculate the maximum acceptable priority group value for the number
* of bits read back. */ * of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{ {
ulMaxPRIGROUPValue--; ulImplementedPrioBits++;
ucMaxPriorityValue <<= ( uint8_t ) 0x01; ucMaxPriorityValue <<= ( uint8_t ) 0x01;
} }
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
* the software to configure PRIGROUP to not have sub-priorities. As
* a result, the least significant bit is always used for sub-priority
* and there are 128 preemption priorities and 2 sub-priorities.
*
* This may cause some confusion in some cases - for example, if
* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
* priority interrupts will be masked in Critical Sections as those
* are at the same preemption priority. This may appear confusing as
* 4 is higher (numerically lower) priority than
* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
* to 4, this confusion does not happen and the behaviour remains the same.
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
{ {
/* Check the CMSIS configuration that defines the number of /* Check the CMSIS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
} }
#endif #endif
@ -290,7 +317,7 @@ BaseType_t xPortStartScheduler( void )
/* Check the FreeRTOS configuration that defines the number of /* Check the FreeRTOS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); configASSERT( ulImplementedPrioBits == configPRIO_BITS );
} }
#endif #endif

35
portable/MikroC/ARM_CM4F/port.c
Unescape Escape View File

@ -299,6 +299,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 ) #if ( configASSERT_DEFINED == 1 )
{ {
volatile uint32_t ulOriginalPriority; volatile uint32_t ulOriginalPriority;
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue; volatile uint8_t ucMaxPriorityValue;
@ -330,20 +331,46 @@ BaseType_t xPortStartScheduler( void )
/* Calculate the maximum acceptable priority group value for the number /* Calculate the maximum acceptable priority group value for the number
* of bits read back. */ * of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{ {
ulMaxPRIGROUPValue--; ulImplementedPrioBits++;
ucMaxPriorityValue <<= ( uint8_t ) 0x01; ucMaxPriorityValue <<= ( uint8_t ) 0x01;
} }
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
* the software to configure PRIGROUP to not have sub-priorities. As
* a result, the least significant bit is always used for sub-priority
* and there are 128 preemption priorities and 2 sub-priorities.
*
* This may cause some confusion in some cases - for example, if
* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
* priority interrupts will be masked in Critical Sections as those
* are at the same preemption priority. This may appear confusing as
* 4 is higher (numerically lower) priority than
* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
* to 4, this confusion does not happen and the behaviour remains the same.
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
{ {
/* Check the CMSIS configuration that defines the number of /* Check the CMSIS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
} }
#endif #endif
@ -352,7 +379,7 @@ BaseType_t xPortStartScheduler( void )
/* Check the FreeRTOS configuration that defines the number of /* Check the FreeRTOS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); configASSERT( ulImplementedPrioBits == configPRIO_BITS );
} }
#endif #endif

35
portable/RVDS/ARM_CM3/port.c
Unescape Escape View File

@ -264,6 +264,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 ) #if ( configASSERT_DEFINED == 1 )
{ {
volatile uint32_t ulOriginalPriority; volatile uint32_t ulOriginalPriority;
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue; volatile uint8_t ucMaxPriorityValue;
@ -295,20 +296,46 @@ BaseType_t xPortStartScheduler( void )
/* Calculate the maximum acceptable priority group value for the number /* Calculate the maximum acceptable priority group value for the number
* of bits read back. */ * of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{ {
ulMaxPRIGROUPValue--; ulImplementedPrioBits++;
ucMaxPriorityValue <<= ( uint8_t ) 0x01; ucMaxPriorityValue <<= ( uint8_t ) 0x01;
} }
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
* the software to configure PRIGROUP to not have sub-priorities. As
* a result, the least significant bit is always used for sub-priority
* and there are 128 preemption priorities and 2 sub-priorities.
*
* This may cause some confusion in some cases - for example, if
* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
* priority interrupts will be masked in Critical Sections as those
* are at the same preemption priority. This may appear confusing as
* 4 is higher (numerically lower) priority than
* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
* to 4, this confusion does not happen and the behaviour remains the same.
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
{ {
/* Check the CMSIS configuration that defines the number of /* Check the CMSIS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
} }
#endif #endif
@ -317,7 +344,7 @@ BaseType_t xPortStartScheduler( void )
/* Check the FreeRTOS configuration that defines the number of /* Check the FreeRTOS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); configASSERT( ulImplementedPrioBits == configPRIO_BITS );
} }
#endif #endif

35
portable/RVDS/ARM_CM4F/port.c
Unescape Escape View File

@ -330,6 +330,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 ) #if ( configASSERT_DEFINED == 1 )
{ {
volatile uint32_t ulOriginalPriority; volatile uint32_t ulOriginalPriority;
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue; volatile uint8_t ucMaxPriorityValue;
@ -361,20 +362,46 @@ BaseType_t xPortStartScheduler( void )
/* Calculate the maximum acceptable priority group value for the number /* Calculate the maximum acceptable priority group value for the number
* of bits read back. */ * of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{ {
ulMaxPRIGROUPValue--; ulImplementedPrioBits++;
ucMaxPriorityValue <<= ( uint8_t ) 0x01; ucMaxPriorityValue <<= ( uint8_t ) 0x01;
} }
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
* the software to configure PRIGROUP to not have sub-priorities. As
* a result, the least significant bit is always used for sub-priority
* and there are 128 preemption priorities and 2 sub-priorities.
*
* This may cause some confusion in some cases - for example, if
* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
* priority interrupts will be masked in Critical Sections as those
* are at the same preemption priority. This may appear confusing as
* 4 is higher (numerically lower) priority than
* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
* to 4, this confusion does not happen and the behaviour remains the same.
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
{ {
/* Check the CMSIS configuration that defines the number of /* Check the CMSIS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
} }
#endif #endif
@ -383,7 +410,7 @@ BaseType_t xPortStartScheduler( void )
/* Check the FreeRTOS configuration that defines the number of /* Check the FreeRTOS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); configASSERT( ulImplementedPrioBits == configPRIO_BITS );
} }
#endif #endif

55
portable/RVDS/ARM_CM4_MPU/port.c
Unescape Escape View File

@ -201,7 +201,7 @@ void vResetPrivilege( void );
/** /**
* @brief Enter critical section. * @brief Enter critical section.
*/ */
#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL; void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
#else #else
void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
@ -210,7 +210,7 @@ void vResetPrivilege( void );
/** /**
* @brief Exit from critical section. * @brief Exit from critical section.
*/ */
#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL; void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
#else #else
void vPortExitCritical( void ) PRIVILEGED_FUNCTION; void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
@ -412,6 +412,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) ); configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
#else #else
/* When using this port on a Cortex-M7 r0p0 or r0p1 core, define /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
* configENABLE_ERRATA_837070_WORKAROUND to 1 in your * configENABLE_ERRATA_837070_WORKAROUND to 1 in your
* FreeRTOSConfig.h. */ * FreeRTOSConfig.h. */
@ -422,7 +423,8 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 ) #if ( configASSERT_DEFINED == 1 )
{ {
volatile uint32_t ulOriginalPriority; volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue; volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API /* Determine the maximum priority from which ISR safe FreeRTOS API
@ -453,20 +455,46 @@ BaseType_t xPortStartScheduler( void )
/* Calculate the maximum acceptable priority group value for the number /* Calculate the maximum acceptable priority group value for the number
* of bits read back. */ * of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{ {
ulMaxPRIGROUPValue--; ulImplementedPrioBits++;
ucMaxPriorityValue <<= ( uint8_t ) 0x01; ucMaxPriorityValue <<= ( uint8_t ) 0x01;
} }
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
* the software to configure PRIGROUP to not have sub-priorities. As
* a result, the least significant bit is always used for sub-priority
* and there are 128 preemption priorities and 2 sub-priorities.
*
* This may cause some confusion in some cases - for example, if
* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
* priority interrupts will be masked in Critical Sections as those
* are at the same preemption priority. This may appear confusing as
* 4 is higher (numerically lower) priority than
* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
* to 4, this confusion does not happen and the behaviour remains the same.
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
{ {
/* Check the CMSIS configuration that defines the number of /* Check the CMSIS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
} }
#endif #endif
@ -475,7 +503,7 @@ BaseType_t xPortStartScheduler( void )
/* Check the FreeRTOS configuration that defines the number of /* Check the FreeRTOS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); configASSERT( ulImplementedPrioBits == configPRIO_BITS );
} }
#endif #endif
@ -559,7 +587,7 @@ void vPortEndScheduler( void )
void vPortEnterCritical( void ) void vPortEnterCritical( void )
{ {
#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
if( portIS_PRIVILEGED() == pdFALSE ) if( portIS_PRIVILEGED() == pdFALSE )
{ {
portRAISE_PRIVILEGE(); portRAISE_PRIVILEGE();
@ -577,16 +605,16 @@ void vPortEnterCritical( void )
portDISABLE_INTERRUPTS(); portDISABLE_INTERRUPTS();
uxCriticalNesting++; uxCriticalNesting++;
} }
#else #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
portDISABLE_INTERRUPTS(); portDISABLE_INTERRUPTS();
uxCriticalNesting++; uxCriticalNesting++;
#endif #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
void vPortExitCritical( void ) void vPortExitCritical( void )
{ {
#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
if( portIS_PRIVILEGED() == pdFALSE ) if( portIS_PRIVILEGED() == pdFALSE )
{ {
portRAISE_PRIVILEGE(); portRAISE_PRIVILEGE();
@ -599,6 +627,7 @@ void vPortExitCritical( void )
{ {
portENABLE_INTERRUPTS(); portENABLE_INTERRUPTS();
} }
portMEMORY_BARRIER(); portMEMORY_BARRIER();
portRESET_PRIVILEGE(); portRESET_PRIVILEGE();
@ -614,7 +643,7 @@ void vPortExitCritical( void )
portENABLE_INTERRUPTS(); portENABLE_INTERRUPTS();
} }
} }
#else #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
configASSERT( uxCriticalNesting ); configASSERT( uxCriticalNesting );
uxCriticalNesting--; uxCriticalNesting--;
@ -622,7 +651,7 @@ void vPortExitCritical( void )
{ {
portENABLE_INTERRUPTS(); portENABLE_INTERRUPTS();
} }
#endif #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/

35
portable/RVDS/ARM_CM7/r0p1/port.c
Unescape Escape View File

@ -314,6 +314,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 ) #if ( configASSERT_DEFINED == 1 )
{ {
volatile uint32_t ulOriginalPriority; volatile uint32_t ulOriginalPriority;
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue; volatile uint8_t ucMaxPriorityValue;
@ -345,20 +346,46 @@ BaseType_t xPortStartScheduler( void )
/* Calculate the maximum acceptable priority group value for the number /* Calculate the maximum acceptable priority group value for the number
* of bits read back. */ * of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{ {
ulMaxPRIGROUPValue--; ulImplementedPrioBits++;
ucMaxPriorityValue <<= ( uint8_t ) 0x01; ucMaxPriorityValue <<= ( uint8_t ) 0x01;
} }
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
* the software to configure PRIGROUP to not have sub-priorities. As
* a result, the least significant bit is always used for sub-priority
* and there are 128 preemption priorities and 2 sub-priorities.
*
* This may cause some confusion in some cases - for example, if
* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
* priority interrupts will be masked in Critical Sections as those
* are at the same preemption priority. This may appear confusing as
* 4 is higher (numerically lower) priority than
* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
* to 4, this confusion does not happen and the behaviour remains the same.
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
{ {
/* Check the CMSIS configuration that defines the number of /* Check the CMSIS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
} }
#endif #endif
@ -367,7 +394,7 @@ BaseType_t xPortStartScheduler( void )
/* Check the FreeRTOS configuration that defines the number of /* Check the FreeRTOS configuration that defines the number of
* priority bits matches the number of priority bits actually queried * priority bits matches the number of priority bits actually queried
* from the hardware. */ * from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); configASSERT( ulImplementedPrioBits == configPRIO_BITS );
} }
#endif #endif

1
portable/Tasking/ARM_CM4F/port.c
Unescape Escape View File

@ -267,4 +267,3 @@ void prvSetupTimerInterrupt( void )
*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
} }
/*-----------------------------------------------------------*/

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