github-forks
/
FreeRTOS-Kernel
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Removing the old -RV32 directory name from parts of the documentation (#1196)

Browse Source
pull/1197/head
Ryan 2 months ago committed by GitHub
parent 7e419c2dd5
commit 874fa7bed4
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
5 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File

4
portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
Unescape Escape View File

@ -31,7 +31,7 @@
* common across all currently supported RISC-V chips (implementations of the * common across all currently supported RISC-V chips (implementations of the
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip: * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
* *
* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
* is common to all currently supported RISC-V chips. There is only one * is common to all currently supported RISC-V chips. There is only one
* portASM.S file because the same file is built for all RISC-V target chips. * portASM.S file because the same file is built for all RISC-V target chips.
* *
@ -46,7 +46,7 @@
* compiler's!) include path. For example, if the chip in use includes a core * compiler's!) include path. For example, if the chip in use includes a core
* local interrupter (CLINT) and does not include any chip specific register * local interrupter (CLINT) and does not include any chip specific register
* extensions then add the path below to the assembler's include path: * extensions then add the path below to the assembler's include path:
* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
* *
*/ */

4
portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
Unescape Escape View File

@ -31,7 +31,7 @@
* common across all currently supported RISC-V chips (implementations of the * common across all currently supported RISC-V chips (implementations of the
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip: * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
* *
* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
* is common to all currently supported RISC-V chips. There is only one * is common to all currently supported RISC-V chips. There is only one
* portASM.S file because the same file is built for all RISC-V target chips. * portASM.S file because the same file is built for all RISC-V target chips.
* *
@ -46,7 +46,7 @@
* compiler's!) include path. For example, if the chip in use includes a core * compiler's!) include path. For example, if the chip in use includes a core
* local interrupter (CLINT) and does not include any chip specific register * local interrupter (CLINT) and does not include any chip specific register
* extensions then add the path below to the assembler's include path: * extensions then add the path below to the assembler's include path:
* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
* *
*/ */

4
portable/GCC/RISC-V/chip_specific_extensions/readme.txt
Unescape Escape View File

@ -3,7 +3,7 @@
* common across all currently supported RISC-V chips (implementations of the * common across all currently supported RISC-V chips (implementations of the
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip: * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
* *
* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
* is common to all currently supported RISC-V chips. There is only one * is common to all currently supported RISC-V chips. There is only one
* portASM.S file because the same file is built for all RISC-V target chips. * portASM.S file because the same file is built for all RISC-V target chips.
* *
@ -18,6 +18,6 @@
* compiler's!) include path. For example, if the chip in use includes a core * compiler's!) include path. For example, if the chip in use includes a core
* local interrupter (CLINT) and does not include any chip specific register * local interrupter (CLINT) and does not include any chip specific register
* extensions then add the path below to the assembler's include path: * extensions then add the path below to the assembler's include path:
* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
* *
*/ */

2
portable/GCC/RISC-V/portASM.S
Unescape Escape View File

@ -32,7 +32,7 @@
* RISC-V ISA), and code which tailors the port to a specific RISC-V chip: * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
* *
* + The code that is common to all RISC-V chips is implemented in * + The code that is common to all RISC-V chips is implemented in
* FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one * FreeRTOS\Source\portable\GCC\RISC-V\portASM.S. There is only one
* portASM.S file because the same file is used no matter which RISC-V chip is * portASM.S file because the same file is used no matter which RISC-V chip is
* in use. * in use.
* *

4
portable/GCC/RISC-V/readme.txt
Unescape Escape View File

@ -3,7 +3,7 @@
* common across all currently supported RISC-V chips (implementations of the * common across all currently supported RISC-V chips (implementations of the
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip: * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
* *
* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
* is common to all currently supported RISC-V chips. There is only one * is common to all currently supported RISC-V chips. There is only one
* portASM.S file because the same file is built for all RISC-V target chips. * portASM.S file because the same file is built for all RISC-V target chips.
* *
@ -18,6 +18,6 @@
* compiler's!) include path. For example, if the chip in use includes a core * compiler's!) include path. For example, if the chip in use includes a core
* local interrupter (CLINT) and does not include any chip specific register * local interrupter (CLINT) and does not include any chip specific register
* extensions then add the path below to the assembler's include path: * extensions then add the path below to the assembler's include path:
* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
* *
*/ */

Write Preview
Loading…
Cancel
Save