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Add in an FM3/IAR

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Richard Barry 14 years ago
parent 4de76dbc82
commit 80db62e711
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167
Demo/CORTEX_MB9B500_IAR_Keil/FreeRTOSConfig.h
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/*
FreeRTOS V7.0.0 - Copyright (C) 2011 Real Time Engineers Ltd.
FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:
Atollic AB - Atollic provides professional embedded systems development
tools for C/C++ development, code analysis and test automation.
See http://www.atollic.com
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
/* Use a guard to ensure the following few definitions are'nt included in
assembly files that include this header file. */
#ifndef __IASMARM__
#include <stdint.h>
extern uint32_t SystemCoreClock;
#endif
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( SystemCoreClock )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 90 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 30 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 0
#define configGENERATE_RUN_TIME_STATS 0
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 2 )
#define configTIMER_QUEUE_LENGTH 10
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
/* Use the system definition, if there is one */
#ifdef __NVIC_PRIO_BITS
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 4 /* 15 priority levels */
#endif
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* The lowest priority. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Priority 5, or 160 as only the top three bits are implemented. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
#define vPortSVCHandler SVC_Handler
#define xPortSysTickHandler SysTick_Handler
/* MAC address configuration. */
#define configMAC_ADDR0 0x00
#define configMAC_ADDR1 0x12
#define configMAC_ADDR2 0x13
#define configMAC_ADDR3 0x10
#define configMAC_ADDR4 0x15
#define configMAC_ADDR5 0x11
/* IP address configuration. */
#define configIP_ADDR0 192
#define configIP_ADDR1 168
#define configIP_ADDR2 0
#define configIP_ADDR3 200
/* Netmask configuration. */
#define configNET_MASK0 255
#define configNET_MASK1 255
#define configNET_MASK2 255
#define configNET_MASK3 0
#endif /* FREERTOS_CONFIG_H */

359
Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/core_cm3.c
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/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.40
* @date 18. February 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ########################## Core Instruction Access ######################### */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/**
* @brief Reverse byte order (16 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
#if (__ARMCC_VERSION < 400677)
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
#if (__ARMCC_VERSION < 400677)
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __CLREX(void)
{
clrex
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* obsolete */
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* obsolete */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* obsolete */
#endif
/* ########################### Core Function Access ########################### */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get IPSR Register value
*
* @return uint32_t IPSR value
*
* return the content of the IPSR register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_IPSR(void)
{
mrs r0, ipsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get APSR Register value
*
* @return uint32_t APSR value
*
* return the content of the APSR register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_APSR(void)
{
mrs r0, apsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get xPSR Register value
*
* @return uint32_t xPSR value
*
* return the content of the xPSR register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_xPSR(void)
{
mrs r0, xpsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the FPSCR value
*
* @return FloatingPointStatusControlRegister
*
* Return the content of the FPSCR register
*/
/**
* @brief Set the FPSCR value
*
* @param fpscr FloatingPointStatusControlRegister
*
* Set the FPSCR register
*/
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* obsolete */
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* obsolete */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* obsolete */
#endif

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Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/core_cm3.h
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Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/mb9bf506n.h
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Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/startup_iar/startup_mb9bf50x.s
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;/************************************************************************/
;/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
;/* */
;/* The following software deliverable is intended for and must only be */
;/* used for reference and in an evaluation laboratory environment. */
;/* It is provided on an as-is basis without charge and is subject to */
;/* alterations. */
;/* It is the user's obligation to fully test the software in its */
;/* environment and to ensure proper functionality, qualification and */
;/* compliance with component specifications. */
;/* */
;/* In the event the software deliverable includes the use of open */
;/* source components, the provisions of the governing open source */
;/* license agreement shall apply with respect to such software */
;/* deliverable. */
;/* FSEU does not warrant that the deliverables do not infringe any */
;/* third party intellectual property right (IPR). In the event that */
;/* the deliverables infringe a third party IPR it is the sole */
;/* responsibility of the customer to obtain necessary licenses to */
;/* continue the usage of the deliverable. */
;/* */
;/* To the maximum extent permitted by applicable law FSEU disclaims all */
;/* warranties, whether express or implied, in particular, but not */
;/* limited to, warranties of merchantability and fitness for a */
;/* particular purpose for which the deliverable is not designated. */
;/* */
;/* To the maximum extent permitted by applicable law, FSEU's liability */
;/* is restricted to intentional misconduct and gross negligence. */
;/* FSEU is not liable for consequential damages. */
;/* */
;/* (V1.5) */
;/************************************************************************/
;/* Startup for IAR */
;/* Version V1.02 */
;/* Date 2011-01-05 */
;/* Target-mcu MB9B5xx */
;/************************************************************************/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset
DCD NMI_Handler ; NMI
DCD HardFault_Handler ; Hard Fault
DCD MemManage_Handler ; MPU Fault
DCD BusFault_Handler ; Bus Fault
DCD UsageFault_Handler ; Usage Fault
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall
DCD DebugMon_Handler ; Debug Monitor
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV
DCD SysTick_Handler ; SysTick
DCD CSV_Handler ; 0: Clock Super Visor
DCD SWDT_Handler ; 1: Software Watchdog Timer
DCD LVD_Handler ; 2: Low Voltage Detector
DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF
DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15
DCD DT_Handler ; 6: Dual Timer / Quad Decoder
DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0
DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0
DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1
DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1
DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2
DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2
DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3
DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3
DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4
DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4
DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5
DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5
DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6
DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6
DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7
DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7
DCD PPG_Handler ; 23: PPG
DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter
DCD ADC0_IRQHandler ; 25: ADC0
DCD ADC1_IRQHandler ; 26: ADC1
DCD ADC2_IRQHandler ; 27: ADC2
DCD MFT_FRT_IRQHandler ; 28: Free-run Timer
DCD MFT_IPC_IRQHandler ; 29: Input Capture
DCD MFT_OPC_IRQHandler ; 30: Output Compare
DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7
DCD CAN0_IRQHandler ; 32: CAN ch.0
DCD CAN1_IRQHandler ; 33: CAN ch.1
DCD USBF_Handler ; 34: USB Function
DCD USB_Handler ; 35: USB Function / USB HOST
DCD DummyHandler ; 36: Reserved
DCD DummyHandler ; 37: Reserved
DCD DMAC0_Handler ; 38: DMAC ch.0
DCD DMAC1_Handler ; 39: DMAC ch.1
DCD DMAC2_Handler ; 40: DMAC ch.2
DCD DMAC3_Handler ; 41: DMAC ch.3
DCD DMAC4_Handler ; 42: DMAC ch.4
DCD DMAC5_Handler ; 43: DMAC ch.5
DCD DMAC6_Handler ; 44: DMAC ch.6
DCD DMAC7_Handler ; 45: DMAC ch.7
DCD DummyHandler ; 46: Reserved
DCD DummyHandler ; 47: Reserved
THUMB
; Dummy Exception Handlers (infinite loops which can be modified)
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK CSV_Handler
SECTION .text:CODE:REORDER(1)
CSV_Handler
B CSV_Handler
PUBWEAK SWDT_Handler
SECTION .text:CODE:REORDER(1)
SWDT_Handler
B SWDT_Handler
PUBWEAK LVD_Handler
SECTION .text:CODE:REORDER(1)
LVD_Handler
B LVD_Handler
PUBWEAK MFT_WG_IRQHandler
SECTION .text:CODE:REORDER(1)
MFT_WG_IRQHandler
B MFT_WG_IRQHandler
PUBWEAK INT0_7_Handler
SECTION .text:CODE:REORDER(1)
INT0_7_Handler
B INT0_7_Handler
PUBWEAK INT8_15_Handler
SECTION .text:CODE:REORDER(1)
INT8_15_Handler
B INT8_15_Handler
PUBWEAK DT_Handler
SECTION .text:CODE:REORDER(1)
DT_Handler
B DT_Handler
PUBWEAK MFS0RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS0RX_IRQHandler
B MFS0RX_IRQHandler
PUBWEAK MFS0TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS0TX_IRQHandler
B MFS0TX_IRQHandler
PUBWEAK MFS1RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS1RX_IRQHandler
B MFS1RX_IRQHandler
PUBWEAK MFS1TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS1TX_IRQHandler
B MFS1TX_IRQHandler
PUBWEAK MFS2RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS2RX_IRQHandler
B MFS2RX_IRQHandler
PUBWEAK MFS2TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS2TX_IRQHandler
B MFS2TX_IRQHandler
PUBWEAK MFS3RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS3RX_IRQHandler
B MFS3RX_IRQHandler
PUBWEAK MFS3TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS3TX_IRQHandler
B MFS3TX_IRQHandler
PUBWEAK MFS4RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS4RX_IRQHandler
B MFS4RX_IRQHandler
PUBWEAK MFS4TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS4TX_IRQHandler
B MFS4TX_IRQHandler
PUBWEAK MFS5RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS5RX_IRQHandler
B MFS5RX_IRQHandler
PUBWEAK MFS5TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS5TX_IRQHandler
B MFS5TX_IRQHandler
PUBWEAK MFS6RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS6RX_IRQHandler
B MFS6RX_IRQHandler
PUBWEAK MFS6TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS6TX_IRQHandler
B MFS6TX_IRQHandler
PUBWEAK MFS7RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS7RX_IRQHandler
B MFS7RX_IRQHandler
PUBWEAK MFS7TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS7TX_IRQHandler
B MFS7TX_IRQHandler
PUBWEAK PPG_Handler
SECTION .text:CODE:REORDER(1)
PPG_Handler
B PPG_Handler
PUBWEAK TIM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM_IRQHandler
B TIM_IRQHandler
PUBWEAK ADC0_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC0_IRQHandler
B ADC0_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK ADC2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC2_IRQHandler
B ADC2_IRQHandler
PUBWEAK MFT_FRT_IRQHandler
SECTION .text:CODE:REORDER(1)
MFT_FRT_IRQHandler
B MFT_FRT_IRQHandler
PUBWEAK MFT_IPC_IRQHandler
SECTION .text:CODE:REORDER(1)
MFT_IPC_IRQHandler
B MFT_IPC_IRQHandler
PUBWEAK MFT_OPC_IRQHandler
SECTION .text:CODE:REORDER(1)
MFT_OPC_IRQHandler
B MFT_OPC_IRQHandler
PUBWEAK BT_IRQHandler
SECTION .text:CODE:REORDER(1)
BT_IRQHandler
B BT_IRQHandler
PUBWEAK CAN0_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN0_IRQHandler
B CAN0_IRQHandler
PUBWEAK CAN1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_IRQHandler
B CAN1_IRQHandler
PUBWEAK USBF_Handler
SECTION .text:CODE:REORDER(1)
USBF_Handler
B USBF_Handler
PUBWEAK USB_Handler
SECTION .text:CODE:REORDER(1)
USB_Handler
B USB_Handler
PUBWEAK DMAC0_Handler
SECTION .text:CODE:REORDER(1)
DMAC0_Handler
B DMAC0_Handler
PUBWEAK DMAC1_Handler
SECTION .text:CODE:REORDER(1)
DMAC1_Handler
B DMAC1_Handler
PUBWEAK DMAC2_Handler
SECTION .text:CODE:REORDER(1)
DMAC2_Handler
B DMAC2_Handler
PUBWEAK DMAC3_Handler
SECTION .text:CODE:REORDER(1)
DMAC3_Handler
B DMAC3_Handler
PUBWEAK DMAC4_Handler
SECTION .text:CODE:REORDER(1)
DMAC4_Handler
B DMAC4_Handler
PUBWEAK DMAC5_Handler
SECTION .text:CODE:REORDER(1)
DMAC5_Handler
B DMAC5_Handler
PUBWEAK DMAC6_Handler
SECTION .text:CODE:REORDER(1)
DMAC6_Handler
B DMAC6_Handler
PUBWEAK DMAC7_Handler
SECTION .text:CODE:REORDER(1)
DMAC7_Handler
B DMAC7_Handler
PUBWEAK DummyHandler
SECTION .text:CODE:REORDER(1)
DummyHandler
B DummyHandler
END

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/************************************************************************/
/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
/* */
/* The following software deliverable is intended for and must only be */
/* used for reference and in an evaluation laboratory environment. */
/* It is provided on an as-is basis without charge and is subject to */
/* alterations. */
/* It is the user's obligation to fully test the software in its */
/* environment and to ensure proper functionality, qualification and */
/* compliance with component specifications. */
/* */
/* In the event the software deliverable includes the use of open */
/* source components, the provisions of the governing open source */
/* license agreement shall apply with respect to such software */
/* deliverable. */
/* FSEU does not warrant that the deliverables do not infringe any */
/* third party intellectual property right (IPR). In the event that */
/* the deliverables infringe a third party IPR it is the sole */
/* responsibility of the customer to obtain necessary licenses to */
/* continue the usage of the deliverable. */
/* */
/* To the maximum extent permitted by applicable law FSEU disclaims all */
/* warranties, whether express or implied, in particular, but not */
/* limited to, warranties of merchantability and fitness for a */
/* particular purpose for which the deliverable is not designated. */
/* */
/* To the maximum extent permitted by applicable law, FSEU's liability */
/* is restricted to intentional misconduct and gross negligence. */
/* FSEU is not liable for consequential damages. */
/* */
/* (V1.5) */
/************************************************************************/
#include <stdint.h>
#include "mb9bf506n.h"
/*--------------------- Clock Configuration ----------------------------------*/
//
// <e0> Clock Configuration
// <h> System Clock Configuration
// <o1.1> SCM_CTL.MOSCE: Main clock oscillation enable
// <o2.0..3> CSW_TMR.MOWT: Main clock stabilization wait time
// <i> Default: ~ 500 ns
// < 0=> ~ 500 ns
// < 1=> ~ 8 us
// < 2=> ~ 16 us
// < 3=> ~ 32 us
// < 4=> ~ 64 us
// < 5=> ~ 128 us
// < 6=> ~ 256 us
// < 7=> ~ 512 us
// < 8=> ~ 1.0 ms
// < 9=> ~ 2.0 ms
// <10=> ~ 4.0 ms
// <11=> ~ 8.0 ms
// <12=> ~ 33.0 ms
// <13=> ~ 131 ms
// <14=> ~ 524 ms
// <15=> ~ 2.0 s
// <o1.3> SCM_CTL.SOSCE: Sub clock oscillation enable
// <o2.4..6> CSW_TMR.SOWT: SOWT: Sub clock stabilization wait time
// <i> Default: ~ 31.19 ms
// <0=> ~ 31.19 ms
// <1=> ~ 62.44 ms
// <2=> ~ 0.125 s
// <3=> ~ 0.25 s
// <4=> ~ 0.50 s
// <5=> ~ 1.00 s
// <6=> ~ 2.00 s
// <7=> ~ 4.00 s
// <e1.4> SCM_CTL.PLLE: PLL oscillation enable
// <i> fPLLO Max = 120MHz, CLKPLL Min = 60MHz
// <i> CLKPLL = (CLKMO / PLLK) * PLLN
// <o4.4..7> PLL_CTL1.PLLK: PLL input clock frequency division
// <1-16><#-1>
// <o5.0..4> PLL_CTL1.PLLN: PLL feedback frequency division
// <1-32><#-1>
// <o4.0..3> PLL_CTL1.PLLM: PLL VCO clock frequency division
// <1-16><#-1>
// <o3.0..2> PSW_TMR.POWT: PLL clock stabilization wait time
// <i> Default: ~ 128 us
// <0=> ~ 128 us
// <1=> ~ 256 us
// <2=> ~ 512 us
// <3=> ~ 1.02 ms
// <4=> ~ 2.05 ms
// <5=> ~ 4.10 ms
// <6=> ~ 8.20 ms
// <7=> ~ 16.40 ms
// </e>
// <o1.5..7> SCM_CTL.RCS: Master clock switch control
// <i> Default: Master Clock = CLKHC
// <0=> Master Clock = CLKHC
// <1=> Master Clock = CLKMO
// <2=> Master Clock = CLKPLL
// <4=> Master Clock = CLKLC
// <5=> Master Clock = CLKSO
// </h>
//
// <h> Base Clock Prescaler
// <o6.0..2> BSC_PSR.BSR: Base clock frequency division
// <i> Default: HCLK = Master Clock
// <i> HCLK Max = 80MHz
// <0=> HCLK = Master Clock
// <1=> HCLK = Master Clock / 2
// <2=> HCLK = Master Clock / 3
// <3=> HCLK = Master Clock / 4
// <4=> HCLK = Master Clock / 6
// <5=> HCLK = Master Clock / 8
// <6=> HCLK = Master Clock / 16
// </h>
//
// <h> APB0 Prescaler
// <o7.0..1> APBC0_PSR.APBC0: APB0 bus clock frequency division
// <i> PCLK0 Max = 40MHz
// <i> Default: PCLK0 = HCLK
// <0=> PCLK0 = HCLK
// <1=> PCLK0 = HCLK / 2
// <2=> PCLK0 = HCLK / 4
// <3=> PCLK0 = HCLK / 8
// </h>
//
// <h> APB1 Prescaler
// <o8.0..1> APBC1_PSR.APBC1: APB1 bus clock frequency
// <i> PCLK1 Max = 40MHz
// <i> Default: PCLK1 = HCLK
// <0=> PCLK1 = HCLK
// <1=> PCLK1 = HCLK / 2
// <2=> PCLK1 = HCLK / 4
// <3=> PCLK1 = HCLK / 8
// <o8.7> APBC1_PSR.APBC1EN: APB1 clock enable
// </h>
//
// <h> APB2 Prescaler
// <o9.0..1> APBC2_PSR.APBC2: APB2 bus clock frequency
// <i> PCLK2 Max = 40MHz
// <i> Default: PCLK2 = HCLK
// <0=> PCLK2 = HCLK
// <1=> PCLK2 = HCLK / 2
// <2=> PCLK2 = HCLK / 4
// <3=> PCLK2 = HCLK / 8
// <o9.7> APBC2_PSR.APBC2EN: APB2 clock enable
// </h>
//
// <h> SW Watchdog Clock Prescaler
// <o10.0..1>SWC_PSR.SWDS: Software watchdog clock frequency division
// <i> Default: SWDGOGCLK = PCLK0
// <0=> SWDGOGCLK = PCLK0
// <1=> SWDGOGCLK = PCLK0 / 2
// <2=> SWDGOGCLK = PCLK0 / 4
// <3=> SWDGOGCLK = PCLK0 / 8
// </h>
//
// <h> Trace Clock Prescaler
// <o11.0> TTC_PSR.TTC: Trace clock frequency division
// <i> Default: TPIUCLK = HCLK
// <0=> TPIUCLK = HCLK
// <1=> TPIUCLK = HCLK / 2
// </h>
//
// </e>
#define CLOCK_SETUP 1
#define SCM_CTL_Val 0x00000052
#define CSW_TMR_Val 0x0000005C
#define PSW_TMR_Val 0x00000000
#define PLL_CTL1_Val 0x00000000
#define PLL_CTL2_Val 0x00000013
#define BSC_PSR_Val 0x00000000
#define APBC0_PSR_Val 0x00000001
#define APBC1_PSR_Val 0x00000082
#define APBC2_PSR_Val 0x00000081
#define SWC_PSR_Val 0x00000003
#define TTC_PSR_Val 0x00000000
/*--------------------- WatchDog Configuration -------------------------------*/
//
// <o0.0> HW Watchdog disable
#define HWWD_DISABLE 0x00000001
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
Check the register settings
*----------------------------------------------------------------------------*/
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
#define CHECK_RSVD(val, mask) (val & mask)
/* Clock Configuration -------------------------------------------------------*/
#if (CHECK_RSVD((SCM_CTL_Val), ~0x000000FA))
#error "SCM_CTL: Invalid values of reserved bits!"
#endif
#if ((SCM_CTL_Val & 0xE0) == 0x40) && ((SCM_CTL_Val & 0x10) != 0x10)
#error "SCM_CTL: CLKPLL is selected but PLL is not enabled!"
#endif
#if (CHECK_RSVD((CSW_TMR_Val), ~0x0000007F))
#error "CSW_TMR: Invalid values of reserved bits!"
#endif
#if ((SCM_CTL_Val & 0x10)) /* if PLL is used */
#if (CHECK_RSVD((PSW_TMR_val), ~0x00000007))
#error "PSW_TMR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FF))
#error "PLL_CTL1: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000001F))
#error "PLL_CTL2: Invalid values of reserved bits!"
#endif
#endif
#if (CHECK_RSVD((BSC_PSR_Val), ~0x00000007))
#error "BSC_PSR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((APBC0_PSR_Val), ~0x00000003))
#error "APBC0_PSR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((APBC1_PSR_Val), ~0x00000083))
#error "APBC1_PSR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((APBC2_PSR_Val), ~0x00000083))
#error "APBC2_PSR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((SWC_PSR_Val), ~0x00000003))
#error "SWC_PSR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((TTC_PSR_Val), ~0x00000001))
#error "TTC_PSR: Invalid values of reserved bits!"
#endif
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __CLKMO ( 4000000UL) /* External 4MHz Crystal */
#define __CLKSO ( 32768UL) /* External 32KHz Crystal */
#define __CLKHC ( 4000000UL) /* Internal 4MHz RC Oscillator */
#define __CLKLC ( 100000UL) /* Internal 100KHz RC Oscillator */
/* CLKPLL = (CLKMO / PLLK) * PLLN */
#define __PLLK (((PLL_CTL1_Val >> 4) & 0x0F) + 1)
#define __PLLN (((PLL_CTL2_Val ) & 0x1F) + 1)
#define __PLLCLK ((__CLKMO * __PLLN) / __PLLK)
/* Determine core clock frequency according to settings */
#if (((SCM_CTL_Val >> 5) & 0x07) == 0)
#define __MASTERCLK (__CLKHC)
#elif (((SCM_CTL_Val >> 5) & 0x07) == 1)
#define __MASTERCLK (__CLKMO)
#elif (((SCM_CTL_Val >> 5) & 0x07) == 2)
#define __MASTERCLK (__PLLCLK)
#elif (((SCM_CTL_Val >> 5) & 0x07) == 4)
#define __MASTERCLK (__CLKLC)
#elif (((SCM_CTL_Val >> 5) & 0x07) == 5)
#define __MASTERCLK (__CLKSO)
#else
#define __MASTERCLK (0UL)
#endif
#if ((BSC_PSR_Val & 0x07) == 0)
#define __HCLK (__MASTERCLK / 1)
#elif ((BSC_PSR_Val & 0x07) == 1)
#define __HCLK (__MASTERCLK / 2)
#elif ((BSC_PSR_Val & 0x07) == 2)
#define __HCLK (__MASTERCLK / 3)
#elif ((BSC_PSR_Val & 0x07) == 3)
#define __HCLK (__MASTERCLK / 4)
#elif ((BSC_PSR_Val & 0x07) == 4)
#define __HCLK (__MASTERCLK / 6)
#elif ((BSC_PSR_Val & 0x07) == 5)
#define __HCLK (__MASTERCLK / 8)
#elif ((BSC_PSR_Val & 0x07) == 6)
#define __HCLK (__MASTERCLK /16)
#else
#define __HCLK (0UL)
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __HCLK; /*!< System Clock Frequency (Core Clock)*/
/**
* Retrieve the system core clock
*
* @param none
* @return none
*
* @brief retrieve system core clock from register settings.
*/
void SystemCoreClockUpdate (void) {
uint32_t masterClk;
uint32_t u32RegisterRead;
switch ((FM3_CRG->SCM_CTL >> 5) & 0x07) {
case 0: /* internal High-speed Cr osc. */
masterClk = __CLKHC;
break;
case 1: /* external main osc. */
masterClk = __CLKMO;
break;
case 2: /* PLL clock */
u32RegisterRead = (__CLKMO * (((FM3_CRG->PLL_CTL2) & 0x1F) + 1));
masterClk = (u32RegisterRead / (((FM3_CRG->PLL_CTL1 >> 4) & 0x0F) + 1));
break;
case 4: /* internal Low-speed CR osc. */
masterClk = __CLKLC;
break;
case 5: /* external Sub osc. */
masterClk = __CLKSO;
break;
default:
masterClk = 0Ul;
break;
}
switch (FM3_CRG->BSC_PSR & 0x07) {
case 0:
SystemCoreClock = masterClk;
break;
case 1:
SystemCoreClock = masterClk / 2;
break;
case 2:
SystemCoreClock = masterClk / 3;
break;
case 3:
SystemCoreClock = masterClk / 4;
break;
case 4:
SystemCoreClock = masterClk / 6;
break;
case 5:
SystemCoreClock = masterClk /8;
break;
case 6:
SystemCoreClock = masterClk /16;
break;
default:
SystemCoreClock = 0Ul;
break;
}
}
/*
* Set CR Trimming Data
*
* @param none
* @return none
*
* @brief Update CR trimming with Flash
* trimming data.
*/
static void CrtrimSet(void)
{
/* CR Trimming Data */
if( 0x000003FF != (FM3_FLASH_IF->CRTRMM & 0x000003FF) )
{
/* UnLock (MCR_FTRM) */
FM3_CRTRIM->MCR_RLR = 0x1ACCE554;
/* Set MCR_FTRM */
FM3_CRTRIM->MCR_FTRM = FM3_FLASH_IF->CRTRMM;
/* Lock (MCR_FTRM) */
FM3_CRTRIM->MCR_RLR = 0x00000000;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void) {
uint32_t u32RegisterRead;
#if (HWWD_DISABLE) /* HW Watchdog Disable */
FM3_HWWDT->WDG_LCK = 0x1ACCE551; /* HW Watchdog Unlock */
FM3_HWWDT->WDG_LCK = 0xE5331AAE;
FM3_HWWDT->WDG_CTL = 0; /* HW Watchdog stop */
#endif
#if (CLOCK_SETUP) /* Clock Setup */
FM3_CRG->BSC_PSR = BSC_PSR_Val; /* set System Clock presacaler */
FM3_CRG->APBC0_PSR = APBC0_PSR_Val; /* set APB0 presacaler */
FM3_CRG->APBC1_PSR = APBC1_PSR_Val; /* set APB1 presacaler */
FM3_CRG->APBC2_PSR = APBC2_PSR_Val; /* set APB2 presacaler */
FM3_CRG->SWC_PSR = SWC_PSR_Val | (1UL << 7); /* set SW Watchdog presacaler */
FM3_CRG->TTC_PSR = TTC_PSR_Val; /* set Trace Clock presacaler */
FM3_CRG->CSW_TMR = CSW_TMR_Val; /* set oscillation stabilization wait time */
if (SCM_CTL_Val & (1UL << 1)) { /* Main clock oscillator enabled ? */
FM3_CRG->SCM_CTL |= (1UL << 1); /* enable main oscillator */
while (!(FM3_CRG->SCM_STR & (1UL << 1))); /* wait for Main clock oscillation stable */
}
if (SCM_CTL_Val & (1UL << 3)) { /* Sub clock oscillator enabled ? */
FM3_CRG->SCM_CTL |= (1UL << 3); /* enable sub oscillator */
while (!(FM3_CRG->SCM_STR & (1UL << 3))); /* wait for Sub clock oscillation stable */
}
FM3_CRG->PSW_TMR = PSW_TMR_Val; /* set PLL stabilization wait time */
FM3_CRG->PLL_CTL1 = PLL_CTL1_Val; /* set PLLM and PLLK */
FM3_CRG->PLL_CTL2 = PLL_CTL2_Val; /* set PLLN */
if (SCM_CTL_Val & (1UL << 4)) { /* PLL enabled ? */
FM3_CRG->SCM_CTL |= (1UL << 4); /* enable PLL */
while (!(FM3_CRG->SCM_STR & (1UL << 4))); /* wait for PLL stable */
}
FM3_CRG->SCM_CTL |= (SCM_CTL_Val & 0xE0); /* Set Master Clock switch */
do
{
u32RegisterRead = (FM3_CRG->SCM_CTL & 0xE0);
}while ((FM3_CRG->SCM_STR & 0xE0) != u32RegisterRead);
#endif
CrtrimSet();
}

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/************************************************************************/
/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
/* */
/* The following software deliverable is intended for and must only be */
/* used for reference and in an evaluation laboratory environment. */
/* It is provided on an as-is basis without charge and is subject to */
/* alterations. */
/* It is the user's obligation to fully test the software in its */
/* environment and to ensure proper functionality, qualification and */
/* compliance with component specifications. */
/* */
/* In the event the software deliverable includes the use of open */
/* source components, the provisions of the governing open source */
/* license agreement shall apply with respect to such software */
/* deliverable. */
/* FSEU does not warrant that the deliverables do not infringe any */
/* third party intellectual property right (IPR). In the event that */
/* the deliverables infringe a third party IPR it is the sole */
/* responsibility of the customer to obtain necessary licenses to */
/* continue the usage of the deliverable. */
/* */
/* To the maximum extent permitted by applicable law FSEU disclaims all */
/* warranties, whether express or implied, in particular, but not */
/* limited to, warranties of merchantability and fitness for a */
/* particular purpose for which the deliverable is not designated. */
/* */
/* To the maximum extent permitted by applicable law, FSEU's liability */
/* is restricted to intentional misconduct and gross negligence. */
/* FSEU is not liable for consequential damages. */
/* */
/* (V1.5) */
/************************************************************************/
#ifndef _SYSTEM_MB9B5XX_H_
#define _SYSTEM_MB9B5XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* Clock
*/
extern uint32_t SystemCoreClock; /* Core Clock CMSIS V 1.3 */
extern const uint32_t SystemFrequency; /* Master Clock */
extern uint32_t SysFreHCLK; /* HCLK */
extern uint32_t SysFrePCLK0; /* PCLK0 */
extern uint32_t SysFrePCLK1; /* PCLK1 */
extern uint32_t SysFrePCLK2; /* PCLK2 */
extern uint32_t SysFreTPIU; /* TPIU */
/*
* Setup the microcontroller system
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_MB9B5XX_H_ */

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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\RTOSDemo_IAR.ewp</path>
</project>
<batchBuild/>
</workspace>

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/*
FreeRTOS V7.0.0 - Copyright (C) 2011 Real Time Engineers Ltd.
FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:
Atollic AB - Atollic provides professional embedded systems development
tools for C/C++ development, code analysis and test automation.
See http://www.atollic.com
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
* main-blinky.c is included when the "Blinky" build configuration is used.
* main-full.c is included when the "Full" build configuration is used.
*
* main-blinky.c (this file) defines a very simple demo that creates two tasks,
* one queue, and one timer. It also demonstrates how Cortex-M3 interrupts can
* interact with FreeRTOS tasks/timers.
*
* This simple demo project runs on the SmartFusion A2F-EVAL-KIT evaluation
* board, which is populated with an A2F200M3F SmartFusion mixed signal FPGA.
* The A2F200M3F incorporates a Cortex-M3 microcontroller.
*
* The idle hook function:
* The idle hook function demonstrates how to query the amount of FreeRTOS heap
* space that is remaining (see vApplicationIdleHook() defined in this file).
*
* The main() Function:
* main() creates one software timer, one queue, and two tasks. It then starts
* the scheduler.
*
* The Queue Send Task:
* The queue send task is implemented by the prvQueueSendTask() function in
* this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
* block for 200 milliseconds, before sending the value 100 to the queue that
* was created within main(). Once the value is sent, the task loops back
* around to block for another 200 milliseconds.
*
* The Queue Receive Task:
* The queue receive task is implemented by the prvQueueReceiveTask() function
* in this file. prvQueueReceiveTask() sits in a loop that causes it to
* repeatedly attempt to read data from the queue that was created within
* main(). When data is received, the task checks the value of the data, and
* if the value equals the expected 100, toggles the green LED. The 'block
* time' parameter passed to the queue receive function specifies that the task
* should be held in the Blocked state indefinitely to wait for data to be
* available on the queue. The queue receive task will only leave the Blocked
* state when the queue send task writes to the queue. As the queue send task
* writes to the queue every 200 milliseconds, the queue receive task leaves
* the Blocked state every 200 milliseconds, and therefore toggles the LED
* every 200 milliseconds.
*
* The LED Software Timer and the Button Interrupt:
* The user button SW1 is configured to generate an interrupt each time it is
* pressed. The interrupt service routine switches an LED on, and resets the
* LED software timer. The LED timer has a 5000 millisecond (5 second) period,
* and uses a callback function that is defined to just turn the LED off again.
* Therefore, pressing the user button will turn the LED on, and the LED will
* remain on until a full five seconds pass without the button being pressed.
*/
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "timers.h"
/* Fujitsu drivers/libraries. */
#include "mb9bf506n.h"
#include "system_mb9bf50x.h"
/* Priorities at which the tasks are created. */
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The rate at which data is sent to the queue, specified in milliseconds, and
converted to ticks using the portTICK_RATE_MS constant. */
#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )
/* The number of items the queue can hold. This is 1 as the receive task
will remove items as they are added, meaning the send task should always find
the queue empty. */
#define mainQUEUE_LENGTH ( 1 )
/* The LED toggle by the queue receive task. */
#define mainTASK_CONTROLLED_LED 0x0100UL
/* The LED turned on by the button interrupt, and turned off by the LED timer. */
#define mainTIMER_CONTROLLED_LED 0x0200UL
/*-----------------------------------------------------------*/
/*
* Setup the NVIC, LED outputs, and button inputs.
*/
static void prvSetupHardware( void );
/*
* The tasks as described in the comments at the top of this file.
*/
static void prvQueueReceiveTask( void *pvParameters );
static void prvQueueSendTask( void *pvParameters );
/*
* The LED timer callback function. This does nothing but switch off the
* LED defined by the mainTIMER_CONTROLLED_LED constant.
*/
static void vLEDTimerCallback( xTimerHandle xTimer );
/*-----------------------------------------------------------*/
/* The queue used by both tasks. */
static xQueueHandle xQueue = NULL;
/* The LED software timer. This uses vLEDTimerCallback() as its callback
function. */
static xTimerHandle xLEDTimer = NULL;
/* Maintains the current LED output state. */
static volatile unsigned long ulGPIOState = 0xffffUL;
/*-----------------------------------------------------------*/
int main(void)
{
/* Configure the NVIC, LED outputs and button inputs. */
prvSetupHardware();
/* Create the queue. */
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
if( xQueue != NULL )
{
/* Start the two tasks as described in the comments at the top of this
file. */
xTaskCreate( prvQueueReceiveTask, ( signed char * ) "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL );
xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
/* Create the software timer that is responsible for turning off the LED
if the button is not pushed within 5000ms, as described at the top of
this file. */
xLEDTimer = xTimerCreate( ( const signed char * ) "LEDTimer", /* A text name, purely to help debugging. */
( 5000 / portTICK_RATE_MS ), /* The timer period, in this case 5000ms (5s). */
pdFALSE, /* This is a one shot timer, so xAutoReload is set to pdFALSE. */
( void * ) 0, /* The ID is not used, so can be set to anything. */
vLEDTimerCallback /* The callback function that switches the LED off. */
);
/* Start the tasks and timer running. */
vTaskStartScheduler();
}
/* If all is well, the scheduler will now be running, and the following line
will never be reached. If the following line does execute, then there was
insufficient FreeRTOS heap memory available for the idle and/or timer tasks
to be created. See the memory management section on the FreeRTOS web site
for more details. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void vLEDTimerCallback( xTimerHandle xTimer )
{
/* The timer has expired - so no button pushes have occurred in the last
five seconds - turn the LED off. NOTE - accessing the LED port should use
a critical section because it is accessed from multiple tasks, and the
button interrupt - in this trivial case, for simplicity, the critical
section is omitted. */
ulGPIOState |= mainTIMER_CONTROLLED_LED;
FM3_GPIO->PDOR3 = ulGPIOState;
}
/*-----------------------------------------------------------*/
/* The ISR executed when the user button is pushed. */
void INT0_7_Handler( void )
{
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
/* The button was pushed, so ensure the LED is on before resetting the
LED timer. The LED timer will turn the LED off if the button is not
pushed within 5000ms. */
ulGPIOState &= ~mainTIMER_CONTROLLED_LED;
FM3_GPIO->PDOR3 = ulGPIOState;
/* This interrupt safe FreeRTOS function can be called from this interrupt
because the interrupt priority is below the
configMAX_SYSCALL_INTERRUPT_PRIORITY setting in FreeRTOSConfig.h. */
xTimerResetFromISR( xLEDTimer, &xHigherPriorityTaskWoken );
/* Clear the interrupt before leaving. */
FM3_EXTI->EICL = 0x0000;
/* If calling xTimerResetFromISR() caused a task (in this case the timer
service/daemon task) to unblock, and the unblocked task has a priority
higher than or equal to the task that was interrupted, then
xHigherPriorityTaskWoken will now be set to pdTRUE, and calling
portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */
portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
}
/*-----------------------------------------------------------*/
static void prvQueueSendTask( void *pvParameters )
{
portTickType xNextWakeTime;
const unsigned long ulValueToSend = 100UL;
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again.
The block time is specified in ticks, the constant used converts ticks
to ms. While in the Blocked state this task will not consume any CPU
time. */
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
/* Send to the queue - causing the queue receive task to unblock and
toggle an LED. 0 is used as the block time so the sending operation
will not block - it shouldn't need to block as the queue should always
be empty at this point in the code. */
xQueueSend( xQueue, &ulValueToSend, 0 );
}
}
/*-----------------------------------------------------------*/
static void prvQueueReceiveTask( void *pvParameters )
{
unsigned long ulReceivedValue;
for( ;; )
{
/* Wait until something arrives in the queue - this task will block
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
FreeRTOSConfig.h. */
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
/* To get here something must have been received from the queue, but
is it the expected value? If it is, toggle the green LED. */
if( ulReceivedValue == 100UL )
{
/* NOTE - accessing the LED port should use a critical section
because it is accessed from multiple tasks, and the button interrupt
- in this trivial case, for simplicity, the critical section is
omitted. */
if( ( ulGPIOState & mainTASK_CONTROLLED_LED ) != 0 )
{
ulGPIOState &= ~mainTASK_CONTROLLED_LED;
}
else
{
ulGPIOState |= mainTASK_CONTROLLED_LED;
}
FM3_GPIO->PDOR3 = ulGPIOState;
}
}
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
SystemInit();
SystemCoreClockUpdate();
/* No analog inputs. */
FM3_GPIO->ADE = 0x00FF;
/* LED seg1 to GPIO output (P18->P1F). */
FM3_GPIO->DDR1 = 0xFF00;
FM3_GPIO->PFR1 = 0x0000;
/* LED seg2 to GPIO output (P30->P3F). */
FM3_GPIO->DDR3 = 0xFF00;
FM3_GPIO->PFR3 = 0x0000;
/* Start with all LEDs off. */
FM3_GPIO->PDOR3 = ulGPIOState;
FM3_GPIO->PDOR1 = ulGPIOState;
/* Set the switches to input (P18->P1F). */
FM3_GPIO->DDR5 = 0x0000;
FM3_GPIO->PFR5 = 0x0000;
/* setting INT02_1 */
/* MB9BF500(120pin) pin63->P11,AN01,SIN1_1,INT02_1,RX1_2 */
// GPIO->EPFR06 = 0x00000020; /* bit5,4:EINT02S=0b10 EINT-ch2 use INT02_1 */
// GPIO->ADE &= 0xFFFD; /* bit2:ADE2=0b0 AN01pin use digital input/output pin */
// GPIO->PFR1 |= 0x0002; /* bit2:PFR1_2=0b1 P11pin use peripheral port */
/* I/O port setting end */
FM3_EXTI->ENIR = 0x0000; /* INT interrupt disable */
FM3_EXTI->ELVR = 0x0030; /* bit5,4:LB2,LA2=0b11 INT2 low level edge */
FM3_EXTI->EICL = 0x0000; /* bit2:ECL=0b0 INT2 interrupt request clear */
// FM3_EXTI->ENIR = 0x0004; /* bit2:EN2=0b1 enable INT2 */
FM3_EXTI->ENIR = 0x0001; /* Enable INT0. */
/* Setup the GPIO and the NVIC for the switch used in this simple demo. */
NVIC_SetPriority( EXINT0_7_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
NVIC_EnableIRQ( EXINT0_7_IRQn );
// MSS_GPIO_config( MSS_GPIO_8, MSS_GPIO_INPUT_MODE | MSS_GPIO_IRQ_EDGE_NEGATIVE );
// MSS_GPIO_enable_irq( MSS_GPIO_8 );
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* Called if a call to pvPortMalloc() fails because there is insufficient
free memory available in the FreeRTOS heap. pvPortMalloc() is called
internally by FreeRTOS API functions that create tasks, queues, software
timers, and semaphores. The size of the FreeRTOS heap is set by the
configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
function is called if a stack overflow is detected. */
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
volatile size_t xFreeStackSpace;
/* This function is called on each cycle of the idle task. In this case it
does nothing useful, other than report the amout of FreeRTOS heap that
remains unallocated. */
xFreeStackSpace = xPortGetFreeHeapSize();
if( xFreeStackSpace > 100 )
{
/* By now, the kernel has allocated everything it is going to, so
if there is a lot of heap remaining unallocated then
the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be
reduced accordingly. */
}
}
/*-----------------------------------------------------------*/
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