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Add Dave project for the XMC4500.

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pull/4/head
Richard Barry 12 years ago
parent d1d925ab36
commit 6acac72ff1
14 changed files with 6481 additions and 0 deletions
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106
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/.cproject
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?>
<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.ifx.xmc4000.appDebug.607051084">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ifx.xmc4000.appDebug.607051084" moduleId="org.eclipse.cdt.core.settings" name="XMC4500">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.ifx.xmc4000.errorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactName="${ProjName}" buildArtefactType="com.ifx.xmc4000.appBuildArtefactType" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=com.ifx.xmc4000.appBuildArtefactType" description="" id="com.ifx.xmc4000.appDebug.607051084" name="XMC4500" parent="com.ifx.xmc4000.appDebug">
<folderInfo id="com.ifx.xmc4000.appDebug.607051084." name="/" resourcePath="">
<toolChain id="com.ifx.xmc4000.appDebug.toolChain.1759539149" name="ARM-GCC Application for XMC" superClass="com.ifx.xmc4000.appDebug.toolChain">
<option id="com.ifx.xmc4000.option.debugging.level.1802412347" name="Debug level" superClass="com.ifx.xmc4000.option.debugging.level" value="org.eclipse.cdt.cross.arm.gnu.base.option.debugging.level.max" valueType="enumerated"/>
<option id="com.ifx.xmc4000.option.targetPath.75554300" name="Target Path" superClass="com.ifx.xmc4000.option.targetPath" value="/ProcessorsInfo/XMC4000/XMC4500 Series/XMC4500-F144x1024" valueType="string"/>
<option id="com.ifx.xmc4000.option.targetName.1214792959" name="Target Name" superClass="com.ifx.xmc4000.option.targetName" value="XMC4500-F144x1024" valueType="string"/>
<option id="com.ifx.xmc4000.option.startupFilePrefrence.2100908094" name="Startup File Preference" superClass="com.ifx.xmc4000.option.startupFilePrefrence" value="true" valueType="boolean"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.ifx.xmc4000.targetPlatform.1734084429" isAbstract="false" name="Windows Platform" osList="win32" superClass="com.ifx.xmc4000.targetPlatform"/>
<builder buildPath="${workspace_loc:/RTOSDemo/Debug}" id="com.ifx.XMC4000.toolchainBuilder.1543365862" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="XMC Builder" superClass="com.ifx.XMC4000.toolchainBuilder"/>
<tool id="com.ifx.xmc4000.appDebug.compiler.1635621846" name="ARM-GCC C Compiler" superClass="com.ifx.xmc4000.appDebug.compiler">
<option id="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.optimization.level.1306428872" name="Optimization level" superClass="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.optimization.level" value="org.eclipse.cdt.cross.arm.gnu.base.option.optimization.level.none" valueType="enumerated"/>
<option id="com.ifx.xmc4000.compiler.option.include.paths.2132094169" name="Include paths (-I)" superClass="com.ifx.xmc4000.compiler.option.include.paths" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Common_Demo_Source/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/ARM_CM4F}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${ARM_GCC_HOME}/arm-none-eabi/include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../emWin/Start/GUI/inc&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/XMC4500_series/Include&quot;"/>
</option>
<option id="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.preprocessor.def.597668784" name="Defined symbols (-D)" superClass="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.preprocessor.def" valueType="definedSymbols">
<listOptionValue builtIn="false" value="UC_ID=4502"/>
</option>
<inputType id="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input.947657962" superClass="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input"/>
</tool>
<tool id="com.ifx.xmc4000.appDebug.cppcompiler.1089177015" name="ARM-GCC C++ Compiler" superClass="com.ifx.xmc4000.appDebug.cppcompiler">
<option id="org.eclipse.cdt.cross.arm.gnu.cpp.compiler.option.optimization.level.478794105" name="Optimization level" superClass="org.eclipse.cdt.cross.arm.gnu.cpp.compiler.option.optimization.level" value="org.eclipse.cdt.cross.arm.gnu.base.option.optimization.level.none" valueType="enumerated"/>
<option id="com.ifx.xmc4000.cppcompiler.option.include.paths.1815651512" name="Include paths (-I)" superClass="com.ifx.xmc4000.cppcompiler.option.include.paths" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${ARM_GCC_HOME}/arm-none-eabi/include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../emWin/Start/GUI/inc&quot;"/>
<listOptionValue builtIn="false" value="&quot;${ARM_GCC_HOME}/arm-none-eabi/include/c++/4.6.2&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/XMC4500_series/Include&quot;"/>
</option>
</tool>
<tool id="com.ifx.xmc4000.appDebug.assembler.1113299181" name="ARM-GCC Assembler" superClass="com.ifx.xmc4000.appDebug.assembler">
<option id="org.eclipse.cdt.cross.arm.gnu.assembler.option.preprocessor.def.1414012373" name="Defined symbols (-D)" superClass="org.eclipse.cdt.cross.arm.gnu.assembler.option.preprocessor.def" valueType="definedSymbols">
<listOptionValue builtIn="false" value="UC_ID=4502"/>
</option>
<inputType id="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input.859825253" superClass="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input"/>
</tool>
<tool id="com.ifx.xmc4000.appDebug.linker.540417974" name="ARM-GCC C Linker" superClass="com.ifx.xmc4000.appDebug.linker">
<option id="com.ifx.xmc4000.appLinker.option.scriptfile.1274916363" name="Script file (-T)" superClass="com.ifx.xmc4000.appLinker.option.scriptfile" value="../LinkerScripts/RTOSDemo_XMC4500.ld" valueType="string"/>
<inputType id="com.ifx.xmc4000.appLinker.inputType.193148015" name="ARM-GCC for XMC Linker Input Type" superClass="com.ifx.xmc4000.appLinker.inputType">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
</tool>
<tool id="com.ifx.xmc4000.appDebug.cpplinker.1425994416" name="ARM-GCC C++ Linker" superClass="com.ifx.xmc4000.appDebug.cpplinker"/>
<tool id="com.ifx.xmc4000.libLinker.1022326266" name="ARM-GCC Archiver" superClass="com.ifx.xmc4000.libLinker"/>
<tool id="com.ifx.xmc4000.appDebug.createflash.496475414" name="ARM-GCC Create Flash Image" superClass="com.ifx.xmc4000.appDebug.createflash"/>
<tool id="com.ifx.xmc4000.appDebug.createlisting.130181717" name="ARM-GCC Create Listing" superClass="com.ifx.xmc4000.appDebug.createlisting"/>
<tool id="com.ifx.xmc4000.printsize.1124241582" name="ARM-GCC Print Size" superClass="com.ifx.xmc4000.printsize"/>
</toolChain>
</folderInfo>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="RTOSDemo.com.ifx.xmc4000.appProject.1454830415" name="ARM-GCC Application for XMC Project" projectType="com.ifx.xmc4000.appProject"/>
</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="com.ifx.xmc4000.appRelease.1833453587;com.ifx.xmc4000.appRelease.1833453587.;com.ifx.xmc4000.appRelease.compiler.1453708254;org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input.403412067">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.cross.arm.gnu.ARM_CS_GCCWinManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.ifx.xmc4000.appRelease.1833453587;com.ifx.xmc4000.appRelease.1833453587.;com.ifx.xmc4000.appRelease.assembler.1016067260;org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input.1614170329">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.cross.arm.gnu.ARM_CS_GCCWinManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.ifx.xmc4000.appDebug.607051084;com.ifx.xmc4000.appDebug.607051084.;com.ifx.xmc4000.appDebug.compiler.1635621846;org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input.947657962">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.cross.arm.gnu.ARM_CS_GCCWinManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.ifx.xmc4000.appDebug.607051084;com.ifx.xmc4000.appDebug.607051084.;com.ifx.xmc4000.appDebug.assembler.1113299181;org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input.859825253">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.cross.arm.gnu.ARM_CS_GCCWinManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
<project-mappings/>
</storageModule>
<storageModule moduleId="refreshScope"/>
</cproject>

84
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/.project
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>RTOSDemo</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
<dictionary>
<key>?name?</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.append_environment</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildArguments</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildCommand</key>
<value>&quot;${ARM_GCC_HOME}/bin/make&quot;</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildLocation</key>
<value>${workspace_loc:/RTOSDemo/Debug}</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
<value>clean</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.contents</key>
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
<value>false</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
<value>true</value>
</dictionary>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>com.ifx.xmc4000.xmc4000Nature</nature>
<nature>com.dave.common.daveBenchNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
</projectDescription>

3
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/.settings/com.dave.mbs.xc800.prefs
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ACTIVE_CONFIG_NAME=Debug
MBS_PROVIDER_ID_KEY=com.dave.mbs.xmc4000.xmc4000MbsFactory
eclipse.preferences.version=1

31
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/ARM_toolset_settings_XMC4500.jlink
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[BREAKPOINTS]
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="UNSPECIFIED"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

55
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/CreateProjectDirectoryStructure.bat
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REM This file should be executed from the command line prior to the first
REM build. It will be necessary to refresh the Eclipse project once the
REM .bat file has been executed (normally just press F5 to refresh).
REM Copies all the required files from their location within the standard
REM FreeRTOS directory structure to under the Eclipse project directory.
REM This permits the Eclipse project to be used in 'managed' mode and without
REM having to setup any linked resources.
REM Standard paths
SET FREERTOS_SOURCE=..\..\Source
SET COMMON_SOURCE=..\Common\minimal
SET COMMON_INCLUDE=..\Common\include
REM Have the files already been copied?
IF EXIST FreeRTOS_Source Goto END
REM Create the required directory structure.
MD FreeRTOS_Source
MD FreeRTOS_Source\include
MD FreeRTOS_Source\portable
MD FreeRTOS_Source\portable\GCC
MD FreeRTOS_Source\portable\GCC\ARM_CM4F
MD FreeRTOS_Source\portable\MemMang
MD Common_Demo_Source
MD Common_Demo_Source\include
REM Copy the core kernel files into the SDK projects directory
copy %FREERTOS_SOURCE%\tasks.c FreeRTOS_Source
copy %FREERTOS_SOURCE%\queue.c FreeRTOS_Source
copy %FREERTOS_SOURCE%\list.c FreeRTOS_Source
copy %FREERTOS_SOURCE%\timers.c FreeRTOS_Source
REM Copy the common header files into the SDK projects directory
copy %FREERTOS_SOURCE%\include\*.* FreeRTOS_Source\include
REM Copy the portable layer files into the projects directory
copy %FREERTOS_SOURCE%\portable\GCC\ARM_CM4F\*.* FreeRTOS_Source\portable\GCC\ARM_CM4F
REM Copy the basic memory allocation files into the SDK projects directory
copy %FREERTOS_SOURCE%\portable\MemMang\heap_4.c FreeRTOS_Source\portable\MemMang
REM Copy the files that define the common demo tasks.
copy %COMMON_SOURCE%\dynamic.c Common_Demo_Source
copy %COMMON_SOURCE%\blocktim.c Common_Demo_Source
copy %COMMON_SOURCE%\semtest.c Common_Demo_Source
copy %COMMON_SOURCE%\GenQTest.c Common_Demo_Source
copy %COMMON_SOURCE%\recmutex.c Common_Demo_Source
copy %COMMON_SOURCE%\sp_flop.c Common_Demo_Source
copy %COMMON_SOURCE%\countsem.c Common_Demo_Source
REM Copy the common demo file headers.
copy %COMMON_INCLUDE%\*.h Common_Demo_Source\include
: END

196
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/FreeRTOSConfig.h
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/*
FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to distribute
>>! a combined work that includes FreeRTOS without being obliged to provide
>>! the source code for proprietary components outside of the FreeRTOS
>>! kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#include <stdint.h>
extern uint32_t SystemCoreClock;
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( SystemCoreClock )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 22800 ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 1
#define configGENERATE_RUN_TIME_STATS 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 2 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 6 /* 63 priority levels */
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x3f
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names. */
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
#define xPortSysTickHandler SysTick_Handler
/* Demo application specific settings. */
#if UC_ID == 4502
/* Hardware includes. */
#include "XMC4500.h"
#include "System_XMC4500.h"
/* Configure pin P3.9 for the LED. */
#define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 )
/* To toggle the single LED */
#define configTOGGLE_LED() ( PORT3->OMR = 0x02000200 )
#elif defined( PART_XMC4400 )
/* Hardware includes. */
#include "XMC4400.h"
#include "System_XMC4200.h"
/* Configure pin P5.2 for the LED. */
#define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 )
/* To toggle the single LED */
#define configTOGGLE_LED() ( PORT5->OMR = 0x00040004 )
#elif defined( PART_XMC4200 )
/* Hardware includes. */
#include "XMC4200.h"
#include "System_XMC4200.h"
/* Configure pin P2.1 for the LED. */
#define configCONFIGURE_LED() PORT2->IOCR0 = 0x00008000; PORT2->HWSEL &= ~0x0000000cUL
/* To toggle the single LED */
#define configTOGGLE_LED() ( PORT2->OMR = 0x00020002 )
#else
#error Part number not specified in project options
#endif
#endif /* FREERTOS_CONFIG_H */

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FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/GPIO.h
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FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/LinkerScripts/RTOSDemo_XMC4500.ld
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/* Generated Linker Script file */
/*
* Template Version 1.0 dated 11 Oct 2012
*/
OUTPUT_FORMAT("elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(__Xmc4500_reset_cortex_m)
GROUP(-lxmclibcstubs)
MEMORY
{
FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0x100000
FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0x100000
PSRAM_1(!RX) : ORIGIN = 0x10000000, LENGTH = 0x10000
DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x10000
DSRAM_2_comm(!RX) : ORIGIN = 0x30000000, LENGTH = 0x8000
}
stack_size = 2048;
SECTIONS
{
/* TEXT section */
.text : AT(ORIGIN(FLASH_1_uncached))
{
sText = .;
*(.Xmc4500.reset);
*(.Xmc4500.postreset);
*(.XmcStartup);
*(.text .text.* .gnu.linkonce.t.*);
/* ARM <->THUMB interworking */
*(.glue*)
*(.v4*)
*(.vfp11_veneer)
/* C++ Support */
KEEP(*(.init))
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
KEEP(*(.fini))
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
/* Exception handling support */
__extab_start = .;
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(4);
__extab_end = ABSOLUTE(.);
} > FLASH_1_cached
/* Exception handling, exidx needs a dedicated section */
.ARM.exidx ABSOLUTE(__extab_end): AT(__extab_end | 0x04000000)
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
. = ALIGN(4);
__exidx_end = ABSOLUTE(.);
} > FLASH_1_cached
/* CONST data section */
.rodata ABSOLUTE(__exidx_end): AT(__exidx_end | 0x04000000)
{
*(.rodata .rodata.*)
*(.gnu.linkonce.r*)
} > FLASH_1_cached
. = ALIGN(16);
/* End of RO-DATA and start of LOAD region for DATA */
eROData = . | 0x04000000;
/* DSRAM layout (Lowest to highest)*/
/* Fully Descending Stack <-> BSS <-> DATA <-> HEAP */
/* Dummy section for stack */
Stack (NOLOAD) :
{
. = . + stack_size;
__Xmc4500_stack = .;
} > DSRAM_1_system
Communication_Buffers :
{
*DMA_Descriptors.o (COMMON);
} > DSRAM_2_comm
/* BSS section */
.bss :
{
__Xmc4500_sBSS = .;
* (.bss);
* (.bss*);
* (EXCLUDE_FILE(*DMA_Descriptors.o) COMMON);
*(.gnu.linkonce.b*)
__Xmc4500_eBSS = ALIGN(4);
} > DSRAM_1_system
/* Yes, the size must be kept outside */
__Xmc4500_BSS_Size = __Xmc4500_eBSS - __Xmc4500_sBSS;
/* Standard DATA and user defined DATA/BSS/CONST sections */
.data ABSOLUTE(ALIGN(16)): AT(eROData)
{
__Xmc4500_sData = .;
* (.data);
* (.data*);
*(*.data);
*(.gnu.linkonce.d*)
__Xmc4500_eData = ALIGN(4);
} > DSRAM_1_system
/* Yes, the size must be kept outside */
__Xmc4500_Data_Size = __Xmc4500_eData - __Xmc4500_sData;
/* Heap - Bank1*/
__Xmc4500_heap_start = ALIGN(8);
__Xmc4500_heap_end = ORIGIN(DSRAM_1_system) + LENGTH (DSRAM_1_system);
Heap_Bank1_Start = __Xmc4500_heap_start;
Heap_Bank1_Size = __Xmc4500_heap_end - __Xmc4500_heap_start;
Heap_Bank1_End = ABSOLUTE(__Xmc4500_heap_end);
/* Heap - Bank2 */
DSRAM2_Heap :
{
/* To host DATA in DSRAM2 above heap, please be sure to augment
* program loader code in the startup file */
Heap_Bank2_Start = .;
} > DSRAM_2_comm
Heap_Bank2_Size = LENGTH(DSRAM_2_comm) - (Heap_Bank2_Start - ORIGIN(DSRAM_2_comm));
/* Heap - Bank3 */
PSRAM_Heap :
{
/* To host DATA in PSRAM above heap, please be sure to augment
* program loader code in the startup file */
Heap_Bank3_Start = .;
} > PSRAM_1
Heap_Bank3_Size = LENGTH(PSRAM_1) - (Heap_Bank3_Start - ORIGIN(PSRAM_1));
/DISCARD/ :
{
*(.comment)
}
.stab 0 (NOLOAD) : { *(.stab) }
.stabstr 0 (NOLOAD) : { *(.stabstr) }
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_pubtypes 0 : { *(.debug_pubtypes) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* DWARF 2.1 */
.debug_ranges 0 : { *(.debug_ranges) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* Build attributes */
.build_attributes 0 : { *(.ARM.attributes) }
}

45
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/RTOSDemo.launch
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
<booleanAttribute key="com.tasking.debug.cdt.core.ATTR_RUN_IN_SEPARATE_PROCESS" value="true"/>
<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="J-Link over USB (SWD)"/>
<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="Infineon Hexagon Application Kit XMC4500 Series"/>
<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
<stringAttribute key="debugger_configuration.debug_instrument_module" value="dijlinkarm"/>
<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fARMv7M.sre"/>
<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="SWD"/>
<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\RTOSDemo.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RTOSDemo"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/RTOSDemo"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
</launchConfiguration>

642
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/startup_XMC4500.s
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/*****************************************************************************/
/* Startup_XMC4500.s: Startup file for XMC4500 device series */
/*****************************************************************************/
/* ********************* Version History *********************************** */
/* ***************************************************************************
V1.0 , July 2011, First version for XIP profile
V1.1 , Oct 2011, Program loading code included (GH: b to main changed)
V1.2 , Nov, 01, 2011 GH :Removed second definition of section .Xmc4500.reset
at line 186.
V1.3 , Nov, 16, 2011 GH :Removed PMU0_1_IRQHandler and respective weak function
declaration.
V1.4 , Dec, 16, 2011 PKB:Jump to __Xmc4500_start_c reinstated for RTOS integration
V1.5 , Jan, 10, 2012 PKB:Migrated to GCC from ARM
V1.6 , Jan, 16, 2012 PKB:Branch prediction turned off, Parity errors cleared.
V1.7 , Apr, 17, 2012 PKB:Added decision function for PLL initialization
V1.8 , Apr, 20, 2012 PKB:Handshake with DAVE code engine added
V1.9 , Jun, 14, 2012 PKB:Removed the handshake protocol towards simplification
V1.10, Aug, 13, 2012 PKB:Flash Wait states handling
V1.11, Oct, 11, 2012 PKB:C++ support. Call to global constructors
V1.12, Jan, 23, 2013 PKB:XMC4 Prefetch bug workaround
**************************************************************************** */
/**
* @file Startup_XMC4500.s
* XMC4000 Device Series
* @version V1.12
* @date Jan 2013
*
Copyright (C) 2013 Infineon Technologies AG. All rights reserved.
*
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed
* within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <uc_id.inc>
/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
/*
* STEP_AB and below have the prefetch bug. A veneer defined below will first
* be executed which in turn branches to the final exception handler.
*
* In addition to defining the veneers, the vector table must for these buggy
* devices contain the veneers.
*/
/* A macro to setup a vector table entry based on STEP ID */
.macro Entry Handler
#if (UC_STEP > STEP_AB)
.long \Handler
#else
.long \Handler\()_Veneer
#endif
.endm
/* A macro to ease definition of the various handlers based on STEP ID */
#if (UC_STEP <= STEP_AB)
/* First define the final exception handler */
.macro Insert_ExceptionHandler Handler_Func
.weak \Handler_Func
.type \Handler_Func, %function
\Handler_Func:
B .
.size \Handler_Func, . - \Handler_Func
/* And then define a veneer that will branch to the final excp handler */
.weak \Handler_Func\()_Veneer
.type \Handler_Func\()_Veneer, %function
\Handler_Func\()_Veneer:
LDR R0, =\Handler_Func
PUSH {LR}
BLX R0
POP {PC}
.size \Handler_Func\()_Veneer, . - \Handler_Func\()_Veneer
.endm
#else
/* No prefetch bug, hence define only the final exception handler */
.macro Insert_ExceptionHandler Handler_Func
.weak \Handler_Func
.type \Handler_Func, %function
\Handler_Func:
B .
.size \Handler_Func, . - \Handler_Func
.endm
#endif
/* =============END : MACRO DEFINITION MACRO DEFINITION ================== */
/* ================== START OF VECTOR TABLE DEFINITION ====================== */
/* Vector Table - This gets programed into VTOR register by onchip BootROM */
.syntax unified
.section ".Xmc4500.reset"
.globl __Xmc4500_interrupt_vector_cortex_m
.type __Xmc4500_interrupt_vector_cortex_m, %object
__Xmc4500_interrupt_vector_cortex_m:
.long __Xmc4500_stack /* Top of Stack */
.long __Xmc4500_reset_cortex_m /* Reset Handler */
Entry NMI_Handler /* NMI Handler */
Entry HardFault_Handler /* Hard Fault Handler */
Entry MemManage_Handler /* MPU Fault Handler */
Entry BusFault_Handler /* Bus Fault Handler */
Entry UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
Entry DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals */
Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */
Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */
Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */
Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */
Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */
Entry ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */
Entry ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */
Entry ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */
Entry ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */
.long 0 /* Not Available */
Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */
Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */
Entry VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */
Entry VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */
Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */
Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */
Entry VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */
Entry VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */
Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */
Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */
Entry VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */
Entry VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */
Entry VADC0_G2_0_IRQHandler /* Handler name for SR VADC0_G2_0 */
Entry VADC0_G2_1_IRQHandler /* Handler name for SR VADC0_G2_1 */
Entry VADC0_G2_2_IRQHandler /* Handler name for SR VADC0_G2_2 */
Entry VADC0_G2_3_IRQHandler /* Handler name for SR VADC0_G2_3 */
Entry VADC0_G3_0_IRQHandler /* Handler name for SR VADC0_G3_0 */
Entry VADC0_G3_1_IRQHandler /* Handler name for SR VADC0_G3_1 */
Entry VADC0_G3_2_IRQHandler /* Handler name for SR VADC0_G3_2 */
Entry VADC0_G3_3_IRQHandler /* Handler name for SR VADC0_G3_3 */
Entry DSD0_0_IRQHandler /* Handler name for SR DSD0_0 */
Entry DSD0_1_IRQHandler /* Handler name for SR DSD0_1 */
Entry DSD0_2_IRQHandler /* Handler name for SR DSD0_2 */
Entry DSD0_3_IRQHandler /* Handler name for SR DSD0_3 */
Entry DSD0_4_IRQHandler /* Handler name for SR DSD0_4 */
Entry DSD0_5_IRQHandler /* Handler name for SR DSD0_5 */
Entry DSD0_6_IRQHandler /* Handler name for SR DSD0_6 */
Entry DSD0_7_IRQHandler /* Handler name for SR DSD0_7 */
Entry DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */
Entry DAC0_1_IRQHandler /* Handler name for SR DAC0_0 */
Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */
Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */
Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */
Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */
Entry CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */
Entry CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */
Entry CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */
Entry CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */
Entry CCU42_0_IRQHandler /* Handler name for SR CCU42_0 */
Entry CCU42_1_IRQHandler /* Handler name for SR CCU42_1 */
Entry CCU42_2_IRQHandler /* Handler name for SR CCU42_2 */
Entry CCU42_3_IRQHandler /* Handler name for SR CCU42_3 */
Entry CCU43_0_IRQHandler /* Handler name for SR CCU43_0 */
Entry CCU43_1_IRQHandler /* Handler name for SR CCU43_1 */
Entry CCU43_2_IRQHandler /* Handler name for SR CCU43_2 */
Entry CCU43_3_IRQHandler /* Handler name for SR CCU43_3 */
Entry CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */
Entry CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */
Entry CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */
Entry CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */
Entry CCU81_0_IRQHandler /* Handler name for SR CCU81_0 */
Entry CCU81_1_IRQHandler /* Handler name for SR CCU81_1 */
Entry CCU81_2_IRQHandler /* Handler name for SR CCU81_2 */
Entry CCU81_3_IRQHandler /* Handler name for SR CCU81_3 */
Entry POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */
Entry POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */
Entry POSIF1_0_IRQHandler /* Handler name for SR POSIF1_0 */
Entry POSIF1_1_IRQHandler /* Handler name for SR POSIF1_1 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */
Entry CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */
Entry CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */
Entry CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */
Entry CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */
Entry CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */
Entry CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */
Entry CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */
Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */
Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */
Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */
Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */
Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */
Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */
Entry USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */
Entry USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */
Entry USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */
Entry USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */
Entry USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */
Entry USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */
Entry USIC2_0_IRQHandler /* Handler name for SR USIC2_0 */
Entry USIC2_1_IRQHandler /* Handler name for SR USIC2_1 */
Entry USIC2_2_IRQHandler /* Handler name for SR USIC2_2 */
Entry USIC2_3_IRQHandler /* Handler name for SR USIC2_3 */
Entry USIC2_4_IRQHandler /* Handler name for SR USIC2_4 */
Entry USIC2_5_IRQHandler /* Handler name for SR USIC2_5 */
Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */
.long 0 /* Not Available */
Entry FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */
Entry GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */
Entry SDMMC0_0_IRQHandler /* Handler name for SR SDMMC0_0 */
Entry USB0_0_IRQHandler /* Handler name for SR USB0_0 */
Entry ETH0_0_IRQHandler /* Handler name for SR ETH0_0 */
.long 0 /* Not Available */
Entry GPDMA1_0_IRQHandler /* Handler name for SR GPDMA1_0 */
.long 0 /* Not Available */
.size __Xmc4500_interrupt_vector_cortex_m, . - __Xmc4500_interrupt_vector_cortex_m
/* ================== END OF VECTOR TABLE DEFINITION ======================= */
/* ================== START OF VECTOR ROUTINES ============================= */
.thumb
/* ======================================================================== */
/* Reset Handler */
.thumb_func
.globl __Xmc4500_reset_cortex_m
.type __Xmc4500_reset_cortex_m, %function
__Xmc4500_reset_cortex_m:
.fnstart
/* C routines are likely to be called. Setup the stack now */
/* This is already setup by BootROM,hence this step is optional */
LDR SP,=__Xmc4500_stack
/* Clock tree, External memory setup etc may be done here */
LDR R0, =SystemInit
BLX R0
/*
SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is
weakly defined here though for a potential override.
*/
LDR R0, =SystemInit_DAVE3
BLX R0
B __Xmc4500_Program_Loader
.pool
.cantunwind
.fnend
.size __Xmc4500_reset_cortex_m,.-__Xmc4500_reset_cortex_m
/* ======================================================================== */
/* __Xmc4500_reset must yield control to __Xmc4500_Program_Loader before control
to C land is given */
.section .Xmc4500.postreset,"x",%progbits
__Xmc4500_Program_Loader:
.fnstart
/* Memories are accessible now*/
/* DATA COPY */
/* R0 = Start address, R1 = Destination address, R2 = Size */
LDR R0, =eROData
LDR R1, =__Xmc4500_sData
LDR R2, =__Xmc4500_Data_Size
/* Is there anything to be copied? */
CMP R2,#0
BEQ SKIPCOPY
/* For bytecount less than 4, at least 1 word must be copied */
CMP R2,#4
BCS STARTCOPY
/* Byte count < 4 ; so bump it up */
MOV R2,#4
STARTCOPY:
/*
R2 contains byte count. Change it to word count. It is ensured in the
linker script that the length is always word aligned.
*/
LSR R2,R2,#2 /* Divide by 4 to obtain word count */
/* The proverbial loop from the schooldays */
COPYLOOP:
LDR R3,[R0]
STR R3,[R1]
SUBS R2,#1
BEQ SKIPCOPY
ADD R0,#4
ADD R1,#4
B COPYLOOP
SKIPCOPY:
/* BSS CLEAR */
LDR R0, =__Xmc4500_sBSS /* Start of BSS */
LDR R1, =__Xmc4500_BSS_Size /* BSS size in bytes */
/* Find out if there are items assigned to BSS */
CMP R1,#0
BEQ SKIPCLEAR
/* At least 1 word must be copied */
CMP R1,#4
BCS STARTCLEAR
/* Byte count < 4 ; so bump it up to a word*/
MOV R1,#4
STARTCLEAR:
LSR R1,R1,#2 /* BSS size in words */
MOV R2,#0
CLEARLOOP:
STR R2,[R0]
SUBS R1,#1
BEQ SKIPCLEAR
ADD R0,#4
B CLEARLOOP
SKIPCLEAR:
/* Remap vector table */
/* This is already setup by BootROM,hence this step is optional */
LDR R0, =__Xmc4500_interrupt_vector_cortex_m
LDR R1, =SCB_VTOR
STR R0,[R1]
/* Update System Clock */
LDR R0,=SystemCoreClockUpdate
BLX R0
/* C++ : Call global constructors */
LDR R0,=__libc_init_array
BLX R0
/* Reset stack pointer before zipping off to user application, Optional */
LDR SP,=__Xmc4500_stack
MOV R0,#0
MOV R1,#0
LDR PC, =main
.pool
.cantunwind
.fnend
.size __Xmc4500_Program_Loader,.-__Xmc4500_Program_Loader
/* ======================================================================== */
/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
/* Default exception Handlers - Users may override this default functionality by
defining handlers of the same name in their C code */
.thumb
.text
Insert_ExceptionHandler NMI_Handler
/* ======================================================================== */
Insert_ExceptionHandler HardFault_Handler
/* ======================================================================== */
Insert_ExceptionHandler MemManage_Handler
/* ======================================================================== */
Insert_ExceptionHandler BusFault_Handler
/* ======================================================================== */
Insert_ExceptionHandler UsageFault_Handler
/* ======================================================================== */
Insert_ExceptionHandler SVC_Handler
/* ======================================================================== */
Insert_ExceptionHandler DebugMon_Handler
/* ======================================================================== */
Insert_ExceptionHandler PendSV_Handler
/* ======================================================================== */
Insert_ExceptionHandler SysTick_Handler
/* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
/* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
/* IRQ Handlers */
Insert_ExceptionHandler SCU_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU1_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU1_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU1_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU1_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler PMU0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_C0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_C0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_C0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_C0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G1_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G1_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G1_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G1_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G2_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G2_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G2_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G2_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G3_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G3_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G3_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G3_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DSD0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DSD0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DSD0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DSD0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DSD0_4_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DSD0_5_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DSD0_6_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DSD0_7_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DAC0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DAC0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU40_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU40_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU40_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU40_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU41_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU41_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU41_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU41_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU42_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU42_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU42_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU42_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU43_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU43_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU43_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU43_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU80_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU80_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU80_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU80_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU81_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU81_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU81_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU81_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler POSIF0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler POSIF0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler POSIF1_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler POSIF1_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_4_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_5_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_6_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_7_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_4_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_5_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_4_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_5_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC2_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC2_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC2_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC2_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC2_4_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC2_5_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler LEDTS0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler FCE0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler GPDMA0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler SDMMC0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USB0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ETH0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler GPDMA1_0_IRQHandler
/* ======================================================================== */
/* ======================================================================== */
/* ============= END OF INTERRUPT HANDLER DEFINITION ====================== */
/* ======== Decision function queried by CMSIS startup for PLL setup ====== */
/* In the absence of DAVE code engine, CMSIS SystemInit() must perform clock
tree setup.
This decision routine defined here will always return TRUE.
When overridden by a definition defined in DAVE code engine, this routine
returns FALSE indicating that the code engine has performed the clock setup
*/
.weak AllowPLLInitByStartup
.type AllowPLLInitByStartup, %function
AllowPLLInitByStartup:
MOV R0,#1
BX LR
.size AllowPLLInitByStartup, . - AllowPLLInitByStartup
/* ====== Definition of the default weak SystemInit_DAVE3 function =========
If DAVE3 requires an extended SystemInit it will create its own version of
SystemInit_DAVE3 which overrides this weak definition. Example includes
setting up of external memory interfaces.
*/
.section ".XmcStartup"
.weak SystemInit_DAVE3
.type SystemInit_DAVE3, %function
SystemInit_DAVE3:
NOP
BX LR
.size SystemInit_DAVE3, . - SystemInit_DAVE3
/* ======================================================================== */
/* ======================================================================== */
/* ======================== Data references =============================== */
.equ SCB_VTOR, 0xE000ED08
.equ PREF_PCON, 0x58004000
.equ SCU_GCU_PEEN, 0x5000413C
.equ SCU_GCU_PEFLAG, 0x50004150
.equ FLASH_FCON, 0x58002014
.end

705
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/system_XMC4500.c
Unescape Escape View File

@ -0,0 +1,705 @@
/**************************************************************************//**
* @file system_XMC4500.c
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File
* for the Infineon XMC4500 Device Series
* @version V3.0.1 Alpha
* @date 17. September 2012
*
* @note
* Copyright (C) 2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include "system_XMC4500.h"
#include <XMC4500.h>
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/*!< System Clock Frequency (Core Clock)*/
uint32_t SystemCoreClock;
/* clock definitions, do not modify! */
#define SCU_CLOCK_CRYSTAL 1
#define SCU_CLOCK_BACK_UP_FACTORY 2
#define SCU_CLOCK_BACK_UP_AUTOMATIC 3
#define HIB_CLOCK_FOSI 1
#define HIB_CLOCK_OSCULP 2
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Watchdog Configuration -------------------------------
//
// <e> Watchdog Configuration
// <o1.0> Disable Watchdog
//
// </e>
*/
#define WDT_SETUP 1
#define WDTENB_nVal 0x00000001
/*--------------------- CLOCK Configuration -------------------------------
//
// <e> Main Clock Configuration
// <o1.0..1> CPU clock divider
// <0=> fCPU = fSYS
// <1=> fCPU = fSYS / 2
// <o2.0..1> Peripheral Bus clock divider
// <0=> fPB = fCPU
// <1=> fPB = fCPU / 2
// <o3.0..1> CCU Bus clock divider
// <0=> fCCU = fCPU
// <1=> fCCU = fCPU / 2
//
// </e>
//
*/
#define SCU_CLOCK_SETUP 1
#define SCU_CPUCLKCR_DIV 0x00000000
#define SCU_PBCLKCR_DIV 0x00000000
#define SCU_CCUCLKCR_DIV 0x00000000
/* not avalible in config wizzard*/
/*
* mandatory clock parameters **************************************************
*
* source for clock generation
* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
*
**************************************************************************************/
// Selection of imput lock for PLL
/*************************************************************************************/
#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY
//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC
/*************************************************************************************/
// Standby clock selection for Backup clock source trimming
/*************************************************************************************/
#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP
//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI
/*************************************************************************************/
// Global clock parameters
/*************************************************************************************/
#define CLOCK_FSYS 120000000
#define CLOCK_CRYSTAL_FREQUENCY 12000000
#define CLOCK_BACK_UP 24000000
/*************************************************************************************/
/* OSC_HP setup parameters */
/*************************************************************************************/
#define SCU_OSC_HP_MODE 0xF0
#define SCU_OSCHPWDGDIV 2
/*************************************************************************************/
/* MAIN PLL setup parameters */
/*************************************************************************************/
//Divider settings for external crystal @ 12 MHz
/*************************************************************************************/
#define SCU_PLL_K1DIV 1
#define SCU_PLL_K2DIV 3
#define SCU_PLL_PDIV 1
#define SCU_PLL_NDIV 79
/*************************************************************************************/
//Divider settings for use of backup clock source trimmed
/*************************************************************************************/
//#define SCU_PLL_K1DIV 1
//#define SCU_PLL_K2DIV 3
//#define SCU_PLL_PDIV 3
//#define SCU_PLL_NDIV 79
/*************************************************************************************/
/*--------------------- USB CLOCK Configuration ---------------------------
//
// <e> USB Clock Configuration
//
// </e>
//
*/
#define SCU_USB_CLOCK_SETUP 0
/* not avalible in config wizzard*/
#define SCU_USBPLL_PDIV 0
#define SCU_USBPLL_NDIV 31
#define SCU_USBDIV 3
/*--------------------- Flash Wait State Configuration -------------------------------
//
// <e> Flash Wait State Configuration
// <o1.0..3> Flash Wait State
// <0=> 3 WS
// <1=> 4 WS
// <2=> 5 WS
// <3=> 6 WS
// </e>
//
*/
#define PMU_FLASH 1
#define PMU_FLASH_WS 0x00000000
/*--------------------- CLOCKOUT Configuration -------------------------------
//
// <e> Clock OUT Configuration
// <o1.0..1> Clockout Source Selection
// <0=> System Clock
// <2=> Divided value of USB PLL output
// <3=> Divided value of PLL Clock
// <o2.0..4> Clockout divider <1-10><#-1>
// <o3.0..1> Clockout Pin Selection
// <0=> P1.15
// <1=> P0.8
//
//
// </e>
//
*/
#define SCU_CLOCKOUT_SETUP 0
#define SCU_CLOCKOUT_SOURCE 0x00000003
#define SCU_CLOCKOUT_DIV 0x00000009
#define SCU_CLOCKOUT_PIN 0x00000001
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/*!< System Clock Frequency (Core Clock)*/
#if SCU_CLOCK_SETUP
uint32_t SystemCoreClock = CLOCK_FSYS;
#else
uint32_t SystemCoreClock = CLOCK_BACK_UP;
#endif
/*----------------------------------------------------------------------------
static functions declarations
*----------------------------------------------------------------------------*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void);
#endif
#if (SCU_USB_CLOCK_SETUP == 1)
static int USBClockSetup(void);
#endif
/**
* @brief Setup the microcontroller system.
* Initialize the PLL and update the
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
int temp;
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
/* Setup the WDT */
#if WDT_SETUP
WDT->CTR &= ~WDTENB_nVal;
#endif
/* Setup the Flash Wait State */
#if PMU_FLASH
temp = FLASH0->FCON;
temp &= ~FLASH_FCON_WSPFLASH_Msk;
temp |= PMU_FLASH_WS+3;
FLASH0->FCON = temp;
#endif
/* Setup the clockout */
#if SCU_CLOCKOUT_SETUP
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;
/*set PLL div for clkout */
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;
if (SCU_CLOCKOUT_PIN) {
PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */
PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
//PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */
}
else {
PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
//PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */
}
#endif
/* Setup the System clock */
#if SCU_CLOCK_SETUP
SystemClockSetup();
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/
/* Setup the USB PL */
#if SCU_USB_CLOCK_SETUP
USBClockSetup();
#endif
}
/**
* @brief Update SystemCoreClock according to Clock Register Values
* @note -
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
unsigned int PDIV;
unsigned int NDIV;
unsigned int K2DIV;
unsigned int long VCO;
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
if (SCU_CLK->SYSCLKCR == 0x00010000)
{
if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){
/* check if PLL is locked */
/* read back divider settings */
PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;
NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;
K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;
if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){
/* the selected clock is the Backup clock fofi */
VCO = (CLOCK_BACK_UP/PDIV)*NDIV;
SystemCoreClock = VCO/K2DIV;
/* in case the sysclock div is used */
SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
}
else
{
/* the selected clock is the PLL external oscillator */
VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;
SystemCoreClock = VCO/K2DIV;
/* in case the sysclock div is used */
SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
}
}
}
else
{
SystemCoreClock = CLOCK_BACK_UP;
}
}
/**
* @brief -
* @note -
* @param None
* @retval None
*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void)
{
int temp;
unsigned int long VCO;
int stepping_K2DIV;
/* this weak function enables DAVE3 clock App usage */
if(AllowPLLInitByStartup()){
/* check if PLL is switched on */
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
}
/* Enable OSC_HP if not already on*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
{
/********************************************************************************************************************/
/* Use external crystal for PLL clock input */
/********************************************************************************************************************/
if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
/* setup OSC WDG devider */
SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
/* select external OSC as PLL input */
SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
/* Timeout for wait loop ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
do
{
;/* wait for ~150ms */
}while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
return(0);/* Return Error */
}
}
else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)
{
/********************************************************************************************************************/
/* Use factory trimming Back-up clock for PLL clock input */
/********************************************************************************************************************/
/* PLL Back up clock selected */
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
}
else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)
{
/********************************************************************************************************************/
/* Use automatic trimming Back-up clock for PLL clock input */
/********************************************************************************************************************/
/* check for HIB Domain enabled */
if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/
/* check for HIB Domain is not in reset state */
if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)
SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/
/* PLL Back up clock selected */
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)
{
/****************************************************************************************************************/
/* Use fOSI as source of the standby clock */
/****************************************************************************************************************/
SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
for(temp=0;temp<=0xFFFF;temp++);
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
}
else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)
{
/****************************************************************************************************************/
/* Use fULP as source of the standby clock */
/****************************************************************************************************************/
/*check OSCUL if running correct*/
if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)
{
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);
SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/
/*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/
/* select OSCUL clock for RTC*/
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
/*enable OSCULP WDG Alarm Enable*/
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
/*wait now for clock is stable */
do
{
SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
for(temp=0;temp<=0xFFFF;temp++);
}
while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);
SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
}
// now OSCULP is running and can be used
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
/*TRIAL for delay loop*/
for(temp=0;temp<=0xFFFF;temp++);
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
/*TRIAL for delay loop*/
for(temp=0;temp<=0xFFFF;temp++);
}
}
/********************************************************************************************************************/
/* Setup and look the main PLL */
/********************************************************************************************************************/
if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){
/* Systen is still running from internal clock */
/* select FOFI as system clock */
if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/24000000)-1;
/* Go to bypass the Main PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
/* disconnect OSC_HP to PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
/* we may have to set OSCDISCDIS */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/* connect OSC_HP to PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
/* wait for PLL Lock */
/* setup time out loop */
/* Timeout for wait loo ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)
{
/* Go back to the Main PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
}
else return(0);
/*********************************************************
here we need to setup the system clock divider
*********************************************************/
SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
/* Switch system clock to PLL */
SCU_CLK->SYSCLKCR |= 0x00010000;
/* we may have to reset OSCDISCDIS */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/*********************************************************/
/*********************************************************
here the ramp up of the system clock starts FSys < 60MHz
*********************************************************/
if (CLOCK_FSYS > 60000000){
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/60000000)-1;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
}
else
{
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
return(1);
}
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/********************************/
/*********************************************************
here the ramp up of the system clock starts FSys < 90MHz
*********************************************************/
if (CLOCK_FSYS > 90000000){
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/90000000)-1;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
}
else
{
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
return(1);
}
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/********************************/
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
}
}/* end this weak function enables DAVE3 clock App usage */
return(1);
}
#endif
/**
* @brief -
* @note -
* @param None
* @retval None
*/
#if (SCU_USB_CLOCK_SETUP == 1)
static int USBClockSetup(void)
{
/* this weak function enables DAVE3 clock App usage */
if(AllowPLLInitByStartup()){
/* check if PLL is switched on */
if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
}
/* check and if not already running enable OSC_HP */
if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
/* check if Main PLL is switched on for OSC WD*/
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
}
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
/* setup OSC WDG devider */
SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
/* Timeout for wait loop ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
do
{
;/* wait for ~150ms */
}while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
return(0);/* Return Error */
}
/* Setup USB PLL */
/* Go to bypass the Main PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
/* disconnect OSC_FI to PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
/* Setup devider settings for main PLL */
SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));
/* Setup USBDIV settings USB clock */
SCU_CLK->USBCLKCR = SCU_USBDIV;
/* we may have to set OSCDISCDIS */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
/* connect OSC_FI to PLL */
SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
/* wait for PLL Lock */
while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
}/* end this weak function enables DAVE3 clock App usage */
return(1);
}
#endif

224
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main.c
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/*
FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to distribute
>>! a combined work that includes FreeRTOS without being obliged to provide
>>! the source code for proprietary components outside of the FreeRTOS
>>! kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* This project provides two demo applications. A simple blinky style project,
* and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
* select between the two. The simply blinky demo is implemented and described
* in main_blinky.c. The more comprehensive test and demo application is
* implemented and described in main_full.c.
*
* This file implements the code that is not demo specific, including the
* hardware setup and FreeRTOS hook functions.
*
*
* Additional code:
*
* This demo does not contain a non-kernel interrupt service routine that
* can be used as an example for application writers to use as a reference.
* Therefore, the framework of a dummy (not installed) handler is provided
* in this file. The dummy function is called Dummy_IRQHandler(). Please
* ensure to read the comments in the function itself, but more importantly,
* the notes on the function contained on the documentation page for this demo
* that is found on the FreeRTOS.org web site.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
or 0 to run the more comprehensive test and demo application. */
#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
/*-----------------------------------------------------------*/
/*
* Set up the hardware ready to run this demo.
*/
static void prvSetupHardware( void );
/*
* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
* main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
*/
extern void main_blinky( void );
extern void main_full( void );
/*-----------------------------------------------------------*/
int main( void )
{
/* Prepare the hardware to run this demo. */
prvSetupHardware();
/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
of this file. */
#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
{
main_blinky();
}
#else
{
main_full();
}
#endif
return 0;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
configCONFIGURE_LED();
/* Ensure all priority bits are assigned as preemption priority bits. */
NVIC_SetPriorityGrouping( 0 );
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* vApplicationMallocFailedHook() will only be called if
configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
function that will get called if a call to pvPortMalloc() fails.
pvPortMalloc() is called internally by the kernel whenever a task, queue,
timer or semaphore is created. It is also called by various parts of the
demo application. If heap_1.c or heap_2.c are used, then the size of the
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
to query the size of free heap space that remains (although it does not
provide information on how the remaining heap might be fragmented). */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
task. It is essential that code added to this hook function never attempts
to block in any way (for example, call xQueueReceive() with a block time
specified, or call vTaskDelay()). If the application makes use of the
vTaskDelete() API function (as this demo application does) then it is also
important that vApplicationIdleHook() is permitted to return to its calling
function, because it is the responsibility of the idle task to clean up
memory allocated by the kernel to any task that has since been deleted. */
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
function is called if a stack overflow is detected. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationTickHook( void )
{
/* This function will be called by each tick interrupt if
configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
added here, but the tick hook is called from an interrupt context, so
code must not attempt to block, and only the interrupt safe FreeRTOS API
functions can be used (those that end in FromISR()). */
}
/*-----------------------------------------------------------*/
#ifdef JUST_AN_EXAMPLE_ISR
void Dummy_IRQHandler(void)
{
long lHigherPriorityTaskWoken = pdFALSE;
/* Clear the interrupt if necessary. */
Dummy_ClearITPendingBit();
/* This interrupt does nothing more than demonstrate how to synchronise a
task with an interrupt. A semaphore is used for this purpose. Note
lHigherPriorityTaskWoken is initialised to zero. */
xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );
/* If there was a task that was blocked on the semaphore, and giving the
semaphore caused the task to unblock, and the unblocked task has a priority
higher than the current Running state task (the task that this interrupt
interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE
internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the
portEND_SWITCHING_ISR() macro will result in a context switch being pended to
ensure this interrupt returns directly to the unblocked, higher priority,
task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */
portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
}
#endif /* JUST_AN_EXAMPLE_ISR */

232
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_blinky.c
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@ -0,0 +1,232 @@
/*
FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to distribute
>>! a combined work that includes FreeRTOS without being obliged to provide
>>! the source code for proprietary components outside of the FreeRTOS
>>! kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky style
* project, and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
* in main.c. This file implements the simply blinky style version.
*
* NOTE 2: This file only contains the source code that is specific to the
* basic demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware, are defined in main.c.
******************************************************************************
*
* main_blinky() creates one queue, and two tasks. It then starts the
* scheduler.
*
* The Queue Send Task:
* The queue send task is implemented by the prvQueueSendTask() function in
* this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
* block for 200 milliseconds, before sending the value 100 to the queue that
* was created within main_blinky(). Once the value is sent, the task loops
* back around to block for another 200 milliseconds.
*
* The Queue Receive Task:
* The queue receive task is implemented by the prvQueueReceiveTask() function
* in this file. prvQueueReceiveTask() sits in a loop where it repeatedly
* blocks on attempts to read data from the queue that was created within
* main_blinky(). When data is received, the task checks the value of the
* data, and if the value equals the expected 100, toggles the LED. The 'block
* time' parameter passed to the queue receive function specifies that the
* task should be held in the Blocked state indefinitely to wait for data to
* be available on the queue. The queue receive task will only leave the
* Blocked state when the queue send task writes to the queue. As the queue
* send task writes to the queue every 200 milliseconds, the queue receive
* task leaves the Blocked state every 200 milliseconds, and therefore toggles
* the LED every 200 milliseconds.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Priorities at which the tasks are created. */
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The rate at which data is sent to the queue. The 200ms value is converted
to ticks using the portTICK_RATE_MS constant. */
#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )
/* The number of items the queue can hold. This is 1 as the receive task
will remove items as they are added, meaning the send task should always find
the queue empty. */
#define mainQUEUE_LENGTH ( 1 )
/* Values passed to the two tasks just to check the task parameter
functionality. */
#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )
#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )
/*-----------------------------------------------------------*/
/*
* The tasks as described in the comments at the top of this file.
*/
static void prvQueueReceiveTask( void *pvParameters );
static void prvQueueSendTask( void *pvParameters );
/*
* Called by main() to create the simply blinky style application if
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
*/
void main_blinky( void );
/*-----------------------------------------------------------*/
/* The queue used by both tasks. */
static xQueueHandle xQueue = NULL;
/*-----------------------------------------------------------*/
void main_blinky( void )
{
/* Create the queue. */
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
if( xQueue != NULL )
{
/* Start the two tasks as described in the comments at the top of this
file. */
xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */
mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
NULL ); /* The task handle is not required, so NULL is passed. */
xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );
/* Start the tasks and timer running. */
vTaskStartScheduler();
}
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was insufficient FreeRTOS heap memory available for the idle and/or
timer tasks to be created. See the memory management section on the
FreeRTOS web site for more details. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvQueueSendTask( void *pvParameters )
{
portTickType xNextWakeTime;
const unsigned long ulValueToSend = 100UL;
/* Check the task parameter is as expected. */
configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again.
The block time is specified in ticks, the constant used converts ticks
to ms. While in the Blocked state this task will not consume any CPU
time. */
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
/* Send to the queue - causing the queue receive task to unblock and
toggle the LED. 0 is used as the block time so the sending operation
will not block - it shouldn't need to block as the queue should always
be empty at this point in the code. */
xQueueSend( xQueue, &ulValueToSend, 0U );
}
}
/*-----------------------------------------------------------*/
static void prvQueueReceiveTask( void *pvParameters )
{
unsigned long ulReceivedValue;
/* Check the task parameter is as expected. */
configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );
for( ;; )
{
/* Wait until something arrives in the queue - this task will block
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
FreeRTOSConfig.h. */
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
/* To get here something must have been received from the queue, but
is it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == 100UL )
{
configTOGGLE_LED();
ulReceivedValue = 0U;
}
}
}
/*-----------------------------------------------------------*/

662
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c
Unescape Escape View File

@ -0,0 +1,662 @@
/*
FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to distribute
>>! a combined work that includes FreeRTOS without being obliged to provide
>>! the source code for proprietary components outside of the FreeRTOS
>>! kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky style
* project, and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
* in main.c. This file implements the comprehensive test and demo version.
*
* NOTE 2: This file only contains the source code that is specific to the
* full demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware, are defined in main.c.
******************************************************************************
*
* main_full() creates all the demo application tasks and a software timer, then
* starts the scheduler. The web documentation provides more details of the
* standard demo application tasks, which provide no particular functionality,
* but do provide a good example of how to use the FreeRTOS API.
*
* In addition to the standard demo tasks, the following tasks and tests are
* defined and/or created within this file:
*
* "Reg test" tasks - These fill both the core and floating point registers with
* known values, then check that each register maintains its expected value for
* the lifetime of the task. Each task uses a different set of values. The reg
* test tasks execute with a very low priority, so get preempted very
* frequently. A register containing an unexpected value is indicative of an
* error in the context switching mechanism.
*
* "Check" timer - The check software timer period is initially set to three
* seconds. The callback function associated with the check software timer
* checks that all the standard demo tasks, and the register check tasks, are
* not only still executing, but are executing without reporting any errors. If
* the check software timer discovers that a task has either stalled, or
* reported an error, then it changes its own execution period from the initial
* three seconds, to just 200ms. The check software timer callback function
* also toggles the single LED each time it is called. This provides a visual
* indication of the system status: If the LED toggles every three seconds,
* then no issues have been discovered. If the LED toggles every 200ms, then
* an issue has been discovered with at least one task.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "timers.h"
#include "semphr.h"
/* Standard demo application includes. */
#include "flop.h"
#include "integer.h"
#include "PollQ.h"
#include "semtest.h"
#include "dynamic.h"
#include "BlockQ.h"
#include "blocktim.h"
#include "countsem.h"
#include "GenQTest.h"
#include "recmutex.h"
#include "death.h"
/* Priorities for the demo application tasks. */
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
/* A block time of zero simply means "don't block". */
#define mainDONT_BLOCK ( 0UL )
/* The period after which the check timer will expire, in ms, provided no errors
have been reported by any of the standard demo tasks. ms are converted to the
equivalent in ticks using the portTICK_RATE_MS constant. */
#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )
/* The period at which the check timer will expire, in ms, if an error has been
reported in one of the standard demo tasks. ms are converted to the equivalent
in ticks using the portTICK_RATE_MS constant. */
#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )
/*-----------------------------------------------------------*/
/*
* The check timer callback function, as described at the top of this file.
*/
static void prvCheckTimerCallback( xTimerHandle xTimer );
/*
* Register check tasks, and the tasks used to write over and check the contents
* of the FPU registers, as described at the top of this file. The nature of
* these files necessitates that they are written in an assembly file.
*/
static void prvRegTest1Task( void *pvParameters ) __attribute__((naked));
static void prvRegTest2Task( void *pvParameters ) __attribute__((naked));
/*-----------------------------------------------------------*/
/* The following two variables are used to communicate the status of the
register check tasks to the check software timer. If the variables keep
incrementing, then the register check tasks has not discovered any errors. If
a variable stops incrementing, then an error has been found. */
volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
/*-----------------------------------------------------------*/
void main_full( void )
{
xTimerHandle xCheckTimer = NULL;
/* Start all the other standard demo/test tasks. The have not particular
functionality, but do demonstrate how to use the FreeRTOS API and test the
kernel port. */
vStartDynamicPriorityTasks();
vCreateBlockTimeTasks();
vStartCountingSemaphoreTasks();
vStartGenericQueueTasks( tskIDLE_PRIORITY );
vStartRecursiveMutexTasks();
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartMathTasks( mainFLOP_TASK_PRIORITY );
/* Create the register check tasks, as described at the top of this
file */
xTaskCreate( prvRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
xTaskCreate( prvRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
/* Create the software timer that performs the 'check' functionality,
as described at the top of this file. */
xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */
( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */
pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
( void * ) 0, /* The ID is not used, so can be set to anything. */
prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */
);
if( xCheckTimer != NULL )
{
xTimerStart( xCheckTimer, mainDONT_BLOCK );
}
/* Start the scheduler. */
vTaskStartScheduler();
/* If all is well, the scheduler will now be running, and the following line
will never be reached. If the following line does execute, then there was
insufficient FreeRTOS heap memory available for the idle and/or timer tasks
to be created. See the memory management section on the FreeRTOS web site
for more details. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvCheckTimerCallback( xTimerHandle xTimer )
{
static long lChangedTimerPeriodAlready = pdFALSE;
static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
unsigned long ulErrorFound = pdFALSE;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none have detected an error. */
if( xAreMathsTaskStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
/* Check that the register test 1 task is still running. */
if( ulLastRegTest1Value == ulRegTest1LoopCounter )
{
ulErrorFound = pdTRUE;
}
ulLastRegTest1Value = ulRegTest1LoopCounter;
/* Check that the register test 2 task is still running. */
if( ulLastRegTest2Value == ulRegTest2LoopCounter )
{
ulErrorFound = pdTRUE;
}
ulLastRegTest2Value = ulRegTest2LoopCounter;
/* Toggle the check LED to give an indication of the system status. If
the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then
everything is ok. A faster toggle indicates an error. */
configTOGGLE_LED();
/* Have any errors been latch in ulErrorFound? If so, shorten the
period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.
This will result in an increase in the rate at which mainCHECK_LED
toggles. */
if( ulErrorFound != pdFALSE )
{
if( lChangedTimerPeriodAlready == pdFALSE )
{
lChangedTimerPeriodAlready = pdTRUE;
/* This call to xTimerChangePeriod() uses a zero block time.
Functions called from inside of a timer callback function must
*never* attempt to block. */
xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );
}
}
}
/*-----------------------------------------------------------*/
/* This is a naked function. */
static void prvRegTest1Task( void *pvParameters )
{
__asm volatile
(
" /* Fill the core registers with known values. */ \n"
" mov r0, #100 \n"
" mov r1, #101 \n"
" mov r2, #102 \n"
" mov r3, #103 \n"
" mov r4, #104 \n"
" mov r5, #105 \n"
" mov r6, #106 \n"
" mov r7, #107 \n"
" mov r8, #108 \n"
" mov r9, #109 \n"
" mov r10, #110 \n"
" mov r11, #111 \n"
" mov r12, #112 \n"
" \n"
" /* Fill the VFP registers with known values. */ \n"
" vmov d0, r0, r1 \n"
" vmov d1, r2, r3 \n"
" vmov d2, r4, r5 \n"
" vmov d3, r6, r7 \n"
" vmov d4, r8, r9 \n"
" vmov d5, r10, r11 \n"
" vmov d6, r0, r1 \n"
" vmov d7, r2, r3 \n"
" vmov d8, r4, r5 \n"
" vmov d9, r6, r7 \n"
" vmov d10, r8, r9 \n"
" vmov d11, r10, r11 \n"
" vmov d12, r0, r1 \n"
" vmov d13, r2, r3 \n"
" vmov d14, r4, r5 \n"
" vmov d15, r6, r7 \n"
" \n"
"reg1_loop: \n"
" /* Check all the VFP registers still contain the values set above.\n"
" First save registers that are clobbered by the test. */ \n"
" push { r0-r1 } \n"
" \n"
" vmov r0, r1, d0 \n"
" cmp r0, #100 \n"
" bne reg1_error_loopf \n"
" cmp r1, #101 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d1 \n"
" cmp r0, #102 \n"
" bne reg1_error_loopf \n"
" cmp r1, #103 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d2 \n"
" cmp r0, #104 \n"
" bne reg1_error_loopf \n"
" cmp r1, #105 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d3 \n"
" cmp r0, #106 \n"
" bne reg1_error_loopf \n"
" cmp r1, #107 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d4 \n"
" cmp r0, #108 \n"
" bne reg1_error_loopf \n"
" cmp r1, #109 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d5 \n"
" cmp r0, #110 \n"
" bne reg1_error_loopf \n"
" cmp r1, #111 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d6 \n"
" cmp r0, #100 \n"
" bne reg1_error_loopf \n"
" cmp r1, #101 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d7 \n"
" cmp r0, #102 \n"
" bne reg1_error_loopf \n"
" cmp r1, #103 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d8 \n"
" cmp r0, #104 \n"
" bne reg1_error_loopf \n"
" cmp r1, #105 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d9 \n"
" cmp r0, #106 \n"
" bne reg1_error_loopf \n"
" cmp r1, #107 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d10 \n"
" cmp r0, #108 \n"
" bne reg1_error_loopf \n"
" cmp r1, #109 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d11 \n"
" cmp r0, #110 \n"
" bne reg1_error_loopf \n"
" cmp r1, #111 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d12 \n"
" cmp r0, #100 \n"
" bne reg1_error_loopf \n"
" cmp r1, #101 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d13 \n"
" cmp r0, #102 \n"
" bne reg1_error_loopf \n"
" cmp r1, #103 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d14 \n"
" cmp r0, #104 \n"
" bne reg1_error_loopf \n"
" cmp r1, #105 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d15 \n"
" cmp r0, #106 \n"
" bne reg1_error_loopf \n"
" cmp r1, #107 \n"
" bne reg1_error_loopf \n"
" \n"
" /* Restore the registers that were clobbered by the test. */\n"
" pop {r0-r1} \n"
" \n"
" /* VFP register test passed. Jump to the core register test. */\n"
" b reg1_loopf_pass \n"
" \n"
"reg1_error_loopf: \n"
" /* If this line is hit then a VFP register value was found to be\n"
" incorrect. */ \n"
" b reg1_error_loopf \n"
" \n"
"reg1_loopf_pass: \n"
" \n"
" cmp r0, #100 \n"
" bne reg1_error_loop \n"
" cmp r1, #101 \n"
" bne reg1_error_loop \n"
" cmp r2, #102 \n"
" bne reg1_error_loop \n"
" cmp r3, #103 \n"
" bne reg1_error_loop \n"
" cmp r4, #104 \n"
" bne reg1_error_loop \n"
" cmp r5, #105 \n"
" bne reg1_error_loop \n"
" cmp r6, #106 \n"
" bne reg1_error_loop \n"
" cmp r7, #107 \n"
" bne reg1_error_loop \n"
" cmp r8, #108 \n"
" bne reg1_error_loop \n"
" cmp r9, #109 \n"
" bne reg1_error_loop \n"
" cmp r10, #110 \n"
" bne reg1_error_loop \n"
" cmp r11, #111 \n"
" bne reg1_error_loop \n"
" cmp r12, #112 \n"
" bne reg1_error_loop \n"
" \n"
" /* Everything passed, increment the loop counter. */ \n"
" push { r0-r1 } \n"
" ldr r0, =ulRegTest1LoopCounter \n"
" ldr r1, [r0] \n"
" adds r1, r1, #1 \n"
" str r1, [r0] \n"
" pop { r0-r1 } \n"
" \n"
" /* Start again. */ \n"
" b reg1_loop \n"
" \n"
"reg1_error_loop: \n"
" /* If this line is hit then there was an error in a core register value.\n"
" The loop ensures the loop counter stops incrementing. */\n"
" b reg1_error_loop \n"
" nop "
);
}
/*-----------------------------------------------------------*/
/* This is a naked function. */
static void prvRegTest2Task( void *pvParameters )
{
__asm volatile
(
" /* Set all the core registers to known values. */ \n"
" mov r0, #-1 \n"
" mov r1, #1 \n"
" mov r2, #2 \n"
" mov r3, #3 \n"
" mov r4, #4 \n"
" mov r5, #5 \n"
" mov r6, #6 \n"
" mov r7, #7 \n"
" mov r8, #8 \n"
" mov r9, #9 \n"
" mov r10, #10 \n"
" mov r11, #11 \n"
" mov r12, #12 \n"
" \n"
" /* Set all the VFP to known values. */ \n"
" vmov d0, r0, r1 \n"
" vmov d1, r2, r3 \n"
" vmov d2, r4, r5 \n"
" vmov d3, r6, r7 \n"
" vmov d4, r8, r9 \n"
" vmov d5, r10, r11 \n"
" vmov d6, r0, r1 \n"
" vmov d7, r2, r3 \n"
" vmov d8, r4, r5 \n"
" vmov d9, r6, r7 \n"
" vmov d10, r8, r9 \n"
" vmov d11, r10, r11 \n"
" vmov d12, r0, r1 \n"
" vmov d13, r2, r3 \n"
" vmov d14, r4, r5 \n"
" vmov d15, r6, r7 \n"
" \n"
"reg2_loop: \n"
" \n"
" /* Check all the VFP registers still contain the values set above.\n"
" First save registers that are clobbered by the test. */ \n"
" push { r0-r1 } \n"
" \n"
" vmov r0, r1, d0 \n"
" cmp r0, #-1 \n"
" bne reg2_error_loopf \n"
" cmp r1, #1 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d1 \n"
" cmp r0, #2 \n"
" bne reg2_error_loopf \n"
" cmp r1, #3 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d2 \n"
" cmp r0, #4 \n"
" bne reg2_error_loopf \n"
" cmp r1, #5 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d3 \n"
" cmp r0, #6 \n"
" bne reg2_error_loopf \n"
" cmp r1, #7 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d4 \n"
" cmp r0, #8 \n"
" bne reg2_error_loopf \n"
" cmp r1, #9 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d5 \n"
" cmp r0, #10 \n"
" bne reg2_error_loopf \n"
" cmp r1, #11 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d6 \n"
" cmp r0, #-1 \n"
" bne reg2_error_loopf \n"
" cmp r1, #1 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d7 \n"
" cmp r0, #2 \n"
" bne reg2_error_loopf \n"
" cmp r1, #3 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d8 \n"
" cmp r0, #4 \n"
" bne reg2_error_loopf \n"
" cmp r1, #5 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d9 \n"
" cmp r0, #6 \n"
" bne reg2_error_loopf \n"
" cmp r1, #7 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d10 \n"
" cmp r0, #8 \n"
" bne reg2_error_loopf \n"
" cmp r1, #9 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d11 \n"
" cmp r0, #10 \n"
" bne reg2_error_loopf \n"
" cmp r1, #11 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d12 \n"
" cmp r0, #-1 \n"
" bne reg2_error_loopf \n"
" cmp r1, #1 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d13 \n"
" cmp r0, #2 \n"
" bne reg2_error_loopf \n"
" cmp r1, #3 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d14 \n"
" cmp r0, #4 \n"
" bne reg2_error_loopf \n"
" cmp r1, #5 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d15 \n"
" cmp r0, #6 \n"
" bne reg2_error_loopf \n"
" cmp r1, #7 \n"
" bne reg2_error_loopf \n"
" \n"
" /* Restore the registers that were clobbered by the test. */\n"
" pop {r0-r1} \n"
" \n"
" /* VFP register test passed. Jump to the core register test. */\n"
" b reg2_loopf_pass \n"
" \n"
"reg2_error_loopf: \n"
" /* If this line is hit then a VFP register value was found to be\n"
" incorrect. */ \n"
" b reg2_error_loopf \n"
" \n"
"reg2_loopf_pass: \n"
" \n"
" cmp r0, #-1 \n"
" bne reg2_error_loop \n"
" cmp r1, #1 \n"
" bne reg2_error_loop \n"
" cmp r2, #2 \n"
" bne reg2_error_loop \n"
" cmp r3, #3 \n"
" bne reg2_error_loop \n"
" cmp r4, #4 \n"
" bne reg2_error_loop \n"
" cmp r5, #5 \n"
" bne reg2_error_loop \n"
" cmp r6, #6 \n"
" bne reg2_error_loop \n"
" cmp r7, #7 \n"
" bne reg2_error_loop \n"
" cmp r8, #8 \n"
" bne reg2_error_loop \n"
" cmp r9, #9 \n"
" bne reg2_error_loop \n"
" cmp r10, #10 \n"
" bne reg2_error_loop \n"
" cmp r11, #11 \n"
" bne reg2_error_loop \n"
" cmp r12, #12 \n"
" bne reg2_error_loop \n"
" \n"
" /* Increment the loop counter to indicate this test is still functioning\n"
" correctly. */ \n"
" push { r0-r1 } \n"
" ldr r0, =ulRegTest2LoopCounter \n"
" ldr r1, [r0] \n"
" adds r1, r1, #1 \n"
" str r1, [r0] \n"
" pop { r0-r1 } \n"
" \n"
" /* Start again. */ \n"
" b reg2_loop \n"
" \n"
"reg2_error_loop: \n"
" /* If this line is hit then there was an error in a core register value.\n"
" This loop ensures the loop counter variable stops incrementing. */\n"
" b reg2_error_loop \n"
" nop \n"
);
}
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