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RISC-V: refine fpu reg context offset (#1257)

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RISC-V: refine fpu reg context offset

pxCode and mstatus stored at index 0 and 1 are based on XLEN.
Therefore, the correct formula to calculate the FPU register index
should be ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) ).

Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
main
Saiiijchan 22 hours ago committed by GitHub
parent bb47bc02f2
commit 64fd9291ef
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1 changed files with 67 additions and 66 deletions
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133
portable/GCC/RISC-V/portContext.h
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@ -87,6 +87,7 @@
#define portFPU_REG_SIZE ( __riscv_flen / 8 )
#define portFPU_REG_COUNT 33 /* 32 Floating point registers plus one CSR. */
#define portFPU_REG_OFFSET( regIndex ) ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) )
#define portFPU_CONTEXT_SIZE ( portFPU_REG_SIZE * portFPU_REG_COUNT )
#else
#error configENABLE_FPU must not be set to 1 if the hardwar does not have FPU
@ -103,78 +104,78 @@
.macro portcontexSAVE_FPU_CONTEXT
addi sp, sp, -( portFPU_CONTEXT_SIZE )
/* Store the FPU registers. */
store_f f0, 2 * portFPU_REG_SIZE( sp )
store_f f1, 3 * portFPU_REG_SIZE( sp )
store_f f2, 4 * portFPU_REG_SIZE( sp )
store_f f3, 5 * portFPU_REG_SIZE( sp )
store_f f4, 6 * portFPU_REG_SIZE( sp )
store_f f5, 7 * portFPU_REG_SIZE( sp )
store_f f6, 8 * portFPU_REG_SIZE( sp )
store_f f7, 9 * portFPU_REG_SIZE( sp )
store_f f8, 10 * portFPU_REG_SIZE( sp )
store_f f9, 11 * portFPU_REG_SIZE( sp )
store_f f10, 12 * portFPU_REG_SIZE( sp )
store_f f11, 13 * portFPU_REG_SIZE( sp )
store_f f12, 14 * portFPU_REG_SIZE( sp )
store_f f13, 15 * portFPU_REG_SIZE( sp )
store_f f14, 16 * portFPU_REG_SIZE( sp )
store_f f15, 17 * portFPU_REG_SIZE( sp )
store_f f16, 18 * portFPU_REG_SIZE( sp )
store_f f17, 19 * portFPU_REG_SIZE( sp )
store_f f18, 20 * portFPU_REG_SIZE( sp )
store_f f19, 21 * portFPU_REG_SIZE( sp )
store_f f20, 22 * portFPU_REG_SIZE( sp )
store_f f21, 23 * portFPU_REG_SIZE( sp )
store_f f22, 24 * portFPU_REG_SIZE( sp )
store_f f23, 25 * portFPU_REG_SIZE( sp )
store_f f24, 26 * portFPU_REG_SIZE( sp )
store_f f25, 27 * portFPU_REG_SIZE( sp )
store_f f26, 28 * portFPU_REG_SIZE( sp )
store_f f27, 29 * portFPU_REG_SIZE( sp )
store_f f28, 30 * portFPU_REG_SIZE( sp )
store_f f29, 31 * portFPU_REG_SIZE( sp )
store_f f30, 32 * portFPU_REG_SIZE( sp )
store_f f31, 33 * portFPU_REG_SIZE( sp )
store_f f0, portFPU_REG_OFFSET( 0 )( sp )
store_f f1, portFPU_REG_OFFSET( 1 )( sp )
store_f f2, portFPU_REG_OFFSET( 2 )( sp )
store_f f3, portFPU_REG_OFFSET( 3 )( sp )
store_f f4, portFPU_REG_OFFSET( 4 )( sp )
store_f f5, portFPU_REG_OFFSET( 5 )( sp )
store_f f6, portFPU_REG_OFFSET( 6 )( sp )
store_f f7, portFPU_REG_OFFSET( 7 )( sp )
store_f f8, portFPU_REG_OFFSET( 8 )( sp )
store_f f9, portFPU_REG_OFFSET( 9 )( sp )
store_f f10, portFPU_REG_OFFSET( 10 )( sp )
store_f f11, portFPU_REG_OFFSET( 11 )( sp )
store_f f12, portFPU_REG_OFFSET( 12 )( sp )
store_f f13, portFPU_REG_OFFSET( 13 )( sp )
store_f f14, portFPU_REG_OFFSET( 14 )( sp )
store_f f15, portFPU_REG_OFFSET( 15 )( sp )
store_f f16, portFPU_REG_OFFSET( 16 )( sp )
store_f f17, portFPU_REG_OFFSET( 17 )( sp )
store_f f18, portFPU_REG_OFFSET( 18 )( sp )
store_f f19, portFPU_REG_OFFSET( 19 )( sp )
store_f f20, portFPU_REG_OFFSET( 20 )( sp )
store_f f21, portFPU_REG_OFFSET( 21 )( sp )
store_f f22, portFPU_REG_OFFSET( 22 )( sp )
store_f f23, portFPU_REG_OFFSET( 23 )( sp )
store_f f24, portFPU_REG_OFFSET( 24 )( sp )
store_f f25, portFPU_REG_OFFSET( 25 )( sp )
store_f f26, portFPU_REG_OFFSET( 26 )( sp )
store_f f27, portFPU_REG_OFFSET( 27 )( sp )
store_f f28, portFPU_REG_OFFSET( 28 )( sp )
store_f f29, portFPU_REG_OFFSET( 29 )( sp )
store_f f30, portFPU_REG_OFFSET( 30 )( sp )
store_f f31, portFPU_REG_OFFSET( 31 )( sp )
csrr t0, fcsr
store_x t0, 34 * portFPU_REG_SIZE( sp )
store_x t0, portFPU_REG_OFFSET( 32 )( sp )
.endm
/*-----------------------------------------------------------*/
.macro portcontextRESTORE_FPU_CONTEXT
/* Restore the FPU registers. */
load_f f0, 2 * portFPU_REG_SIZE( sp )
load_f f1, 3 * portFPU_REG_SIZE( sp )
load_f f2, 4 * portFPU_REG_SIZE( sp )
load_f f3, 5 * portFPU_REG_SIZE( sp )
load_f f4, 6 * portFPU_REG_SIZE( sp )
load_f f5, 7 * portFPU_REG_SIZE( sp )
load_f f6, 8 * portFPU_REG_SIZE( sp )
load_f f7, 9 * portFPU_REG_SIZE( sp )
load_f f8, 10 * portFPU_REG_SIZE( sp )
load_f f9, 11 * portFPU_REG_SIZE( sp )
load_f f10, 12 * portFPU_REG_SIZE( sp )
load_f f11, 13 * portFPU_REG_SIZE( sp )
load_f f12, 14 * portFPU_REG_SIZE( sp )
load_f f13, 15 * portFPU_REG_SIZE( sp )
load_f f14, 16 * portFPU_REG_SIZE( sp )
load_f f15, 17 * portFPU_REG_SIZE( sp )
load_f f16, 18 * portFPU_REG_SIZE( sp )
load_f f17, 19 * portFPU_REG_SIZE( sp )
load_f f18, 20 * portFPU_REG_SIZE( sp )
load_f f19, 21 * portFPU_REG_SIZE( sp )
load_f f20, 22 * portFPU_REG_SIZE( sp )
load_f f21, 23 * portFPU_REG_SIZE( sp )
load_f f22, 24 * portFPU_REG_SIZE( sp )
load_f f23, 25 * portFPU_REG_SIZE( sp )
load_f f24, 26 * portFPU_REG_SIZE( sp )
load_f f25, 27 * portFPU_REG_SIZE( sp )
load_f f26, 28 * portFPU_REG_SIZE( sp )
load_f f27, 29 * portFPU_REG_SIZE( sp )
load_f f28, 30 * portFPU_REG_SIZE( sp )
load_f f29, 31 * portFPU_REG_SIZE( sp )
load_f f30, 32 * portFPU_REG_SIZE( sp )
load_f f31, 33 * portFPU_REG_SIZE( sp )
load_x t0, 34 * portFPU_REG_SIZE( sp )
load_f f0, portFPU_REG_OFFSET( 0 )( sp )
load_f f1, portFPU_REG_OFFSET( 1 )( sp )
load_f f2, portFPU_REG_OFFSET( 2 )( sp )
load_f f3, portFPU_REG_OFFSET( 3 )( sp )
load_f f4, portFPU_REG_OFFSET( 4 )( sp )
load_f f5, portFPU_REG_OFFSET( 5 )( sp )
load_f f6, portFPU_REG_OFFSET( 6 )( sp )
load_f f7, portFPU_REG_OFFSET( 7 )( sp )
load_f f8, portFPU_REG_OFFSET( 8 )( sp )
load_f f9, portFPU_REG_OFFSET( 9 )( sp )
load_f f10, portFPU_REG_OFFSET( 10 )( sp )
load_f f11, portFPU_REG_OFFSET( 11 )( sp )
load_f f12, portFPU_REG_OFFSET( 12 )( sp )
load_f f13, portFPU_REG_OFFSET( 13 )( sp )
load_f f14, portFPU_REG_OFFSET( 14 )( sp )
load_f f15, portFPU_REG_OFFSET( 15 )( sp )
load_f f16, portFPU_REG_OFFSET( 16 )( sp )
load_f f17, portFPU_REG_OFFSET( 17 )( sp )
load_f f18, portFPU_REG_OFFSET( 18 )( sp )
load_f f19, portFPU_REG_OFFSET( 19 )( sp )
load_f f20, portFPU_REG_OFFSET( 20 )( sp )
load_f f21, portFPU_REG_OFFSET( 21 )( sp )
load_f f22, portFPU_REG_OFFSET( 22 )( sp )
load_f f23, portFPU_REG_OFFSET( 23 )( sp )
load_f f24, portFPU_REG_OFFSET( 24 )( sp )
load_f f25, portFPU_REG_OFFSET( 25 )( sp )
load_f f26, portFPU_REG_OFFSET( 26 )( sp )
load_f f27, portFPU_REG_OFFSET( 27 )( sp )
load_f f28, portFPU_REG_OFFSET( 28 )( sp )
load_f f29, portFPU_REG_OFFSET( 29 )( sp )
load_f f30, portFPU_REG_OFFSET( 30 )( sp )
load_f f31, portFPU_REG_OFFSET( 31 )( sp )
load_x t0, portFPU_REG_OFFSET( 32 )( sp )
csrw fcsr, t0
addi sp, sp, ( portFPU_CONTEXT_SIZE )
.endm

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