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CI-CD Updates (#768)

Browse Source 
* Use new version of CI-CD Actions
* Use cSpell spell check, and use ubuntu-20.04 for formatting check
* Format and spell check all files in the portable directory
* Remove the https:// from #errors and #warnings as uncrustify attempts to change it to /*
* Use checkout@v3 instead of checkout@v2 on all jobs
---------
pull/659/head
Soren Ptak 1 year ago committed by GitHub
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commit 5fb9b50da8
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485 changed files with 112534 additions and 111325 deletions
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918
.github/.cSpellWords.txt vendored
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@ -0,0 +1,918 @@
AASR
ABETRG
ABSR
ABTSZ
ACCAH
ACCAL
ACCAU
ACCBH
ACCBL
ACCBU
ACLK
acpa
ACPA
acpc
ACPC
addi
addiu
ADTRG
aeevt
AEEVT
AERR
AIRCR
ALMIEN
ALMV
ANDC
ANDCCR
APIC
APROCFREQ
APSR
ARMCM
Armv
ARMVFP
ASTRINGZ
aswtrg
ASWTRG
Ateml
ATMEGA
Atmel
ATMEL
atomatic
ATPASTE
AVRDX
BANDL
bcpb
BCPB
bcpc
BCPC
beevt
BEEVT
BERR
bfextu
Biagioni
bics
BISR
BODIEN
BODSTS
BRGR
brhi
brne
bswtrg
BSWTRG
CANEN
CANRX
CANTX
capitalisation
cbmc
CBMC
cbor
CBOR
CCIE
CCMP
CCNT
CCNTR
CCPN
CCPR
CDTY
CDTYR
CFBS
CFRC
CHDIV
CHDR
CHRL
CHSR
CICR
CISR
CKDIV
CKEY
CKGR
CKLO
CKPS
CLDIV
CLKA
CLKB
CLKEN
clki
CLKI
CLKP
CLKS
CLKSTA
CLRB
CLRF
CLRPSW
CMCNT
CMCON
CMCOR
CMCR
CMIE
cmock
Cmock
CMock
CMOCK
cmpx
CMSIS
CMSTR
CNTE
coalescences
CODAN
codecov
CODR
comms
COMPA
CONFG
CORTUS
coverity
Coverity
covfs
COVFS
CPACR
cpas
CPAS
cpbs
CPBS
cpcdis
CPCDIS
CPCS
cpcstop
CPCSTOP
CPCTRG
CPIV
CPRD
CPRDR
CPRE
cpsid
cpsie
CPSR
CPUID
CRCB
crflash
CRGFLG
CRGINT
crhook
croutine
CRTV
CSAAT
csrr
csrs
csrw
CTCR
ctest
CTRLA
CTSIC
CUPD
CUPDR
CWGR
cxsf
CYGNAL
DADR
daif
DAIFCLR
DAIFSET
DATAR
DATAW
DATNB
DATRDY
DBGU
DCDIC
DCMR
DCOUNT
decf
decfsz
DECNT
DFPU
DFREERTOS
dicr
DICR
DIVB
DLYBCS
DLYBCT
DLYBS
DLYI
DNDEBUG
DOCOUNT
DOENDH
DOENDL
DOHIGH
DOLOW
DOSTARTH
DOSTARTL
DPFPU
DPLB
DPOPM
DPSW
DPUSHM
DRDY
DRFCS
DRPT
DRXD
DSLPE
DSNACK
DSPIC
DSRIC
DSWPAG
DTGLE
DTREN
DTXD
DUNITY
DVAR
EABI
ecall
ECIT
ECRS
ECRSDV
eevt
EEVT
eevtedg
EEVTEDG
EFRHD
EINT
EIPC
EIPSW
Elektronika
EMACB
EMDC
EMDIO
emption
endm
ENDRX
ENDTX
enetrg
ENETRG
ENMFILE
EOICR
epage
EPEDS
EPINT
EPTYPE
EQIC
EQIF
EQMK
EREFCK
eret
ERRA
ERSTL
ERXCK
ERXDV
ERXER
Espeche
Espressif
ESTATUS
ETRCS
ETRGEDG
etrgs
ETRGS
ETXCK
ETXEN
ETXER
evba
EVBA
EWARM
EWAVR
EWRL
EWRX
EXID
expandnl
EXTRSM
FADD
FCMD
fcolor
FCSE
fdiagnostics
fdiv
FDIV
FEDPICC
FERR
FFDR
FFER
FFSR
FIDI
FLASH
Flsh
FLSH
FMCN
FMRXNE
FMXR
fninit
fnsave
FNTR
FOSC
FPCCR
FPCSR
FPSW
FPUL
FRDY
Frieder
FSDEN
FSEDGE
FSLEN
FSOS
FSR
fwait
GCACC
GCTRL
getvect
GIEH
GIEL
GIRQ
GLBSTATE
GMSK
GNURX
GOVRE
gpio
GPIO
GPNVM
GPTA
HCLK
Hitach
HRESP
HWHSH
HWORD
HWRD
IADR
IADRSZ
ICCAVR
ICCBPR
ICCEOIR
ICCIAR
ICCICAR
ICCPMR
ICCR
ICCRPR
ICCRX
ICERST
ICSR
IDCR
IECR
IFDR
IFER
IFLASH
IFSR
imajeff
INACK
INDF
inpw
INTE
INTFRCH
INTFRCL
INTIT
INTTM
IODEFINE
IORLW
IPEN
IPLB
ipsr
IPSR
iret
IRET
IRXFCS
ISRAM
ISRR
ISR's
ISRS
ISRTICK
ITIF
ITMC
ITMK
ittt
JFRAME
JTAG
JTVIC
Kamil
kbhit
Kbyte
Krutmann
LAPIC
LCDR
LCOL
lcov
ldaa
LDATA
LDBDIS
LDBSTOP
ldmdb
LDMFD
ldmia
LDRA
ldras
LDRAS
ldrb
ldrbs
LDRBS
LDRNE
ldsr
lidt
LINKR
LJMP
LLIO
lovrs
LOVRS
lpcount
lpend
lpstart
LPTHREAD
lsls
LSPEN
LSPENS
ltorg
LWRD
MABT
MACL
MAINF
MAINRDY
MAIR
Mang
Mbits
mcause
MCFR
MCKA
MCKB
MCKR
MCKRDY
MCLK
MCU
MDDR
MDER
MDIO
MDLC
MDSR
mepc
mevents
MFCR
mfear
mfedr
mfesr
mffsr
mfgpr
mfhi
MFID
mflo
mfloat
mfmsr
mfpu
mhartid
MIDE
Mikro
MIKROC
misra
Misra
MISRA
MMCR
MMSYSERR
MOSC
MOSCS
MOSI
movem
moveq
MOVF
MOVFF
movhi
movia
movlb
movlw
movne
movs
movw
MOVWF
movx
MPLAB
MPUCTRL
MQTT
MRDY
MREAD
mret
mrseq
mrsne
MRTR
MSBF
MSDIS
MSEN
mspgcc
msreq
mstatus
MSTATUS
MSTP
MSTPA
MSTPCR
MSTPCRA
MSTPCRC
MSTR
MTCR
mthi
MTIOA
MTIOB
mtlo
mtsr
MVFACGU
MVFACHI
MVFACLO
MVFACMI
MVFC
MVTACGU
MVTACHI
MVTACLO
MVTC
MVTIPL
NCFGR
NCPHA
NEBP
NFIQ
Nios
NIOSII
NIRQ
NOGIC
noheap
nostdint
NPCS
NRSTL
NSACR
NSFPU
NSSR
NTRST
NVIC
ODAT
ODSR
OPMOD
optimisations
OPTIMISED
optimiser
ORCCR
orrs
OSCBYPASS
OSCEN
OSCOFF
OSCOUNT
OSMC
outpw
OVLY
OVRE
OVRES
OVRUN
OWATCOM
OWDR
OWER
OWSR
PAGEN
PCDR
PCER
PCKR
PCLATH
PCLATU
PCLK
PCLKSEL
PCSR
PCXI
PDSR
PEIE
PENDSV
PENDSVCLEAR
PENDSVSET
PENSVCLEAR
PERIODH
PERIODL
periph
PERIPH
PFRE
phelter
PHYA
PICNT
pico
picolibc
Picolibc
PICOLIBC
PIEN
PIIR
PIMR
PIOA
PIOB
PISR
PITC
PITEN
PITIEN
PIVR
PLLB
PLLR
popa
popm
POPNE
POPW
popx
portcomn
PORTEN
portex
portisr
POWERUP
ppuc
PPUDR
PPUER
PPUSR
ppux
PRCR
PREA
PREB
PRIA
Prioritised
PRIS
PROCDLY
PRODH
PRODL
PROGE
Prokic
prtmacro
psha
psplim
PSPLIM
PSTDBY
PSVPAG
PTCR
PTSR
Pulpino
PUON
pusha
pushf
pushm
PUSHNE
PUSHW
pushx
PWMC
RAMPZ
RASR
Rationalised
Raynald
RBAR
RBOF
RBQP
RBSY
RCALL
RCAP
RCIF
RCMR
RCOMP
RCOUNT
rddsp
RDRF
reent
REENT
REGA
RELD
Renesas
reta
reti
RETP
RETTO
RFEIA
RFMR
RIIC
RIPL
riscv
RLAR
RLCE
RLES
RLEX
RMII
RMWUPE
RNCR
RNPR
ROUSSET
ROVR
RSHR
rslcx
RSLCX
RSMINPR
RSTC
RSTEP
RSTIT
RSTNACK
RSTRX
RSTSTA
RSTTX
Rsvd
RTAR
RTCEN
RTCSC
RTIE
RTIF
RTIFRC
RTMR
RTOR
RTSEN
RTSR
RTTC
RTVR
RVDS
RXBRK
RXBUFF
RXBYTECNT
RXDIS
Rxed
RXEN
RXENA
RXOVERWRITE
RXRDY
RXRSM
RXSETUP
RXSUSP
RXSYN
RXTEN
RXUBR
SBYCR
SCALL
SCBR
SCDR
SCER
SCSR
SDCC
SECU
SENDA
SETB
SETEN
SETPSW
SETR
setvect
SFRC
SHLL
SHLR
SHPR
SHTIM
SIFIVE
sinclude
SODR
SOFTIRQ
SPCK
SPIEN
SPSR
SRCMP
SREG
SRSDB
SSBY
SSIR
SSKEY
staa
Stellaris
STILM
STKPTR
stmdb
stmia
stsr
STTBRK
STTDLY
STTOUT
STTTO
SVACC
svcne
SVDIS
svlcx
SVMST
SWAPW
SWHSH
SWINR
SWINT
SWINTR
SWRST
SWTRG
synchronise
SYSC
TACCR
TACCTL
TACLR
TACTL
TBCTRL
TBLPTRH
TBLPTRL
TBLPTRU
TBLPTRUH
TBLPTRUL
TBQP
TBSY
tcclks
TCCR
TCKPS
TCLK
TCMR
TCOMP
TDES
TDESMOD
TDMI
TDRE
TEOF
TFLG
TFMR
TGRA
THALT
TIAO
TICKISR
TIMFRZ
TIMSK
TIOA
TIOB
tmcsr
TMCSR
TMIF
TMKAEN
TMKAIF
TMKAMK
TMMK
TMPR
TMRLR
TNCR
TNPR
TOSU
TOVF
TPCS
TPFR
TRAPA
TRGEN
TRGSEL
TSHR
tstfsz
TSTP
TSTR
TTGR
TUND
TUNDR
TWCK
TXBUFE
TXCOMP
TXDIS
TXEMPTY
TXEN
TXENA
TXERR
TXIE
TXIF
TXPKTRDY
TXRDY
TXSYN
TXTEN
TXUBR
TXVC
TXVDIS
UDCP
uncrustify
UNRE
unsuspended
URAD
URAT
URSTEN
URSTIEN
URSTS
Usart
USART
USPRG
USRIO
utest
utilises
utilising
VDDCORE
vect
VECT
VECTACTIVE
visualisation
vldmdbeq
vldmia
vldmiaeq
VMSRNE
vpop
VPOPNE
vpush
VPUSHNE
VRPM
Vrtc
vstmdbeq
vstmiaeq
VTOR
W
WAVESEL
wavsel
Wcolor
Wconversion
WDCR
WDDBGHLT
WDDIS
WDERR
WDFIEN
WDIDLEHLT
WDMR
WDRPROC
WDRSTEN
WDRSTT
WDSR
WDTC
wdtcon
WDUNF
Werror
WESTAT
Weverything
Wextra
winmm
WIZC
Wpedantic
wrdsp
WREG
Wunused
XEXC
XPAR
xparameters
XPSR
XRAM
xtal
XTENSA

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.github/lexicon.txt vendored
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2
.github/pull_request_process.md vendored
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@ -1,6 +1,6 @@
# Pull Request Process
This document explains the stages that a Pull Request (PR) goes through when a pull request is submitted to a git repository in the FreeRTOS organization in Github. Before you start a PR, please read and familiarize yourself with [CONTRIBUTING.md](.github/CONTRIBUTING.md)
This document explains the stages that a Pull Request (PR) goes through when a pull request is submitted to a git repository in the FreeRTOS organization in Github. Before you start a PR, please read and familiarize yourself with [CONTRIBUTING.md](CONTRIBUTING.md)
## ****Terminologies****

8
.github/scripts/kernel_checker.py vendored
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@ -36,7 +36,8 @@ from common.header_checker import HeaderChecker
KERNEL_IGNORED_FILES = [
'FreeRTOS-openocd.c',
'Makefile',
'.DS_Store'
'.DS_Store',
'cspell.config.yaml'
]
KERNEL_IGNORED_EXTENSIONS = [
@ -88,7 +89,10 @@ KERNEL_IGNORED_PATTERNS = [
r'.*portable/IAR/AtmelSAM7S64/.*AT91SAM7.*',
r'.*portable/GCC/ARM7_AT91SAM7S/.*',
r'.*portable/MPLAB/PIC18F/stdio.h',
r'.*portable/ThirdParty/xClang/XCOREAI/*'
r'.*portable/ThirdParty/xClang/XCOREAI/*',
r'.*IAR/ARM_C*',
r'.*IAR/78K0R/*',
r'.*CCS/MSP430X/*'
]
KERNEL_THIRD_PARTY_PATTERNS = [

4
.github/workflows/auto-release.yml vendored
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@ -31,14 +31,14 @@ jobs:
# Currently FreeRTOS/.github/scripts houses the release script. Download it for upcoming usage
- name: Checkout FreeRTOS Release Tools
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
repository: FreeRTOS/FreeRTOS
path: tools
# Simpler git auth if we use checkout action and forward the repo to release script
- name: Checkout FreeRTOS Kernel
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
path: local_kernel
fetch-depth: 0

92
.github/workflows/ci.yml vendored
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@ -6,75 +6,53 @@ on:
branches: [main]
workflow_dispatch:
jobs:
formatting:
runs-on: ubuntu-20.04
steps:
- uses: actions/checkout@v3
- name: Check Formatting of FreeRTOS-Kernel Files
uses: FreeRTOS/CI-CD-Github-Actions/formatting@main
spell-check:
runs-on: ubuntu-latest
steps:
- name: Checkout Parent Repo
uses: actions/checkout@v2
with:
ref: main
repository: aws/aws-iot-device-sdk-embedded-C
path: main
- name: Clone This Repo
uses: actions/checkout@v2
uses: actions/checkout@v3
- name: Run spellings check
uses: FreeRTOS/CI-CD-Github-Actions/spellings@main
with:
path: ./kernel
- name: Install spell
run: |
sudo apt-get install spell
sudo apt-get install util-linux
- name: Check spelling
run: |
PATH=$PATH:main/tools/spell
# Make sure that the portable directory is not included in the spellcheck.
sed -i 's/find $DIRNAME/find $DIRNAME -not -path '*portable*'/g' main/tools/spell/find-unknown-comment-words
find-unknown-comment-words --directory kernel/ --lexicon ./kernel/.github/lexicon.txt
if [ "$?" = "0" ]; then
exit 0
else
exit 1
fi
formatting:
runs-on: ubuntu-20.04
path: ./
exclude-files: History.txt
link-verifier:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- name: Install Uncrustify
run: sudo apt-get install uncrustify=0.69.0+dfsg1-1build1
- name: Run Uncrustify
run: |
uncrustify --version
find . portable/MemMang/* portable/Common/* \( -name portable \) -prune -false -o -iname "*.[hc]" -exec uncrustify --check -c .github/uncrustify.cfg {} +
- name: Check For Trailing Whitespace
run: |
set +e
grep --exclude="*.md" --exclude-dir=".git" -rnI -e "[[:blank:]]$" .
if [ "$?" = "0" ]; then
echo "Files have trailing whitespace."
exit 1
else
exit 0
fi
shell: bash
- name: Check for CRLF
working-directory: ${{ inputs.path }}
run: |
set +e
find . -path ./.git -prune -o -exec file {} + | grep "CRLF"
if [ "$?" = "0" ]; then
echo "Files have CRLF line endings."
exit 1
else
exit 0
fi
shell: bash
- name: Clone This Repo
uses: actions/checkout@v3
- name: Link Verification
uses: FreeRTOS/CI-CD-Github-Actions/link-verifier@v2
url-check:
runs-on: ubuntu-latest
steps:
- name: Clone This Repo
uses: actions/checkout@v2
- uses: actions/checkout@v3
with:
path: ./kernel
- name: URL Checker
run: |
bash kernel/.github/actions/url_verifier.sh kernel
verify-manifest:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
with:
submodules: true
fetch-depth: 0
- name: Run manifest verifier
uses: FreeRTOS/CI-CD-GitHub-Actions/manifest-verifier@main
with:
path: ./
fail-on-incorrect-version: true

4
.github/workflows/git-secrets.yml vendored
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@ -7,11 +7,11 @@ jobs:
git-secrets:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- uses: actions/checkout@v3
with:
submodules: recursive
- name: Checkout awslabs/git-secrets
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
repository: awslabs/git-secrets
ref: master

4
.github/workflows/kernel-checks.yml vendored
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@ -18,7 +18,7 @@ jobs:
# There is shared code, hosted by FreeRTOS/FreeRTOS, with deps needed by header checker
- name: Checkout FreeRTOS Tools
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
repository: FreeRTOS/FreeRTOS
ref: main
@ -26,7 +26,7 @@ jobs:
# Checkout user pull request changes
- name: Checkout Pull Request
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
path: inspect

20
.github/workflows/kernel-demos.yml vendored
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@ -7,7 +7,7 @@ jobs:
runs-on: windows-latest
steps:
- name: Checkout the FreeRTOS/FreeRTOS Repository
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
ref: main
repository: FreeRTOS/FreeRTOS
@ -16,7 +16,7 @@ jobs:
# Checkout user pull request changes
- name: Checkout Pull Request
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
path: ./FreeRTOS/Source
@ -36,7 +36,7 @@ jobs:
runs-on: windows-latest
steps:
- name: Checkout the FreeRTOS/FreeRTOS Repository
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
ref: main
repository: FreeRTOS/FreeRTOS
@ -45,7 +45,7 @@ jobs:
# Checkout user pull request changes
- name: Checkout Pull Request
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
path: ./FreeRTOS/Source
@ -61,7 +61,7 @@ jobs:
runs-on: ubuntu-latest
steps:
- name: Checkout the FreeRTOS/FreeRTOS Repository
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
ref: main
repository: FreeRTOS/FreeRTOS
@ -70,7 +70,7 @@ jobs:
# Checkout user pull request changes
- name: Checkout Pull Request
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
path: ./FreeRTOS/Source
@ -95,7 +95,7 @@ jobs:
runs-on: ubuntu-latest
steps:
- name: Checkout the FreeRTOS/FreeRTOS Repository
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
ref: main
repository: FreeRTOS/FreeRTOS
@ -104,7 +104,7 @@ jobs:
# Checkout user pull request changes
- name: Checkout Pull Request
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
path: ./FreeRTOS/Source
@ -124,7 +124,7 @@ jobs:
runs-on: ubuntu-latest
steps:
- name: Checkout the FreeRTOS/FreeRTOS Repository
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
ref: main
repository: FreeRTOS/FreeRTOS
@ -146,7 +146,7 @@ jobs:
# Checkout user pull request changes
- name: Checkout Pull Request
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
path: ./FreeRTOS/Source

4
.github/workflows/unit-tests.yml vendored
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@ -6,7 +6,7 @@ jobs:
runs-on: ubuntu-20.04
steps:
- name: Checkout Parent Repository
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
ref: main
repository: FreeRTOS/FreeRTOS
@ -15,7 +15,7 @@ jobs:
# Checkout user pull request changes
- name: Checkout Pull Request
uses: actions/checkout@v2
uses: actions/checkout@v3
with:
path: ./FreeRTOS/Source

2
CMakeLists.txt
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@ -4,7 +4,7 @@ cmake_minimum_required(VERSION 3.15)
# FREERTOS_PORT, if not specified and native port detected, uses the native compile.
#
# User is responsible for one library target:
# freertos_config ,typcially an INTERFACE library
# freertos_config ,typically an INTERFACE library
#
# DEPRECATED: FREERTOS_CONFIG_FILE_DIRECTORY - but still supported if no freertos_config defined for now.
# May be removed at some point in the future.

67
README.md
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@ -1,14 +1,28 @@
[![CMock Unit Tests](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml/badge.svg?branch=main&event=push)](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml?query=branch%3Amain+event%3Apush+workflow%3A%22CMock+Unit+Tests%22++)
[![codecov](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel/badge.svg?branch=main)](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel)
## Getting started
This repository contains FreeRTOS kernel source/header files and kernel ports only. This repository is referenced as a submodule in [FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS) repository, which contains pre-configured demo application projects under ```FreeRTOS/Demo``` directory.
The easiest way to use FreeRTOS is to start with one of the pre-configured demo application projects. That way you will have the correct FreeRTOS source files included, and the correct include paths configured. Once a demo application is building and executing you can remove the demo application files, and start to add in your own application source files. See the [FreeRTOS Kernel Quick Start Guide](https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html) for detailed instructions and other useful links.
Additionally, for FreeRTOS kernel feature information refer to the [Developer Documentation](https://www.FreeRTOS.org/features.html), and [API Reference](https://www.FreeRTOS.org/a00106.html).
This repository contains FreeRTOS kernel source/header files and kernel
ports only. This repository is referenced as a submodule in
[FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS)
repository, which contains pre-configured demo application projects under
```FreeRTOS/Demo``` directory.
The easiest way to use FreeRTOS is to start with one of the pre-configured demo
application projects. That way you will have the correct FreeRTOS source files
included, and the correct include paths configured. Once a demo application is
building and executing you can remove the demo application files, and start to
add in your own application source files. See the
[FreeRTOS Kernel Quick Start Guide](https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html)
for detailed instructions and other useful links.
Additionally, for FreeRTOS kernel feature information refer to the
[Developer Documentation](https://www.FreeRTOS.org/features.html),
and [API Reference](https://www.FreeRTOS.org/a00106.html).
### Getting help
If you have any questions or need assistance troubleshooting your FreeRTOS project, we have an active community that can help on the [FreeRTOS Community Support Forum](https://forums.freertos.org).
If you have any questions or need assistance troubleshooting your FreeRTOS project,
we have an active community that can help on the
[FreeRTOS Community Support Forum](https://forums.freertos.org).
## To consume FreeRTOS-Kernel
@ -99,22 +113,49 @@ See the readme file in the ```./portable``` directory for more information.
- The ```./include``` directory contains the real time kernel header files.
### Code Formatting
FreeRTOS files are formatted using the "uncrustify" tool. The configuration file used by uncrustify can be found in the [.github/uncrustify.cfg](.github/uncrustify.cfg) file.
FreeRTOS files are formatted using the
"[uncrustify](https://github.com/uncrustify/uncrustify)" tool.
The configuration file used by uncrustify can be found in the
[FreeRTOS/CI-CD-GitHub-Actions's](https://github.com/FreeRTOS/CI-CD-Github-Actions)
[uncrustify.cfg](https://github.com/FreeRTOS/CI-CD-Github-Actions/tree/main/formatting)
file.
### Line Endings
File checked into the FreeRTOS-Kernel repository use unix-style LF line endings for the best compatibility with git.
File checked into the FreeRTOS-Kernel repository use unix-style LF line endings
for the best compatibility with git.
For optimal compatibility with Microsoft Windows tools, it is best to enable the git autocrlf feature. You can enable this setting for the current repository using the following command:
For optimal compatibility with Microsoft Windows tools, it is best to enable
the git autocrlf feature. You can enable this setting for the current
repository using the following command:
```
git config core.autocrlf true
```
### Git History Optimizations
Some commits in this repository perform large refactors which touch many lines and lead to unwanted behavior when using the `git blame` command. You can configure git to ignore the list of large refactor commits in this repository with the following command:
Some commits in this repository perform large refactors which touch many lines
and lead to unwanted behavior when using the `git blame` command. You can
configure git to ignore the list of large refactor commits in this repository
with the following command:
```
git config blame.ignoreRevsFile .git-blame-ignore-revs
```
### Spelling
*lexicon.txt* contains words that are not traditionally found in an English dictionary. It is used by the spellchecker to verify the various jargon, variable names, and other odd words used in the FreeRTOS code base. If your pull request fails to pass the spelling and you believe this is a mistake, then add the word to *lexicon.txt*.
Note that only the FreeRTOS Kernel source files are checked for proper spelling, the portable section is ignored.
### Spelling and Formatting
We recommend using [Visual Studio Code](https://code.visualstudio.com),
commonly referred to as VSCode, when working on the FreeRTOS-Kernel.
The FreeRTOS-Kernel also uses [cSpell](https://cspell.org/) as part of its
spelling check. The config file for which can be found at [cspell.config.yaml](cspell.config.yaml)
There is additionally a
[cSpell plugin for VSCode](https://marketplace.visualstudio.com/items?itemName=streetsidesoftware.code-spell-checker)
that can be used as well.
*[.cSpellWords.txt](.github/.cSpellWords.txt)* contains words that are not
traditionally found in an English dictionary. It is used by the spellchecker
to verify the various jargon, variable names, and other odd words used in the
FreeRTOS code base are correct. If your pull request fails to pass the spelling
and you believe this is a mistake, then add the word to
*[.cSpellWords.txt](.github/.cSpellWords.txt)*. When adding a word please
then sort the list, which can be done by running the bash command:
`sort -u .cSpellWords.txt -o .cSpellWords.txt`
Note that only the FreeRTOS-Kernel Source Files, [include](include),
[portable/MemMang](portable/MemMang), and [portable/Common](portable/Common)
files are checked for proper spelling, and formatting at this time.

31
cspell.config.yaml
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@ -0,0 +1,31 @@
---
$schema: https://raw.githubusercontent.com/streetsidesoftware/cspell/main/cspell.schema.json
version: '0.2'
# Allows things like stringLength
allowCompoundWords: true
# Read files not to spell check from the git ignore
useGitignore: true
# Language settings for C
languageSettings:
- caseSensitive: false
enabled: true
languageId: c
locale: "*"
# Add a dictionary, and the path to the word list
dictionaryDefinitions:
- name: freertos-words
path: '.github/.cSpellWords.txt'
addWords: true
dictionaries:
- freertos-words
# Paths and files to ignore
ignorePaths:
- 'dependency'
- 'docs'
- 'ThirdParty'
- 'History.txt'

2
portable/ARMv8M/ReadMe.txt
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@ -1,4 +1,4 @@
This directory tree contains the master copy of the FreeeRTOS Armv8-M and
This directory tree contains the master copy of the FreeRTOS Armv8-M and
Armv8.1-M ports.
Do not use the files located here! These file are copied into separate
FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to each

34
portable/ARMv8M/non_secure/port.c
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@ -431,7 +431,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -446,7 +447,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -459,7 +461,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulSystemCallStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -1108,13 +1111,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1155,7 +1161,7 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1215,13 +1221,16 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1262,7 +1271,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1284,6 +1293,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
@ -1291,6 +1301,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
else
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
@ -1330,13 +1341,16 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulTaskStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1374,7 +1388,7 @@ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEG
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1499,6 +1513,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
@ -1511,6 +1526,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
ulIndex++;
}
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;

9
portable/ARMv8M/secure/context/secure_context.c
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@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint32_t ulIPSR, ulSecureContextIndex;
@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;

9
portable/ARMv8M/secure/context/secure_context.h
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@ -108,7 +108,8 @@ void SecureContext_Init( void );
* @param[in] xSecureContextHandle Context handle corresponding to the
* context to be freed.
*/
void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
/**
* @brief Loads the given context.
@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be loaded.
*/
void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
/**
* @brief Saves the given context.
@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be saved.
*/
void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
#endif /* __SECURE_CONTEXT_H__ */

2
portable/ARMv8M/secure/init/secure_init.c
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@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
* permitted. CP11 should be programmed to the same value as CP10. */
*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
/* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
* that we can enable/disable lazy stacking in port.c file. */
*( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );

51
portable/BCC/16BitDOS/Flsh186/port.c
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@ -27,16 +27,16 @@
*/
/*
Changes from V1.00:
* Changes from V1.00:
*
+ Call to taskYIELD() from within tick ISR has been replaced by the more
efficient portSWITCH_CONTEXT().
+ efficient portSWITCH_CONTEXT().
+ ISR function definitions renamed to include the prv prefix.
Changes from V2.6.1
+
+ Changes from V2.6.1
+
+ Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
macro to be consistent with the later ports.
+ macro to be consistent with the later ports.
*/
/*-----------------------------------------------------------
@ -69,14 +69,16 @@ static void prvSetTickFrequency( uint32_t ulTickRateHz );
static void prvExitFunction( void );
/* The ISR used depends on whether the preemptive or cooperative scheduler
is being used. */
* is being used. */
#if ( configUSE_PREEMPTION == 1 )
/* Tick service routine used by the scheduler when preemptive scheduling is
being used. */
* being used. */
static void __interrupt __far prvPreemptiveTick( void );
#else
/* Tick service routine used by the scheduler when cooperative scheduling is
being used. */
* being used. */
static void __interrupt __far prvNonPreemptiveTick( void );
#endif
@ -89,8 +91,8 @@ static void __interrupt __far prvYieldProcessor( void );
static BaseType_t xSchedulerRunning = pdFALSE;
/* Points to the original routine installed on the vector we use for manual
context switches. This is then used to restore the original routine during
prvExitFunction(). */
* context switches. This is then used to restore the original routine during
* prvExitFunction(). */
static void( __interrupt __far * pxOldSwitchISR )();
/* Used to restore the original DOS context when the scheduler is ended. */
@ -104,11 +106,11 @@ BaseType_t xPortStartScheduler( void )
/* This is called with interrupts already disabled. */
/* Remember what was on the interrupts we are going to use
so we can put them back later if required. */
* so we can put them back later if required. */
pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
/* Put our manual switch (yield) function on a known
vector. */
* vector. */
_dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
#if ( configUSE_PREEMPTION == 1 )
@ -144,7 +146,7 @@ BaseType_t xPortStartScheduler( void )
/*-----------------------------------------------------------*/
/* The ISR used depends on whether the preemptive or cooperative scheduler
is being used. */
* is being used. */
#if ( configUSE_PREEMPTION == 1 )
static void __interrupt __far prvPreemptiveTick( void )
{
@ -158,15 +160,15 @@ is being used. */
/* Reset the PIC ready for the next time. */
portRESET_PIC();
}
#else
#else /* if ( configUSE_PREEMPTION == 1 ) */
static void __interrupt __far prvNonPreemptiveTick( void )
{
/* Same as preemptive tick, but the cooperative scheduler is being used
so we don't have to switch in the context of the next task. */
* so we don't have to switch in the context of the next task. */
xTaskIncrementTick();
portRESET_PIC();
}
#endif
#endif /* if ( configUSE_PREEMPTION == 1 ) */
/*-----------------------------------------------------------*/
static void __interrupt __far prvYieldProcessor( void )
@ -179,8 +181,8 @@ static void __interrupt __far prvYieldProcessor( void )
void vPortEndScheduler( void )
{
/* Jump back to the processor state prior to starting the
scheduler. This means we are not going to be using a
task stack frame so the task can be deleted. */
* scheduler. This means we are not going to be using a
* task stack frame so the task can be deleted. */
longjmp( xJumpBuf, 1 );
}
/*-----------------------------------------------------------*/
@ -191,18 +193,19 @@ const uint16_t usTimerDisable = 0x0000;
uint16_t usTimer0Control;
/* Interrupts should be disabled here anyway - but no
harm in making sure. */
* harm in making sure. */
portDISABLE_INTERRUPTS();
if( xSchedulerRunning == pdTRUE )
{
/* Put back the switch interrupt routines that was in place
before the scheduler started. */
* before the scheduler started. */
_dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
}
/* Disable the timer used for the tick to ensure the scheduler is
not called before restoring interrupts. There was previously nothing
on this timer so there is no old ISR to restore. */
* not called before restoring interrupts. There was previously nothing
* on this timer so there is no old ISR to restore. */
portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );
/* Restart the DOS tick. */

3
portable/BCC/16BitDOS/Flsh186/prtmacro.h
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@ -64,7 +64,8 @@ typedef unsigned short UBaseType_t;
/*-----------------------------------------------------------*/
/* Critical section handling. */
#define portENTER_CRITICAL() __asm{ pushf } \
#define portENTER_CRITICAL() \
__asm { pushf } \
__asm { cli } \
#define portEXIT_CRITICAL() __asm { popf }

69
portable/BCC/16BitDOS/PC/port.c
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@ -27,15 +27,15 @@
*/
/*
Changes from V2.6.1
* Changes from V2.6.1
*
+ Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
macro to be consistent with the later ports.
Changes from V4.0.1
+ macro to be consistent with the later ports.
+
+ Changes from V4.0.1
+
+ Add function prvSetTickFrequencyDefault() to set the DOS tick back to
its proper value when the scheduler exits.
+ its proper value when the scheduler exits.
*/
#include <stdlib.h>
@ -62,19 +62,21 @@ static void prvSetTickFrequency( uint32_t ulTickRateHz );
static void prvExitFunction( void );
/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC
directly. We chain to the DOS tick as close as possible to the standard DOS
tick rate. */
* directly. We chain to the DOS tick as close as possible to the standard DOS
* tick rate. */
static void prvPortResetPIC( void );
/* The ISR used depends on whether the preemptive or cooperative
scheduler is being used. */
* scheduler is being used. */
#if ( configUSE_PREEMPTION == 1 )
/* Tick service routine used by the scheduler when preemptive scheduling is
being used. */
* being used. */
static void __interrupt __far prvPreemptiveTick( void );
#else
/* Tick service routine used by the scheduler when cooperative scheduling is
being used. */
* being used. */
static void __interrupt __far prvNonPreemptiveTick( void );
#endif
@ -82,7 +84,7 @@ scheduler is being used. */
static void __interrupt __far prvYieldProcessor( void );
/* Set the tick frequency back so the floppy drive works correctly when the
scheduler exits. */
* scheduler exits. */
static void prvSetTickFrequencyDefault( void );
/*lint -e956 File scopes necessary here. */
@ -112,7 +114,7 @@ pxISR pxOriginalTickISR;
/* This is called with interrupts already disabled. */
/* Remember what was on the interrupts we are going to use
so we can put them back later if required. */
* so we can put them back later if required. */
pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );
pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
@ -120,15 +122,15 @@ pxISR pxOriginalTickISR;
prvSetTickFrequency( configTICK_RATE_HZ );
/* Put our manual switch (yield) function on a known
vector. */
* vector. */
_dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
/* Put the old tick on a different interrupt number so we can
call it when we want. */
* call it when we want. */
_dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );
/* The ISR used depends on whether the preemptive or cooperative
scheduler is being used. */
* scheduler is being used. */
#if ( configUSE_PREEMPTION == 1 )
{
/* Put our tick switch function on the timer interrupt. */
@ -142,8 +144,8 @@ pxISR pxOriginalTickISR;
#endif
/* Setup a counter that is used to call the DOS interrupt as close
to it's original frequency as can be achieved given our chosen tick
frequency. */
* to it's original frequency as can be achieved given our chosen tick
* frequency. */
sDOSTickCounter = portTICKS_PER_DOS_TICK;
/* Clean up function if we want to return to DOS. */
@ -165,7 +167,7 @@ pxISR pxOriginalTickISR;
/*-----------------------------------------------------------*/
/* The ISR used depends on whether the preemptive or cooperative
scheduler is being used. */
* scheduler is being used. */
#if ( configUSE_PREEMPTION == 1 )
static void __interrupt __far prvPreemptiveTick( void )
{
@ -179,15 +181,15 @@ scheduler is being used. */
/* Reset the PIC ready for the next time. */
prvPortResetPIC();
}
#else
#else /* if ( configUSE_PREEMPTION == 1 ) */
static void __interrupt __far prvNonPreemptiveTick( void )
{
/* Same as preemptive tick, but the cooperative scheduler is being used
so we don't have to switch in the context of the next task. */
* so we don't have to switch in the context of the next task. */
xTaskIncrementTick();
prvPortResetPIC();
}
#endif
#endif /* if ( configUSE_PREEMPTION == 1 ) */
/*-----------------------------------------------------------*/
static void __interrupt __far prvYieldProcessor( void )
@ -200,19 +202,22 @@ static void __interrupt __far prvYieldProcessor( void )
static void prvPortResetPIC( void )
{
/* We are going to call the DOS tick interrupt at as close a
frequency to the normal DOS tick as possible. */
* frequency to the normal DOS tick as possible. */
/* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */
--sDOSTickCounter;
if( sDOSTickCounter <= 0 )
{
sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK;
__asm{ int portSWITCH_INT_NUMBER + 1 };
__asm {
int portSWITCH_INT_NUMBER + 1
};
}
else
{
/* Reset the PIC as the DOS tick is not being called to
do it. */
* do it. */
__asm
{
mov al, 20H
@ -225,8 +230,8 @@ static void prvPortResetPIC( void )
void vPortEndScheduler( void )
{
/* Jump back to the processor state prior to starting the
scheduler. This means we are not going to be using a
task stack frame so the task can be deleted. */
* scheduler. This means we are not going to be using a
* task stack frame so the task can be deleted. */
longjmp( xJumpBuf, 1 );
}
/*-----------------------------------------------------------*/
@ -236,8 +241,9 @@ static void prvExitFunction( void )
void( __interrupt __far * pxOriginalTickISR )();
/* Interrupts should be disabled here anyway - but no
harm in making sure. */
* harm in making sure. */
portDISABLE_INTERRUPTS();
if( xSchedulerRunning == pdTRUE )
{
/* Set the DOS tick back onto the timer ticker. */
@ -246,12 +252,13 @@ void ( __interrupt __far *pxOriginalTickISR )();
prvSetTickFrequencyDefault();
/* Put back the switch interrupt routines that was in place
before the scheduler started. */
* before the scheduler started. */
_dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
_dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );
}
/* The tick timer is back how DOS wants it. We can re-enable
interrupts without the scheduler being called. */
* interrupts without the scheduler being called. */
portENABLE_INTERRUPTS();
}
/*-----------------------------------------------------------*/

3
portable/BCC/16BitDOS/PC/prtmacro.h
Unescape Escape View File

@ -64,7 +64,8 @@ typedef unsigned short UBaseType_t;
/*-----------------------------------------------------------*/
/* Critical section management. */
#define portENTER_CRITICAL() __asm{ pushf } \
#define portENTER_CRITICAL() \
__asm { pushf } \
__asm { cli } \
#define portEXIT_CRITICAL() __asm { popf }

10
portable/BCC/16BitDOS/common/portasm.h
Unescape Escape View File

@ -48,10 +48,10 @@ void portSWITCH_CONTEXT( void );
void portFIRST_CONTEXT( void );
/* There are slightly different versions depending on whether you are building
to include debugger information. If debugger information is used then there
are a couple of extra bytes left of the ISR stack (presumably for use by the
debugger). The true stack pointer is then stored in the bp register. We add
2 to the stack pointer to remove the extra bytes before we restore our context. */
* to include debugger information. If debugger information is used then there
* are a couple of extra bytes left of the ISR stack (presumably for use by the
* debugger). The true stack pointer is then stored in the bp register. We add
* 2 to the stack pointer to remove the extra bytes before we restore our context. */
#define portSWITCH_CONTEXT() \
asm { mov ax, seg pxCurrentTCB } \
@ -84,4 +84,4 @@ debugger). The true stack pointer is then stored in the bp register. We add
__asm { iret }
#endif
#endif /* ifndef PORT_ASM_H */

32
portable/BCC/16BitDOS/common/portcomn.c
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@ -27,14 +27,14 @@
*/
/*
Changes from V1.00:
* Changes from V1.00:
*
+ pxPortInitialiseStack() now initialises the stack of new tasks to the
same format used by the compiler. This allows the compiler generated
interrupt mechanism to be used for context switches.
Changes from V2.6.1
+ same format used by the compiler. This allows the compiler generated
+ interrupt mechanism to be used for context switches.
+
+ Changes from V2.6.1
+
+ Move usPortCheckFreeStackSpace() to tasks.c.
*/
@ -46,12 +46,14 @@ Changes from V2.6.1
/*-----------------------------------------------------------*/
/* See header file for description. */
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
StackType_t DS_Reg = 0;
/* Place a few bytes of known values on the bottom of the stack.
This is just useful for debugging. */
* This is just useful for debugging. */
*pxTopOfStack = 0x1111;
pxTopOfStack--;
@ -68,8 +70,8 @@ StackType_t DS_Reg = 0;
/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
/* We are going to start the scheduler using a return from interrupt
instruction to load the program counter, so first there would be the
function call with parameters preamble. */
* instruction to load the program counter, so first there would be the
* function call with parameters preamble. */
*pxTopOfStack = FP_SEG( pvParameters );
pxTopOfStack--;
@ -89,8 +91,8 @@ StackType_t DS_Reg = 0;
pxTopOfStack--;
/* The remaining registers would be pushed on the stack by our context
switch function. These are loaded with values simply to make debugging
easier. */
* switch function. These are loaded with values simply to make debugging
* easier. */
*pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
@ -103,7 +105,9 @@ StackType_t DS_Reg = 0;
pxTopOfStack--;
/* We need the true data segment. */
__asm{ MOV DS_Reg, DS };
__asm {
MOV DS_Reg, DS
};
*pxTopOfStack = DS_Reg; /* DS */
pxTopOfStack--;

0
portable/CCS/ARM_CM3/port.c
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0
portable/CCS/ARM_CM4F/port.c
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42
portable/CCS/ARM_Cortex-R4/port.c
Unescape Escape View File

@ -58,7 +58,7 @@ uint32_t ulCriticalNesting = 9999;
#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
/* The number of words on the stack frame between the saved Top Of Stack and
R0 (in which the parameters are passed. */
* R0 (in which the parameters are passed. */
#define portSPACE_BETWEEN_TOS_AND_PARAMETERS ( 12 )
/*-----------------------------------------------------------*/
@ -69,7 +69,7 @@ extern void vPortStartFirstTask( void );
/*-----------------------------------------------------------*/
/* Saved as part of the task context. Set to pdFALSE if the task does not
require an FPU context. */
* require an FPU context. */
uint32_t ulTaskHasFPUContext = 0;
/*-----------------------------------------------------------*/
@ -78,7 +78,9 @@ uint32_t ulTaskHasFPUContext = 0;
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
StackType_t * pxOriginalTOS;
@ -92,11 +94,11 @@ StackType_t *pxOriginalTOS;
#endif
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. */
* expected by the portRESTORE_CONTEXT() macro. */
/* First on the stack is the return address - which is the start of the as
the task has not executed yet. The offset is added to make the return
address appear as it would within an IRQ ISR. */
* the task has not executed yet. The offset is added to make the return
* address appear as it would within an IRQ ISR. */
*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
pxTopOfStack--;
@ -132,11 +134,11 @@ StackType_t *pxOriginalTOS;
*pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
pxTopOfStack--;
}
#else
#else /* ifdef portPRELOAD_TASK_REGISTERS */
{
pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS;
}
#endif
#endif /* ifdef portPRELOAD_TASK_REGISTERS */
/* Function parameters are passed in R0. */
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
@ -156,8 +158,8 @@ StackType_t *pxOriginalTOS;
pxTopOfStack--;
/* The last thing on the stack is the tasks ulUsingFPU value, which by
default is set to indicate that the stack frame does not include FPU
registers. */
* default is set to indicate that the stack frame does not include FPU
* registers. */
*pxTopOfStack = pdFALSE;
}
#endif
@ -208,7 +210,7 @@ BaseType_t xPortStartScheduler(void)
ulCriticalNesting = 0;
/* Start the first task. This is done from portASM.asm as ARM mode must be
used. */
* used. */
vPortStartFirstTask();
/* Should not get here! */
@ -222,7 +224,7 @@ BaseType_t xPortStartScheduler(void)
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
Artificially force an assert. */
* Artificially force an assert. */
configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
@ -237,11 +239,11 @@ void vPortEndScheduler(void)
portRTI_INTFLAG_REG = 0x00000001;
/* Increment the tick count - this may make a delaying task ready
to run - but a context switch is not performed. */
* to run - but a context switch is not performed. */
xTaskIncrementTick();
}
#else
#else /* if configUSE_PREEMPTION == 0 */
/*
**************************************************************************
@ -252,7 +254,7 @@ void vPortEndScheduler(void)
*/
void vPortPreemptiveTick( void );
#endif
#endif /* if configUSE_PREEMPTION == 0 */
/*-----------------------------------------------------------*/
@ -264,9 +266,9 @@ void vPortEnterCritical( void )
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
portDISABLE_INTERRUPTS();
/* Now interrupts are disabled ulCriticalNesting can be accessed
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
/* Now that interrupts are disabled, ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
@ -283,7 +285,7 @@ void vPortExitCritical( void )
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
re-enabled. */
* re-enabled. */
if( ulCriticalNesting == 0 )
{
/* Enable interrupts as per portENABLE_INTERRUPTS(). */
@ -300,7 +302,7 @@ void vPortExitCritical( void )
extern void vPortInitialiseFPSCR( void );
/* A task is registering the fact that it needs an FPU context. Set the
FPU flag (saved as part of the task context. */
* FPU flag (saved as part of the task context. */
ulTaskHasFPUContext = pdTRUE;
/* Initialise the floating point status register. */

2
portable/CCS/ARM_Cortex-R4/portmacro.h
Unescape Escape View File

@ -60,7 +60,7 @@ typedef unsigned long UBaseType_t;
#define portMAX_DELAY ( TickType_t ) 0xFFFFFFFFF
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
not need to be guarded with a critical section. */
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#else
#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.

60
portable/CCS/MSP430X/data_model.h
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@ -1,32 +1,34 @@
; /*
; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * SPDX-License-Identifier: MIT
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
; * this software and associated documentation files (the "Software"), to deal in
; * the Software without restriction, including without limitation the rights to
; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
; * the Software, and to permit persons to whom the Software is furnished to do so,
; * subject to the following conditions:
; *
; * The above copyright notice and this permission notice shall be included in all
; * copies or substantial portions of the Software.
; *
; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
; *
; * https://www.FreeRTOS.org
; * https://github.com/FreeRTOS
; *
; */
* ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
* ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* ; *
* ; * SPDX-License-Identifier: MIT
* ; *
* ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
* ; * this software and associated documentation files (the "Software"), to deal in
* ; * the Software without restriction, including without limitation the rights to
* ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* ; * the Software, and to permit persons to whom the Software is furnished to do so,
* ; * subject to the following conditions:
* ; *
* ; * The above copyright notice and this permission notice shall be included in all
* ; * copies or substantial portions of the Software.
* ; *
* ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* ; *
* ; * https://www.FreeRTOS.org
* ; * https://github.com/FreeRTOS
* ; *
* ; */
.if $DEFINED( __LARGE_DATA_MODEL__ )
.
if $DEFINED( __LARGE_DATA_MODEL__ )
.define "pushm.a", pushm_x
.define "popm.a", popm_x
.define "push.a", push_x
@ -40,7 +42,9 @@
.define "mov.w", mov_x
.endif
.if $DEFINED( __LARGE_CODE_MODEL__ )
.
if $DEFINED( __LARGE_CODE_MODEL__ )
.define "calla", call_x
.define "reta", ret_x
.else

50
portable/CCS/MSP430X/port.c
Unescape Escape View File

@ -35,24 +35,24 @@
*----------------------------------------------------------*/
/* Constants required for hardware setup. The tick ISR runs off the ACLK,
not the MCLK. */
* not the MCLK. */
#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 )
#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 )
/* We require the address of the pxCurrentTCB variable, but don't want to know
any details of its type. */
* any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
/* Each task maintains a count of the critical section nesting depth. Each
time a critical section is entered the count is incremented. Each time a
critical section is exited the count is decremented - with interrupts only
being re-enabled if the count is zero.
usCriticalNesting will get set to zero when the scheduler starts, but must
not be initialised to zero as this will cause problems during the startup
sequence. */
* time a critical section is entered the count is incremented. Each time a
* critical section is exited the count is decremented - with interrupts only
* being re-enabled if the count is zero.
*
* usCriticalNesting will get set to zero when the scheduler starts, but must
* not be initialised to zero as this will cause problems during the startup
* sequence. */
volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
/*-----------------------------------------------------------*/
@ -70,25 +70,27 @@ void vPortSetupTimerInterrupt( void );
*
* See the header file portable.h.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
uint16_t * pusTopOfStack;
uint32_t * pulTopOfStack, ulTemp;
/*
Place a few bytes of known values on the bottom of the stack.
This is just useful for debugging and can be included if required.
* Place a few bytes of known values on the bottom of the stack.
* This is just useful for debugging and can be included if required.
*
* pxTopOfStack = ( StackType_t ) 0x1111;
pxTopOfStack--;
* pxTopOfStack--;
* pxTopOfStack = ( StackType_t ) 0x2222;
pxTopOfStack--;
* pxTopOfStack--;
* pxTopOfStack = ( StackType_t ) 0x3333;
pxTopOfStack--;
* pxTopOfStack--;
*/
/* Data types are need either 16 bits or 32 bits depending on the data
and code model used. */
* and code model used. */
if( sizeof( pxCode ) == sizeof( uint16_t ) )
{
pusTopOfStack = ( uint16_t * ) pxTopOfStack;
@ -137,19 +139,19 @@ uint32_t *pulTopOfStack, ulTemp;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x4444;
pxTopOfStack--;
#else
#else /* ifdef PRELOAD_REGISTER_VALUES */
pxTopOfStack -= 3;
*pxTopOfStack = ( StackType_t ) pvParameters;
pxTopOfStack -= 9;
#endif
#endif /* ifdef PRELOAD_REGISTER_VALUES */
/* A variable is used to keep track of the critical section nesting.
This variable has to be stored as part of the task context and is
initially set to zero. */
* This variable has to be stored as part of the task context and is
* initially set to zero. */
*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
/* Return a pointer to the top of the stack we have generated so this can
be stored in the task control block for the task. */
* be stored in the task control block for the task. */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
@ -157,7 +159,7 @@ uint32_t *pulTopOfStack, ulTemp;
void vPortEndScheduler( void )
{
/* It is unlikely that the MSP430 port will get stopped. If required simply
disable the tick interrupt here. */
* disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
@ -184,5 +186,3 @@ extern void vPortTickISR( void );
vPortCooperativeTickISR();
#endif
}

2
portable/CCS/MSP430X/portmacro.h
Unescape Escape View File

@ -139,7 +139,7 @@ extern void vTaskSwitchContext( void );
void vApplicationSetupTimerInterrupt( void );
/* sizeof( int ) != sizeof( long ) so a full printf() library is required if
run time stats information is to be displayed. */
* run time stats information is to be displayed. */
#define portLU_PRINTF_SPECIFIER_REQUIRED
#endif /* PORTMACRO_H */

21
portable/CodeWarrior/ColdFire_V1/port.c
Unescape Escape View File

@ -46,17 +46,20 @@ asm void interrupt VectorNumber_VL1swi vPortYieldISR( void );
static void prvSetupTimerInterrupt( void );
/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This
will be set to 0 prior to the first task being started. */
* will be set to 0 prior to the first task being started. */
static uint32_t ulCriticalNesting = 0x9999UL;
/*-----------------------------------------------------------*/
StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
uint32_t ulOriginalA5;
__asm{ MOVE.L A5, ulOriginalA5 };
__asm {
MOVE.L A5, ulOriginalA5
};
*pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
@ -75,7 +78,7 @@ uint32_t ulOriginalA5;
/* Parameter in A0. */
*( pxTopOfStack + 8 ) = ( StackType_t ) pvParameters;
/* A5 must be maintained as it is resurved by the compiler. */
/* A5 must be maintained as it is reserved by the compiler. */
*( pxTopOfStack + 13 ) = ulOriginalA5;
return pxTopOfStack;
@ -107,7 +110,7 @@ static void prvSetupTimerInterrupt( void )
RTCMOD = portRTC_CLOCK_HZ / configTICK_RATE_HZ;
/* Enable the RTC to generate interrupts - interrupts are already disabled
when this code executes. */
* when this code executes. */
RTCSC_RTIE = 1;
}
/*-----------------------------------------------------------*/
@ -123,19 +126,20 @@ void vPortEnterCritical( void )
if( ulCriticalNesting == 0UL )
{
/* Guard against context switches being pended simultaneously with a
critical section being entered. */
* critical section being entered. */
do
{
portDISABLE_INTERRUPTS();
if( INTC_FRC == 0UL )
{
break;
}
portENABLE_INTERRUPTS();
} while( 1 );
}
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
@ -143,6 +147,7 @@ void vPortEnterCritical( void )
void vPortExitCritical( void )
{
ulCriticalNesting--;
if( ulCriticalNesting == 0 )
{
portENABLE_INTERRUPTS();

12
portable/CodeWarrior/ColdFire_V2/port.c
Unescape Escape View File

@ -37,7 +37,7 @@
#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000 )
/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This
will be set to 0 prior to the first task being started. */
* will be set to 0 prior to the first task being started. */
static uint32_t ulCriticalNesting = 0x9999UL;
@ -58,7 +58,9 @@ static uint32_t ulCriticalNesting = 0x9999UL;
/*-----------------------------------------------------------*/
StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
*pxTopOfStack = ( StackType_t ) pvParameters;
pxTopOfStack--;
@ -107,19 +109,20 @@ void vPortEnterCritical( void )
if( ulCriticalNesting == 0UL )
{
/* Guard against context switches being pended simultaneously with a
critical section being entered. */
* critical section being entered. */
do
{
portDISABLE_INTERRUPTS();
if( MCF_INTC0_INTFRCH == 0UL )
{
break;
}
portENABLE_INTERRUPTS();
} while( 1 );
}
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
@ -127,6 +130,7 @@ void vPortEnterCritical( void )
void vPortExitCritical( void )
{
ulCriticalNesting--;
if( ulCriticalNesting == 0 )
{
portENABLE_INTERRUPTS();

58
portable/CodeWarrior/HCS12/port.c
Unescape Escape View File

@ -43,7 +43,7 @@
static void prvSetupTimerInterrupt( void );
/* Interrupt service routines have to be in non-banked memory - as does the
scheduler startup function. */
* scheduler startup function. */
#pragma CODE_SEG __NEAR_SEG NON_BANKED
/* Manual context switch function. This is the SWI ISR. */
@ -53,19 +53,19 @@ scheduler startup function. */
void interrupt vPortTickInterrupt( void );
/* Simply called by xPortStartScheduler(). xPortStartScheduler() does not
start the scheduler directly because the header file containing the
xPortStartScheduler() prototype is part of the common kernel code, and
therefore cannot use the CODE_SEG pragma. */
* start the scheduler directly because the header file containing the
* xPortStartScheduler() prototype is part of the common kernel code, and
* therefore cannot use the CODE_SEG pragma. */
static BaseType_t xBankedStartScheduler( void );
#pragma CODE_SEG DEFAULT
/* Calls to portENTER_CRITICAL() can be nested. When they are nested the
critical section should not be left (i.e. interrupts should not be re-enabled)
until the nesting depth reaches 0. This variable simply tracks the nesting
depth. Each task maintains it's own critical nesting depth variable so
uxCriticalNesting is saved and restored from the task stack during a context
switch. */
* critical section should not be left (i.e. interrupts should not be re-enabled)
* until the nesting depth reaches 0. This variable simply tracks the nesting
* depth. Each task maintains it's own critical nesting depth variable so
* uxCriticalNesting is saved and restored from the task stack during a context
* switch. */
volatile UBaseType_t uxCriticalNesting = 0xff;
/*-----------------------------------------------------------*/
@ -73,25 +73,27 @@ volatile UBaseType_t uxCriticalNesting = 0xff;
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
/*
Place a few bytes of known values on the bottom of the stack.
This can be uncommented to provide useful stack markers when debugging.
* Place a few bytes of known values on the bottom of the stack.
* This can be uncommented to provide useful stack markers when debugging.
*
* pxTopOfStack = ( StackType_t ) 0x11;
pxTopOfStack--;
* pxTopOfStack--;
* pxTopOfStack = ( StackType_t ) 0x22;
pxTopOfStack--;
* pxTopOfStack--;
* pxTopOfStack = ( StackType_t ) 0x33;
pxTopOfStack--;
* pxTopOfStack--;
*/
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. In this case the stack as
expected by the HCS12 RTI instruction. */
* expected by the portRESTORE_CONTEXT() macro. In this case the stack as
* expected by the HCS12 RTI instruction. */
/* The address of the task function is placed in the stack byte at a time. */
@ -123,7 +125,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
pxTopOfStack--;
/* CCR: Note that when the task starts interrupts will be enabled since
"I" bit of CCR is cleared */
* "I" bit of CCR is cleared */
*pxTopOfStack = ( StackType_t ) 0x00;
pxTopOfStack--;
@ -134,7 +136,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
#endif
/* Finally the critical nesting depth is initialised with 0 (not within
a critical section). */
* a critical section). */
*pxTopOfStack = ( StackType_t ) 0x00;
return pxTopOfStack;
@ -157,10 +159,10 @@ static void prvSetupTimerInterrupt( void )
BaseType_t xPortStartScheduler( void )
{
/* xPortStartScheduler() does not start the scheduler directly because
the header file containing the xPortStartScheduler() prototype is part
of the common kernel code, and therefore cannot use the CODE_SEG pragma.
Instead it simply calls the locally defined xBankedStartScheduler() -
which does use the CODE_SEG pragma. */
* the header file containing the xPortStartScheduler() prototype is part
* of the common kernel code, and therefore cannot use the CODE_SEG pragma.
* Instead it simply calls the locally defined xBankedStartScheduler() -
* which does use the CODE_SEG pragma. */
return xBankedStartScheduler();
}
@ -171,7 +173,7 @@ BaseType_t xPortStartScheduler( void )
static BaseType_t xBankedStartScheduler( void )
{
/* Configure the timer that will generate the RTOS tick. Interrupts are
disabled when this function is called. */
* disabled when this function is called. */
prvSetupTimerInterrupt();
/* Restore the context of the first task. */
@ -222,15 +224,15 @@ void interrupt vPortTickInterrupt( void )
TFLG1 = 1;
/* Restore the context of a task - which may be a different task
to that interrupted. */
* to that interrupted. */
portRESTORE_CONTEXT();
}
#else
#else /* if configUSE_PREEMPTION == 1 */
{
xTaskIncrementTick();
TFLG1 = 1;
}
#endif
#endif /* if configUSE_PREEMPTION == 1 */
}
#pragma CODE_SEG DEFAULT

5
portable/CodeWarrior/HCS12/portmacro.h
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@ -120,6 +120,7 @@ typedef unsigned char UBaseType_t;
*/
#ifdef BANKED_MODEL
/*
* Load the stack pointer for the task, then pull the critical nesting
* count and PPAGE register from the stack. The remains of the
@ -155,7 +156,7 @@ typedef unsigned char UBaseType_t;
__asm( "ldx pxCurrentTCB" ); \
__asm( "sts 0, x" ); \
}
#else
#else /* ifdef BANKED_MODEL */
/*
* These macros are as per the BANKED versions above, but without saving
@ -183,7 +184,7 @@ typedef unsigned char UBaseType_t;
__asm( "ldx pxCurrentTCB" ); \
__asm( "sts 0, x" ); \
}
#endif
#endif /* ifdef BANKED_MODEL */
/*
* Utility macro to call macros above in correct order in order to perform a

38
portable/GCC/ARM7_AT91FR40008/port.c
Unescape Escape View File

@ -74,22 +74,24 @@ extern void vPortISRStartFirstTask( void );
*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
StackType_t * pxOriginalTOS;
pxOriginalTOS = pxTopOfStack;
/* To ensure asserts in tasks.c don't fail, although in this case the assert
is not really required. */
* is not really required. */
pxTopOfStack--;
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. */
* expected by the portRESTORE_CONTEXT() macro. */
/* First on the stack is the return address - which in this case is the
start of the task. The offset is added to make the return address appear
as it would within an IRQ ISR. */
* start of the task. The offset is added to make the return address appear
* as it would within an IRQ ISR. */
*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
pxTopOfStack--;
@ -123,12 +125,12 @@ StackType_t *pxOriginalTOS;
pxTopOfStack--;
/* When the task starts is will expect to find the function parameter in
R0. */
* R0. */
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
pxTopOfStack--;
/* The last thing onto the stack is the status register, which is set for
system mode, with interrupts enabled. */
* system mode, with interrupts enabled. */
*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
#ifdef THUMB_INTERWORK
@ -141,9 +143,9 @@ StackType_t *pxOriginalTOS;
pxTopOfStack--;
/* Some optimisation levels use the stack differently to others. This
means the interrupt flags cannot always be stored on the stack and will
instead be stored in a variable, which is then saved as part of the
tasks context. */
* means the interrupt flags cannot always be stored on the stack and will
* instead be stored in a variable, which is then saved as part of the
* tasks context. */
*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
return pxTopOfStack;
@ -153,7 +155,7 @@ StackType_t *pxOriginalTOS;
BaseType_t xPortStartScheduler( void )
{
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
* here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
@ -167,7 +169,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* It is unlikely that the ARM port will require this function as there
is nothing to return to. */
* is nothing to return to. */
}
/*-----------------------------------------------------------*/
@ -191,8 +193,8 @@ volatile uint32_t ulDummy;
ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
/* Store interrupt handler function address in tick timer vector register...
The ISR installed depends on whether the preemptive or cooperative
scheduler is being used. */
* The ISR installed depends on whether the preemptive or cooperative
* scheduler is being used. */
#if configUSE_PREEMPTION == 1
{
extern void( vPreemptiveTick )( void );
@ -209,8 +211,8 @@ volatile uint32_t ulDummy;
AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;
/* Enable the tick timer interrupt...
First at timer level */
*
* First at timer level */
portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
/* Then at the AIC level. */
@ -220,14 +222,14 @@ volatile uint32_t ulDummy;
if( ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 2 ) ) <= 0xFFFF )
{
/* The tick rate is fast enough for us to use the faster timer input
clock (main clock / 2). */
* clock (main clock / 2). */
portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 2 );
}
else
{
/* We must use a slower timer input clock (main clock / 8) because the
tick rate is too slow for the faster input clock. */
* tick rate is too slow for the faster input clock. */
portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 8 );
}

36
portable/GCC/ARM7_AT91FR40008/portISR.c
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@ -34,10 +34,10 @@
*----------------------------------------------------------*/
/*
Changes from V3.2.4
* Changes from V3.2.4
*
+ The assembler statements are now included in a single asm block rather
than each line having its own asm block.
+ than each line having its own asm block.
*/
@ -67,7 +67,7 @@ void vPortISRStartFirstTask( void );
void vPortISRStartFirstTask( void )
{
/* Simply start the scheduler. This is included here as it can only be
called from ARM mode. */
* called from ARM mode. */
portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
@ -83,8 +83,8 @@ void vPortISRStartFirstTask( void )
void vPortYieldProcessor( void )
{
/* Within an IRQ ISR the link register has an offset from the true return
address, but an SWI ISR does not. Add the offset manually so the same
ISR return code can be used in both cases. */
* address, but an SWI ISR does not. Add the offset manually so the same
* ISR return code can be used in both cases. */
asm volatile ( "ADD LR, LR, #4" );
/* Perform the context switch. First save the context of the current task. */
@ -106,7 +106,7 @@ void vPortYieldProcessor( void )
#if configUSE_PREEMPTION == 0
/* The cooperative scheduler requires a normal IRQ service routine to
simply increment the system tick. */
* simply increment the system tick. */
void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) );
void vNonPreemptiveTick( void )
{
@ -124,7 +124,7 @@ void vPortYieldProcessor( void )
#else /* else preemption is turned on */
/* The preemptive scheduler is defined as "naked" as the full context is
saved on entry as part of the context switch. */
* saved on entry as part of the context switch. */
void vPreemptiveTick( void ) __attribute__( ( naked ) );
void vPreemptiveTick( void )
{
@ -132,14 +132,14 @@ void vPortYieldProcessor( void )
portSAVE_CONTEXT();
/* WARNING - Do not use local (stack) variables here. Use globals
if you must! */
* if you must! */
static volatile uint32_t ulDummy;
/* Clear tick timer interrupt indication. */
ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
/* Increment the RTOS tick count, then look for the highest priority
task that is ready to run. */
* task that is ready to run. */
if( xTaskIncrementTick() != pdFALSE )
{
vTaskSwitchContext();
@ -152,7 +152,7 @@ void vPortYieldProcessor( void )
portRESTORE_CONTEXT();
}
#endif
#endif /* if configUSE_PREEMPTION == 0 */
/*-----------------------------------------------------------*/
/*
@ -191,9 +191,9 @@ void vPortYieldProcessor( void )
#endif /* THUMB_INTERWORK */
/* The code generated by the GCC compiler uses the stack in different ways at
different optimisation levels. The interrupt flags can therefore not always
be saved to the stack. Instead the critical section nesting level is stored
in a variable, which is then saved as part of the stack context. */
* different optimisation levels. The interrupt flags can therefore not always
* be saved to the stack. Instead the critical section nesting level is stored
* in a variable, which is then saved as part of the stack context. */
void vPortEnterCritical( void )
{
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
@ -204,9 +204,9 @@ void vPortEnterCritical( void )
"MSR CPSR, R0 \n\t" /* Write back modified value. */
"LDMIA SP!, {R0}" ); /* Pop R0. */
/* Now interrupts are disabled ulCriticalNesting can be accessed
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
/* Now that interrupts are disabled, ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
@ -218,7 +218,7 @@ void vPortExitCritical( void )
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
re-enabled. */
* re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Enable interrupts as per portEXIT_CRITICAL(). */

32
portable/GCC/ARM7_AT91FR40008/portmacro.h
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@ -27,26 +27,26 @@
*/
/*
Changes from V3.2.3
* Changes from V3.2.3
*
+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
Changes from V3.2.4
+
+ Changes from V3.2.4
+
+ Removed the use of the %0 parameter within the assembler macros and
replaced them with hard coded registers. This will ensure the
assembler does not select the link register as the temp register as
was occasionally happening previously.
+ replaced them with hard coded registers. This will ensure the
+ assembler does not select the link register as the temp register as
+ was occasionally happening previously.
+
+ The assembler statements are now included in a single asm block rather
than each line having its own asm block.
Changes from V4.5.0
+ than each line having its own asm block.
+
+ Changes from V4.5.0
+
+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
and replaced them with portYIELD_FROM_ISR() macro. Application code
should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
macros as per the V4.5.1 demo code.
+ and replaced them with portYIELD_FROM_ISR() macro. Application code
+ should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+ macros as per the V4.5.1 demo code.
*/
#ifndef PORTMACRO_H

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90
portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
Unescape Escape View File

@ -1,50 +1,50 @@
//* ----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//* ----------------------------------------------------------------------------
//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//* ----------------------------------------------------------------------------
//* File Name : lib_AT91SAM7X256.h
//* Object : AT91SAM7X256 inlined functions
//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
//*
//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005//
//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//
//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//
//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//
//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//
//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//
//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//
//* ----------------------------------------------------------------------------
/** ---------------------------------------------------------------------------- */
/** ATMEL Microcontroller Software Support - ROUSSET - */
/** ---------------------------------------------------------------------------- */
/** DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/** ---------------------------------------------------------------------------- */
/** File Name : lib_AT91SAM7X256.h */
/** Object : AT91SAM7X256 inlined functions */
/** Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */
/** */
/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */
/** CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// */
/** CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// */
/** CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// */
/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */
/** CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// */
/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */
/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */
/** CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// */
/** CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */
/** CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */
/** CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */
/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */
/** CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// */
/** CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */
/** CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */
/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
/** CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */
/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */
/** CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */
/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
/** CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// */
/** ---------------------------------------------------------------------------- */
#include "AT91SAM7X256.h"
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_ConfigureIt
//* \brief Interrupt Handler Initialization
//*----------------------------------------------------------------------------
/**---------------------------------------------------------------------------- */
/** \fn AT91F_AIC_ConfigureIt */
/** \brief Interrupt Handler Initialization */
/**---------------------------------------------------------------------------- */

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34
portable/GCC/ARM7_AT91SAM7S/port.c
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@ -83,22 +83,24 @@ extern void vPortISRStartFirstTask( void );
*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
StackType_t * pxOriginalTOS;
pxOriginalTOS = pxTopOfStack;
/* To ensure asserts in tasks.c don't fail, although in this case the assert
is not really required. */
* is not really required. */
pxTopOfStack--;
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. */
* expected by the portRESTORE_CONTEXT() macro. */
/* First on the stack is the return address - which in this case is the
start of the task. The offset is added to make the return address appear
as it would within an IRQ ISR. */
* start of the task. The offset is added to make the return address appear
* as it would within an IRQ ISR. */
*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
pxTopOfStack--;
@ -132,12 +134,12 @@ StackType_t *pxOriginalTOS;
pxTopOfStack--;
/* When the task starts is will expect to find the function parameter in
R0. */
* R0. */
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
pxTopOfStack--;
/* The last thing onto the stack is the status register, which is set for
system mode, with interrupts enabled. */
* system mode, with interrupts enabled. */
*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
#ifdef THUMB_INTERWORK
@ -150,9 +152,9 @@ StackType_t *pxOriginalTOS;
pxTopOfStack--;
/* Some optimisation levels use the stack differently to others. This
means the interrupt flags cannot always be stored on the stack and will
instead be stored in a variable, which is then saved as part of the
tasks context. */
* means the interrupt flags cannot always be stored on the stack and will
* instead be stored in a variable, which is then saved as part of the
* tasks context. */
*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
return pxTopOfStack;
@ -162,7 +164,7 @@ StackType_t *pxOriginalTOS;
BaseType_t xPortStartScheduler( void )
{
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
* here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
@ -176,7 +178,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* It is unlikely that the ARM port will require this function as there
is nothing to return to. */
* is nothing to return to. */
}
/*-----------------------------------------------------------*/
@ -188,24 +190,20 @@ static void prvSetupTimerInterrupt( void )
AT91PS_PITC pxPIT = AT91C_BASE_PITC;
/* Setup the AIC for PIT interrupts. The interrupt routine chosen depends
on whether the preemptive or cooperative scheduler is being used. */
* on whether the preemptive or cooperative scheduler is being used. */
#if configUSE_PREEMPTION == 0
extern void( vNonPreemptiveTick ) ( void );
AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vNonPreemptiveTick );
#else
extern void( vPreemptiveTick )( void );
AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vPreemptiveTick );
#endif
/* Configure the PIT period. */
pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
/* Enable the interrupt. Global interrupts are disabled at this point so
this is safe. */
* this is safe. */
AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS;
}
/*-----------------------------------------------------------*/

38
portable/GCC/ARM7_AT91SAM7S/portISR.c
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@ -34,10 +34,10 @@
*----------------------------------------------------------*/
/*
Changes from V3.2.4
* Changes from V3.2.4
*
+ The assembler statements are now included in a single asm block rather
than each line having its own asm block.
+ than each line having its own asm block.
*/
/* Scheduler includes. */
@ -69,7 +69,7 @@ void vPortISRStartFirstTask( void );
void vPortISRStartFirstTask( void )
{
/* Simply start the scheduler. This is included here as it can only be
called from ARM mode. */
* called from ARM mode. */
portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
@ -85,8 +85,8 @@ void vPortISRStartFirstTask( void )
void vPortYieldProcessor( void )
{
/* Within an IRQ ISR the link register has an offset from the true return
address, but an SWI ISR does not. Add the offset manually so the same
ISR return code can be used in both cases. */
* address, but an SWI ISR does not. Add the offset manually so the same
* ISR return code can be used in both cases. */
__asm volatile ( "ADD LR, LR, #4" );
/* Perform the context switch. First save the context of the current task. */
@ -108,15 +108,15 @@ void vPortYieldProcessor( void )
#if configUSE_PREEMPTION == 0
/* The cooperative scheduler requires a normal IRQ service routine to
simply increment the system tick. */
* simply increment the system tick. */
void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) );
void vNonPreemptiveTick( void )
{
uint32_t ulDummy;
/* Increment the tick count - which may wake some tasks but as the
preemptive scheduler is not being used any woken task is not given
processor time no matter what its priority. */
* preemptive scheduler is not being used any woken task is not given
* processor time no matter what its priority. */
xTaskIncrementTick();
/* Clear the PIT interrupt. */
@ -126,10 +126,10 @@ void vPortYieldProcessor( void )
AT91C_BASE_AIC->AIC_EOICR = ulDummy;
}
#else
#else /* if configUSE_PREEMPTION == 0 */
/* The preemptive scheduler is defined as "naked" as the full context is
saved on entry as part of the context switch. */
* saved on entry as part of the context switch. */
void vPreemptiveTick( void ) __attribute__( ( naked ) );
void vPreemptiveTick( void )
{
@ -149,7 +149,7 @@ void vPortYieldProcessor( void )
portRESTORE_CONTEXT();
}
#endif
#endif /* if configUSE_PREEMPTION == 0 */
/*-----------------------------------------------------------*/
/*
@ -185,9 +185,9 @@ void vPortEnableInterruptsFromThumb( void )
/* The code generated by the GCC compiler uses the stack in different ways at
different optimisation levels. The interrupt flags can therefore not always
be saved to the stack. Instead the critical section nesting level is stored
in a variable, which is then saved as part of the stack context. */
* different optimisation levels. The interrupt flags can therefore not always
* be saved to the stack. Instead the critical section nesting level is stored
* in a variable, which is then saved as part of the stack context. */
void vPortEnterCritical( void )
{
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
@ -198,9 +198,9 @@ void vPortEnterCritical( void )
"MSR CPSR, R0 \n\t" /* Write back modified value. */
"LDMIA SP!, {R0}" ); /* Pop R0. */
/* Now interrupts are disabled ulCriticalNesting can be accessed
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
/* Now that interrupts are disabled, ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
@ -212,7 +212,7 @@ void vPortExitCritical( void )
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
re-enabled. */
* re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Enable interrupts as per portEXIT_CRITICAL(). */

32
portable/GCC/ARM7_AT91SAM7S/portmacro.h
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@ -27,26 +27,26 @@
*/
/*
Changes from V3.2.3
* Changes from V3.2.3
*
+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
Changes from V3.2.4
+
+ Changes from V3.2.4
+
+ Removed the use of the %0 parameter within the assembler macros and
replaced them with hard coded registers. This will ensure the
assembler does not select the link register as the temp register as
was occasionally happening previously.
+ replaced them with hard coded registers. This will ensure the
+ assembler does not select the link register as the temp register as
+ was occasionally happening previously.
+
+ The assembler statements are now included in a single asm block rather
than each line having its own asm block.
Changes from V4.5.0
+ than each line having its own asm block.
+
+ Changes from V4.5.0
+
+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
and replaced them with portYIELD_FROM_ISR() macro. Application code
should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
macros as per the V4.5.1 demo code.
+ and replaced them with portYIELD_FROM_ISR() macro. Application code
+ should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+ macros as per the V4.5.1 demo code.
*/
#ifndef PORTMACRO_H

35
portable/GCC/ARM7_LPC2000/port.c
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@ -79,22 +79,24 @@ extern void vPortISRStartFirstTask( void );
*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
StackType_t * pxOriginalTOS;
pxOriginalTOS = pxTopOfStack;
/* To ensure asserts in tasks.c don't fail, although in this case the assert
is not really required. */
* is not really required. */
pxTopOfStack--;
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. */
* expected by the portRESTORE_CONTEXT() macro. */
/* First on the stack is the return address - which in this case is the
start of the task. The offset is added to make the return address appear
as it would within an IRQ ISR. */
* start of the task. The offset is added to make the return address appear
* as it would within an IRQ ISR. */
*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
pxTopOfStack--;
@ -128,12 +130,12 @@ StackType_t *pxOriginalTOS;
pxTopOfStack--;
/* When the task starts is will expect to find the function parameter in
R0. */
* R0. */
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
pxTopOfStack--;
/* The last thing onto the stack is the status register, which is set for
system mode, with interrupts enabled. */
* system mode, with interrupts enabled. */
*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
@ -145,9 +147,9 @@ StackType_t *pxOriginalTOS;
pxTopOfStack--;
/* Some optimisation levels use the stack differently to others. This
means the interrupt flags cannot always be stored on the stack and will
instead be stored in a variable, which is then saved as part of the
tasks context. */
* means the interrupt flags cannot always be stored on the stack and will
* instead be stored in a variable, which is then saved as part of the
* tasks context. */
*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
return pxTopOfStack;
@ -157,7 +159,7 @@ StackType_t *pxOriginalTOS;
BaseType_t xPortStartScheduler( void )
{
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
* here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
@ -171,7 +173,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* It is unlikely that the ARM port will require this function as there
is nothing to return to. */
* is nothing to return to. */
}
/*-----------------------------------------------------------*/
@ -181,17 +183,18 @@ void vPortEndScheduler( void )
static void prvSetupTimerInterrupt( void )
{
uint32_t ulCompareMatch;
extern void( vTickISR )( void );
/* A 1ms tick does not require the use of the timer prescale. This is
defaulted to zero but can be used if necessary. */
* defaulted to zero but can be used if necessary. */
T0_PR = portPRESCALE_VALUE;
/* Calculate the match value required for our wanted tick rate. */
ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
/* Protect against divide by zero. Using an if() statement still results
in a warning - hence the #if. */
* in a warning - hence the #if. */
#if portPRESCALE_VALUE != 0
{
ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
@ -207,13 +210,13 @@ extern void ( vTickISR )( void );
VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
/* The ISR installed depends on whether the preemptive or cooperative
scheduler is being used. */
* scheduler is being used. */
VICVectAddr0 = ( int32_t ) vTickISR;
VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
/* Start the timer - interrupts are disabled when this function is called
so it is okay to do this here. */
* so it is okay to do this here. */
T0_TCR = portENABLE_TIMER;
}
/*-----------------------------------------------------------*/

46
portable/GCC/ARM7_LPC2000/portISR.c
Unescape Escape View File

@ -34,21 +34,21 @@
*----------------------------------------------------------*/
/*
Changes from V2.5.2
* Changes from V2.5.2
*
+ The critical section management functions have been changed. These no
longer modify the stack and are safe to use at all optimisation levels.
The functions are now also the same for both ARM and THUMB modes.
Changes from V2.6.0
+ longer modify the stack and are safe to use at all optimisation levels.
+ The functions are now also the same for both ARM and THUMB modes.
+
+ Changes from V2.6.0
+
+ Removed the 'static' from the definition of vNonPreemptiveTick() to
allow the demo to link when using the cooperative scheduler.
Changes from V3.2.4
+ allow the demo to link when using the cooperative scheduler.
+
+ Changes from V3.2.4
+
+ The assembler statements are now included in a single asm block rather
than each line having its own asm block.
+ than each line having its own asm block.
*/
@ -78,7 +78,7 @@ void vPortISRStartFirstTask( void );
void vPortISRStartFirstTask( void )
{
/* Simply start the scheduler. This is included here as it can only be
called from ARM mode. */
* called from ARM mode. */
portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
@ -94,8 +94,8 @@ void vPortISRStartFirstTask( void )
void vPortYieldProcessor( void )
{
/* Within an IRQ ISR the link register has an offset from the true return
address, but an SWI ISR does not. Add the offset manually so the same
ISR return code can be used in both cases. */
* address, but an SWI ISR does not. Add the offset manually so the same
* ISR return code can be used in both cases. */
__asm volatile ( "ADD LR, LR, #4" );
/* Perform the context switch. First save the context of the current task. */
@ -119,7 +119,7 @@ void vTickISR( void )
portSAVE_CONTEXT();
/* Increment the RTOS tick count, then look for the highest priority
task that is ready to run. */
* task that is ready to run. */
__asm volatile
(
" bl xTaskIncrementTick \t\n" \
@ -174,9 +174,9 @@ void vTickISR( void )
#endif /* THUMB_INTERWORK */
/* The code generated by the GCC compiler uses the stack in different ways at
different optimisation levels. The interrupt flags can therefore not always
be saved to the stack. Instead the critical section nesting level is stored
in a variable, which is then saved as part of the stack context. */
* different optimisation levels. The interrupt flags can therefore not always
* be saved to the stack. Instead the critical section nesting level is stored
* in a variable, which is then saved as part of the stack context. */
void vPortEnterCritical( void )
{
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
@ -187,9 +187,9 @@ void vPortEnterCritical( void )
"MSR CPSR, R0 \n\t" /* Write back modified value. */
"LDMIA SP!, {R0}" ); /* Pop R0. */
/* Now interrupts are disabled ulCriticalNesting can be accessed
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
/* Now that interrupts are disabled, ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
@ -201,7 +201,7 @@ void vPortExitCritical( void )
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
re-enabled. */
* re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Enable interrupts as per portEXIT_CRITICAL(). */

34
portable/GCC/ARM7_LPC23xx/port.c
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@ -79,22 +79,24 @@ extern void vPortISRStartFirstTask( void );
*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
StackType_t * pxOriginalTOS;
pxOriginalTOS = pxTopOfStack;
/* To ensure asserts in tasks.c don't fail, although in this case the assert
is not really required. */
* is not really required. */
pxTopOfStack--;
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. */
* expected by the portRESTORE_CONTEXT() macro. */
/* First on the stack is the return address - which in this case is the
start of the task. The offset is added to make the return address appear
as it would within an IRQ ISR. */
* start of the task. The offset is added to make the return address appear
* as it would within an IRQ ISR. */
*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
pxTopOfStack--;
@ -128,12 +130,12 @@ StackType_t *pxOriginalTOS;
pxTopOfStack--;
/* When the task starts is will expect to find the function parameter in
R0. */
* R0. */
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
pxTopOfStack--;
/* The last thing onto the stack is the status register, which is set for
system mode, with interrupts enabled. */
* system mode, with interrupts enabled. */
*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
@ -145,9 +147,9 @@ StackType_t *pxOriginalTOS;
pxTopOfStack--;
/* Some optimisation levels use the stack differently to others. This
means the interrupt flags cannot always be stored on the stack and will
instead be stored in a variable, which is then saved as part of the
tasks context. */
* means the interrupt flags cannot always be stored on the stack and will
* instead be stored in a variable, which is then saved as part of the
* tasks context. */
*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
return pxTopOfStack;
@ -157,7 +159,7 @@ StackType_t *pxOriginalTOS;
BaseType_t xPortStartScheduler( void )
{
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
* here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
@ -171,7 +173,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* It is unlikely that the ARM port will require this function as there
is nothing to return to. */
* is nothing to return to. */
}
/*-----------------------------------------------------------*/
@ -187,14 +189,14 @@ uint32_t ulCompareMatch;
T0CTCR = 0; /* Timer mode */
/* A 1ms tick does not require the use of the timer prescale. This is
defaulted to zero but can be used if necessary. */
* defaulted to zero but can be used if necessary. */
T0PR = portPRESCALE_VALUE;
/* Calculate the match value required for our wanted tick rate. */
ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
/* Protect against divide by zero. Using an if() statement still results
in a warning - hence the #if. */
* in a warning - hence the #if. */
#if portPRESCALE_VALUE != 0
{
ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
@ -209,7 +211,7 @@ uint32_t ulCompareMatch;
VICIntEnable = 0x00000010;
/* The ISR installed depends on whether the preemptive or cooperative
scheduler is being used. */
* scheduler is being used. */
#if configUSE_PREEMPTION == 1
{
extern void( vPreemptiveTick )( void );
@ -225,7 +227,7 @@ uint32_t ulCompareMatch;
VICVectCntl4 = 1;
/* Start the timer - interrupts are disabled when this function is called
so it is okay to do this here. */
* so it is okay to do this here. */
T0TCR = portENABLE_TIMER;
}
/*-----------------------------------------------------------*/

30
portable/GCC/ARM7_LPC23xx/portISR.c
Unescape Escape View File

@ -60,7 +60,7 @@ void vPortISRStartFirstTask( void );
void vPortISRStartFirstTask( void )
{
/* Simply start the scheduler. This is included here as it can only be
called from ARM mode. */
* called from ARM mode. */
portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
@ -76,8 +76,8 @@ void vPortISRStartFirstTask( void )
void vPortYieldProcessor( void )
{
/* Within an IRQ ISR the link register has an offset from the true return
address, but an SWI ISR does not. Add the offset manually so the same
ISR return code can be used in both cases. */
* address, but an SWI ISR does not. Add the offset manually so the same
* ISR return code can be used in both cases. */
__asm volatile ( "ADD LR, LR, #4" );
/* Perform the context switch. First save the context of the current task. */
@ -100,7 +100,7 @@ void vPortYieldProcessor( void )
#if configUSE_PREEMPTION == 0
/* The cooperative scheduler requires a normal IRQ service routine to
simply increment the system tick. */
* simply increment the system tick. */
void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) );
void vNonPreemptiveTick( void )
{
@ -109,10 +109,10 @@ void vPortYieldProcessor( void )
VICVectAddr = portCLEAR_VIC_INTERRUPT;
}
#else
#else /* if configUSE_PREEMPTION == 0 */
/* The preemptive scheduler is defined as "naked" as the full context is
saved on entry as part of the context switch. */
* saved on entry as part of the context switch. */
void vPreemptiveTick( void ) __attribute__( ( naked ) );
void vPreemptiveTick( void )
{
@ -120,7 +120,7 @@ void vPortYieldProcessor( void )
portSAVE_CONTEXT();
/* Increment the RTOS tick count, then look for the highest priority
task that is ready to run. */
* task that is ready to run. */
__asm volatile
(
" bl xTaskIncrementTick \t\n" \
@ -138,7 +138,7 @@ void vPortYieldProcessor( void )
portRESTORE_CONTEXT();
}
#endif
#endif /* if configUSE_PREEMPTION == 0 */
/*-----------------------------------------------------------*/
/*
@ -177,9 +177,9 @@ void vPortYieldProcessor( void )
#endif /* THUMB_INTERWORK */
/* The code generated by the GCC compiler uses the stack in different ways at
different optimisation levels. The interrupt flags can therefore not always
be saved to the stack. Instead the critical section nesting level is stored
in a variable, which is then saved as part of the stack context. */
* different optimisation levels. The interrupt flags can therefore not always
* be saved to the stack. Instead the critical section nesting level is stored
* in a variable, which is then saved as part of the stack context. */
void vPortEnterCritical( void )
{
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
@ -190,9 +190,9 @@ void vPortEnterCritical( void )
"MSR CPSR, R0 \n\t" /* Write back modified value. */
"LDMIA SP!, {R0}" ); /* Pop R0. */
/* Now interrupts are disabled ulCriticalNesting can be accessed
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
/* Now that interrupts are disabled, ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
@ -204,7 +204,7 @@ void vPortExitCritical( void )
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
re-enabled. */
* re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Enable interrupts as per portEXIT_CRITICAL(). */

32
portable/GCC/ARM7_LPC23xx/portmacro.h
Unescape Escape View File

@ -27,26 +27,26 @@
*/
/*
Changes from V3.2.3
* Changes from V3.2.3
*
+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
Changes from V3.2.4
+
+ Changes from V3.2.4
+
+ Removed the use of the %0 parameter within the assembler macros and
replaced them with hard coded registers. This will ensure the
assembler does not select the link register as the temp register as
was occasionally happening previously.
+ replaced them with hard coded registers. This will ensure the
+ assembler does not select the link register as the temp register as
+ was occasionally happening previously.
+
+ The assembler statements are now included in a single asm block rather
than each line having its own asm block.
Changes from V4.5.0
+ than each line having its own asm block.
+
+ Changes from V4.5.0
+
+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
and replaced them with portYIELD_FROM_ISR() macro. Application code
should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
macros as per the V4.5.1 demo code.
+ and replaced them with portYIELD_FROM_ISR() macro. Application code
+ should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+ macros as per the V4.5.1 demo code.
*/
#ifndef PORTMACRO_H

162
portable/GCC/ARM_CA53_64_BIT/port.c
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@ -34,64 +34,64 @@
#include "task.h"
#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#ifndef configUNIQUE_INTERRUPT_PRIORITIES
#error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#ifndef configSETUP_TICK_INTERRUPT
#error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif /* configSETUP_TICK_INTERRUPT */
#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
#error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Check the configuration. */
#if ( configMAX_PRIORITIES > 32 )
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
#error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
#endif
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/* In case security extensions are implemented. */
#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
#endif
/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
portmacro.h. */
* portmacro.h. */
#ifndef configCLEAR_TICK_INTERRUPT
#define configCLEAR_TICK_INTERRUPT()
#endif
/* A critical section is exited when the critical section nesting count reaches
this value. */
* this value. */
#define portNO_CRITICAL_NESTING ( ( size_t ) 0 )
/* In all GICs 255 can be written to the priority mask register to unmask all
(but the lowest) interrupt priority. */
* (but the lowest) interrupt priority. */
#define portUNMASK_VALUE ( 0xFFUL )
/* Tasks are not created with a floating point context, but can be given a
floating point context after they have been created. A variable is stored as
part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
does not have an FPU context, or any other value if the task does have an FPU
context. */
* floating point context after they have been created. A variable is stored as
* part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
* does not have an FPU context, or any other value if the task does have an FPU
* context. */
#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Constants required to setup the initial task context. */
@ -109,7 +109,7 @@ context. */
/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
point is zero. */
* point is zero. */
#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
/* Masks all bits in the APSR other than the mode bits. */
@ -144,21 +144,21 @@ extern void vPortRestoreTaskContext( void );
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
variable has to be stored as part of the task context and must be initialised to
a non zero value to ensure interrupts don't inadvertently become unmasked before
the scheduler starts. As it is stored as part of the task context it will
automatically be set to 0 when the first task is started. */
* variable has to be stored as part of the task context and must be initialised to
* a non zero value to ensure interrupts don't inadvertently become unmasked before
* the scheduler starts. As it is stored as part of the task context it will
* automatically be set to 0 when the first task is started. */
volatile uint64_t ullCriticalNesting = 9999ULL;
/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
then floating point context must be saved and restored for the task. */
* then floating point context must be saved and restored for the task. */
uint64_t ullPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
uint64_t ullPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
if the nesting depth is 0. */
* if the nesting depth is 0. */
uint64_t ullPortInterruptNesting = 0;
/* Used in the ASM code. */
@ -172,10 +172,12 @@ __attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_C
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. */
* expected by the portRESTORE_CONTEXT() macro. */
/* First all the general purpose registers. */
pxTopOfStack--;
@ -251,13 +253,13 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
pxTopOfStack--;
/* The task will start with a critical nesting count of 0 as interrupts are
enabled. */
* enabled. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
pxTopOfStack--;
/* The task will start without a floating point context. A task that uses
the floating point hardware must call vPortTaskUsesFPU() before executing
any floating point instructions. */
* the floating point hardware must call vPortTaskUsesFPU() before executing
* any floating point instructions. */
*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
return pxTopOfStack;
@ -275,12 +277,12 @@ uint32_t ulAPSR;
volatile uint8_t ucMaxPriorityValue;
/* Determine how many priority bits are implemented in the GIC.
Save the interrupt priority value that is about to be clobbered. */
*
* Save the interrupt priority value that is about to be clobbered. */
ucOriginalPriority = *pucFirstUserPriorityRegister;
/* Determine the number of priority bits available. First write to
all possible bits. */
* all possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
/* Read the value back to see how many bits stuck. */
@ -293,13 +295,13 @@ uint32_t ulAPSR;
}
/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
value. */
* value. */
configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
/* Restore the clobbered interrupt priority register to its original
value. */
* value. */
*pucFirstUserPriorityRegister = ucOriginalPriority;
}
#endif /* configASSERT_DEFINED */
@ -310,25 +312,27 @@ uint32_t ulAPSR;
ulAPSR &= portAPSR_MODE_BITS_MASK;
#if defined( GUEST )
#warning Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH.
#warning "Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH."
configASSERT( ulAPSR == portEL1 );
if( ulAPSR == portEL1 )
#else
configASSERT( ulAPSR == portEL3 );
if( ulAPSR == portEL3 )
#endif
{
/* Only continue if the binary point value is set to its lowest possible
setting. See the comments in vPortValidateInterruptPriority() below for
more information. */
* setting. See the comments in vPortValidateInterruptPriority() below for
* more information. */
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
{
/* Interrupts are turned off in the CPU itself to ensure a tick does
not execute while the scheduler is being started. Interrupts are
automatically turned back on in the CPU when the first task starts
executing. */
* not execute while the scheduler is being started. Interrupts are
* automatically turned back on in the CPU when the first task starts
* executing. */
portDISABLE_INTERRUPTS();
/* Start the timer that generates the tick ISR. */
@ -346,7 +350,7 @@ uint32_t ulAPSR;
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
Artificially force an assert. */
* Artificially force an assert. */
configASSERT( ullCriticalNesting == 1000ULL );
}
/*-----------------------------------------------------------*/
@ -357,15 +361,15 @@ void vPortEnterCritical( void )
uxPortSetInterruptMask();
/* Now interrupts are disabled ullCriticalNesting can be accessed
directly. Increment ullCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
* directly. Increment ullCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
ullCriticalNesting++;
/* This is not the interrupt safe version of the enter critical function so
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
* assert() if it is being called from an interrupt context. Only API
* functions that end in "FromISR" can be used in an interrupt. Only assert if
* the critical nesting count is 1 to protect against recursive calls if the
* assert function also uses a critical section. */
if( ullCriticalNesting == 1ULL )
{
configASSERT( ullPortInterruptNesting == 0 );
@ -378,15 +382,15 @@ void vPortExitCritical( void )
if( ullCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as the critical section is being
exited. */
* exited. */
ullCriticalNesting--;
/* If the nesting level has reached zero then all interrupt
priorities must be re-enabled. */
* priorities must be re-enabled. */
if( ullCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Critical nesting has reached zero so all interrupt priorities
should be unmasked. */
* should be unmasked. */
portCLEAR_INTERRUPT_MASK();
}
}
@ -413,10 +417,10 @@ void FreeRTOS_Tick_Handler( void )
#endif /* configASSERT_DEFINED */
/* Set interrupt mask before altering scheduler structures. The tick
handler runs at the lowest priority, so interrupts cannot already be masked,
so there is no need to save and restore the current mask value. It is
necessary to turn off interrupts in the CPU itself while the ICCPMR is being
updated. */
* handler runs at the lowest priority, so interrupts cannot already be masked,
* so there is no need to save and restore the current mask value. It is
* necessary to turn off interrupts in the CPU itself while the ICCPMR is being
* updated. */
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
__asm volatile ( "dsb sy \n"
"isb sy \n" ::: "memory" );
@ -439,11 +443,11 @@ void FreeRTOS_Tick_Handler( void )
void vPortTaskUsesFPU( void )
{
/* A task is registering the fact that it needs an FPU context. Set the
FPU flag (which is saved as part of the task context). */
* FPU flag (which is saved as part of the task context). */
ullPortTaskHasFPUContext = pdTRUE;
/* Consider initialising the FPSR here - but probably not necessary in
AArch64. */
* AArch64. */
}
/*-----------------------------------------------------------*/
@ -461,8 +465,9 @@ UBaseType_t uxPortSetInterruptMask( void )
uint32_t ulReturn;
/* Interrupt in the CPU must be turned off while the ICCPMR is being
updated. */
* updated. */
portDISABLE_INTERRUPTS();
if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
{
/* Interrupts were already masked. */
@ -475,6 +480,7 @@ uint32_t ulReturn;
__asm volatile ( "dsb sy \n"
"isb sy \n" ::: "memory" );
}
portENABLE_INTERRUPTS();
return ulReturn;
@ -486,31 +492,31 @@ uint32_t ulReturn;
void vPortValidateInterruptPriority( void )
{
/* The following assertion will fail if a service routine (ISR) for
an interrupt that has been assigned a priority above
configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
function. ISR safe FreeRTOS API functions must *only* be called
from interrupts that have been assigned a priority at or below
configMAX_SYSCALL_INTERRUPT_PRIORITY.
Numerically low interrupt priority numbers represent logically high
interrupt priorities, therefore the priority of the interrupt must
be set to a value equal to or numerically *higher* than
configMAX_SYSCALL_INTERRUPT_PRIORITY.
FreeRTOS maintains separate thread and ISR API functions to ensure
interrupt entry is as fast and simple as possible. */
* an interrupt that has been assigned a priority above
* configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
* function. ISR safe FreeRTOS API functions must *only* be called
* from interrupts that have been assigned a priority at or below
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
*
* Numerically low interrupt priority numbers represent logically high
* interrupt priorities, therefore the priority of the interrupt must
* be set to a value equal to or numerically *higher* than
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
*
* FreeRTOS maintains separate thread and ISR API functions to ensure
* interrupt entry is as fast and simple as possible. */
configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
/* Priority grouping: The interrupt controller (GIC) allows the bits
that define each interrupt's priority to be split between bits that
define the interrupt's pre-emption priority bits and bits that define
the interrupt's sub-priority. For simplicity all bits must be defined
to be pre-emption priority bits. The following assertion will fail if
this is not the case (if some bits represent a sub-priority).
The priority grouping is configured by the GIC's binary point register
(ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
possible value (which may be above 0). */
* that define each interrupt's priority to be split between bits that
* define the interrupt's pre-emption priority bits and bits that define
* the interrupt's sub-priority. For simplicity all bits must be defined
* to be pre-emption priority bits. The following assertion will fail if
* this is not the case (if some bits represent a sub-priority).
*
* The priority grouping is configured by the GIC's binary point register
* (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
* possible value (which may be above 0). */
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
}

19
portable/GCC/ARM_CA53_64_BIT/portmacro.h
Unescape Escape View File

@ -62,7 +62,7 @@ typedef uint64_t TickType_t;
#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
not need to be guarded with a critical section. */
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
@ -94,6 +94,7 @@ extern uint64_t ullPortYieldRequired; \
#else
#define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )
#endif
/*-----------------------------------------------------------
* Critical section control
*----------------------------------------------------------*/
@ -116,7 +117,7 @@ extern void vPortInstallFreeRTOSVectorTable( void );
/* These macros do not globally disable/enable interrupts. They do mask off
interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
* interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
#define portENTER_CRITICAL() vPortEnterCritical();
#define portEXIT_CRITICAL() vPortExitCritical();
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask()
@ -125,17 +126,17 @@ interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
not required for this port but included in case common demo code that uses these
macros is used. */
* not required for this port but included in case common demo code that uses these
* macros is used. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/* Prototype of the FreeRTOS tick handler. This must be installed as the
handler for whichever peripheral is used to generate the RTOS tick. */
* handler for whichever peripheral is used to generate the RTOS tick. */
void FreeRTOS_Tick_Handler( void );
/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
before any floating point instructions are executed. */
* before any floating point instructions are executed. */
void vPortTaskUsesFPU( void );
#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
@ -168,7 +169,7 @@ void vPortTaskUsesFPU( void );
#define portINLINE __inline
/* The number of bits to shift for an interrupt priority is dependent on the
number of bits implemented by the interrupt controller. */
* number of bits implemented by the interrupt controller. */
#if configUNIQUE_INTERRUPT_PRIORITIES == 16
#define portPRIORITY_SHIFT 4
#define portMAX_BINARY_POINT_VALUE 3
@ -184,9 +185,9 @@ number of bits implemented by the interrupt controller. */
#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
#define portPRIORITY_SHIFT 0
#define portMAX_BINARY_POINT_VALUE 0
#else
#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
#endif
#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
/* Interrupt controller access addresses. */
#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )

123
portable/GCC/ARM_CA53_64_BIT_SRE/port.c
Unescape Escape View File

@ -34,56 +34,56 @@
#include "task.h"
#ifndef configUNIQUE_INTERRUPT_PRIORITIES
#error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#ifndef configSETUP_TICK_INTERRUPT
#error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif /* configSETUP_TICK_INTERRUPT */
#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
#error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Check the configuration. */
#if ( configMAX_PRIORITIES > 32 )
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
#error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
#endif
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/* In case security extensions are implemented. */
#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
#endif
/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
portmacro.h. */
* portmacro.h. */
#ifndef configCLEAR_TICK_INTERRUPT
#define configCLEAR_TICK_INTERRUPT()
#endif
/* A critical section is exited when the critical section nesting count reaches
this value. */
* this value. */
#define portNO_CRITICAL_NESTING ( ( size_t ) 0 )
/* In all GICs 255 can be written to the priority mask register to unmask all
(but the lowest) interrupt priority. */
* (but the lowest) interrupt priority. */
#define portUNMASK_VALUE ( 0xFFUL )
/* Tasks are not created with a floating point context, but can be given a
floating point context after they have been created. A variable is stored as
part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
does not have an FPU context, or any other value if the task does have an FPU
context. */
* floating point context after they have been created. A variable is stored as
* part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
* does not have an FPU context, or any other value if the task does have an FPU
* context. */
#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Constants required to setup the initial task context. */
@ -132,21 +132,21 @@ extern void vPortRestoreTaskContext( void );
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
variable has to be stored as part of the task context and must be initialised to
a non zero value to ensure interrupts don't inadvertently become unmasked before
the scheduler starts. As it is stored as part of the task context it will
automatically be set to 0 when the first task is started. */
* variable has to be stored as part of the task context and must be initialised to
* a non zero value to ensure interrupts don't inadvertently become unmasked before
* the scheduler starts. As it is stored as part of the task context it will
* automatically be set to 0 when the first task is started. */
volatile uint64_t ullCriticalNesting = 9999ULL;
/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
then floating point context must be saved and restored for the task. */
* then floating point context must be saved and restored for the task. */
uint64_t ullPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
uint64_t ullPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
if the nesting depth is 0. */
* if the nesting depth is 0. */
uint64_t ullPortInterruptNesting = 0;
/* Used in the ASM code. */
@ -157,10 +157,12 @@ __attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_C
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. */
* expected by the portRESTORE_CONTEXT() macro. */
/* First all the general purpose registers. */
pxTopOfStack--;
@ -236,13 +238,13 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
pxTopOfStack--;
/* The task will start with a critical nesting count of 0 as interrupts are
enabled. */
* enabled. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
pxTopOfStack--;
/* The task will start without a floating point context. A task that uses
the floating point hardware must call vPortTaskUsesFPU() before executing
any floating point instructions. */
* the floating point hardware must call vPortTaskUsesFPU() before executing
* any floating point instructions. */
*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
return pxTopOfStack;
@ -254,20 +256,23 @@ BaseType_t xPortStartScheduler( void )
uint32_t ulAPSR;
__asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
ulAPSR &= portAPSR_MODE_BITS_MASK;
#if defined( GUEST )
configASSERT( ulAPSR == portEL1 );
if( ulAPSR == portEL1 )
#else
configASSERT( ulAPSR == portEL3 );
if( ulAPSR == portEL3 )
#endif
{
/* Interrupts are turned off in the CPU itself to ensure a tick does
not execute while the scheduler is being started. Interrupts are
automatically turned back on in the CPU when the first task starts
executing. */
* not execute while the scheduler is being started. Interrupts are
* automatically turned back on in the CPU when the first task starts
* executing. */
portDISABLE_INTERRUPTS();
/* Start the timer that generates the tick ISR. */
@ -284,7 +289,7 @@ uint32_t ulAPSR;
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
Artificially force an assert. */
* Artificially force an assert. */
configASSERT( ullCriticalNesting == 1000ULL );
}
/*-----------------------------------------------------------*/
@ -295,15 +300,15 @@ void vPortEnterCritical( void )
uxPortSetInterruptMask();
/* Now interrupts are disabled ullCriticalNesting can be accessed
directly. Increment ullCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
* directly. Increment ullCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
ullCriticalNesting++;
/* This is not the interrupt safe version of the enter critical function so
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
* assert() if it is being called from an interrupt context. Only API
* functions that end in "FromISR" can be used in an interrupt. Only assert if
* the critical nesting count is 1 to protect against recursive calls if the
* assert function also uses a critical section. */
if( ullCriticalNesting == 1ULL )
{
configASSERT( ullPortInterruptNesting == 0 );
@ -316,15 +321,15 @@ void vPortExitCritical( void )
if( ullCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as the critical section is being
exited. */
* exited. */
ullCriticalNesting--;
/* If the nesting level has reached zero then all interrupt
priorities must be re-enabled. */
* priorities must be re-enabled. */
if( ullCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Critical nesting has reached zero so all interrupt priorities
should be unmasked. */
* should be unmasked. */
portCLEAR_INTERRUPT_MASK();
}
}
@ -354,10 +359,10 @@ void FreeRTOS_Tick_Handler( void )
#endif /* configASSERT_DEFINED */
/* Set interrupt mask before altering scheduler structures. The tick
handler runs at the lowest priority, so interrupts cannot already be masked,
so there is no need to save and restore the current mask value. It is
necessary to turn off interrupts in the CPU itself while the ICCPMR is being
updated. */
* handler runs at the lowest priority, so interrupts cannot already be masked,
* so there is no need to save and restore the current mask value. It is
* necessary to turn off interrupts in the CPU itself while the ICCPMR is being
* updated. */
/* s3_0_c4_c6_0 is ICC_PMR_EL1. */
__asm volatile ( "MSR s3_0_c4_c6_0, %0 \n"
"DSB SY \n"
@ -382,11 +387,11 @@ void FreeRTOS_Tick_Handler( void )
void vPortTaskUsesFPU( void )
{
/* A task is registering the fact that it needs an FPU context. Set the
FPU flag (which is saved as part of the task context). */
* FPU flag (which is saved as part of the task context). */
ullPortTaskHasFPUContext = pdTRUE;
/* Consider initialising the FPSR here - but probably not necessary in
AArch64. */
* AArch64. */
}
/*-----------------------------------------------------------*/
@ -405,10 +410,11 @@ uint32_t ulReturn;
uint64_t ullPMRValue;
/* Interrupt in the CPU must be turned off while the ICCPMR is being
updated. */
* updated. */
portDISABLE_INTERRUPTS();
/* s3_0_c4_c6_0 is ICC_PMR_EL1. */
__asm volatile ( "MRS %0, s3_0_c4_c6_0" : "=r" ( ullPMRValue ) );
if( ullPMRValue == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
{
/* Interrupts were already masked. */
@ -435,22 +441,23 @@ uint64_t ullPMRValue;
void vPortValidateInterruptPriority( void )
{
/* The following assertion will fail if a service routine (ISR) for
an interrupt that has been assigned a priority above
configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
function. ISR safe FreeRTOS API functions must *only* be called
from interrupts that have been assigned a priority at or below
configMAX_SYSCALL_INTERRUPT_PRIORITY.
Numerically low interrupt priority numbers represent logically high
interrupt priorities, therefore the priority of the interrupt must
be set to a value equal to or numerically *higher* than
configMAX_SYSCALL_INTERRUPT_PRIORITY.
FreeRTOS maintains separate thread and ISR API functions to ensure
interrupt entry is as fast and simple as possible. */
* an interrupt that has been assigned a priority above
* configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
* function. ISR safe FreeRTOS API functions must *only* be called
* from interrupts that have been assigned a priority at or below
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
*
* Numerically low interrupt priority numbers represent logically high
* interrupt priorities, therefore the priority of the interrupt must
* be set to a value equal to or numerically *higher* than
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
*
* FreeRTOS maintains separate thread and ISR API functions to ensure
* interrupt entry is as fast and simple as possible. */
uint64_t ullRunningInterruptPriority;
/* s3_0_c12_c11_3 is ICC_RPR_EL1. */
__asm volatile ( "MRS %0, s3_0_c12_c11_3" : "=r" ( ullRunningInterruptPriority ) );
configASSERT( ullRunningInterruptPriority >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
}

19
portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h
Unescape Escape View File

@ -62,7 +62,7 @@ typedef uint64_t TickType_t;
#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
not need to be guarded with a critical section. */
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
@ -94,6 +94,7 @@ extern uint64_t ullPortYieldRequired; \
#else
#define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )
#endif
/*-----------------------------------------------------------
* Critical section control
*----------------------------------------------------------*/
@ -116,7 +117,7 @@ extern void vPortInstallFreeRTOSVectorTable( void );
/* These macros do not globally disable/enable interrupts. They do mask off
interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
* interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
#define portENTER_CRITICAL() vPortEnterCritical();
#define portEXIT_CRITICAL() vPortExitCritical();
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask()
@ -125,17 +126,17 @@ interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
not required for this port but included in case common demo code that uses these
macros is used. */
* not required for this port but included in case common demo code that uses these
* macros is used. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/* Prototype of the FreeRTOS tick handler. This must be installed as the
handler for whichever peripheral is used to generate the RTOS tick. */
* handler for whichever peripheral is used to generate the RTOS tick. */
void FreeRTOS_Tick_Handler( void );
/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
before any floating point instructions are executed. */
* before any floating point instructions are executed. */
void vPortTaskUsesFPU( void );
#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
@ -168,7 +169,7 @@ void vPortTaskUsesFPU( void );
#define portINLINE __inline
/* The number of bits to shift for an interrupt priority is dependent on the
number of bits implemented by the interrupt controller. */
* number of bits implemented by the interrupt controller. */
#if configUNIQUE_INTERRUPT_PRIORITIES == 16
#define portPRIORITY_SHIFT 4
#define portMAX_BINARY_POINT_VALUE 3
@ -184,9 +185,9 @@ number of bits implemented by the interrupt controller. */
#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
#define portPRIORITY_SHIFT 0
#define portMAX_BINARY_POINT_VALUE 0
#else
#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
#endif
#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )

211
portable/GCC/ARM_CA9/port.c
Unescape Escape View File

@ -35,64 +35,64 @@
#include "task.h"
#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#ifndef configUNIQUE_INTERRUPT_PRIORITIES
#error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#ifndef configSETUP_TICK_INTERRUPT
#error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif /* configSETUP_TICK_INTERRUPT */
#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
#error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Check the configuration. */
#if ( configMAX_PRIORITIES > 32 )
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
#error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
#endif
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/* In case security extensions are implemented. */
#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
#endif
/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
portmacro.h. */
* portmacro.h. */
#ifndef configCLEAR_TICK_INTERRUPT
#define configCLEAR_TICK_INTERRUPT()
#endif
/* A critical section is exited when the critical section nesting count reaches
this value. */
* this value. */
#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* In all GICs 255 can be written to the priority mask register to unmask all
(but the lowest) interrupt priority. */
* (but the lowest) interrupt priority. */
#define portUNMASK_VALUE ( 0xFFUL )
/* Tasks are not created with a floating point context, but can be given a
floating point context after they have been created. A variable is stored as
part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
does not have an FPU context, or any other value if the task does have an FPU
context. */
* floating point context after they have been created. A variable is stored as
* part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
* does not have an FPU context, or any other value if the task does have an FPU
* context. */
#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Constants required to setup the initial task context. */
@ -102,19 +102,19 @@ context. */
#define portTHUMB_MODE_ADDRESS ( 0x01UL )
/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
point is zero. */
* point is zero. */
#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
/* Masks all bits in the APSR other than the mode bits. */
#define portAPSR_MODE_BITS_MASK ( 0x1F )
/* The value of the mode bits in the APSR when the CPU is executing in user
mode. */
* mode. */
#define portAPSR_USER_MODE ( 0x10 )
/* The critical section macros only mask interrupts up to an application
determined priority level. Sometimes it is necessary to turn interrupt off in
the CPU itself before modifying certain hardware registers. */
* determined priority level. Sometimes it is necessary to turn interrupt off in
* the CPU itself before modifying certain hardware registers. */
#define portCPU_IRQ_DISABLE() \
__asm volatile ( "CPSID i" ::: "memory" ); \
__asm volatile ( "DSB" ); \
@ -141,8 +141,8 @@ the CPU itself before modifying certain hardware registers. */
#define portBIT_0_SET ( ( uint8_t ) 0x01 )
/* Let the user override the pre-loading of the initial LR with the address of
prvTaskExitError() in case it messes up unwinding of the stack in the
debugger. */
* prvTaskExitError() in case it messes up unwinding of the stack in the
* debugger. */
#ifdef configTASK_RETURN_ADDRESS
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
@ -150,7 +150,7 @@ debugger. */
#endif
/* The space on the stack required to hold the FPU registers. This is 32 64-bit
registers, plus a 32-bit status register. */
* registers, plus a 32-bit status register. */
#define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 )
/*-----------------------------------------------------------*/
@ -190,21 +190,21 @@ void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
variable has to be stored as part of the task context and must be initialised to
a non zero value to ensure interrupts don't inadvertently become unmasked before
the scheduler starts. As it is stored as part of the task context it will
automatically be set to 0 when the first task is started. */
* variable has to be stored as part of the task context and must be initialised to
* a non zero value to ensure interrupts don't inadvertently become unmasked before
* the scheduler starts. As it is stored as part of the task context it will
* automatically be set to 0 when the first task is started. */
volatile uint32_t ulCriticalNesting = 9999UL;
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
a floating point context must be saved and restored for the task. */
* a floating point context must be saved and restored for the task. */
volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
volatile uint32_t ulPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
if the nesting depth is 0. */
* if the nesting depth is 0. */
volatile uint32_t ulPortInterruptNesting = 0UL;
/* Used in the asm file. */
@ -218,14 +218,16 @@ __attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CA
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro.
The fist real value on the stack is the status register, which is set for
system mode, with interrupts enabled. A few NULLs are added first to ensure
GDB does not try decoding a non-existent return address. */
* expected by the portRESTORE_CONTEXT() macro.
*
* The fist real value on the stack is the status register, which is set for
* system mode, with interrupts enabled. A few NULLs are added first to ensure
* GDB does not try decoding a non-existent return address. */
*pxTopOfStack = ( StackType_t ) NULL;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) NULL;
@ -277,21 +279,21 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
pxTopOfStack--;
/* The task will start with a critical nesting count of 0 as interrupts are
enabled. */
* enabled. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
#if ( configUSE_TASK_FPU_SUPPORT == 1 )
{
/* The task will start without a floating point context. A task that
uses the floating point hardware must call vPortTaskUsesFPU() before
executing any floating point instructions. */
* uses the floating point hardware must call vPortTaskUsesFPU() before
* executing any floating point instructions. */
pxTopOfStack--;
*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
}
#elif ( configUSE_TASK_FPU_SUPPORT == 2 )
{
/* The task will start with a floating point context. Leave enough
space for the registers - and ensure they are initialised to 0. */
* space for the registers - and ensure they are initialised to 0. */
pxTopOfStack -= portFPU_REGISTER_WORDS;
memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
@ -299,11 +301,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
*pxTopOfStack = pdTRUE;
ulPortTaskHasFPUContext = pdTRUE;
}
#else
#else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
{
#error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.
#error "Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined."
}
#endif
#endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
return pxTopOfStack;
}
@ -312,14 +314,17 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
static void prvTaskExitError( void )
{
/* A function that implements a task must not exit or attempt to return to
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
* its caller as there is nothing to return to. If a task wants to exit it
* should instead call vTaskDelete( NULL ).
*
* Artificially force an assert() to be triggered if configASSERT() is
* defined, then stop here so application writers can catch the error. */
configASSERT( ulPortInterruptNesting == ~0UL );
portDISABLE_INTERRUPTS();
for( ;; );
for( ; ; )
{
}
}
/*-----------------------------------------------------------*/
@ -334,12 +339,12 @@ uint32_t ulAPSR;
volatile uint8_t ucMaxPriorityValue;
/* Determine how many priority bits are implemented in the GIC.
Save the interrupt priority value that is about to be clobbered. */
*
* Save the interrupt priority value that is about to be clobbered. */
ucOriginalPriority = *pucFirstUserPriorityRegister;
/* Determine the number of priority bits available. First write to
all possible bits. */
* all possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
/* Read the value back to see how many bits stuck. */
@ -352,18 +357,18 @@ uint32_t ulAPSR;
}
/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
value. */
* value. */
configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
/* Restore the clobbered interrupt priority register to its original
value. */
* value. */
*pucFirstUserPriorityRegister = ucOriginalPriority;
}
#endif /* configASSERT_DEFINED */
/* Only continue if the CPU is not in User mode. The CPU must be in a
Privileged mode for the scheduler to start. */
* Privileged mode for the scheduler to start. */
__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" );
ulAPSR &= portAPSR_MODE_BITS_MASK;
configASSERT( ulAPSR != portAPSR_USER_MODE );
@ -371,16 +376,16 @@ uint32_t ulAPSR;
if( ulAPSR != portAPSR_USER_MODE )
{
/* Only continue if the binary point value is set to its lowest possible
setting. See the comments in vPortValidateInterruptPriority() below for
more information. */
* setting. See the comments in vPortValidateInterruptPriority() below for
* more information. */
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
{
/* Interrupts are turned off in the CPU itself to ensure tick does
not execute while the scheduler is being started. Interrupts are
automatically turned back on in the CPU when the first task starts
executing. */
* not execute while the scheduler is being started. Interrupts are
* automatically turned back on in the CPU when the first task starts
* executing. */
portCPU_IRQ_DISABLE();
/* Start the timer that generates the tick ISR. */
@ -392,10 +397,10 @@ uint32_t ulAPSR;
}
/* Will only get here if vTaskStartScheduler() was called with the CPU in
a non-privileged mode or the binary point register was not set to its lowest
possible value. prvTaskExitError() is referenced to prevent a compiler
warning about it being defined but not referenced in the case that the user
defines their own exit address. */
* a non-privileged mode or the binary point register was not set to its lowest
* possible value. prvTaskExitError() is referenced to prevent a compiler
* warning about it being defined but not referenced in the case that the user
* defines their own exit address. */
( void ) prvTaskExitError;
return 0;
}
@ -404,7 +409,7 @@ uint32_t ulAPSR;
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
Artificially force an assert. */
* Artificially force an assert. */
configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
@ -414,16 +419,16 @@ void vPortEnterCritical( void )
/* Mask interrupts up to the max syscall interrupt priority. */
ulPortSetInterruptMask();
/* Now interrupts are disabled ulCriticalNesting can be accessed
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
/* Now that interrupts are disabled, ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
/* This is not the interrupt safe version of the enter critical function so
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
* assert() if it is being called from an interrupt context. Only API
* functions that end in "FromISR" can be used in an interrupt. Only assert if
* the critical nesting count is 1 to protect against recursive calls if the
* assert function also uses a critical section. */
if( ulCriticalNesting == 1 )
{
configASSERT( ulPortInterruptNesting == 0 );
@ -436,15 +441,15 @@ void vPortExitCritical( void )
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as the critical section is being
exited. */
* exited. */
ulCriticalNesting--;
/* If the nesting level has reached zero then all interrupt
priorities must be re-enabled. */
* priorities must be re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Critical nesting has reached zero so all interrupt priorities
should be unmasked. */
* should be unmasked. */
portCLEAR_INTERRUPT_MASK();
}
}
@ -454,10 +459,10 @@ void vPortExitCritical( void )
void FreeRTOS_Tick_Handler( void )
{
/* Set interrupt mask before altering scheduler structures. The tick
handler runs at the lowest priority, so interrupts cannot already be masked,
so there is no need to save and restore the current mask value. It is
necessary to turn off interrupts in the CPU itself while the ICCPMR is being
updated. */
* handler runs at the lowest priority, so interrupts cannot already be masked,
* so there is no need to save and restore the current mask value. It is
* necessary to turn off interrupts in the CPU itself while the ICCPMR is being
* updated. */
portCPU_IRQ_DISABLE();
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
__asm volatile ( "dsb \n"
@ -483,7 +488,7 @@ void FreeRTOS_Tick_Handler( void )
uint32_t ulInitialFPSCR = 0;
/* A task is registering the fact that it needs an FPU context. Set the
FPU flag (which is saved as part of the task context). */
* FPU flag (which is saved as part of the task context). */
ulPortTaskHasFPUContext = pdTRUE;
/* Initialise the floating point status register. */
@ -507,8 +512,9 @@ uint32_t ulPortSetInterruptMask( void )
uint32_t ulReturn;
/* Interrupt in the CPU must be turned off while the ICCPMR is being
updated. */
* updated. */
portCPU_IRQ_DISABLE();
if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
{
/* Interrupts were already masked. */
@ -521,6 +527,7 @@ uint32_t ulReturn;
__asm volatile ( "dsb \n"
"isb \n" ::: "memory" );
}
portCPU_IRQ_ENABLE();
return ulReturn;
@ -532,31 +539,31 @@ uint32_t ulReturn;
void vPortValidateInterruptPriority( void )
{
/* The following assertion will fail if a service routine (ISR) for
an interrupt that has been assigned a priority above
configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
function. ISR safe FreeRTOS API functions must *only* be called
from interrupts that have been assigned a priority at or below
configMAX_SYSCALL_INTERRUPT_PRIORITY.
Numerically low interrupt priority numbers represent logically high
interrupt priorities, therefore the priority of the interrupt must
be set to a value equal to or numerically *higher* than
configMAX_SYSCALL_INTERRUPT_PRIORITY.
FreeRTOS maintains separate thread and ISR API functions to ensure
interrupt entry is as fast and simple as possible. */
* an interrupt that has been assigned a priority above
* configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
* function. ISR safe FreeRTOS API functions must *only* be called
* from interrupts that have been assigned a priority at or below
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
*
* Numerically low interrupt priority numbers represent logically high
* interrupt priorities, therefore the priority of the interrupt must
* be set to a value equal to or numerically *higher* than
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
*
* FreeRTOS maintains separate thread and ISR API functions to ensure
* interrupt entry is as fast and simple as possible. */
configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
/* Priority grouping: The interrupt controller (GIC) allows the bits
that define each interrupt's priority to be split between bits that
define the interrupt's pre-emption priority bits and bits that define
the interrupt's sub-priority. For simplicity all bits must be defined
to be pre-emption priority bits. The following assertion will fail if
this is not the case (if some bits represent a sub-priority).
The priority grouping is configured by the GIC's binary point register
(ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
possible value (which may be above 0). */
* that define each interrupt's priority to be split between bits that
* define the interrupt's pre-emption priority bits and bits that define
* the interrupt's sub-priority. For simplicity all bits must be defined
* to be pre-emption priority bits. The following assertion will fail if
* this is not the case (if some bits represent a sub-priority).
*
* The priority grouping is configured by the GIC's binary point register
* (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
* possible value (which may be above 0). */
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
}

27
portable/GCC/ARM_CA9/portmacro.h
Unescape Escape View File

@ -62,7 +62,7 @@ typedef uint32_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
not need to be guarded with a critical section. */
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
@ -102,7 +102,7 @@ extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
extern void vPortInstallFreeRTOSVectorTable( void );
/* These macros do not globally disable/enable interrupts. They do mask off
interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
* interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
#define portENTER_CRITICAL() vPortEnterCritical();
#define portEXIT_CRITICAL() vPortExitCritical();
#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
@ -113,25 +113,26 @@ interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
not required for this port but included in case common demo code that uses these
macros is used. */
* not required for this port but included in case common demo code that uses these
* macros is used. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/* Prototype of the FreeRTOS tick handler. This must be installed as the
handler for whichever peripheral is used to generate the RTOS tick. */
* handler for whichever peripheral is used to generate the RTOS tick. */
void FreeRTOS_Tick_Handler( void );
/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are
created without an FPU context and must call vPortTaskUsesFPU() to give
themselves an FPU context before using any FPU instructions. If
configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
by default. */
* created without an FPU context and must call vPortTaskUsesFPU() to give
* themselves an FPU context before using any FPU instructions. If
* configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
* by default. */
#if ( configUSE_TASK_FPU_SUPPORT != 2 )
void vPortTaskUsesFPU( void );
#else
/* Each task has an FPU context already, so define this function away to
nothing to prevent it being called accidentally. */
* nothing to prevent it being called accidentally. */
#define vPortTaskUsesFPU()
#endif
#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
@ -165,7 +166,7 @@ by default. */
#define portINLINE __inline
/* The number of bits to shift for an interrupt priority is dependent on the
number of bits implemented by the interrupt controller. */
* number of bits implemented by the interrupt controller. */
#if configUNIQUE_INTERRUPT_PRIORITIES == 16
#define portPRIORITY_SHIFT 4
#define portMAX_BINARY_POINT_VALUE 3
@ -181,9 +182,9 @@ number of bits implemented by the interrupt controller. */
#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
#define portPRIORITY_SHIFT 0
#define portMAX_BINARY_POINT_VALUE 0
#else
#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
#endif
#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
/* Interrupt controller access addresses. */
#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )

34
portable/GCC/ARM_CM23/non_secure/port.c
Unescape Escape View File

@ -431,7 +431,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -446,7 +447,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -459,7 +461,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulSystemCallStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -1108,13 +1111,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1155,7 +1161,7 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1215,13 +1221,16 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1262,7 +1271,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1284,6 +1293,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
@ -1291,6 +1301,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
else
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
@ -1330,13 +1341,16 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulTaskStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1374,7 +1388,7 @@ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEG
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1499,6 +1513,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
@ -1511,6 +1526,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
ulIndex++;
}
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;

9
portable/GCC/ARM_CM23/secure/secure_context.c
Unescape Escape View File

@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint32_t ulIPSR, ulSecureContextIndex;
@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;

9
portable/GCC/ARM_CM23/secure/secure_context.h
Unescape Escape View File

@ -108,7 +108,8 @@ void SecureContext_Init( void );
* @param[in] xSecureContextHandle Context handle corresponding to the
* context to be freed.
*/
void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
/**
* @brief Loads the given context.
@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be loaded.
*/
void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
/**
* @brief Saves the given context.
@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be saved.
*/
void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
#endif /* __SECURE_CONTEXT_H__ */

2
portable/GCC/ARM_CM23/secure/secure_init.c
Unescape Escape View File

@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
* permitted. CP11 should be programmed to the same value as CP10. */
*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
/* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
* that we can enable/disable lazy stacking in port.c file. */
*( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );

34
portable/GCC/ARM_CM23_NTZ/non_secure/port.c
Unescape Escape View File

@ -431,7 +431,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -446,7 +447,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -459,7 +461,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulSystemCallStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -1108,13 +1111,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1155,7 +1161,7 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1215,13 +1221,16 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1262,7 +1271,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1284,6 +1293,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
@ -1291,6 +1301,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
else
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
@ -1330,13 +1341,16 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulTaskStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1374,7 +1388,7 @@ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEG
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1499,6 +1513,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
@ -1511,6 +1526,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
ulIndex++;
}
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;

34
portable/GCC/ARM_CM33/non_secure/port.c
Unescape Escape View File

@ -431,7 +431,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -446,7 +447,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -459,7 +461,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulSystemCallStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -1108,13 +1111,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1155,7 +1161,7 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1215,13 +1221,16 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1262,7 +1271,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1284,6 +1293,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
@ -1291,6 +1301,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
else
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
@ -1330,13 +1341,16 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulTaskStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1374,7 +1388,7 @@ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEG
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1499,6 +1513,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
@ -1511,6 +1526,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
ulIndex++;
}
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;

9
portable/GCC/ARM_CM33/secure/secure_context.c
Unescape Escape View File

@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint32_t ulIPSR, ulSecureContextIndex;
@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;

9
portable/GCC/ARM_CM33/secure/secure_context.h
Unescape Escape View File

@ -108,7 +108,8 @@ void SecureContext_Init( void );
* @param[in] xSecureContextHandle Context handle corresponding to the
* context to be freed.
*/
void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
/**
* @brief Loads the given context.
@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be loaded.
*/
void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
/**
* @brief Saves the given context.
@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be saved.
*/
void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
#endif /* __SECURE_CONTEXT_H__ */

2
portable/GCC/ARM_CM33/secure/secure_init.c
Unescape Escape View File

@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
* permitted. CP11 should be programmed to the same value as CP10. */
*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
/* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
* that we can enable/disable lazy stacking in port.c file. */
*( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );

34
portable/GCC/ARM_CM33_NTZ/non_secure/port.c
Unescape Escape View File

@ -431,7 +431,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -446,7 +447,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -459,7 +461,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulSystemCallStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -1108,13 +1111,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1155,7 +1161,7 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1215,13 +1221,16 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1262,7 +1271,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1284,6 +1293,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
@ -1291,6 +1301,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
else
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
@ -1330,13 +1341,16 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulTaskStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1374,7 +1388,7 @@ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEG
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1499,6 +1513,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
@ -1511,6 +1526,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
ulIndex++;
}
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;

34
portable/GCC/ARM_CM35P/non_secure/port.c
Unescape Escape View File

@ -431,7 +431,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -446,7 +447,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -459,7 +461,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulSystemCallStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -1108,13 +1111,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1155,7 +1161,7 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1215,13 +1221,16 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1262,7 +1271,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1284,6 +1293,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
@ -1291,6 +1301,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
else
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
@ -1330,13 +1341,16 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulTaskStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1374,7 +1388,7 @@ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEG
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1499,6 +1513,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
@ -1511,6 +1526,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
ulIndex++;
}
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;

9
portable/GCC/ARM_CM35P/secure/secure_context.c
Unescape Escape View File

@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint32_t ulIPSR, ulSecureContextIndex;
@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;

9
portable/GCC/ARM_CM35P/secure/secure_context.h
Unescape Escape View File

@ -108,7 +108,8 @@ void SecureContext_Init( void );
* @param[in] xSecureContextHandle Context handle corresponding to the
* context to be freed.
*/
void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
/**
* @brief Loads the given context.
@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be loaded.
*/
void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
/**
* @brief Saves the given context.
@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be saved.
*/
void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
#endif /* __SECURE_CONTEXT_H__ */

2
portable/GCC/ARM_CM35P/secure/secure_init.c
Unescape Escape View File

@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
* permitted. CP11 should be programmed to the same value as CP10. */
*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
/* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
* that we can enable/disable lazy stacking in port.c file. */
*( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );

34
portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
Unescape Escape View File

@ -431,7 +431,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -446,7 +447,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -459,7 +461,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulSystemCallStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -1108,13 +1111,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1155,7 +1161,7 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1215,13 +1221,16 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1262,7 +1271,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1284,6 +1293,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
@ -1291,6 +1301,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
else
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
@ -1330,13 +1341,16 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulTaskStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1374,7 +1388,7 @@ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEG
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1499,6 +1513,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
@ -1511,6 +1526,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
ulIndex++;
}
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;

22
portable/GCC/ARM_CM3_MPU/port.c
Unescape Escape View File

@ -287,6 +287,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
}
xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
@ -467,7 +468,9 @@ void vSystemCallEnter( uint32_t * pulTaskStack ) /* PRIVILEGED_FUNCTION */
uint32_t * pulSystemCallStack;
uint32_t ulSystemCallLocation, i;
const uint32_t ulStackFrameSize = 8;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -548,7 +551,9 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack ) /* PRIVILEGED_FUNCTION */
uint32_t * pulSystemCallStack;
uint32_t ulSystemCallLocation, i;
const uint32_t ulStackFrameSize = 8;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -587,6 +592,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack ) /* PRIVILEGED_FUNCTION */
if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
@ -594,6 +600,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack ) /* PRIVILEGED_FUNCTION */
else
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
@ -637,7 +644,9 @@ void vSystemCallExit( uint32_t * pulSystemCallStack ) /* PRIVILEGED_FUNCTION */
uint32_t * pulTaskStack;
uint32_t ulSystemCallLocation, i;
const uint32_t ulStackFrameSize = 8;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -921,10 +930,10 @@ void vPortEnterCritical( void )
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
}
#else
#else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
#endif
#endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
}
/*-----------------------------------------------------------*/
@ -943,6 +952,7 @@ void vPortExitCritical( void )
{
portENABLE_INTERRUPTS();
}
portMEMORY_BARRIER();
portRESET_PRIVILEGE();
@ -958,7 +968,7 @@ void vPortExitCritical( void )
portENABLE_INTERRUPTS();
}
}
#else
#else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
configASSERT( uxCriticalNesting );
uxCriticalNesting--;
@ -966,7 +976,7 @@ void vPortExitCritical( void )
{
portENABLE_INTERRUPTS();
}
#endif
#endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
}
/*-----------------------------------------------------------*/
@ -1284,11 +1294,13 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress;
xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1UL );
xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
if( ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_ONLY ) == portMPU_REGION_READ_ONLY ) ||
( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) == portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) )
{
xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = tskMPU_READ_PERMISSION;
}
if( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_WRITE ) == portMPU_REGION_READ_WRITE )
{
xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION );
@ -1405,7 +1417,7 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
* devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
* scheduler. Note however that some vendor specific peripheral libraries
* assume a non-zero priority group setting, in which cases using a value
* of zero will result in unpredicable behaviour. */
* of zero will result in unpredictable behaviour. */
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}

4
portable/GCC/ARM_CM3_MPU/portmacro.h
Unescape Escape View File

@ -176,7 +176,9 @@
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/

4
portable/GCC/ARM_CM4F/portmacro.h
Unescape Escape View File

@ -72,9 +72,9 @@
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
typedef uint64_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffULL
#else
#else /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */
#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
#endif
#endif /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */
/*-----------------------------------------------------------*/
/* Architecture specifics. */

41
portable/GCC/ARM_CM4_MPU/port.c
Unescape Escape View File

@ -235,7 +235,8 @@ void vResetPrivilege( void ) __attribute__( ( naked ) );
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -250,7 +251,8 @@ void vResetPrivilege( void ) __attribute__( ( naked ) );
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -263,7 +265,8 @@ void vResetPrivilege( void ) __attribute__( ( naked ) );
* @param pulSystemCallStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -312,6 +315,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
}
xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
@ -497,13 +501,16 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -593,13 +600,16 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -654,6 +664,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
@ -661,6 +672,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
else
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
@ -697,13 +709,16 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulTaskStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -867,6 +882,7 @@ BaseType_t xPortStartScheduler( void )
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
#else
/* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
* configENABLE_ERRATA_837070_WORKAROUND to 1 in your
* FreeRTOSConfig.h. */
@ -1033,10 +1049,10 @@ void vPortEnterCritical( void )
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
}
#else
#else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
#endif
#endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
}
/*-----------------------------------------------------------*/
@ -1055,6 +1071,7 @@ void vPortExitCritical( void )
{
portENABLE_INTERRUPTS();
}
portMEMORY_BARRIER();
portRESET_PRIVILEGE();
@ -1070,7 +1087,7 @@ void vPortExitCritical( void )
portENABLE_INTERRUPTS();
}
}
#else
#else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
configASSERT( uxCriticalNesting );
uxCriticalNesting--;
@ -1078,7 +1095,7 @@ void vPortExitCritical( void )
{
portENABLE_INTERRUPTS();
}
#endif
#endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
}
/*-----------------------------------------------------------*/
@ -1471,11 +1488,13 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress;
xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1UL );
xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
if( ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_ONLY ) == portMPU_REGION_READ_ONLY ) ||
( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) == portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) )
{
xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = tskMPU_READ_PERMISSION;
}
if( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_WRITE ) == portMPU_REGION_READ_WRITE )
{
xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION );
@ -1592,7 +1611,7 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
* devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
* scheduler. Note however that some vendor specific peripheral libraries
* assume a non-zero priority group setting, in which cases using a value
* of zero will result in unpredicable behaviour. */
* of zero will result in unpredictable behaviour. */
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}

12
portable/GCC/ARM_CM4_MPU/portmacro.h
Unescape Escape View File

@ -71,7 +71,7 @@ typedef unsigned long UBaseType_t;
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#else
#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
#error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width."
#endif
/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
@ -208,7 +208,7 @@ typedef struct MPU_REGION_SETTINGS
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
#ifndef configSYSTEM_CALL_STACK_SIZE
#error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
#error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2."
#endif
typedef struct SYSTEM_CALL_STACK_INFO
@ -270,7 +270,9 @@ typedef struct MPU_SETTINGS
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@ -312,7 +314,7 @@ extern void vPortExitCritical( void );
/* Check the configuration. */
#if ( configMAX_PRIORITIES > 32 )
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
#error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
#endif
/* Store/clear the ready priorities in a bit map. */
@ -456,7 +458,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
#warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
#warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
#endif
/*-----------------------------------------------------------*/

34
portable/GCC/ARM_CM55/non_secure/port.c
Unescape Escape View File

@ -431,7 +431,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -446,7 +447,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -459,7 +461,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulSystemCallStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -1108,13 +1111,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1155,7 +1161,7 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1215,13 +1221,16 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1262,7 +1271,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1284,6 +1293,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
@ -1291,6 +1301,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
else
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
@ -1330,13 +1341,16 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulTaskStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1374,7 +1388,7 @@ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEG
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1499,6 +1513,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
@ -1511,6 +1526,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
ulIndex++;
}
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;

9
portable/GCC/ARM_CM55/secure/secure_context.c
Unescape Escape View File

@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint32_t ulIPSR, ulSecureContextIndex;
@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;

9
portable/GCC/ARM_CM55/secure/secure_context.h
Unescape Escape View File

@ -108,7 +108,8 @@ void SecureContext_Init( void );
* @param[in] xSecureContextHandle Context handle corresponding to the
* context to be freed.
*/
void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
/**
* @brief Loads the given context.
@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be loaded.
*/
void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
/**
* @brief Saves the given context.
@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be saved.
*/
void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
#endif /* __SECURE_CONTEXT_H__ */

2
portable/GCC/ARM_CM55/secure/secure_init.c
Unescape Escape View File

@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
* permitted. CP11 should be programmed to the same value as CP10. */
*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
/* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
* that we can enable/disable lazy stacking in port.c file. */
*( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );

34
portable/GCC/ARM_CM55_NTZ/non_secure/port.c
Unescape Escape View File

@ -431,7 +431,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -446,7 +447,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -459,7 +461,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulSystemCallStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -1108,13 +1111,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1155,7 +1161,7 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1215,13 +1221,16 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1262,7 +1271,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1284,6 +1293,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
@ -1291,6 +1301,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
else
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
@ -1330,13 +1341,16 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulTaskStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1374,7 +1388,7 @@ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEG
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1499,6 +1513,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
@ -1511,6 +1526,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
ulIndex++;
}
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;

0
portable/GCC/ARM_CM7/r0p1/port.c
Unescape Escape View File

34
portable/GCC/ARM_CM85/non_secure/port.c
Unescape Escape View File

@ -431,7 +431,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -446,7 +447,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -459,7 +461,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulSystemCallStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -1108,13 +1111,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1155,7 +1161,7 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1215,13 +1221,16 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1262,7 +1271,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1284,6 +1293,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
@ -1291,6 +1301,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
else
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
@ -1330,13 +1341,16 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulTaskStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1374,7 +1388,7 @@ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEG
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1499,6 +1513,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
@ -1511,6 +1526,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
ulIndex++;
}
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;

9
portable/GCC/ARM_CM85/secure/secure_context.c
Unescape Escape View File

@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint32_t ulIPSR, ulSecureContextIndex;
@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
}
/*-----------------------------------------------------------*/
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;

9
portable/GCC/ARM_CM85/secure/secure_context.h
Unescape Escape View File

@ -108,7 +108,8 @@ void SecureContext_Init( void );
* @param[in] xSecureContextHandle Context handle corresponding to the
* context to be freed.
*/
void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
/**
* @brief Loads the given context.
@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be loaded.
*/
void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
/**
* @brief Saves the given context.
@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be saved.
*/
void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
void * pvTaskHandle );
#endif /* __SECURE_CONTEXT_H__ */

2
portable/GCC/ARM_CM85/secure/secure_init.c
Unescape Escape View File

@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
* permitted. CP11 should be programmed to the same value as CP10. */
*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
/* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
* that we can enable/disable lazy stacking in port.c file. */
*( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );

34
portable/GCC/ARM_CM85_NTZ/non_secure/port.c
Unescape Escape View File

@ -431,7 +431,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -446,7 +447,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulTaskStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -459,7 +461,8 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @param pulSystemCallStack The current SP when the SVC was raised.
* @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
*/
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@ -1108,13 +1111,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1155,7 +1161,7 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1215,13 +1221,16 @@ void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FU
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallEnter_1( uint32_t * pulTaskStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1262,7 +1271,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1284,6 +1293,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
@ -1291,6 +1301,7 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
else
{
pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
@ -1330,13 +1341,16 @@ void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
{
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulTaskStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@ -1374,7 +1388,7 @@ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEG
ulStackFrameSize = 8;
}
}
#else
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
}
@ -1499,6 +1513,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
@ -1511,6 +1526,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
ulIndex++;
}
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;

2
portable/GCC/ARM_CR5/port.c
Unescape Escape View File

@ -525,7 +525,7 @@ void vPortEnterCritical( void )
ulPortSetInterruptMask();
/*
* Now interrupts are disabled ulCriticalNesting can be accessed
* Now that interrupts are disabled, ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called.
*/

98
portable/GCC/ARM_CRx_No_GIC/port.c
Unescape Escape View File

@ -49,14 +49,14 @@
#endif
/* A critical section is exited when the critical section nesting count reaches
this value. */
* this value. */
#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* Tasks are not created with a floating point context, but can be given a
floating point context after they have been created. A variable is stored as
part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
does not have an FPU context, or any other value if the task does have an FPU
context. */
* floating point context after they have been created. A variable is stored as
* part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
* does not have an FPU context, or any other value if the task does have an FPU
* context. */
#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Constants required to setup the initial task context. */
@ -68,12 +68,12 @@ context. */
#define portAPSR_MODE_BITS_MASK ( 0x1F )
/* The value of the mode bits in the APSR when the CPU is executing in user
mode. */
* mode. */
#define portAPSR_USER_MODE ( 0x10 )
/* Let the user override the pre-loading of the initial LR with the address of
prvTaskExitError() in case it messes up unwinding of the stack in the
debugger. */
* prvTaskExitError() in case it messes up unwinding of the stack in the
* debugger. */
#ifdef configTASK_RETURN_ADDRESS
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
@ -96,21 +96,21 @@ static void prvTaskExitError( void );
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
variable has to be stored as part of the task context and must be initialised to
a non zero value to ensure interrupts don't inadvertently become unmasked before
the scheduler starts. As it is stored as part of the task context it will
automatically be set to 0 when the first task is started. */
* variable has to be stored as part of the task context and must be initialised to
* a non zero value to ensure interrupts don't inadvertently become unmasked before
* the scheduler starts. As it is stored as part of the task context it will
* automatically be set to 0 when the first task is started. */
volatile uint32_t ulCriticalNesting = 9999UL;
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
a floating point context must be saved and restored for the task. */
* a floating point context must be saved and restored for the task. */
volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
volatile uint32_t ulPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
if the nesting depth is 0. */
* if the nesting depth is 0. */
volatile uint32_t ulPortInterruptNesting = 0UL;
/* Used in the asm file to clear an interrupt. */
@ -121,14 +121,16 @@ __attribute__(( used )) const uint32_t ulICCEOIR = configEOI_ADDRESS;
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro.
The fist real value on the stack is the status register, which is set for
system mode, with interrupts enabled. A few NULLs are added first to ensure
GDB does not try decoding a non-existent return address. */
* expected by the portRESTORE_CONTEXT() macro.
*
* The fist real value on the stack is the status register, which is set for
* system mode, with interrupts enabled. A few NULLs are added first to ensure
* GDB does not try decoding a non-existent return address. */
*pxTopOfStack = ( StackType_t ) NULL;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) NULL;
@ -180,13 +182,13 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
pxTopOfStack--;
/* The task will start with a critical nesting count of 0 as interrupts are
enabled. */
* enabled. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
pxTopOfStack--;
/* The task will start without a floating point context. A task that uses
the floating point hardware must call vPortTaskUsesFPU() before executing
any floating point instructions. */
* the floating point hardware must call vPortTaskUsesFPU() before executing
* any floating point instructions. */
*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
return pxTopOfStack;
@ -196,14 +198,17 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
static void prvTaskExitError( void )
{
/* A function that implements a task must not exit or attempt to return to
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
* its caller as there is nothing to return to. If a task wants to exit it
* should instead call vTaskDelete( NULL ).
*
* Artificially force an assert() to be triggered if configASSERT() is
* defined, then stop here so application writers can catch the error. */
configASSERT( ulPortInterruptNesting == ~0UL );
portDISABLE_INTERRUPTS();
for( ;; );
for( ; ; )
{
}
}
/*-----------------------------------------------------------*/
@ -212,8 +217,9 @@ BaseType_t xPortStartScheduler( void )
uint32_t ulAPSR;
/* Only continue if the CPU is not in User mode. The CPU must be in a
Privileged mode for the scheduler to start. */
* Privileged mode for the scheduler to start. */
__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" );
ulAPSR &= portAPSR_MODE_BITS_MASK;
configASSERT( ulAPSR != portAPSR_USER_MODE );
@ -228,10 +234,10 @@ uint32_t ulAPSR;
}
/* Will only get here if vTaskStartScheduler() was called with the CPU in
a non-privileged mode or the binary point register was not set to its lowest
possible value. prvTaskExitError() is referenced to prevent a compiler
warning about it being defined but not referenced in the case that the user
defines their own exit address. */
* a non-privileged mode or the binary point register was not set to its lowest
* possible value. prvTaskExitError() is referenced to prevent a compiler
* warning about it being defined but not referenced in the case that the user
* defines their own exit address. */
( void ) prvTaskExitError;
return 0;
}
@ -240,7 +246,7 @@ uint32_t ulAPSR;
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
Artificially force an assert. */
* Artificially force an assert. */
configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
@ -249,16 +255,16 @@ void vPortEnterCritical( void )
{
portDISABLE_INTERRUPTS();
/* Now interrupts are disabled ulCriticalNesting can be accessed
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
/* Now that interrupts are disabled, ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
/* This is not the interrupt safe version of the enter critical function so
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
* assert() if it is being called from an interrupt context. Only API
* functions that end in "FromISR" can be used in an interrupt. Only assert if
* the critical nesting count is 1 to protect against recursive calls if the
* assert function also uses a critical section. */
if( ulCriticalNesting == 1 )
{
configASSERT( ulPortInterruptNesting == 0 );
@ -271,15 +277,15 @@ void vPortExitCritical( void )
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as the critical section is being
exited. */
* exited. */
ulCriticalNesting--;
/* If the nesting level has reached zero then all interrupt
priorities must be re-enabled. */
* priorities must be re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Critical nesting has reached zero so all interrupt priorities
should be unmasked. */
* should be unmasked. */
portENABLE_INTERRUPTS();
}
}
@ -309,7 +315,7 @@ void vPortTaskUsesFPU( void )
uint32_t ulInitialFPSCR = 0;
/* A task is registering the fact that it needs an FPU context. Set the
FPU flag (which is saved as part of the task context). */
* FPU flag (which is saved as part of the task context). */
ulPortTaskHasFPUContext = pdTRUE;
/* Initialise the floating point status register. */

19
portable/GCC/ARM_CRx_No_GIC/portmacro.h
Unescape Escape View File

@ -62,7 +62,7 @@ typedef uint32_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
not need to be guarded with a critical section. */
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
@ -88,7 +88,8 @@ extern volatile uint32_t ulPortYieldRequired; \
}
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
#define portYIELD() __asm volatile ( "SWI 0 \n" \
#define portYIELD() \
__asm volatile ( "SWI 0 \n" \
"ISB " ::: "memory" );
@ -106,11 +107,12 @@ extern void vPortInstallFreeRTOSVectorTable( void );
#define portINTERRUPT_ENABLE_BIT ( 1 << 7 )
/* In the absence of a priority mask register, these functions and macros
globally enable and disable interrupts. */
* globally enable and disable interrupts. */
#define portENTER_CRITICAL() vPortEnterCritical();
#define portEXIT_CRITICAL() vPortExitCritical();
#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" ::: "memory" );
#define portDISABLE_INTERRUPTS() __asm volatile ( "CPSID i \n" \
#define portDISABLE_INTERRUPTS() \
__asm volatile ( "CPSID i \n" \
"DSB \n" \
"ISB " ::: "memory" );
@ -119,6 +121,7 @@ __attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTER
volatile uint32_t ulCPSR;
__asm volatile ( "MRS %0, CPSR" : "=r" ( ulCPSR )::"memory" );
ulCPSR &= portINTERRUPT_ENABLE_BIT;
portDISABLE_INTERRUPTS();
return ulCPSR;
@ -130,8 +133,8 @@ volatile uint32_t ulCPSR;
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
not required for this port but included in case common demo code that uses these
macros is used. */
* not required for this port but included in case common demo code that uses these
* macros is used. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
@ -142,11 +145,11 @@ macros is used. */
#endif
/* Prototype of the FreeRTOS tick handler. This must be installed as the
handler for whichever peripheral is used to generate the RTOS tick. */
* handler for whichever peripheral is used to generate the RTOS tick. */
void FreeRTOS_Tick_Handler( void );
/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
before any floating point instructions are executed. */
* before any floating point instructions are executed. */
void vPortTaskUsesFPU( void );
#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()

45
portable/GCC/ATMega323/port.c
Unescape Escape View File

@ -27,12 +27,12 @@
*/
/*
Changes from V2.6.0
*
* Changes from V2.6.0
*
+ AVR port - Replaced the inb() and outb() functions with direct memory
access. This allows the port to be built with the 20050414 build of
WinAVR.
+ access. This allows the port to be built with the 20050414 build of
+ WinAVR.
*/
#include <stdlib.h>
@ -57,7 +57,7 @@ Changes from V2.6.0
/*-----------------------------------------------------------*/
/* We require the address of the pxCurrentTCB variable, but don't want to know
any details of its type. */
* any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
@ -183,12 +183,14 @@ static void prvSetupTimerInterrupt( void );
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
uint16_t usAddress;
/* Place a few bytes of known values on the bottom of the stack.
This is just useful for debugging. */
* This is just useful for debugging. */
*pxTopOfStack = 0x11;
pxTopOfStack--;
@ -198,12 +200,12 @@ uint16_t usAddress;
pxTopOfStack--;
/* Simulate how the stack would look after a call to vPortYield() generated by
the compiler. */
* the compiler. */
/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
/* The start of the task code will be popped off the stack last, so place
it on first. */
* it on first. */
usAddress = ( uint16_t ) pxCode;
*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
@ -213,9 +215,9 @@ uint16_t usAddress;
pxTopOfStack--;
/* Next simulate the stack as if after a call to portSAVE_CONTEXT().
portSAVE_CONTEXT places the flags on the stack immediately after r0
to ensure the interrupts get disabled as soon as possible, and so ensuring
the stack use is minimal should a context switch interrupt occur. */
* portSAVE_CONTEXT places the flags on the stack immediately after r0
* to ensure the interrupts get disabled as soon as possible, and so ensuring
* the stack use is minimal should a context switch interrupt occur. */
*pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
pxTopOfStack--;
*pxTopOfStack = portFLAGS_INT_ENABLED;
@ -307,7 +309,7 @@ BaseType_t xPortStartScheduler( void )
portRESTORE_CONTEXT();
/* Simulate a function call end as generated by the compiler. We will now
jump to the start of the task the context of which we have just restored. */
* jump to the start of the task the context of which we have just restored. */
asm volatile ( "ret" );
/* Should not get here. */
@ -318,7 +320,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* It is unlikely that the AVR port will get stopped. If required simply
disable the tick interrupt here. */
* disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
@ -347,10 +349,12 @@ void vPortYieldFromTick( void ) __attribute__ ( ( naked ) );
void vPortYieldFromTick( void )
{
portSAVE_CONTEXT();
if( xTaskIncrementTick() != pdFALSE )
{
vTaskSwitchContext();
}
portRESTORE_CONTEXT();
asm volatile ( "ret" );
@ -366,7 +370,7 @@ uint32_t ulCompareMatch;
uint8_t ucHighByte, ucLowByte;
/* Using 16bit timer 1 to generate the tick. Correct fuses must be
selected for the configCPU_CLOCK_HZ clock. */
* selected for the configCPU_CLOCK_HZ clock. */
ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
@ -377,7 +381,7 @@ uint8_t ucHighByte, ucLowByte;
ulCompareMatch -= ( uint32_t ) 1;
/* Setup compare match value for compare match A. Interrupts are disabled
before this is called so we need not worry here. */
* before this is called so we need not worry here. */
ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
ulCompareMatch >>= 8;
ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
@ -389,7 +393,7 @@ uint8_t ucHighByte, ucLowByte;
TCCR1B = ucLowByte;
/* Enable the interrupt - this is okay as interrupt are currently globally
disabled. */
* disabled. */
ucLowByte = TIMSK;
ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
TIMSK = ucLowByte;
@ -421,7 +425,4 @@ uint8_t ucHighByte, ucLowByte;
{
xTaskIncrementTick();
}
#endif
#endif /* if configUSE_PREEMPTION == 1 */

14
portable/GCC/ATMega323/portmacro.h
Unescape Escape View File

@ -27,10 +27,10 @@
*/
/*
Changes from V1.2.3
+ portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it
base 16.
* Changes from V1.2.3
*
+ portCPU_CLOCK_HZ definition changed to 8MHz base 10, previously it
+ base 16.
*/
#ifndef PORTMACRO_H
@ -79,11 +79,13 @@ typedef unsigned char UBaseType_t;
/*-----------------------------------------------------------*/
/* Critical section management. */
#define portENTER_CRITICAL() asm volatile ( "in __tmp_reg__, __SREG__" :: ); \
#define portENTER_CRITICAL() \
asm volatile ( "in __tmp_reg__, __SREG__" ::); \
asm volatile ( "cli" ::); \
asm volatile ( "push __tmp_reg__" ::)
#define portEXIT_CRITICAL() asm volatile ( "pop __tmp_reg__" :: ); \
#define portEXIT_CRITICAL() \
asm volatile ( "pop __tmp_reg__" ::); \
asm volatile ( "out __SREG__, __tmp_reg__" ::)
#define portDISABLE_INTERRUPTS() asm volatile ( "cli" ::);

79
portable/GCC/AVR32_UC3/port.c
Unescape Escape View File

@ -27,6 +27,7 @@
*/
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief FreeRTOS port source for AVR32 UC3.
@ -134,13 +135,11 @@ void _init_startup(void)
INTC_init_interrupts();
#if configHEAP_INIT
/* Initialize the heap used by malloc. */
for( pxMem = &__heap_start__; pxMem < ( BaseType_t * ) &__heap_end__; )
{
*pxMem++ = 0xA5A5A5A5;
}
#endif
/* Give the used CPU clock frequency to Newlib, so it can work properly. */
@ -161,7 +160,7 @@ void _init_startup(void)
sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[ 0 ] ) );
usart_init( configDBG_USART_BAUDRATE );
}
#endif
#endif /* if configDBG */
}
/*-----------------------------------------------------------*/
@ -201,7 +200,8 @@ void __malloc_unlock(struct _reent *ptr)
/*-----------------------------------------------------------*/
/* Added as there is no such function in FreeRTOS. */
void *pvPortRealloc( void *pv, size_t xWantedSize )
void * pvPortRealloc( void * pv,
size_t xWantedSize )
{
void * pvReturn;
@ -216,9 +216,10 @@ void *pvReturn;
/*-----------------------------------------------------------*/
/* The cooperative scheduler requires a normal IRQ service routine to
simply increment the system tick. */
* simply increment the system tick. */
/* The preemptive scheduler is defined as "naked" as the full context is saved
on entry as part of the context switch. */
* on entry as part of the context switch. */
__attribute__( ( __naked__ ) ) static void vTick( void )
{
/* Save the context of the interrupted task. */
@ -228,13 +229,14 @@ __attribute__((__naked__)) static void vTick( void )
/* Clear the interrupt flag. */
prvClearTcInt();
#else
/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
clock cycles from now. */
* clock cycles from now. */
prvScheduleNextTick();
#endif
/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
calls in a critical section . */
* calls in a critical section . */
portENTER_CRITICAL();
xTaskIncrementTick();
portEXIT_CRITICAL();
@ -254,17 +256,17 @@ __attribute__((__naked__)) void SCALLYield( void )
/*-----------------------------------------------------------*/
/* The code generated by the GCC compiler uses the stack in different ways at
different optimisation levels. The interrupt flags can therefore not always
be saved to the stack. Instead the critical section nesting level is stored
in a variable, which is then saved as part of the stack context. */
* different optimisation levels. The interrupt flags can therefore not always
* be saved to the stack. Instead the critical section nesting level is stored
* in a variable, which is then saved as part of the stack context. */
__attribute__( ( __noinline__ ) ) void vPortEnterCritical( void )
{
/* Disable interrupts */
portDISABLE_INTERRUPTS();
/* Now interrupts are disabled ulCriticalNesting can be accessed
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
/* Now that interrupts are disabled, ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
@ -274,6 +276,7 @@ __attribute__((__noinline__)) void vPortExitCritical( void )
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
ulCriticalNesting--;
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Enable all interrupt/exception. */
@ -289,10 +292,12 @@ __attribute__((__noinline__)) void vPortExitCritical( void )
*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. */
* expected by the portRESTORE_CONTEXT() macro. */
/* When the task starts, it will expect to find the function parameter in R12. */
pxTopOfStack--;
@ -321,7 +326,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
BaseType_t xPortStartScheduler( void )
{
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
* here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
@ -335,12 +340,12 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* It is unlikely that the AVR32 port will require this function as there
is nothing to return to. */
* is nothing to return to. */
}
/*-----------------------------------------------------------*/
/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
clock cycles from now. */
* clock cycles from now. */
#if ( configTICK_USE_TC == 0 )
static void prvScheduleFirstTick( void )
{
@ -348,12 +353,14 @@ clock cycles from now. */
lCycles = Get_system_register( AVR32_COUNT );
lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
// generation feature does not get disabled.
/* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
/* generation feature does not get disabled. */
if( 0 == lCycles )
{
lCycles++;
}
Set_system_register( AVR32_COMPARE, lCycles );
}
@ -363,35 +370,38 @@ clock cycles from now. */
lCycles = Get_system_register( AVR32_COMPARE );
lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
// generation feature does not get disabled.
/* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
/* generation feature does not get disabled. */
if( 0 == lCycles )
{
lCycles++;
}
lCount = Get_system_register( AVR32_COUNT );
if( lCycles < lCount )
{ // We missed a tick, recover for the next.
{ /* We missed a tick, recover for the next. */
lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
}
Set_system_register( AVR32_COMPARE, lCycles );
}
#else
#else /* if ( configTICK_USE_TC == 0 ) */
__attribute__( ( __noinline__ ) ) static void prvClearTcInt( void )
{
AVR32_TC.channel[ configTICK_TC_CHANNEL ].sr;
}
#endif
#endif /* if ( configTICK_USE_TC == 0 ) */
/*-----------------------------------------------------------*/
/* Setup the timer to generate the tick interrupts. */
static void prvSetupTimerInterrupt( void )
{
#if ( configTICK_USE_TC == 1 )
volatile avr32_tc_t * tc = &AVR32_TC;
// Options for waveform genration.
/* Options for waveform genration. */
tc_waveform_opt_t waveform_opt =
{
.channel = configTICK_TC_CHANNEL, /* Channel selection. */
@ -429,14 +439,13 @@ static void prvSetupTimerInterrupt(void)
.lovrs = 0,
.covfs = 0,
};
#endif
#endif /* if ( configTICK_USE_TC == 1 ) */
/* Disable all interrupt/exception. */
portDISABLE_INTERRUPTS();
/* Register the compare interrupt handler to the interrupt controller and
enable the compare interrupt. */
* enable the compare interrupt. */
#if ( configTICK_USE_TC == 1 )
{
@ -446,8 +455,8 @@ static void prvSetupTimerInterrupt(void)
tc_init_waveform( tc, &waveform_opt );
/* Set the compare triggers.
Remember TC counter is 16-bits, so counting second is not possible!
That's why we configure it to count ms. */
* Remember TC counter is 16-bits, so counting second is not possible!
* That's why we configure it to count ms. */
tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4 ) / configTICK_RATE_HZ );
tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
@ -455,10 +464,10 @@ static void prvSetupTimerInterrupt(void)
/* Start the timer/counter. */
tc_start( tc, configTICK_TC_CHANNEL );
}
#else
#else /* if ( configTICK_USE_TC == 1 ) */
{
INTC_register_interrupt( &vTick, AVR32_CORE_COMPARE_IRQ, INT0 );
prvScheduleFirstTick();
}
#endif
#endif /* if ( configTICK_USE_TC == 1 ) */
}

52
portable/GCC/AVR32_UC3/portmacro.h
Unescape Escape View File

@ -27,6 +27,7 @@
*/
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief FreeRTOS port source for AVR32 UC3.
@ -181,7 +182,8 @@ extern void vPortExitCritical( void );
/* Added as there is no such function in FreeRTOS. */
extern void *pvPortRealloc( void *pv, size_t xSize );
extern void * pvPortRealloc( void * pv,
size_t xSize );
/*-----------------------------------------------------------*/
@ -238,25 +240,25 @@ extern void *pvPortRealloc( void *pv, size_t xSize );
* are not the same between INT0..3 exceptions and the scall exception.
*/
// Task context stack layout:
// R8 (*)
// R9 (*)
// R10 (*)
// R11 (*)
// R12 (*)
// R14/LR (*)
// R15/PC (*)
// SR (*)
// R0
// R1
// R2
// R3
// R4
// R5
// R6
// R7
// ulCriticalNesting
// (*) automatically done for INT0..INT3, but not for SCALL
/* Task context stack layout: */
/* R8 (*) */
/* R9 (*) */
/* R10 (*) */
/* R11 (*) */
/* R12 (*) */
/* R14/LR (*) */
/* R15/PC (*) */
/* SR (*) */
/* R0 */
/* R1 */
/* R2 */
/* R3 */
/* R4 */
/* R5 */
/* R6 */
/* R7 */
/* ulCriticalNesting */
/* (*) automatically done for INT0..INT3, but not for SCALL */
/*
* The ISR used for the scheduler tick depends on whether the cooperative or
@ -291,7 +293,7 @@ extern void *pvPortRealloc( void *pv, size_t xSize );
); \
}
#else
#else /* if configUSE_PREEMPTION == 0 */
/*
* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
@ -405,7 +407,7 @@ extern void *pvPortRealloc( void *pv, size_t xSize );
); \
}
#endif
#endif /* if configUSE_PREEMPTION == 0 */
/*
@ -567,7 +569,7 @@ extern void *pvPortRealloc( void *pv, size_t xSize );
); \
}
#else
#else /* if configUSE_PREEMPTION == 0 */
/*
* ISR entry and exit macros. These are only required if a task switch
@ -630,7 +632,7 @@ extern void *pvPortRealloc( void *pv, size_t xSize );
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
/* level and allow other lower interrupt level to occur). */ \
/* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
/* In this case it's of no use to switch context and restore a new SP because we purposely */ \
/* did not previously save SP in its TCB. */ \
"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \
"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \
@ -684,7 +686,7 @@ extern void *pvPortRealloc( void *pv, size_t xSize );
); \
}
#endif
#endif /* if configUSE_PREEMPTION == 0 */
#define portYIELD() { __asm__ __volatile__ ( "scall" ); }

6
portable/GCC/CORTUS_APS3/port.c
Unescape Escape View File

@ -49,10 +49,12 @@
static void prvSetupTimerInterrupt( void );
/*-----------------------------------------------------------*/
StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
/* Make space on the stack for the context - this leaves a couple of spaces
empty. */
* empty. */
pxTopOfStack -= 20;
/* Fill the registers with known values to assist debugging. */

12
portable/GCC/ColdFire_V2/port.c
Unescape Escape View File

@ -36,12 +36,14 @@
#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000 )
/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This
will be set to 0 prior to the first task being started. */
* will be set to 0 prior to the first task being started. */
static uint32_t ulCriticalNesting = 0x9999UL;
/*-----------------------------------------------------------*/
StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
*pxTopOfStack = ( StackType_t ) pvParameters;
pxTopOfStack--;
@ -90,19 +92,20 @@ void vPortEnterCritical( void )
if( ulCriticalNesting == 0UL )
{
/* Guard against context switches being pended simultaneously with a
critical section being entered. */
* critical section being entered. */
do
{
portDISABLE_INTERRUPTS();
if( MCF_INTC0_INTFRCL == 0UL )
{
break;
}
portENABLE_INTERRUPTS();
} while( 1 );
}
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
@ -110,6 +113,7 @@ void vPortEnterCritical( void )
void vPortExitCritical( void )
{
ulCriticalNesting--;
if( ulCriticalNesting == 0 )
{
portENABLE_INTERRUPTS();

23
portable/GCC/H8S2329/port.c
Unescape Escape View File

@ -64,19 +64,22 @@ void vPortYield( void ) __attribute__ ( ( saveall, interrupt_handler ) );
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
uint32_t ulValue;
/* This requires an even address. */
ulValue = ( uint32_t ) pxTopOfStack;
if( ulValue & 1UL )
{
pxTopOfStack = pxTopOfStack - 1;
}
/* Place a few bytes of known values on the bottom of the stack.
This is just useful for debugging. */
* This is just useful for debugging. */
pxTopOfStack--;
*pxTopOfStack = 0xaa;
pxTopOfStack--;
@ -87,7 +90,7 @@ uint32_t ulValue;
*pxTopOfStack = 0xdd;
/* The initial stack mimics an interrupt stack. First there is the program
counter (24 bits). */
* counter (24 bits). */
ulValue = ( uint32_t ) pxCode;
pxTopOfStack--;
@ -104,8 +107,8 @@ uint32_t ulValue;
*pxTopOfStack = portINITIAL_CCR;
/* Next all the general purpose registers - with the parameters being passed
in ER0. The parameter order must match that used by the compiler when the
"saveall" function attribute is used. */
* in ER0. The parameter order must match that used by the compiler when the
* "saveall" function attribute is used. */
/* ER6 */
pxTopOfStack--;
@ -194,8 +197,8 @@ extern void * pxCurrentTCB;
prvSetupTimerInterrupt();
/* Restore the context of the first task that is going to run. This
mirrors the function epilogue code generated by the compiler when the
"saveall" function attribute is used. */
* mirrors the function epilogue code generated by the compiler when the
* "saveall" function attribute is used. */
asm volatile (
"MOV.L @_pxCurrentTCB, ER6 \n\t"
"MOV.L @ER6, ER7 \n\t"
@ -258,7 +261,7 @@ void vPortYield( void )
portRESTORE_STACK_POINTER();
}
#else
#else /* if ( configUSE_PREEMPTION == 1 ) */
/*
* The cooperative scheduler is being used so all we have to do is
@ -274,7 +277,7 @@ void vPortYield( void )
TSR1 &= ~0x01;
}
#endif
#endif /* if ( configUSE_PREEMPTION == 1 ) */
/*-----------------------------------------------------------*/
/*
@ -294,7 +297,7 @@ const uint32_t ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / po
TGR1A = ulCompareMatch;
/* Start the timer and enable the interrupt - we can do this here as
interrupts are globally disabled when this function is called. */
* interrupts are globally disabled when this function is called. */
TIER1 |= portTGRA_INTERRUPT_ENABLE;
TSTR |= portTIMER_CHANNEL;
}

13
portable/GCC/H8S2329/portmacro.h
Unescape Escape View File

@ -83,7 +83,8 @@ typedef unsigned char UBaseType_t;
#define portDISABLE_INTERRUPTS() asm volatile ( "ORC #0x80, CCR" );
/* Push the CCR then disable interrupts. */
#define portENTER_CRITICAL() asm volatile( "STC CCR, @-ER7" ); \
#define portENTER_CRITICAL() \
asm volatile ( "STC CCR, @-ER7" ); \
portDISABLE_INTERRUPTS();
/* Pop the CCR to set the interrupt masking back to its previous state. */
@ -93,9 +94,9 @@ typedef unsigned char UBaseType_t;
/* Task utilities. */
/* Context switch macros. These macros are very simple as the context
is saved simply by selecting the saveall attribute of the context switch
interrupt service routines. These macros save and restore the stack
pointer to the TCB. */
* is saved simply by selecting the saveall attribute of the context switch
* interrupt service routines. These macros save and restore the stack
* pointer to the TCB. */
#define portSAVE_STACK_POINTER() \
extern void * pxCurrentTCB; \
@ -121,14 +122,14 @@ extern void* pxCurrentTCB; \
/* Macros to allow a context switch from within an application ISR. */
#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); {
#define portEXIT_SWITCHING_ISR( x ) \
if( x ) \
{ \
extern void vTaskSwitchContext( void ); \
vTaskSwitchContext(); \
} \
} portRESTORE_STACK_POINTER();
} \
portRESTORE_STACK_POINTER();
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */

62
portable/GCC/HCS12/port.c
Unescape Escape View File

@ -47,40 +47,40 @@
static void prvSetupTimerInterrupt( void );
/* NOTE: Interrupt service routines must be in non-banked memory - as does the
scheduler startup function. */
* scheduler startup function. */
#define ATTR_NEAR __attribute__( ( near ) )
/* Manual context switch function. This is the SWI ISR. */
// __attribute__((interrupt))
/* __attribute__((interrupt)) */
void ATTR_NEAR vPortYield( void );
/* Tick context switch function. This is the timer ISR. */
// __attribute__((interrupt))
/* __attribute__((interrupt)) */
void ATTR_NEAR vPortTickInterrupt( void );
/* Function in non-banked memory which actually switches to first task. */
BaseType_t ATTR_NEAR xStartSchedulerNear( void );
/* Calls to portENTER_CRITICAL() can be nested. When they are nested the
critical section should not be left (i.e. interrupts should not be re-enabled)
until the nesting depth reaches 0. This variable simply tracks the nesting
depth. Each task maintains it's own critical nesting depth variable so
uxCriticalNesting is saved and restored from the task stack during a context
switch. */
volatile UBaseType_t uxCriticalNesting = 0x80; // un-initialized
* critical section should not be left (i.e. interrupts should not be re-enabled)
* until the nesting depth reaches 0. This variable simply tracks the nesting
* depth. Each task maintains it's own critical nesting depth variable so
* uxCriticalNesting is saved and restored from the task stack during a context
* switch. */
volatile UBaseType_t uxCriticalNesting = 0x80; /* un-initialized */
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. In this case the stack as
expected by the HCS12 RTI instruction. */
* expected by the portRESTORE_CONTEXT() macro. In this case the stack as
* expected by the HCS12 RTI instruction. */
/* The address of the task function is placed in the stack byte at a time. */
@ -104,8 +104,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
*--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 1 );
/* CCR: Note that when the task starts interrupts will be enabled since
"I" bit of CCR is cleared */
*--pxTopOfStack = ( StackType_t ) 0x80; // keeps Stop disabled (MCU default)
* "I" bit of CCR is cleared */
*--pxTopOfStack = ( StackType_t ) 0x80; /* keeps Stop disabled (MCU default) */
/* tmp softregs used by GCC. Values right now don't matter. */
__asm( "\n\
@ -119,11 +119,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
#ifdef BANKED_MODEL
/* The page of the task. */
*--pxTopOfStack = 0x30; // can only directly start in PPAGE 0x30
*--pxTopOfStack = 0x30; /* can only directly start in PPAGE 0x30 */
#endif
/* The critical nesting depth is initialised with 0 (meaning not in
a critical section). */
* a critical section). */
*--pxTopOfStack = ( StackType_t ) 0x00;
@ -141,20 +141,21 @@ static void prvSetupTimerInterrupt( void )
{
/* Enable hardware RTI timer */
/* Ignores configTICK_RATE_HZ */
RTICTL = 0x50; // 16 MHz xtal: 976.56 Hz, 1024mS
CRGINT |= 0x80; // RTIE
RTICTL = 0x50; /* 16 MHz xtal: 976.56 Hz, 1024mS */
CRGINT |= 0x80; /* RTIE */
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
/* xPortStartScheduler() does not start the scheduler directly because
the header file containing the xPortStartScheduler() prototype is part
of the common kernel code, and therefore cannot use the CODE_SEG pragma.
Instead it simply calls the locally defined xNearStartScheduler() -
which does use the CODE_SEG pragma. */
* the header file containing the xPortStartScheduler() prototype is part
* of the common kernel code, and therefore cannot use the CODE_SEG pragma.
* Instead it simply calls the locally defined xNearStartScheduler() -
* which does use the CODE_SEG pragma. */
int16_t register d;
__asm( "jmp xStartSchedulerNear ; will never return" : "=d" ( d ) );
return d;
}
@ -163,7 +164,7 @@ BaseType_t xPortStartScheduler( void )
BaseType_t xStartSchedulerNear( void )
{
/* Configure the timer that will generate the RTOS tick. Interrupts are
disabled when this function is called. */
* disabled when this function is called. */
prvSetupTimerInterrupt();
/* Restore the context of the first task. */
@ -187,9 +188,10 @@ BaseType_t xStartSchedulerNear( void )
void vPortYield( void )
{
portISR_HEAD();
/* NOTE: This is the trap routine (swi) although not defined as a trap.
It will fill the stack the same way as an ISR in order to mix preemtion
and cooperative yield. */
* It will fill the stack the same way as an ISR in order to mix preemtion
* and cooperative yield. */
portSAVE_CONTEXT();
vTaskSwitchContext();
@ -224,14 +226,14 @@ void vPortTickInterrupt( void )
}
/* Restore the context of a task - which may be a different task
to that interrupted. */
* to that interrupted. */
portRESTORE_CONTEXT();
}
#else
#else /* if configUSE_PREEMPTION == 1 */
{
xTaskIncrementTick();
}
#endif
#endif /* if configUSE_PREEMPTION == 1 */
portISR_TAIL();
}

5
portable/GCC/HCS12/portmacro.h
Unescape Escape View File

@ -126,6 +126,7 @@ typedef unsigned char UBaseType_t;
*/
#ifdef BANKED_MODEL
/*
* Load the stack pointer for the task, then pull the critical nesting
* count and PPAGE register from the stack. The remains of the
@ -163,7 +164,7 @@ typedef unsigned char UBaseType_t;
sts 0,x ; Stack \n\
" ); \
}
#else
#else /* ifdef BANKED_MODEL */
/*
* These macros are as per the BANKED versions above, but without saving
@ -195,7 +196,7 @@ typedef unsigned char UBaseType_t;
sts 0,x ; Stack \n\
" ); \
}
#endif
#endif /* ifdef BANKED_MODEL */
/*
* Utility macros to save/restore correct software registers for GCC. This is

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