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@ -100,7 +100,7 @@ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE
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pxTopOfStack--;
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x30303030; /* Initial Value of R30 */
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*pxTopOfStack = ( portSTACK_TYPE ) 0x30303030; /* Initial Value of R30 */
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pxTopOfStack--;
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x19191919; /* Initial Value of R19 */
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*pxTopOfStack = ( portSTACK_TYPE ) 0x19191919; /* Initial Value of R19 */
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pxTopOfStack--;
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x18181818; /* Initial Value of R18 */
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*pxTopOfStack = ( portSTACK_TYPE ) 0x18181818; /* Initial Value of R18 */
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pxTopOfStack--;
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pxTopOfStack--;
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@ -112,7 +112,7 @@ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE
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pxTopOfStack--;
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x14141414; /* Initial Value of R14 */
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*pxTopOfStack = ( portSTACK_TYPE ) 0x14141414; /* Initial Value of R14 */
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pxTopOfStack--;
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x13131313; /* Initial Value of R13 */
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*pxTopOfStack = ( portSTACK_TYPE ) 0x13131313; /* Initial Value of R13 */
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pxTopOfStack--;
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* Initial Value of R12 */
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*pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* Initial Value of R12 */
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pxTopOfStack--;
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pxTopOfStack--;
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@ -136,13 +136,14 @@ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE
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#endif /* configDATA_MODE */
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#endif /* configDATA_MODE */
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*pxTopOfStack = ( portSTACK_TYPE ) 0x22222222; /* Initial Value of R02 */
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*pxTopOfStack = ( portSTACK_TYPE ) 0x22222222; /* Initial Value of R02 */
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pxTopOfStack--;
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R1 is expected to hold the function parameter*/
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*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R1 is expected to hold the function parameter*/
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pxTopOfStack--;
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING;
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*pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING;
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/*
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* Return a pointer to the top of the stack we have generated so this can
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/*
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* be stored in the task control block for the task.
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* Return a pointer to the top of the stack we have generated so this can
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*/
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* be stored in the task control block for the task.
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*/
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return pxTopOfStack;
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return pxTopOfStack;
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}
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}
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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@ -152,8 +153,10 @@ portBASE_TYPE xPortStartScheduler( void )
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/* Setup the hardware to generate the tick. Interrupts are disabled when
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/* Setup the hardware to generate the tick. Interrupts are disabled when
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this function is called. */
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this function is called. */
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prvSetupTimerInterrupt();
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prvSetupTimerInterrupt();
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/* Restore the context of the first task that is going to run. */
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/* Restore the context of the first task that is going to run. */
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vPortStart();
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vPortStart();
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/* Should not get here as the tasks are now running! */
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/* Should not get here as the tasks are now running! */
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return pdTRUE;
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return pdTRUE;
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}
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}
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@ -171,17 +174,16 @@ void vPortEndScheduler( void )
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*/
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*/
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static void prvSetupTimerInterrupt( void )
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static void prvSetupTimerInterrupt( void )
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{
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{
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TM0CE = 0; /* TMM0 operation disable */
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TM0CE = 0; /* TMM0 operation disable */
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TM0EQMK0 = 1; /* INTTM0EQ0 interrupt disable */
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TM0EQMK0 = 1; /* INTTM0EQ0 interrupt disable */
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TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
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TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
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/* Set INTTM0EQ0 level 5 priority */
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/* Set INTTM0EQ0 level 5 priority */
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TM0EQIC0 &= 0xF8;
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TM0EQIC0 &= 0xF8;
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/* TM0EQIC0 |= 0x05;*/
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TM0CTL0 = 0x00;
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TM0CTL0 = 0x00;
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TM0CMP0 = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1); /* divided by 2 because peripherals only run at CPU_CLOCK/2 */
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TM0CMP0 = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1); /* divided by 2 because peripherals only run at CPU_CLOCK/2 */
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TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
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TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
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TM0EQMK0 = 0; /* INTTM0EQ0 interrupt enable */
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TM0EQMK0 = 0; /* INTTM0EQ0 interrupt enable */
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TM0CE = 1; /* TMM0 operation enable */
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TM0CE = 1; /* TMM0 operation enable */
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}
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}
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