Enter sleep mode in the idle task.
Richard Barry
14 years ago
parent
52b4c95301
commit
556fc15e99
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/**
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******************************************************************************
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* @file stm32l1xx_pwr.h
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* @author MCD Application Team
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* @version V1.0.0RC1
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* @date 07/02/2010
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* @brief This file contains all the functions prototypes for the PWR firmware
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* library.
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******************************************************************************
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* @copy
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32L1xx_PWR_H
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#define __STM32L1xx_PWR_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l1xx.h"
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/** @addtogroup STM32L1xx_StdPeriph_Driver
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* @{
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*/
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/** @addtogroup PWR
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* @{
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*/
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/** @defgroup PWR_Exported_Types
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup PWR_Exported_Constants
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* @{
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*/
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/** @defgroup PVD_detection_level
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* @{
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*/
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#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
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#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
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#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
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#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
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#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
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#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
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#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
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#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 /* External input analog voltage
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(Compare internally to VREFINT) */
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#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
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((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
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((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
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((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
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/**
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* @}
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*/
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/** @defgroup WakeUp_Pins
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* @{
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*/
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#define PWR_WakeUpPin_1 ((uint32_t)0x00000000)
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#define PWR_WakeUpPin_2 ((uint32_t)0x00000004)
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#define PWR_WakeUpPin_3 ((uint32_t)0x00000008)
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#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \
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((PIN) == PWR_WakeUpPin_2) || \
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((PIN) == PWR_WakeUpPin_3))
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/**
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* @}
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*/
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/** @defgroup Voltage_Scaling_Ranges
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* @{
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*/
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#define PWR_VoltageScaling_Range1 PWR_CR_VOS_0
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#define PWR_VoltageScaling_Range2 PWR_CR_VOS_1
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#define PWR_VoltageScaling_Range3 PWR_CR_VOS
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#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_VoltageScaling_Range1) || \
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((RANGE) == PWR_VoltageScaling_Range2) || \
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((RANGE) == PWR_VoltageScaling_Range3))
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/**
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* @}
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*/
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/** @defgroup Regulator_state_is_Sleep_STOP_mode
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* @{
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*/
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#define PWR_Regulator_ON ((uint32_t)0x00000000)
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#define PWR_Regulator_LowPower PWR_CR_LPSDSR
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#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
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((REGULATOR) == PWR_Regulator_LowPower))
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/**
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* @}
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*/
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/** @defgroup SLEEP_mode_entry
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* @{
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*/
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#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
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#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
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#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
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/**
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* @}
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*/
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/** @defgroup STOP_mode_entry
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* @{
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*/
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#define PWR_STOPEntry_WFI ((uint8_t)0x01)
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#define PWR_STOPEntry_WFE ((uint8_t)0x02)
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#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
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/**
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* @}
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*/
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/** @defgroup PWR_Flag
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* @{
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*/
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#define PWR_FLAG_WU PWR_CSR_WUF
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#define PWR_FLAG_SB PWR_CSR_SBF
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#define PWR_FLAG_PVDO PWR_CSR_PVDO
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#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
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#define PWR_FLAG_VOS PWR_CSR_VOSF
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#define PWR_FLAG_REGLP PWR_CSR_REGLPF
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#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
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((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \
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((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP))
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#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @defgroup PWR_Exported_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup PWR_Exported_Functions
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* @{
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*/
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void PWR_DeInit(void);
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void PWR_RTCAccessCmd(FunctionalState NewState);
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void PWR_PVDCmd(FunctionalState NewState);
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void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
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void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
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void PWR_FastWakeUpCmd(FunctionalState NewState);
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void PWR_UltraLowPowerCmd(FunctionalState NewState);
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void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling);
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void PWR_EnterLowPowerRunMode(FunctionalState NewState);
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void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry);
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void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
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void PWR_EnterSTANDBYMode(void);
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FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
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void PWR_ClearFlag(uint32_t PWR_FLAG);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32L1xx_PWR_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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@ -0,0 +1,464 @@
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/**
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******************************************************************************
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* @file stm32l1xx_pwr.c
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* @author MCD Application Team
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* @version V1.0.0RC1
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* @date 07/02/2010
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* @brief This file provides all the PWR firmware functions.
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******************************************************************************
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* @copy
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l1xx_pwr.h"
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#include "stm32l1xx_rcc.h"
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/** @addtogroup STM32L1xx_StdPeriph_Driver
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* @{
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*/
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/** @defgroup PWR
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* @brief PWR driver modules
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* @{
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*/
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/** @defgroup PWR_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup PWR_Private_Defines
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* @{
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*/
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/* --------- PWR registers bit address in the alias region ---------- */
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#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
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/* --- CR Register ---*/
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/* Alias word address of DBP bit */
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#define CR_OFFSET (PWR_OFFSET + 0x00)
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#define DBP_BitNumber 0x08
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#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
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/* Alias word address of PVDE bit */
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#define PVDE_BitNumber 0x04
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#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
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/* Alias word address of ULP bit */
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#define ULP_BitNumber 0x09
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#define CR_ULP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))
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/* Alias word address of FWU bit */
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#define FWU_BitNumber 0x0A
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#define CR_FWU_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))
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/* --- CSR Register ---*/
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/* Alias word address of EWUP bit */
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#define CSR_OFFSET (PWR_OFFSET + 0x04)
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#define EWUP_BitNumber 0x08
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#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
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/* ------------------ PWR registers bit mask ------------------------ */
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/* CR register bit mask */
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#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
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#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
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#define CR_VOS_MASK ((uint32_t)0xFFFFE7FF)
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/**
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* @}
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*/
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/** @defgroup PWR_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup PWR_Private_Variables
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup PWR_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup PWR_Private_Functions
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* @{
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*/
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/**
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* @brief Deinitializes the PWR peripheral registers to their default reset values.
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* @param None
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* @retval None
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*/
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void PWR_DeInit(void)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
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}
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/**
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* @brief Enables or disables access to the RTC and backup registers.
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* @param NewState: new state of the access to the RTC and backup registers.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_RTCAccessCmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
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}
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/**
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* @brief Enables or disables the Power Voltage Detector(PVD).
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* @param NewState: new state of the PVD.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_PVDCmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
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}
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/**
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* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
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* @param PWR_PVDLevel: specifies the PVD detection level
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* This parameter can be one of the following values:
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* @arg PWR_PVDLevel_0: PVD detection level set to 1.9V
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* @arg PWR_PVDLevel_1: PVD detection level set to 2.1V
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* @arg PWR_PVDLevel_2: PVD detection level set to 2.3V
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* @arg PWR_PVDLevel_3: PVD detection level set to 2.5V
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* @arg PWR_PVDLevel_4: PVD detection level set to 2.7V
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* @arg PWR_PVDLevel_5: PVD detection level set to 2.9V
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* @arg PWR_PVDLevel_6: PVD detection level set to 3.1V
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* @arg PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT)
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* @retval None
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*/
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void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
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{
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
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tmpreg = PWR->CR;
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/* Clear PLS[7:5] bits */
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tmpreg &= CR_PLS_MASK;
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/* Set PLS[7:5] bits according to PWR_PVDLevel value */
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tmpreg |= PWR_PVDLevel;
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/* Store the new value */
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PWR->CR = tmpreg;
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}
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/**
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* @brief Enables or disables the WakeUp Pin functionality.
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* @param PWR_WakeUpPin: specifies the WakeUpPin.
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* This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.
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* @param NewState: new state of the WakeUp Pin functionality.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
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{
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__IO uint32_t tmp = 0;
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/* Check the parameters */
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assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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tmp = CSR_EWUP_BB + PWR_WakeUpPin;
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*(__IO uint32_t *) (tmp) = (uint32_t)NewState;
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}
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/**
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* @brief Enables or disables the Fast WakeUp from Ultra Low Power mode.
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* @param NewState: new state of the Fast WakeUp functionality.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_FastWakeUpCmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CR_FWU_BB = (uint32_t)NewState;
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}
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/**
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* @brief Enables or disables the Ultra Low Power mode.
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* @param NewState: new state of the Ultra Low Power mode.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_UltraLowPowerCmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CR_ULP_BB = (uint32_t)NewState;
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}
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/**
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* @brief Configures the voltage scaling range.
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* @param PWR_VoltageScaling: specifies the voltage scaling range.
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* This parameter can be:
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* @arg PWR_VoltageScaling_Range1: Voltage Scaling Range 1
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* @arg PWR_VoltageScaling_Range2: Voltage Scaling Range 2
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* @arg PWR_VoltageScaling_Range3: Voltage Scaling Range 3
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* @retval None
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*/
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void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling)
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{
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uint32_t tmp = 0;
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/* Check the parameters */
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assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(PWR_VoltageScaling));
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tmp = PWR->CR;
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tmp &= CR_VOS_MASK;
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tmp |= PWR_VoltageScaling;
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PWR->CR = tmp & 0xFFFFFFF3;
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}
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||||
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||||
/**
|
||||
* @brief Enters/Exits the Low Power Run mode.
|
||||
* @param NewState: new state of the Low Power Run mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterLowPowerRunMode(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
PWR->CR |= PWR_CR_LPSDSR;
|
||||
PWR->CR |= PWR_CR_LPRUN;
|
||||
}
|
||||
else
|
||||
{
|
||||
PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN);
|
||||
PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Sleep mode.
|
||||
* @param PWR_Regulator: specifies the regulator state in Sleep mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_Regulator_ON: Sleep mode with regulator ON
|
||||
* @arg PWR_Regulator_LowPower: Sleep mode with regulator in low power mode
|
||||
* @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
|
||||
* @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
|
||||
|
||||
assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
|
||||
|
||||
/* Select the regulator state in Sleep mode ---------------------------------*/
|
||||
tmpreg = PWR->CR;
|
||||
|
||||
/* Clear PDDS and LPDSR bits */
|
||||
tmpreg &= CR_DS_MASK;
|
||||
|
||||
/* Set LPDSR bit according to PWR_Regulator value */
|
||||
tmpreg |= PWR_Regulator;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
|
||||
|
||||
/* Select SLEEP mode entry -------------------------------------------------*/
|
||||
if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STOP mode.
|
||||
* @param PWR_Regulator: specifies the regulator state in STOP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_Regulator_ON: STOP mode with regulator ON
|
||||
* @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
|
||||
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
|
||||
* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
|
||||
|
||||
/* Select the regulator state in STOP mode ---------------------------------*/
|
||||
tmpreg = PWR->CR;
|
||||
/* Clear PDDS and LPDSR bits */
|
||||
tmpreg &= CR_DS_MASK;
|
||||
|
||||
/* Set LPDSR bit according to PWR_Regulator value */
|
||||
tmpreg |= PWR_Regulator;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP;
|
||||
|
||||
/* Select STOP mode entry --------------------------------------------------*/
|
||||
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__WFE();
|
||||
}
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STANDBY mode.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
/* Clear Wake-up flag */
|
||||
PWR->CR |= PWR_CR_CWUF;
|
||||
|
||||
/* Select STANDBY mode */
|
||||
PWR->CR |= PWR_CR_PDDS;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP;
|
||||
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM )
|
||||
__force_stores();
|
||||
#endif
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified PWR flag is set or not.
|
||||
* @param PWR_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
* @arg PWR_FLAG_PVDO: PVD Output
|
||||
* @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag
|
||||
* @arg PWR_FLAG_VOS: Voltage Scaling select flag
|
||||
* @arg PWR_FLAG_REGLP: Regulator LP flag
|
||||
* @retval The new state of PWR_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
|
||||
|
||||
if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the PWR's pending flags.
|
||||
* @param PWR_FLAG: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_ClearFlag(uint32_t PWR_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
|
||||
|
||||
PWR->CR |= PWR_FLAG << 2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
|
||||
Loading…
Reference in New Issue