diff --git a/Demo/Cortex_STM32L152_IAR/FreeRTOSConfig.h b/Demo/Cortex_STM32L152_IAR/FreeRTOSConfig.h index a4aa0374f..5c9a376f5 100644 --- a/Demo/Cortex_STM32L152_IAR/FreeRTOSConfig.h +++ b/Demo/Cortex_STM32L152_IAR/FreeRTOSConfig.h @@ -67,7 +67,7 @@ *----------------------------------------------------------*/ #define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 +#define configUSE_IDLE_HOOK 1 #define configUSE_TICK_HOOK 1 #define configCPU_CLOCK_HZ ( 32000000UL ) #define configTICK_RATE_HZ ( ( portTickType ) 1000 ) diff --git a/Demo/Cortex_STM32L152_IAR/RTOSDemo.ewp b/Demo/Cortex_STM32L152_IAR/RTOSDemo.ewp index 6f8de65c3..bcf508825 100644 --- a/Demo/Cortex_STM32L152_IAR/RTOSDemo.ewp +++ b/Demo/Cortex_STM32L152_IAR/RTOSDemo.ewp @@ -1788,6 +1788,9 @@ $PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_gpio.c + + $PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_pwr.c + $PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_rcc.c diff --git a/Demo/Cortex_STM32L152_IAR/main.c b/Demo/Cortex_STM32L152_IAR/main.c index 9329e6528..8dbf6daba 100644 --- a/Demo/Cortex_STM32L152_IAR/main.c +++ b/Demo/Cortex_STM32L152_IAR/main.c @@ -367,5 +367,12 @@ void vApplicationMallocFailedHook( void ) { for( ;; ); } +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + PWR_EnterSleepMode( PWR_Regulator_ON, PWR_SLEEPEntry_WFI ); +} + diff --git a/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dni b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dni index 42f771af7..fab1365c8 100644 --- a/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dni +++ b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dni @@ -1,5 +1,5 @@ [DebugChecksum] -Checksum=-72575356 +Checksum=818382432 [DisAssemblyWindow] NumStates=_ 1 State 1=_ 1 @@ -70,6 +70,10 @@ ShowTimeLog=1 ShowTimeSum=0 Title0=Power [mA] Setup0=0 1 0 500 2 0 4 1 0 +[Disassemble mode] +mode=0 +[Breakpoints] +Count=0 [Log file] LoggingEnabled=_ 0 LogFile=_ "" @@ -77,6 +81,9 @@ Category=_ 0 [TermIOLog] LoggingEnabled=_ 0 LogFile=_ "" +[Aliases] +Count=0 +SuppressDialog=0 [SWOTraceWindow] PcSampling=0 InterruptLogs=0 @@ -96,10 +103,3 @@ Enabled=0 Mode=3 Graph=0 Symbiont=0 -[Disassemble mode] -mode=0 -[Breakpoints] -Count=0 -[Aliases] -Count=0 -SuppressDialog=0 diff --git a/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.wsdt b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.wsdt index 3428edc3d..0b5da45ab 100644 --- a/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.wsdt +++ b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.wsdt @@ -12,12 +12,12 @@ - 364272727 + 348272727 20121632481201622 - + TabID-27630-4718 @@ -25,24 +25,24 @@ Workspace - RTOSDemoRTOSDemo/FreeRTOS_SourceRTOSDemo/FreeRTOS_Source/PortableRTOSDemo/Standard_Demo_Code + RTOSDemoRTOSDemo/FreeRTOS_SourceRTOSDemo/FreeRTOS_Source/PortableRTOSDemo/Standard_Demo_CodeRTOSDemo/System_and_ST_CodeRTOSDemo/System_and_ST_Code/Peripheral_LibraryRTOSDemo/System_and_ST_Code/Peripheral_Library/stm32l1xx_pwr.c - 0TabID-10002-7709BuildBuildTabID-18437-21512Debug LogDebug-Log0 + 0TabID-10002-7709BuildBuildTabID-18437-21512Debug LogDebug-Log0 - TextEditor$WS_DIR$\main.c0116488448840TextEditor$WS_DIR$\..\Common\Minimal\GenQTest.c05311820518238TextEditor$WS_DIR$\FreeRTOSConfig.h06143594359TextEditor$WS_DIR$\..\..\Source\portable\MemMang\heap_2.c021297759817TextEditor$WS_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c016170947094TextEditor$WS_DIR$\system_and_ST_code\stm32l1xx_it.c04522442244TextEditor$WS_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s0100456745670100000010000001 + TextEditor$WS_DIR$\main.c03361304513045TextEditor$WS_DIR$\..\Common\Minimal\GenQTest.c05311820518238TextEditor$WS_DIR$\FreeRTOSConfig.h06136653665TextEditor$WS_DIR$\..\..\Source\portable\MemMang\heap_2.c021297759817TextEditor$WS_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c016170947094TextEditor$WS_DIR$\system_and_ST_code\stm32l1xx_it.c04522442244TextEditor$WS_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s010045674567TextEditor$WS_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_pwr.c038982128230TextEditor$WS_DIR$\system_and_ST_code\stm32l1xx_conf.h001632163280100000010000001 - iaridepm.enu1-2-2740438-2-2200200119048203666261905755601-2-21981682-2-216842001002381203666119048203666 + iaridepm.enu1-2-2740438-2-2200200119048203666261905755601-2-21981682-2-216842001002381203666119048203666 diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_pwr.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_pwr.h new file mode 100644 index 000000000..d96aa9e15 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_pwr.h @@ -0,0 +1,208 @@ +/** + ****************************************************************************** + * @file stm32l1xx_pwr.h + * @author MCD Application Team + * @version V1.0.0RC1 + * @date 07/02/2010 + * @brief This file contains all the functions prototypes for the PWR firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_PWR_H +#define __STM32L1xx_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/** @addtogroup STM32L1xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/** @defgroup PWR_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Constants + * @{ + */ + +/** @defgroup PVD_detection_level + * @{ + */ + +#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 /* External input analog voltage + (Compare internally to VREFINT) */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ + ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ + ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ + ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) +/** + * @} + */ + +/** @defgroup WakeUp_Pins + * @{ + */ + +#define PWR_WakeUpPin_1 ((uint32_t)0x00000000) +#define PWR_WakeUpPin_2 ((uint32_t)0x00000004) +#define PWR_WakeUpPin_3 ((uint32_t)0x00000008) +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \ + ((PIN) == PWR_WakeUpPin_2) || \ + ((PIN) == PWR_WakeUpPin_3)) +/** + * @} + */ + + +/** @defgroup Voltage_Scaling_Ranges + * @{ + */ + +#define PWR_VoltageScaling_Range1 PWR_CR_VOS_0 +#define PWR_VoltageScaling_Range2 PWR_CR_VOS_1 +#define PWR_VoltageScaling_Range3 PWR_CR_VOS + +#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_VoltageScaling_Range1) || \ + ((RANGE) == PWR_VoltageScaling_Range2) || \ + ((RANGE) == PWR_VoltageScaling_Range3)) +/** + * @} + */ + +/** @defgroup Regulator_state_is_Sleep_STOP_mode + * @{ + */ + +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower PWR_CR_LPSDSR +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ + ((REGULATOR) == PWR_Regulator_LowPower)) +/** + * @} + */ + +/** @defgroup SLEEP_mode_entry + * @{ + */ + +#define PWR_SLEEPEntry_WFI ((uint8_t)0x01) +#define PWR_SLEEPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE)) + +/** + * @} + */ + +/** @defgroup STOP_mode_entry + * @{ + */ + +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) + +/** + * @} + */ + +/** @defgroup PWR_Flag + * @{ + */ + +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF +#define PWR_FLAG_VOS PWR_CSR_VOSF +#define PWR_FLAG_REGLP PWR_CSR_REGLPF + +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \ + ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP)) + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions + * @{ + */ + +void PWR_DeInit(void); +void PWR_RTCAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState); +void PWR_FastWakeUpCmd(FunctionalState NewState); +void PWR_UltraLowPowerCmd(FunctionalState NewState); +void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling); +void PWR_EnterLowPowerRunMode(FunctionalState NewState); +void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_PWR_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c new file mode 100644 index 000000000..e6b8716da --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c @@ -0,0 +1,464 @@ +/** + ****************************************************************************** + * @file stm32l1xx_pwr.c + * @author MCD Application Team + * @version V1.0.0RC1 + * @date 07/02/2010 + * @brief This file provides all the PWR firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_pwr.h" +#include "stm32l1xx_rcc.h" + +/** @addtogroup STM32L1xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup PWR + * @brief PWR driver modules + * @{ + */ + +/** @defgroup PWR_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Defines + * @{ + */ + +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of DBP bit */ +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) + +/* Alias word address of PVDE bit */ +#define PVDE_BitNumber 0x04 +#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) + +/* Alias word address of ULP bit */ +#define ULP_BitNumber 0x09 +#define CR_ULP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4)) + +/* Alias word address of FWU bit */ +#define FWU_BitNumber 0x0A +#define CR_FWU_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of EWUP bit */ +#define CSR_OFFSET (PWR_OFFSET + 0x04) +#define EWUP_BitNumber 0x08 +#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) +#define CR_VOS_MASK ((uint32_t)0xFFFFE7FF) + +/** + * @} + */ + +/** @defgroup PWR_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @param None + * @retval None + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the RTC and backup registers. + * @param NewState: new state of the access to the RTC and backup registers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_RTCAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param NewState: new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDLevel: specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_PVDLevel_0: PVD detection level set to 1.9V + * @arg PWR_PVDLevel_1: PVD detection level set to 2.1V + * @arg PWR_PVDLevel_2: PVD detection level set to 2.3V + * @arg PWR_PVDLevel_3: PVD detection level set to 2.5V + * @arg PWR_PVDLevel_4: PVD detection level set to 2.7V + * @arg PWR_PVDLevel_5: PVD detection level set to 2.9V + * @arg PWR_PVDLevel_6: PVD detection level set to 3.1V + * @arg PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT) + * @retval None + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + + tmpreg = PWR->CR; + + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_MASK; + + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param PWR_WakeUpPin: specifies the WakeUpPin. + * This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3. + * @param NewState: new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin)); + + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + tmp = CSR_EWUP_BB + PWR_WakeUpPin; + + *(__IO uint32_t *) (tmp) = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Fast WakeUp from Ultra Low Power mode. + * @param NewState: new state of the Fast WakeUp functionality. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_FastWakeUpCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_FWU_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Ultra Low Power mode. + * @param NewState: new state of the Ultra Low Power mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_UltraLowPowerCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_ULP_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the voltage scaling range. + * @param PWR_VoltageScaling: specifies the voltage scaling range. + * This parameter can be: + * @arg PWR_VoltageScaling_Range1: Voltage Scaling Range 1 + * @arg PWR_VoltageScaling_Range2: Voltage Scaling Range 2 + * @arg PWR_VoltageScaling_Range3: Voltage Scaling Range 3 + * @retval None + */ +void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(PWR_VoltageScaling)); + + tmp = PWR->CR; + + tmp &= CR_VOS_MASK; + tmp |= PWR_VoltageScaling; + + PWR->CR = tmp & 0xFFFFFFF3; + +} + +/** + * @brief Enters/Exits the Low Power Run mode. + * @param NewState: new state of the Low Power Run mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_EnterLowPowerRunMode(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + PWR->CR |= PWR_CR_LPSDSR; + PWR->CR |= PWR_CR_LPRUN; + } + else + { + PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN); + PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR); + } +} + +/** + * @brief Enters Sleep mode. + * @param PWR_Regulator: specifies the regulator state in Sleep mode. + * This parameter can be one of the following values: + * @arg PWR_Regulator_ON: Sleep mode with regulator ON + * @arg PWR_Regulator_LowPower: Sleep mode with regulator in low power mode + * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + + assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry)); + + /* Select the regulator state in Sleep mode ---------------------------------*/ + tmpreg = PWR->CR; + + /* Clear PDDS and LPDSR bits */ + tmpreg &= CR_DS_MASK; + + /* Set LPDSR bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } +} + +/** + * @brief Enters STOP mode. + * @param PWR_Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_Regulator_ON: STOP mode with regulator ON + * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode + * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction + * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction + * @retval None + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDSR bits */ + tmpreg &= CR_DS_MASK; + + /* Set LPDSR bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); +} + +/** + * @brief Enters STANDBY mode. + * @param None + * @retval None + */ +void PWR_EnterSTANDBYMode(void) +{ + /* Clear Wake-up flag */ + PWR->CR |= PWR_CR_CWUF; + + /* Select STANDBY mode */ + PWR->CR |= PWR_CR_PDDS; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + +/* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @arg PWR_FLAG_PVDO: PVD Output + * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag + * @arg PWR_FLAG_VOS: Voltage Scaling select flag + * @arg PWR_FLAG_REGLP: Regulator LP flag + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @retval None + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h index aa6693d8b..cd79da065 100644 --- a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h @@ -37,7 +37,7 @@ /* #include "stm32l1xx_i2c.h" */ /* #include "stm32l1xx_iwdg.h" */ /* #include "stm32l1xx_lcd.h" */ -/* #include "stm32l1xx_pwr.h" */ +#include "stm32l1xx_pwr.h" #include "stm32l1xx_rcc.h" /* #include "stm32l1xx_rtc.h" */ #include "stm32l1xx_spi.h"