Finalise XMC1000 IAR demos.

FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/IAR_Specific/startup_XMC1100.s

@@ -0,0 +1,333 @@
+;**********************************************************************************
+;*
+;* Part one of the system initialization code, contains low-level
+;* initialization, plain thumb variant.
+;*
+;* Copyright 2013 IAR Systems. All rights reserved.
+;*
+;* $Revision: 64600 $
+;*
+;******************* Version History **********************************************   
+;  V5, Feb, 6, 2013 TYS:a) Add DAVE3_CE defination, 
+;                       b) Remove Math,ADC,CCU8,POSIF,LEDTS,BCCU0 interrupt
+;                       c) Change AllowPLLInitByStartup to AllowClkInitByStartup 
+;  V6, May, 16,2013 TYS:a) Add XMC1100_SCU.inc 
+;     
+;**********************************************************************************
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+#ifdef DAVE_CE
+#include "XMC1100_SCU.inc"
+#include "Device_Data.h"
+#else
+#define CLKVAL1_SSW 0x00000100
+#define CLKVAL2_SSW 0x00000000
+#endif 
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+        DCD     0                         ; 0x8
+        DCD     0                         ; 0xC
+        DCD     CLKVAL1_SSW               ; 0x10 CLK_VAL1 - (CLKCR default)
+        DCD     CLKVAL2_SSW               ; 0x14 CLK_VAL2 - (CGATCLR0 default)
+
+        SECTION .vect_table:CODE:ROOT(2)
+        THUMB
+        LDR     R0,=HardFault_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=SVC_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=PendSV_Handler
+        BX      R0
+        LDR     R0,=SysTick_Handler
+        BX      R0
+
+        ; External Interrupts
+        LDR     R0,=SCU_0_IRQHandler      ; Handler name for SR SCU_0
+        BX      R0
+        LDR     R0,=SCU_1_IRQHandler      ; Handler name for SR SCU_1
+        BX      R0
+        LDR     R0,=SCU_2_IRQHandler      ; Handler name for SR SCU_2
+        BX      R0
+        LDR     R0,=ERU0_0_IRQHandler     ; Handler name for SR ERU0_0
+        BX      R0
+        LDR     R0,=ERU0_1_IRQHandler     ; Handler name for SR ERU0_1
+        BX      R0
+        LDR     R0,=ERU0_2_IRQHandler     ; Handler name for SR ERU0_2
+        BX      R0
+        LDR     R0,=ERU0_3_IRQHandler     ; Handler name for SR ERU0_3
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=USIC0_0_IRQHandler    ; Handler name for SR USIC0_0
+        BX      R0
+        LDR     R0,=USIC0_1_IRQHandler    ; Handler name for SR USIC0_1
+        BX      R0
+        LDR     R0,=USIC0_2_IRQHandler    ; Handler name for SR USIC0_2
+        BX      R0
+        LDR     R0,=USIC0_3_IRQHandler    ; Handler name for SR USIC0_3
+        BX      R0
+        LDR     R0,=USIC0_4_IRQHandler    ; Handler name for SR USIC0_4
+        BX      R0
+        LDR     R0,=USIC0_5_IRQHandler    ; Handler name for SR USIC0_5
+        BX      R0
+        LDR     R0,=VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
+        BX      R0
+        LDR     R0,=VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=CCU40_0_IRQHandler    ; Handler name for SR CCU40_0
+        BX      R0
+        LDR     R0,=CCU40_1_IRQHandler    ; Handler name for SR CCU40_1
+        BX      R0
+        LDR     R0,=CCU40_2_IRQHandler    ; Handler name for SR CCU40_2
+        BX      R0
+        LDR     R0,=CCU40_3_IRQHandler    ; Handler name for SR CCU40_3
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        EXTERN  SystemInit
+        SECTION .text:CODE:NOROOT(2)
+
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =SystemInit_DAVE3
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK Undef_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Undef_Handler
+        B Undef_Handler
+
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B HardFault_Handler
+
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B SVC_Handler
+
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B PendSV_Handler
+
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B SysTick_Handler
+
+
+        PUBWEAK SCU_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SCU_0_IRQHandler
+        B SCU_0_IRQHandler
+
+        PUBWEAK SCU_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SCU_1_IRQHandler
+        B SCU_1_IRQHandler
+
+
+        PUBWEAK SCU_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SCU_2_IRQHandler
+        B SCU_2_IRQHandler
+
+
+        PUBWEAK ERU0_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ERU0_0_IRQHandler
+        B ERU0_0_IRQHandler
+
+
+        PUBWEAK ERU0_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ERU0_1_IRQHandler
+        B ERU0_1_IRQHandler
+
+
+        PUBWEAK ERU0_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ERU0_2_IRQHandler
+        B ERU0_2_IRQHandler
+
+
+        PUBWEAK ERU0_3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ERU0_3_IRQHandler
+        B ERU0_3_IRQHandler
+
+
+        PUBWEAK USIC0_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_0_IRQHandler
+        B USIC0_0_IRQHandler
+
+
+        PUBWEAK USIC0_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_1_IRQHandler
+        B USIC0_1_IRQHandler
+
+
+        PUBWEAK USIC0_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_2_IRQHandler
+        B USIC0_2_IRQHandler
+
+
+        PUBWEAK USIC0_3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_3_IRQHandler
+        B USIC0_3_IRQHandler
+
+
+        PUBWEAK USIC0_4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_4_IRQHandler
+        B USIC0_4_IRQHandler
+
+
+        PUBWEAK USIC0_5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_5_IRQHandler
+        B USIC0_5_IRQHandler
+
+
+        PUBWEAK VADC0_C0_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+VADC0_C0_0_IRQHandler
+        B VADC0_C0_0_IRQHandler
+
+
+        PUBWEAK VADC0_C0_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+VADC0_C0_1_IRQHandler
+        B VADC0_C0_1_IRQHandler
+
+
+        PUBWEAK CCU40_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCU40_0_IRQHandler
+        B CCU40_0_IRQHandler
+
+
+        PUBWEAK CCU40_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCU40_1_IRQHandler
+        B CCU40_1_IRQHandler
+
+
+        PUBWEAK CCU40_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCU40_2_IRQHandler
+        B CCU40_2_IRQHandler
+
+
+        PUBWEAK CCU40_3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCU40_3_IRQHandler
+        B CCU40_3_IRQHandler
+
+
+; Definition of the default weak SystemInit_DAVE3 function
+;If DAVE3 requires an extended SystemInit it will create its own version of
+;SystemInit_DAVE3 which overrides this weak definition. Example includes
+;setting up of external memory interfaces.
+
+        PUBWEAK SystemInit_DAVE3
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SystemInit_DAVE3
+        NOP
+        BX LR
+
+;Decision function queried by CMSIS startup for Clock tree setup ======== */
+;In the absence of DAVE code engine, CMSIS SystemInit() must perform clock tree setup.
+;This decision routine defined here will always return TRUE.
+;When overridden by a definition defined in DAVE code engine, this routine
+;returns FALSE indicating that the code engine has performed the clock setup
+
+        PUBWEAK AllowClkInitByStartup
+        SECTION .text:CODE:REORDER:NOROOT(2)
+AllowClkInitByStartup
+        MOVS  R0,#1
+        BX    LR
+
+        END

FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/IAR_Specific/startup_XMC1200.s

@@ -7,10 +7,10 @@
 ;*
 ;* $Revision: 64600 $
 ;*
-;******************* Version History **********************************************
+;******************* Version History **********************************************   
-;
-;  V6, May, 16,2013 TYS:a) Add XMC1200_SCU.inc
 ;
+;  V6, May, 16,2013 TYS:a) Add XMC1200_SCU.inc 
+;     
 ;**********************************************************************************
 ;
 ; The modules in this file are included in the libraries, and may be replaced
@@ -29,7 +29,7 @@
 #else
 #define CLKVAL1_SSW 0x00000100
 #define CLKVAL2_SSW 0x00000000
-#endif
+#endif 
 
         ;; Forward declaration of sections.
         SECTION CSTACK:DATA:NOROOT(3)

FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/IAR_Specific/startup_XMC1300.s

@@ -0,0 +1,390 @@
+;************************************************
+;*
+;* Part one of the system initialization code, contains low-level
+;* initialization, plain thumb variant.
+;*
+;* Copyright 2013 IAR Systems. All rights reserved.
+;*
+;* $Revision: 64600 $
+;*
+;******************* Version History **********************************************   
+;
+;  V6, May, 16,2013 TYS:a) Add XMC1300_SCU.inc 
+;     
+;**********************************************************************************
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+#ifdef DAVE_CE
+#include "XMC1300_SCU.inc"
+#include "Device_Data.h"
+#else
+#define CLKVAL1_SSW 0x00000100
+#define CLKVAL2_SSW 0x00000000
+#endif         
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+        DCD     0                         ; 0x8
+        DCD     0                         ; 0xC
+        DCD     CLKVAL1_SSW               ; 0x10 CLK_VAL1 - (CLKCR default)
+        DCD     CLKVAL2_SSW               ; 0x14 CLK_VAL2 - (CGATCLR0 default)
+
+        SECTION .vect_table:CODE:ROOT(2)
+        THUMB
+        LDR     R0,=HardFault_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=SVC_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=PendSV_Handler
+        BX      R0
+        LDR     R0,=SysTick_Handler
+        BX      R0
+
+        ; External Interrupts
+        LDR     R0,=SCU_0_IRQHandler      ; Handler name for SR SCU_0
+        BX      R0
+        LDR     R0,=SCU_1_IRQHandler      ; Handler name for SR SCU_1
+        BX      R0
+        LDR     R0,=SCU_2_IRQHandler      ; Handler name for SR SCU_2
+        BX      R0
+        LDR     R0,=ERU0_0_IRQHandler     ; Handler name for SR ERU0_0
+        BX      R0
+        LDR     R0,=ERU0_1_IRQHandler     ; Handler name for SR ERU0_1
+        BX      R0
+        LDR     R0,=ERU0_2_IRQHandler     ; Handler name for SR ERU0_2
+        BX      R0
+        LDR     R0,=ERU0_3_IRQHandler     ; Handler name for SR ERU0_3
+        BX      R0
+        LDR     R0,=MATH0_0_IRQHandler    ; Handler name for SR MATH0_0
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=USIC0_0_IRQHandler    ; Handler name for SR USIC0_0
+        BX      R0
+        LDR     R0,=USIC0_1_IRQHandler    ; Handler name for SR USIC0_1
+        BX      R0
+        LDR     R0,=USIC0_2_IRQHandler    ; Handler name for SR USIC0_2
+        BX      R0
+        LDR     R0,=USIC0_3_IRQHandler    ; Handler name for SR USIC0_3
+        BX      R0
+        LDR     R0,=USIC0_4_IRQHandler    ; Handler name for SR USIC0_4
+        BX      R0
+        LDR     R0,=USIC0_5_IRQHandler    ; Handler name for SR USIC0_5
+        BX      R0
+        LDR     R0,=VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
+        BX      R0
+        LDR     R0,=VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
+        BX      R0
+        LDR     R0,=VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
+        BX      R0
+        LDR     R0,=VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
+        BX      R0
+        LDR     R0,=VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
+        BX      R0
+        LDR     R0,=VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
+        BX      R0
+        LDR     R0,=CCU40_0_IRQHandler    ; Handler name for SR CCU40_0
+        BX      R0
+        LDR     R0,=CCU40_1_IRQHandler    ; Handler name for SR CCU40_1
+        BX      R0
+        LDR     R0,=CCU40_2_IRQHandler    ; Handler name for SR CCU40_2
+        BX      R0
+        LDR     R0,=CCU40_3_IRQHandler    ; Handler name for SR CCU40_3
+        BX      R0
+        LDR     R0,=CCU80_0_IRQHandler    ; Handler name for SR CCU80_0
+        BX      R0
+        LDR     R0,=CCU80_1_IRQHandler    ; Handler name for SR CCU80_1
+        BX      R0
+        LDR     R0,=POSIF0_0_IRQHandler   ; Handler name for SR POSIF0_0
+        BX      R0
+        LDR     R0,=POSIF0_1_IRQHandler   ; Handler name for SR POSIF0_1
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=BCCU0_0_IRQHandler    ; Handler name for SR BCCU0_0
+        BX      R0
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        EXTERN  SystemInit
+        SECTION .text:CODE:NOROOT(2)
+
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =SystemInit_DAVE3
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK Undef_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Undef_Handler
+        B Undef_Handler
+
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B HardFault_Handler
+
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B SVC_Handler
+
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B PendSV_Handler
+
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B SysTick_Handler
+
+
+        PUBWEAK SCU_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SCU_0_IRQHandler
+        B SCU_0_IRQHandler
+
+        PUBWEAK SCU_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SCU_1_IRQHandler
+        B SCU_1_IRQHandler
+
+
+        PUBWEAK SCU_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SCU_2_IRQHandler
+        B SCU_2_IRQHandler
+
+
+        PUBWEAK ERU0_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ERU0_0_IRQHandler
+        B ERU0_0_IRQHandler
+
+
+        PUBWEAK ERU0_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ERU0_1_IRQHandler
+        B ERU0_1_IRQHandler
+
+
+        PUBWEAK ERU0_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ERU0_2_IRQHandler
+        B ERU0_2_IRQHandler
+
+
+        PUBWEAK ERU0_3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ERU0_3_IRQHandler
+        B ERU0_3_IRQHandler
+
+
+        PUBWEAK MATH0_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MATH0_0_IRQHandler
+        B MATH0_0_IRQHandler
+
+
+        PUBWEAK USIC0_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_0_IRQHandler
+        B USIC0_0_IRQHandler
+
+
+        PUBWEAK USIC0_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_1_IRQHandler
+        B USIC0_1_IRQHandler
+
+
+        PUBWEAK USIC0_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_2_IRQHandler
+        B USIC0_2_IRQHandler
+
+
+        PUBWEAK USIC0_3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_3_IRQHandler
+        B USIC0_3_IRQHandler
+
+
+        PUBWEAK USIC0_4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_4_IRQHandler
+        B USIC0_4_IRQHandler
+
+
+        PUBWEAK USIC0_5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_5_IRQHandler
+        B USIC0_5_IRQHandler
+
+
+        PUBWEAK VADC0_C0_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+VADC0_C0_0_IRQHandler
+        B VADC0_C0_0_IRQHandler
+
+
+        PUBWEAK VADC0_C0_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+VADC0_C0_1_IRQHandler
+        B VADC0_C0_1_IRQHandler
+
+
+        PUBWEAK VADC0_G0_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+VADC0_G0_0_IRQHandler
+        B VADC0_G0_0_IRQHandler
+
+
+        PUBWEAK VADC0_G0_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+VADC0_G0_1_IRQHandler
+        B VADC0_G0_1_IRQHandler
+
+
+        PUBWEAK VADC0_G1_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+VADC0_G1_0_IRQHandler
+        B VADC0_G1_0_IRQHandler
+
+
+        PUBWEAK VADC0_G1_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+VADC0_G1_1_IRQHandler
+        B VADC0_G1_1_IRQHandler
+
+
+        PUBWEAK CCU40_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCU40_0_IRQHandler
+        B CCU40_0_IRQHandler
+
+
+        PUBWEAK CCU40_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCU40_1_IRQHandler
+        B CCU40_1_IRQHandler
+
+
+        PUBWEAK CCU40_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCU40_2_IRQHandler
+        B CCU40_2_IRQHandler
+
+
+        PUBWEAK CCU40_3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCU40_3_IRQHandler
+        B CCU40_3_IRQHandler
+
+
+        PUBWEAK CCU80_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCU80_0_IRQHandler
+        B CCU80_0_IRQHandler
+
+
+        PUBWEAK CCU80_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCU80_1_IRQHandler
+        B CCU80_1_IRQHandler
+
+
+        PUBWEAK POSIF0_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+POSIF0_0_IRQHandler
+        B POSIF0_0_IRQHandler
+
+
+        PUBWEAK POSIF0_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+POSIF0_1_IRQHandler
+        B POSIF0_1_IRQHandler
+
+
+        PUBWEAK BCCU0_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BCCU0_0_IRQHandler
+        B BCCU0_0_IRQHandler
+
+; Definition of the default weak SystemInit_DAVE3 function
+;If DAVE3 requires an extended SystemInit it will create its own version of
+;SystemInit_DAVE3 which overrides this weak definition. Example includes
+;setting up of external memory interfaces.
+
+        PUBWEAK SystemInit_DAVE3
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SystemInit_DAVE3
+        NOP
+        BX LR
+
+;Decision function queried by CMSIS startup for Clock tree setup ======== */
+;In the absence of DAVE code engine, CMSIS SystemInit() must perform clock tree setup.
+;This decision routine defined here will always return TRUE.
+;When overridden by a definition defined in DAVE code engine, this routine
+;returns FALSE indicating that the code engine has performed the clock setup
+
+        PUBWEAK AllowClkInitByStartup
+        SECTION .text:CODE:REORDER:NOROOT(2)
+AllowClkInitByStartup
+        MOVS  R0,#1
+        BX    LR
+
+        END

FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/IAR_Specific/system_XMC1100.c

@@ -0,0 +1,130 @@
+/******************************************************************************
+ * @file     system_XMC1100.c
+ * @brief    Device specific initialization for the XMC1100-Series according 
+ * to CMSIS
+ * @version  V1.4
+ * @date     01 Feb 2013
+ *
+ * @note
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with 
+ * Infineon’s microcontrollers.
+ *   
+ * This file can be freely distributed within development tools that are 
+ * supporting such microcontrollers.
+ *  
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+/*
+ * *************************** Change history ********************************
+ * V1.2, 13 Dec 2012, PKB : Created change history table
+ * V1.3, 20 Dec 2012, PKB : Fixed SystemCoreClock computation
+ * V1.3, 01 Feb 2013, PKB : SCU_CLOCK -> SCU_CLK
+ */
+
+#include "system_XMC1100.h"
+#include <XMC1100.h>
+
+/*---------------------------------------------------------------------------
+ Extern definitions 
+ *--------------------------------------------------------------------------*/
+extern uint32_t AllowClkInitByStartup(void);
+
+/*----------------------------------------------------------------------------
+  Clock Global defines
+ *----------------------------------------------------------------------------*/
+#define DCO_DCLK                  64000000UL
+#define DCO_DCLK_MULTIPLIER       16384000UL
+#define DCO_DCLK_DIVIDER          9UL
+#define MCLK_MHZ                  32000000UL
+#define KHZ_MULTIPLIER            1000UL
+#define FRACBITS                  8UL
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/*!< System Clock Frequency (Core Clock) (MCLK on TIMM1) */
+uint32_t SystemCoreClock;
+
+/*----------------------------------------------------------------------------
+  Fixed point math definitions
+ *----------------------------------------------------------------------------*/
+typedef int32_t Q_24_8;
+typedef int32_t Q_15_0;
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{    
+
+  /*
+   * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE
+   * Clock app.
+   */ 
+  if(AllowClkInitByStartup()){ 
+  /* Do not change default values of IDIV,FDIV and RTCCLKSEL */
+  /* ====== Default configuration ======= */
+  /*
+   * MCLK    = DCO_DCLK
+   * PCLK    = MCLK
+   * RTC CLK = Standby clock
+   */
+  }
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  * @note   -  
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t IDIV, FDIV, CLKCR, Clock;
+
+  CLKCR = SCU_CLK -> CLKCR;
+  IDIV = (CLKCR & SCU_CLK_CLKCR_IDIV_Msk) >> SCU_CLK_CLKCR_IDIV_Pos;
+  FDIV = (CLKCR & SCU_CLK_CLKCR_FDIV_Msk) >> SCU_CLK_CLKCR_FDIV_Pos;
+  
+  if(IDIV)
+  {
+    /* Divider is enabled and used */
+    if(0 == FDIV)
+     {
+       /* No fractional divider, so MCLK = DCO_Clk / (2 * IDIV) */
+       Clock = MCLK_MHZ / IDIV;
+     }
+    else
+     {
+       /* Both integer and fractional divider must be considered */
+       /* 1. IDIV + FDIV/256 */
+       Q_24_8 FDiv_IDiv_Sum = (IDIV << FRACBITS) + FDIV;  
+
+       /* 2. Fixed point division Q24.8 / Q9.8 = Q15.0 */
+       Q_15_0 ClockVal = (DCO_DCLK_MULTIPLIER << FRACBITS)/ FDiv_IDiv_Sum;
+       Clock = ((uint32_t)ClockVal) * KHZ_MULTIPLIER;
+       Clock = Clock >> DCO_DCLK_DIVIDER;
+     }
+  }
+  else
+  {
+    /* Divider bypassed. Simply divide DCO_DCLK by 2 */
+    Clock = MCLK_MHZ;
+  }
+
+  /* Finally with the math class over, update SystemCoreClock */
+  SystemCoreClock = Clock;  
+}
+

FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/IAR_Specific/system_XMC1100.h

@@ -0,0 +1,55 @@
+/******************************************************************************
+ * @file     system_XMC1100.h
+ * @brief    Device specific initialization for the XMC1100-Series according 
+ * to CMSIS
+ * @version  V1.1
+ * @date     13 Dec 2012
+ *
+ * @note
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with 
+ * Infineon’s microcontrollers.
+ *   
+ * This file can be freely distributed within development tools that are 
+ * supporting such microcontrollers.
+ *  
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+/*
+ * *************************** Change history ********************************
+ * V1.1, 13 Dec 2012, PKB : Created change history table, extern reference
+ */
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+extern uint32_t SystemCoreClock;
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void);
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  * @note   -  
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void);
+

FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/IAR_Specific/system_XMC1200.c

@@ -1,6 +1,6 @@
 /******************************************************************************
  * @file     system_XMC1200.c
- * @brief    Device specific initialization for the XMC1200-Series according
+ * @brief    Device specific initialization for the XMC1200-Series according 
  * to CMSIS
  * @version  V1.4
  * @date     01 Feb 2013
@@ -10,12 +10,12 @@
 
  *
  * @par
- * Infineon Technologies AG (Infineon) is supplying this software for use with
+ * Infineon Technologies AG (Infineon) is supplying this software for use with 
  * Infineon’s microcontrollers.
- *
+ *   
- * This file can be freely distributed within development tools that are
+ * This file can be freely distributed within development tools that are 
  * supporting such microcontrollers.
- *
+ *  
  *
  * @par
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -36,7 +36,7 @@
 #include <XMC1200.h>
 
 /*---------------------------------------------------------------------------
- Extern definitions
+ Extern definitions 
  *--------------------------------------------------------------------------*/
 extern uint32_t AllowClkInitByStartup(void);
 
@@ -67,13 +67,13 @@ typedef int32_t Q_15_0;
   * @retval None
   */
 void SystemInit(void)
-{
+{    
 
   /*
    * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE
    * Clock app.
-   */
+   */ 
-  if(AllowClkInitByStartup()){
+  if(AllowClkInitByStartup()){ 
   /* Do not change default values of IDIV,FDIV and RTCCLKSEL */
   /* ====== Default configuration ======= */
   /*
@@ -86,7 +86,7 @@ void SystemInit(void)
 
 /**
   * @brief  Update SystemCoreClock according to Clock Register Values
-  * @note   -
+  * @note   -  
   * @param  None
   * @retval None
   */
@@ -97,7 +97,7 @@ void SystemCoreClockUpdate(void)
   CLKCR = SCU_CLK -> CLKCR;
   IDIV = (CLKCR & SCU_CLK_CLKCR_IDIV_Msk) >> SCU_CLK_CLKCR_IDIV_Pos;
   FDIV = (CLKCR & SCU_CLK_CLKCR_FDIV_Msk) >> SCU_CLK_CLKCR_FDIV_Pos;
-
+  
   if(IDIV)
   {
     /* Divider is enabled and used */
@@ -110,7 +110,7 @@ void SystemCoreClockUpdate(void)
      {
        /* Both integer and fractional divider must be considered */
        /* 1. IDIV + FDIV/256 */
-       Q_24_8 FDiv_IDiv_Sum = (IDIV << FRACBITS) + FDIV;
+       Q_24_8 FDiv_IDiv_Sum = (IDIV << FRACBITS) + FDIV;  
 
        /* 2. Fixed point division Q24.8 / Q9.8 = Q15.0 */
        Q_15_0 ClockVal = (DCO_DCLK_MULTIPLIER << FRACBITS)/ FDiv_IDiv_Sum;
@@ -125,6 +125,6 @@ void SystemCoreClockUpdate(void)
   }
 
   /* Finally with the math class over, update SystemCoreClock */
-  SystemCoreClock = Clock;
+  SystemCoreClock = Clock;  
 }
 

FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/IAR_Specific/system_XMC1300.c

@@ -0,0 +1,130 @@
+/******************************************************************************
+ * @file     system_XMC1300.c
+ * @brief    Device specific initialization for the XMC1300-Series according 
+ * to CMSIS
+ * @version  V1.4
+ * @date     01 Feb 2013
+ *
+ * @note
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with 
+ * Infineon’s microcontrollers.
+ *   
+ * This file can be freely distributed within development tools that are 
+ * supporting such microcontrollers.
+ *  
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+/*
+ * *************************** Change history ********************************
+ * V1.2, 13 Dec 2012, PKB : Created change history table
+ * V1.3, 20 Dec 2012, PKB : Fixed SystemCoreClock computation
+ * V1.4, 02 Feb 2013, PKB : SCU_CLOCK -> SCU_CLK
+ */
+
+#include "system_XMC1300.h"
+#include <XMC1300.h>
+
+/*---------------------------------------------------------------------------
+ Extern definitions 
+ *--------------------------------------------------------------------------*/
+extern uint32_t AllowClkInitByStartup(void);
+
+/*----------------------------------------------------------------------------
+  Clock Global defines
+ *----------------------------------------------------------------------------*/
+#define DCO_DCLK                  64000000UL
+#define DCO_DCLK_MULTIPLIER       16384000UL
+#define DCO_DCLK_DIVIDER          9UL
+#define MCLK_MHZ                  32000000UL
+#define KHZ_MULTIPLIER            1000UL
+#define FRACBITS                  8UL
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/*!< System Clock Frequency (Core Clock) (MCLK on TIMM1) */
+uint32_t SystemCoreClock;
+
+/*----------------------------------------------------------------------------
+  Fixed point math definitions
+ *----------------------------------------------------------------------------*/
+typedef int32_t Q_24_8;
+typedef int32_t Q_15_0;
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{    
+
+  /*
+   * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE
+   * Clock app.
+   */ 
+  if(AllowClkInitByStartup()){ 
+  /* Do not change default values of IDIV,FDIV and RTCCLKSEL */
+  /* ====== Default configuration ======= */
+  /*
+   * MCLK    = DCO_DCLK
+   * PCLK    = MCLK
+   * RTC CLK = Standby clock
+   */
+  }
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  * @note   -  
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t IDIV, FDIV, CLKCR, Clock;
+
+  CLKCR = SCU_CLK -> CLKCR;
+  IDIV = (CLKCR & SCU_CLK_CLKCR_IDIV_Msk) >> SCU_CLK_CLKCR_IDIV_Pos;
+  FDIV = (CLKCR & SCU_CLK_CLKCR_FDIV_Msk) >> SCU_CLK_CLKCR_FDIV_Pos;
+  
+  if(IDIV)
+  {
+    /* Divider is enabled and used */
+    if(0 == FDIV)
+     {
+       /* No fractional divider, so MCLK = DCO_Clk / (2 * IDIV) */
+       Clock = MCLK_MHZ / IDIV;
+     }
+    else
+     {
+       /* Both integer and fractional divider must be considered */
+       /* 1. IDIV + FDIV/256 */
+       Q_24_8 FDiv_IDiv_Sum = (IDIV << FRACBITS) + FDIV;  
+
+       /* 2. Fixed point division Q24.8 / Q9.8 = Q15.0 */
+       Q_15_0 ClockVal = (DCO_DCLK_MULTIPLIER << FRACBITS)/ FDiv_IDiv_Sum;
+       Clock = ((uint32_t)ClockVal) * KHZ_MULTIPLIER;
+       Clock = Clock >> DCO_DCLK_DIVIDER;
+     }
+  }
+  else
+  {
+    /* Divider bypassed. Simply divide DCO_DCLK by 2 */
+    Clock = MCLK_MHZ;
+  }
+
+  /* Finally with the math class over, update SystemCoreClock */
+  SystemCoreClock = Clock;  
+}
+

FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/IAR_Specific/system_XMC1300.h

@@ -0,0 +1,54 @@
+/******************************************************************************
+ * @file     system_XMC1300.h
+ * @brief    Device specific initialization for the XMC1300-Series according 
+ * to CMSIS
+ * @version  V1.1
+ * @date     13 Dec 2012
+ *
+ * @note
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with 
+ * Infineon’s microcontrollers.
+ *   
+ * This file can be freely distributed within development tools that are 
+ * supporting such microcontrollers.
+ *  
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+/*
+ * *************************** Change history *********************************
+ * V1.1, 13 Dec 2012, PKB, Created this table, added extern and stdint
+ */
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+extern uint32_t SystemCoreClock;
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void);
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  * @note   -  
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void);
+

FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1100.c

@@ -71,7 +71,7 @@
 #include "task.h"
 
 /* Hardware includes. */
-#include <XMC1200.h>
+#include <XMC1100.h>
 
 /* Standard demo include. */
 #include "partest.h"

FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1300.c

@@ -71,7 +71,7 @@
 #include "task.h"
 
 /* Hardware includes. */
-#include <XMC1200.h>
+#include <XMC1300.h>
 
 /* Standard demo include. */
 #include "partest.h"

FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.uvopt

@@ -73,7 +73,7 @@
       <OPTFL>
         <tvExp>1</tvExp>
         <tvExpOptDlg>0</tvExpOptDlg>
-        <IsCurrentTarget>0</IsCurrentTarget>
+        <IsCurrentTarget>1</IsCurrentTarget>
       </OPTFL>
       <CpuCode>255</CpuCode>
       <Books>
@@ -150,7 +150,7 @@
         <SetRegEntry>
           <Number>0</Number>
           <Key>DLGUARM</Key>
-          <Name></Name>
+          <Name>/</Name>
         </SetRegEntry>
         <SetRegEntry>
           <Number>0</Number>
@@ -497,7 +497,7 @@
       <OPTFL>
         <tvExp>1</tvExp>
         <tvExpOptDlg>0</tvExpOptDlg>
-        <IsCurrentTarget>1</IsCurrentTarget>
+        <IsCurrentTarget>0</IsCurrentTarget>
       </OPTFL>
       <CpuCode>255</CpuCode>
       <Books>
@@ -665,7 +665,7 @@
         <aSer4>0</aSer4>
         <StkLoc>0</StkLoc>
         <TrcWin>0</TrcWin>
-        <newCpu>3</newCpu>
+        <newCpu>0</newCpu>
         <uProt>0</uProt>
       </DebugFlag>
       <LintExecutable></LintExecutable>
@@ -682,32 +682,32 @@
     <File>
       <GroupNumber>1</GroupNumber>
       <FileNumber>1</FileNumber>
-      <FileType>1</FileType>
+      <FileType>2</FileType>
       <tvExp>0</tvExp>
       <Focus>0</Focus>
       <ColumnNumber>0</ColumnNumber>
       <tvExpOptDlg>0</tvExpOptDlg>
-      <TopLine>0</TopLine>
+      <TopLine>120</TopLine>
-      <CurrentLine>0</CurrentLine>
+      <CurrentLine>132</CurrentLine>
       <bDave2>0</bDave2>
-      <PathWithFileName>.\system_XMC1200.c</PathWithFileName>
+      <PathWithFileName>.\Keil_Specific\startup_XMC1000.s</PathWithFileName>
-      <FilenameWithoutPath>system_XMC1200.c</FilenameWithoutPath>
+      <FilenameWithoutPath>startup_XMC1000.s</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>1</GroupNumber>
       <FileNumber>2</FileNumber>
-      <FileType>2</FileType>
+      <FileType>1</FileType>
       <tvExp>0</tvExp>
       <Focus>0</Focus>
       <ColumnNumber>0</ColumnNumber>
       <tvExpOptDlg>0</tvExpOptDlg>
-      <TopLine>120</TopLine>
+      <TopLine>0</TopLine>
-      <CurrentLine>132</CurrentLine>
+      <CurrentLine>0</CurrentLine>
       <bDave2>0</bDave2>
-      <PathWithFileName>.\Keil_Specific\startup_XMC1000.s</PathWithFileName>
+      <PathWithFileName>.\Keil_Specific\system_XMC1300.c</PathWithFileName>
-      <FilenameWithoutPath>startup_XMC1000.s</FilenameWithoutPath>
+      <FilenameWithoutPath>system_XMC1300.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -722,8 +722,8 @@
       <TopLine>0</TopLine>
       <CurrentLine>0</CurrentLine>
       <bDave2>0</bDave2>
-      <PathWithFileName>.\Keil_Specific\system_XMC1300.c</PathWithFileName>
+      <PathWithFileName>.\Keil_Specific\system_XMC1100.c</PathWithFileName>
-      <FilenameWithoutPath>system_XMC1300.c</FilenameWithoutPath>
+      <FilenameWithoutPath>system_XMC1100.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -735,11 +735,11 @@
       <Focus>0</Focus>
       <ColumnNumber>0</ColumnNumber>
       <tvExpOptDlg>0</tvExpOptDlg>
-      <TopLine>1</TopLine>
+      <TopLine>0</TopLine>
-      <CurrentLine>33</CurrentLine>
+      <CurrentLine>0</CurrentLine>
       <bDave2>0</bDave2>
-      <PathWithFileName>.\Keil_Specific\system_XMC1100.c</PathWithFileName>
+      <PathWithFileName>.\Keil_Specific\system_XMC1200.c</PathWithFileName>
-      <FilenameWithoutPath>system_XMC1100.c</FilenameWithoutPath>
+      <FilenameWithoutPath>system_XMC1200.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -807,8 +807,8 @@
       <Focus>0</Focus>
       <ColumnNumber>0</ColumnNumber>
       <tvExpOptDlg>0</tvExpOptDlg>
-      <TopLine>2385</TopLine>
+      <TopLine>2152</TopLine>
-      <CurrentLine>2386</CurrentLine>
+      <CurrentLine>2153</CurrentLine>
       <bDave2>0</bDave2>
       <PathWithFileName>..\..\Source\tasks.c</PathWithFileName>
       <FilenameWithoutPath>tasks.c</FilenameWithoutPath>
@@ -823,8 +823,8 @@
       <Focus>0</Focus>
       <ColumnNumber>0</ColumnNumber>
       <tvExpOptDlg>0</tvExpOptDlg>
-      <TopLine>216</TopLine>
+      <TopLine>0</TopLine>
-      <CurrentLine>224</CurrentLine>
+      <CurrentLine>0</CurrentLine>
       <bDave2>0</bDave2>
       <PathWithFileName>..\..\Source\portable\RVDS\ARM_CM0\port.c</PathWithFileName>
       <FilenameWithoutPath>port.c</FilenameWithoutPath>
@@ -863,7 +863,7 @@
       <Focus>0</Focus>
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@@ -879,8 +879,8 @@
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       <tvExpOptDlg>0</tvExpOptDlg>
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       <FilenameWithoutPath>RegTest_Keil.s</FilenameWithoutPath>
@@ -957,10 +957,10 @@
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FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.uvproj

@@ -393,9 +393,19 @@
           <GroupName>System</GroupName>
           <Files>
             <File>
-              <FileName>system_XMC1200.c</FileName>
+              <FileName>startup_XMC1000.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\Keil_Specific\startup_XMC1000.s</FilePath>
+            </File>
+            <File>
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               <FileType>1</FileType>
-              <FilePath>.\system_XMC1200.c</FilePath>
+              <FilePath>.\Keil_Specific\system_XMC1300.c</FilePath>
+            </File>
+            <File>
+              <FileName>system_XMC1100.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Keil_Specific\system_XMC1100.c</FilePath>
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@@ -438,19 +448,9 @@
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+              <FilePath>.\Keil_Specific\system_XMC1200.c</FilePath>
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@@ -1077,11 +1077,6 @@
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               <FileName>startup_XMC1000.s</FileName>
               <FileType>2</FileType>
@@ -1177,6 +1172,11 @@
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             </File>
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+              <FileType>1</FileType>
+              <FilePath>.\Keil_Specific\system_XMC1200.c</FilePath>
+            </File>
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@@ -1803,9 +1803,14 @@
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+              <FileName>startup_XMC1000.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\Keil_Specific\startup_XMC1000.s</FilePath>
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@@ -1848,14 +1853,14 @@
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+              <FilePath>.\Keil_Specific\system_XMC1100.c</FilePath>
             </File>
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FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main.c

@@ -122,7 +122,7 @@ int main( void )
 {
 	/* Prepare the hardware to run this demo. */
 	prvSetupHardware();
-	
+
 	/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
 	of this file. */
 	#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1

FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo.dni

@@ -1,5 +1,5 @@
 [DebugChecksum]
-Checksum=1895932204
+Checksum=1582513185
 [Stack]
 FillEnabled=0
 OverflowWarningsEnabled=1

FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo.wsdt

@@ -33,7 +33,7 @@
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